Low-cost high-performance solar cell and manufacturing process thereof

Abstract

This invention relates to the field of photovoltaic cell technology, specifically disclosing a low-cost, high-performance solar cell and its manufacturing process. It includes: a silicon wafer, a tunneling oxide layer formed on the silicon wafer, and doped polycrystalline silicon. N-type doped regions and P-type doped regions are formed on the doped polycrystalline silicon, with intrinsic polycrystalline silicon separating the N-type and P-type doped regions. A semiconductor layer is formed on the doped polycrystalline silicon, the semiconductor layer being one or more layers of TiO2, WO3, MoO3, TeO2, or NiO. N-type electrodes are formed on the semiconductor layer corresponding to the N-type doped regions, and P-type electrodes are formed on the semiconductor layer corresponding to the P-type doped regions. The N-type and P-type electrodes are in contact with the semiconductor layer. This invention's low-cost, high-performance solar cell can use low-cost metal paste sintering as electrodes, offering advantages of low cost and high performance.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and specifically discloses a low-cost, high-performance solar cell and its manufacturing process. Background Technology

[0002] In the commercialization of solar cell technology, cost reduction and efficiency improvement have always been among the most important goals. Solar cell technology typically uses silver paste and rapid sintering processes to form electrodes. Due to silver's excellent chemical stability, high conductivity, and low contact resistance with silicon, most solar cell technologies still use silver as the electrode material. However, the high cost of silver has also contributed to the increased cost of solar cells.

[0003] To address this issue, various electrode formation technologies using non-precious metal materials have been proposed. For example, patent (US9293624B2) describes a copper electrode electroplating technique, while patent (WO2012 / 047404) discloses a method for forming copper electrodes through a plating process. The copper electrode plating technique in patent (US9293624B2) has drawbacks: it requires forming contact holes and applying masks to prevent electrode material from being plated in non-electrode formation areas. Furthermore, to prevent copper diffusion, protective layers need to be coated on both sides, making the process more complex and increasing costs. In the copper paste coating patent (WO2012 / 047404), the cost reduction effect of partially using silver is not significant. Additionally, because copper oxidizes, only low-temperature sintering is possible. Therefore, compared to high-temperature sintering processes, copper electrodes have higher resistance under the same electrode design.

[0004] Currently, apart from PERC technology, most high-efficiency solar cell technologies (such as HJT, TopCon, and IBC) still use silver electrodes; however, even in PERC solar cell technology, aluminum paste is only used on the P-type electrode on the back side, limiting the potential for cost savings. For N-type electrodes, aluminum reacts with silicon to form P-type doping, making it difficult to apply.

[0005] Regarding back-contact solar cells using P-type silicon wafers, the patent (US2023 / 0307573A1) describes a back-contact solar cell fabrication technique similar to PERC technology, using silver paste for the N-type electrode and aluminum paste for the P-type electrode. While this patent (US2023 / 0307573A1) applies to back-contact solar cell structures based on P-type silicon wafers, it is similar to PERC technology, using aluminum for the P-type electrode, but still using silver for the N-type electrode, which limits its application. It is evident that existing technologies cannot completely replace silver paste, and even with partial application of silver paste, it is difficult to effectively reduce the amount of silver used.

[0006] In view of the shortcomings of the existing technology, there is an urgent need to provide a new low-cost, high-performance solar cell. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-cost, high-performance solar cell and its manufacturing process.

[0008] On the one hand, this invention discloses a low-cost, high-performance solar cell, employing the following technical solution: A low-cost, high-performance solar cell and its manufacturing process are disclosed, comprising: a silicon wafer, a tunneling oxide layer formed on the silicon wafer, and doped polycrystalline silicon, wherein N-type doped regions and P-type doped regions are formed on the doped polycrystalline silicon, and intrinsic polycrystalline silicon is spaced between the N-type doped regions and the P-type doped regions; a semiconductor layer is formed on the doped polycrystalline silicon and the intrinsic polycrystalline silicon, wherein the material of the semiconductor layer includes one or more layers of TiO2, WO3, MoO3, TeO2 or NiO; an N-type electrode is formed on the semiconductor layer corresponding to the N-type doped region, and a P-type electrode is formed on the semiconductor layer corresponding to the P-type doped region, wherein the N-type electrode and the P-type electrode are in contact with the semiconductor layer.

[0009] Preferably, the thickness of the doped polycrystalline silicon is 20nm~100nm, and the thickness of the semiconductor layer is 10nm~100nm. Preferably, the semiconductor layer above the P-type doped region has the same thickness or is thinner than the semiconductor layer above the N-type doped region.

[0010] Preferably, the thickness of the semiconductor layer above the N-type doped region is 40~70nm, and the thickness of the semiconductor layer above the P-type doped region is 20~70nm.

[0011] Preferably, a metal alloy is formed between the semiconductor layer and the contact surface of the P-type electrode and / or N-type electrode.

[0012] Preferably, the semiconductor layer contains 0-5 wt% dopant, the dopant including one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N), and oxygen (O).

[0013] Preferably, the P-type electrode and / or the N-type electrode comprises Al, Ag, Cu, or a mixture of any two or three of Al, Ag, Cu.

[0014] Preferably, the P-type electrode and / or the N-type electrode are formed from aluminum paste, wherein the silicon content in the aluminum paste is 0~20wt%.

[0015] Preferably, it also includes a passivation layer.

[0016] Preferably, the passivation layer is formed on the semiconductor layer.

[0017] Preferably, the passivation layer is formed on the doped polysilicon and the intrinsic polysilicon, the semiconductor layer is formed on the passivation layer, and the semiconductor layer passes through the passivation layer and contacts the doped polysilicon.

[0018] Preferably, the passivation layer is made of SiN. x SiO x SiON x Or a combination of one or more layers of Al2O3.

[0019] On the other hand, this invention discloses a manufacturing process for low-cost, high-performance solar cells, employing the following technical solution: A manufacturing process for low-cost, high-performance solar cells includes the following steps: S1. Forming a tunneling oxide layer and intrinsic polycrystalline silicon on a silicon wafer; S2. Selectively implant boron and phosphorus into the intrinsic polysilicon to form doped polysilicon, and alternately form N-type doped regions and P-type doped regions on the doped polysilicon, with intrinsic polysilicon left between the N-type doped regions and the P-type doped regions as isolation. S3. Form a semiconductor layer on doped polysilicon; S4. An N-type electrode and a P-type electrode are formed on the semiconductor layer, such that the N-type electrode is in contact with the semiconductor layer above the N-type doped region, and the P-type electrode is in contact with the semiconductor layer above the P-type doped region.

[0020] Preferably, in S2, boron and phosphorus are selectively implanted by ion implantation, printing of doping paste and heat treatment, or by using a mask and doping diffusion furnace.

[0021] Preferably, in step S3, the semiconductor layer above the P-type doped region is subjected to laser ablation, or a metal alloy is formed on the semiconductor layer above the P-type doped region to make the semiconductor layer above the P-type doped region thinner than the semiconductor layer above the N-type doped region.

[0022] Preferably, in step S4, an N-type electrode and a P-type electrode are formed by simultaneously printing metal paste on the semiconductor layer and sintering, or by separately printing metal paste on the semiconductor layer and sintering.

[0023] Compared with the prior art, the present invention has at least the following beneficial effects: 1. Application of low-cost electrode paste: When using aluminum paste to form electrodes in traditional N-type polycrystalline silicon, there are problems such as the formation of P-type doping due to the reaction between aluminum and polycrystalline silicon, or the decrease in passivation characteristics due to the diffusion of aluminum in polycrystalline silicon. This invention prevents the diffusion of aluminum into polycrystalline silicon through a semiconductor layer, while having good contact resistance with aluminum, thus allowing the use of low-cost metal electrodes such as aluminum; 2. Reducing the thickness of polycrystalline silicon: When traditional metal electrodes directly contact polycrystalline silicon, the diffusion and spikes of metal ions make it difficult to reduce the thickness of the polycrystalline silicon, thus requiring the thickness to be maintained above a certain value. Therefore, it is difficult to reduce the parasitic absorption of light by the thick polycrystalline silicon layer, especially under low back-side current conditions, which also hinders the improvement of bifacial efficiency. This invention solves these problems by forming a semiconductor layer on doped polycrystalline silicon, allowing the metal electrode to contact the semiconductor layer without contacting the underlying doped polycrystalline silicon, thereby reducing the thickness of the polycrystalline silicon. Furthermore, the larger band gap of the semiconductor layer can further reduce light absorption loss. 3. Simple manufacturing process: The semiconductor layer mentioned in this invention can be prepared using the same manufacturing process as doped polycrystalline silicon. It can be processed at low temperatures and has high temperature stability. Therefore, it will not be affected in subsequent high-temperature processes. It can be prepared based on the existing solar cell manufacturing process without adding any additional processes. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of the low-cost, high-performance solar cells in Examples 1-3; Figure 2 This is a schematic diagram of step S1 of the manufacturing process for the low-cost, high-performance solar cell in Example 1. Figure 3 This is a schematic diagram of step S2 of the manufacturing process for the low-cost, high-performance solar cell in Example 1. Figure 4 This is a schematic diagram of step S3 of the manufacturing process for the low-cost, high-performance solar cell in Example 1. Figure 5 This is a schematic diagram of step S4 of the manufacturing process for the low-cost, high-performance solar cell in Example 1. Figure 6 This is a schematic diagram of the structure of the low-cost, high-performance solar cell in Example 4; Figure 7 This is a schematic diagram of step S4 of the manufacturing process for the low-cost, high-performance solar cell in Example 4. Figure 8 This is a schematic diagram of S4, another aspect of the manufacturing process for the low-cost, high-performance solar cell in Example 4. Figure 9 To display the back-side light absorption and reflectance maps of different materials; Figure 10 To display the back absorbance diagrams of different materials; Figure 11 The contact resistance characteristics between the aluminum electrode and the doped polycrystalline silicon and semiconductor layer are shown in the diagram. Figure 12 Photoluminescence intensity characteristics of photoluminescence detection for doped polycrystalline silicon.

[0025] Explanation of icon numbers: 1. Tunneling oxide layer; 2. Intrinsic polysilicon; 3. P-type doped region; 4. N-type doped region; 5. Semiconductor layer; 6. Passivation layer; 7. P-type electrode; 8. N-type electrode. Detailed Implementation

[0026] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] This invention is applied to TBC structures using tunneling oxide layers and doped polycrystalline silicon, aiming to enable the technology to be used on top of existing electrode sintering processes by directly using conventional aluminum paste and sintering processes. This patent simultaneously uses a semiconductor layer above both the P-type and N-type doped regions to prevent aluminum diffusion, allowing for excellent metal contact of aluminum not only on the P-type electrode but also in the N-type doped region. High-efficiency and low-cost solar cells are manufactured using low-cost aluminum paste and conventional sintering processes to form the electrodes.

[0028] Example 1 See Figure 1 In embodiment (1a), the low-cost, high-performance solar cell includes: a silicon wafer, a tunneling oxide layer 1, doped polycrystalline silicon, and a semiconductor layer 5 sequentially formed on the silicon wafer. The doped polycrystalline silicon has P-type doped regions 3 and N-type doped regions 4, with intrinsic polycrystalline silicon 2 spaced between the P-type doped regions 3 and N-type doped regions 4; the semiconductor layer 5 is formed entirely on the doped polycrystalline silicon and the intrinsic polycrystalline silicon 2, and the material of the semiconductor layer 5 is TiO2; a P-type electrode 7 is formed on the semiconductor layer 5 corresponding to the P-type doped region 3, and an N-type electrode 8 is formed on the semiconductor layer 5 corresponding to the N-type doped region 4, with the P-type electrode 7 and the N-type electrode 8 in contact with the semiconductor layer 5.

[0029] In this embodiment, refer to Figure 2-5 The manufacturing process for low-cost, high-performance solar cells includes the following steps: S1. Formation of tunneling oxide layer and intrinsic polysilicon: see Figure 2A tunneling oxide layer and intrinsic polysilicon are formed on the back side of a silicon wafer. The tunneling oxide layer is formed by heat treatment of the silicon wafer surface, and its thickness is 1-2 nm. The intrinsic polysilicon is formed by LPCVD deposition, and its thickness is 20 nm. The tunneling oxide layer can also be formed on the silicon wafer by oxidation in a vacuum apparatus or by a wet process. The intrinsic polysilicon can be deposited using methods such as PVD or PECVD, or implanted through a diffusion furnace, or prepared using various other processes.

[0030] S2, Formation of doped polycrystalline silicon: see Figure 3 In intrinsic polysilicon, boron and phosphorus are selectively implanted through printing doping paste and heat treatment to form alternating P-type and N-type doped regions, with intrinsic polysilicon remaining between the N-type and P-type doped regions as isolation. In addition to being formed through printing doping paste and heat treatment, doped polysilicon can also be formed by ion implantation or by using a mask and a doping diffusion furnace.

[0031] S3. Forming a semiconductor layer: See Figure 4 TiO2 is deposited as a semiconductor layer on doped polysilicon and intrinsic polysilicon via PVD deposition, with a thickness of 60 nm. The secondary conductor layer can also be deposited using vacuum deposition methods such as PECVD and ALD, or paste printing. The semiconductor layer can be doped with other elements, including one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N), and oxygen (O), with dopant content ranging from 0 to 5 wt%. Alternatively, the semiconductor layer can be a TiO2 / TiO2 layer sequentially deposited outwards on the doped polysilicon. x (Al-doped TiO) x Double-layer semiconductor layers, such as TiO2 / WO3 or TiO2 / MoO3, have lower energy loss from charge collection and lower light reflectivity.

[0032] S4. Forming a metal electrode: See Figure 5 Aluminum paste is simultaneously printed onto the semiconductor layer above the P-type and N-type doped regions. Then, rapid thermal processing forms the P-type and N-type electrodes. These electrodes directly contact the semiconductor layer, not the underlying doped polysilicon. Depending on the specific requirements, the P-type and N-type electrodes can be printed separately. The rapid thermal processing temperature is set to 920℃, with a peak temperature between 840 and 920℃. The aluminum paste may contain silicon, with a silicon content between 0 and 20 wt%. A TiAl metal alloy is formed between the semiconductor layer and the contact surfaces of the N-type and P-type electrodes to prevent oxygen from diffusing from the semiconductor layer into the Al metal electrodes.

[0033] Unlike other commonly used photovoltaic materials, such as TiN, TiON, and Ti, although it can also block the diffusion of Al or Cu metals, its performance in solar cells has the following problems: 1. See Figure 9 Due to its high conductivity, it cannot be used in back-contact solar cells. Electrons collected from the N-type doped region can flow through the material and then recombine with holes from the P-type doped region, which will cause a huge current leakage.

[0034] 2. See Figure 10 Due to its high light reflectivity, the bifaciality of the solar cell is very low. Since most of the light is absorbed or reflected, the efficiency of the solar cell will be very low when light shines on its back.

[0035] Therefore, the invention uses TiO2, WO3, MoO3, TeO2 or NiO as the semiconductor layer material to block Al diffusion, which has the advantages of low conductivity and light reflection / absorption rate, and is particularly suitable for solar cells that receive light from both sides.

[0036] Example 2 The difference from Example 1 is that, see Figure 1 In (1b), SiO is also deposited on semiconductor layer 5. x As passivation layer 6, the metal electrode passes through passivation layer 6 to contact the semiconductor layer 5. The material of the passivation layer can also be SiN. x SiO x SiON x The passivation layer, consisting of one or more layers of Al2O3, can form a stable surface layer to reduce electron recombination and surface reflection, thereby improving the efficiency of solar cells.

[0037] Example 3 The difference from Example 2 is that, see Figure 1 In (1c), the semiconductor layer 5 and the passivation layer 6 are inverted. After the passivation layer 6 is deposited on the doped polysilicon and the intrinsic polysilicon, the passivation layer 6 is removed locally above the P-type doped region 3 and the N-type doped region 4 by laser to form a contact hole. The semiconductor layer 5 is deposited on the entire surface of the passivation layer 6 so that the semiconductor layer 5 contacts the P-type doped region 3 and the N-type doped region 4 through the contact hole.

[0038] Example 4 The difference from Example 1 is that in S4, see Figure 6 The semiconductor layer 5 above the P-type doped region 3 is thinner than the semiconductor layer 5 above the N-type doped region 4. In this embodiment, see Figure 7The semiconductor layer on top of the polycrystalline silicon in the P-type doped region can be made slightly thinner by using laser ablation. The semiconductor layer above the P-type doped region is 40 nm, and the semiconductor layer above the N-type semiconductor is 60 nm. In this embodiment, the laser is ultraviolet light with a wavelength of 355 nm and an energy density of 0.1~0.5 J / cm². 2 Since ultraviolet lasers have better selective absorption of the second semiconductor with a larger bandgap, they are more suitable.

[0039] Alternatively, the semiconductor layer above the P-type doped region can be made thinner than the semiconductor layer above the N-type doped region by forming a metal alloy on the semiconductor layer above the P-type doped region. See Figure 8 First, a thin TiO2 semiconductor layer is formed on a polycrystalline silicon layer. Then, Ti metal is formed on top of the semiconductor layer. Only the first type of aluminum paste is printed above the P-type doped region and sintered, so that TiAl metal alloy and P-type electrode are formed on the P-type doped region, while TiO2 is formed in other areas. A second type of aluminum paste is printed above the N-type doped region and sintered, so that the semiconductor layer above the P-type doped region is thinner than the semiconductor layer above the N-type doped region.

[0040] By adjusting the semiconductor thickness above the P-type doped region and the N-type doped region, the contact resistance of aluminum in the P-type doped region 3 can be optimized, while preventing damage caused by aluminum diffusion in the N-type doped region 4. The specific research is as follows.

[0041] Research has revealed that aluminum diffusion in tunneling oxide / doped polysilicon contributes to passivation damage in tunneling oxide / doped polysilicon. 1. The problem of aluminum doping into N-type doped polysilicon regions: Diffused aluminum leads to Al doping in the N-type doped polysilicon layer. Increased Al doping eventually transforms the N-type doping into P-type doping, resulting in a decrease in the N-type doping efficiency of the polysilicon. In contrast, P-type doped polysilicon does not have this problem because it has the same polarity as Al doping.

[0042] 2. The problem of Al further diffusing into the tunneling oxide layer: This will cause passivation loss to P-type and N-type doped polysilicon.

[0043] Therefore, we explored the optimal semiconductor layer thickness corresponding to N-type doping and P-type doping: Figure 11 a) in the figure shows the contact resistance characteristics between the N-type doped polycrystalline silicon and the aluminum electrode. Figure 11 b) shows the contact resistance characteristics between the P-type doped polycrystalline silicon and semiconductor layer and the aluminum electrode.

[0044] like Figure 11As shown in a), in the bilayer structure of N-type doped polycrystalline silicon and semiconductor layer, aluminum exhibits excellent contact resistance, and the contact resistance remains very stable with minimal fluctuations even when the thickness of the semiconductor layer varies. This is because the tunneling oxide layer applied to the semiconductor layer has a good energy level matching relationship with the conduction band of the N-type doped polycrystalline silicon.

[0045] like Figure 11 As shown in b), in the bilayer structure of P-type doped polysilicon and semiconductor layer, the contact resistance decreases as the thickness decreases. This phenomenon is due to the misalignment of the valence band energy levels between the P-type doped polysilicon and the semiconductor layer. Below a certain thickness, the tunneling effect becomes the dominant effect of electrons passing through the semiconductor layer's energy band, thereby reducing the contact resistance. As mentioned earlier, the reason why aluminum paste and high-temperature sintering processes are difficult to apply to doped polysilicon is that 1) aluminum reacts with silicon to form P-type doping, and 2) aluminum diffuses into the tunneling oxide layer under the doped polysilicon, destroying the passivation properties of the oxide film.

[0046] It is evident that, without the passivation losses associated with doped polysilicon, a thinner semiconductor layer results in a lower contact resistivity. Furthermore, using materials such as TiO2 as the semiconductor layer allows for excellent band alignment that matches the N-type doped polysilicon, resulting in good electron collection (because its resistivity is not strongly dependent on the semiconductor layer thickness). For P-type doped polysilicon, holes can be collected by TiO2; therefore, a thinner TiO2 layer above the P-type doped region leads to even lower resistivity.

[0047] Figure 12 The results show the measurement results of the reduced passivation effect caused by aluminum diffusion in a bilayer structure of doped polycrystalline silicon and a semiconductor layer. Photoluminescence (PL) detection is an analytical technique widely used in the field of solar cells to analyze changes in passivation characteristics. In this invention, it is applied to analyze the reduced passivation effect caused by aluminum diffusion. The results in the figure are the average PL intensity.

[0048] like Figure 12 As shown, the decrease in PL intensity indicates a reduction in passivation characteristics caused by aluminum diffusion. Particularly in the N-type doped polysilicon region, even with a relatively thick semiconductor layer, the PL intensity decreases sharply. This is because aluminum diffusion and doping through N-type polysilicon weakens the N-type doping field passivation effect. Figure 10 As can be seen, when the semiconductor layer thickness is reduced to a certain range, the PL intensity of P-type and N-type doped polysilicon exhibits a bend but remains unchanged.

[0049] Therefore, this invention proposes an optimal range for semiconductor layer thickness: 40-70 nm for the semiconductor layer above the N-type doped region and 20-70 nm for the semiconductor layer above the P-type doped region. That is, within this optimal range, the polycrystalline silicon in the N-type doped region will not be diffused and doped with Al, and its passivation quality will not be reduced by P-type doping, thus exhibiting high PL strength, good passivation characteristics, and lower contact resistance with the Al metal electrode. In the thinner P-type doped region, Al diffuses into the polycrystalline silicon but not into the tunneling oxide layer, and even if the P-type doped region is doped with Al, its passivation quality will not be reduced, while also exhibiting lower contact resistance with the Al metal electrode. This allows the solar cell of this invention to both use low-cost paste to form the metal electrode and exhibit excellent solar cell performance.

[0050] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A low cost high performance solar cell characterized in that, include: A silicon wafer, a tunneling oxide layer formed on the silicon wafer, and doped polycrystalline silicon, wherein N-type doped regions and P-type doped regions are formed on the doped polycrystalline silicon, and intrinsic polycrystalline silicon is spaced between the N-type doped regions and the P-type doped regions; a semiconductor layer is formed on the doped polycrystalline silicon and the intrinsic polycrystalline silicon, and the material of the semiconductor layer includes one or more layers of TiO2, WO3, MoO3, TeO2 or NiO; an N-type electrode is formed on the semiconductor layer corresponding to the N-type doped region, and a P-type electrode is formed on the semiconductor layer corresponding to the P-type doped region, and the N-type electrode and the P-type electrode are in contact with the semiconductor layer.

2. The low cost high performance solar cell of claim 1, wherein, The thickness of the doped polycrystalline silicon is 20nm~100nm, and the thickness of the semiconductor layer is 10nm~100nm.

3. The low cost high performance solar cell of claim 1, wherein, The semiconductor layer above the P-type doped region has the same or thinner thickness than the semiconductor layer above the N-type doped region.

4. The low cost high performance solar cell of claim 1, wherein, The thickness of the semiconductor layer above the N-type doped region is 40~70nm, and the thickness of the semiconductor layer above the P-type doped region is 20~70nm.

5. A low-cost, high-performance solar cell according to claim 1, characterized in that, A metal alloy is formed between the semiconductor layer and the contact surface of the P-type electrode and / or N-type electrode.

6. A low-cost, high-performance solar cell according to claim 1, characterized in that, The semiconductor layer contains 0-5 wt% dopant, which includes one or more of aluminum (Al), boron (B), vanadium (V), niobium (Nb), nitrogen (N), and oxygen (O).

7. The low cost high performance solar cell as claimed in claim 1, wherein, The P-type electrode and / or the N-type electrode comprises Al, Ag, Cu, or a mixture of any two or three of Al, Ag, Cu.

8. The low cost high performance solar cell of claim 1, wherein, The P-type electrode and / or the N-type electrode are formed from aluminum paste, wherein the silicon content in the aluminum paste is 0~20wt%.

9. The low cost high performance solar cell of claim 1, wherein, It also includes a passivation layer formed on the semiconductor layer.

10. The low cost high performance solar cell of claim 1, wherein, It also includes a passivation layer formed on the doped polysilicon and intrinsic polysilicon, a semiconductor layer formed on the passivation layer, the semiconductor layer passing through the passivation layer and contacting the doped polysilicon, and the material of the passivation layer being SiN. x SiO x SiON x Or a combination of one or more layers of Al2O3.

11. The process for the production of low cost high performance solar cells as claimed in any one of claims 1 to 10 wherein, Includes the following steps: S1. Forming a tunneling oxide layer and intrinsic polycrystalline silicon on a silicon wafer; S2. Selectively implant boron and phosphorus into the intrinsic polysilicon to form doped polysilicon, and alternately form N-type doped regions and P-type doped regions on the doped polysilicon, with intrinsic polysilicon left between the N-type doped regions and the P-type doped regions as isolation. S3. Form a semiconductor layer on doped polysilicon; S4. An N-type electrode and a P-type electrode are formed on the semiconductor layer, such that the N-type electrode is in contact with the semiconductor layer above the N-type doped region, and the P-type electrode is in contact with the semiconductor layer above the P-type doped region.

12. The process for manufacturing a low cost high performance solar cell as claimed in claim 11 wherein, In S2, boron and phosphorus are selectively implanted by ion implantation, printing and heat treatment of doping paste, or by using a mask and doping diffusion furnace. In S3, the semiconductor layer above the P-type doped region is subjected to laser ablation, or a metal alloy is formed on the semiconductor layer above the P-type doped region to make the semiconductor layer above the P-type doped region thinner than the semiconductor layer above the N-type doped region. In step S4, N-type electrodes and P-type electrodes are formed by simultaneously printing metal paste on the semiconductor layer and sintering, or by separately printing metal paste on the semiconductor layer and sintering.

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