A tbc cell and method of making the same

Abstract

This invention relates to the field of solar cell technology and discloses a TBC cell and its fabrication method, comprising: fabricating a tunneling layer and an intrinsic amorphous silicon layer on the back side of a silicon wafer; locally fabricating a first barrier layer on the back side of the intrinsic amorphous silicon layer; converting the intrinsic amorphous silicon layer in the non-first barrier layer region into a boron-doped polycrystalline silicon layer by boron diffusion; removing the first barrier layer locally by laser patterning to expose the intrinsic amorphous silicon layer in the laser region; wet etching to form a gap region and expose the boron-doped polycrystalline silicon layer and the intrinsic amorphous silicon layer in the non-laser region; locally fabricating a second barrier layer on the back side of the gap region silicon wafer and the boron-doped polycrystalline silicon layer; converting the exposed intrinsic amorphous silicon layer into a phosphorus-doped polycrystalline silicon layer by phosphorus diffusion; removing the second barrier layer and texturing; fabricating a passivation antireflection film on the front and back sides, and metallizing it to form a first and a second metal electrode. This method can easily form a gap region, and the boron and phosphorus-doped polycrystalline silicon layers have no height difference. It has fewer processes, less damage, and lower cost, and can improve cell efficiency.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically to a TBC cell and its preparation method. Background Technology

[0002] Topcon (tunneling oxide passivated contact) solar cells, due to their unique structure, enable selective carrier transport, thus improving Voc (open-circuit voltage) and FF (fill factor), and consequently enhancing photoelectric conversion efficiency. Back-contact (BC) solar cells have their positive and negative electrodes integrated in an interdigitated pattern on the back side. These cells have no metal electrodes on the front, preventing light loss due to electrode shading. Therefore, BC cells exhibit higher short-circuit current, effectively improving photoelectric conversion efficiency. TBC (transient-contact BC) solar cells combine TOPCon and BC technologies, simultaneously fabricating alternating P+ polycrystalline silicon layers (P+polysi layers) and N+ polycrystalline silicon layers (N+polysi layers) on the back side, significantly improving photoelectric conversion efficiency.

[0003] The fabrication process of TBC cells typically requires two to three steps using advanced laser equipment such as femtosecond lasers (e.g., laser patterning and grooving). For example, a method for fabricating a TBC solar cell, as disclosed in CN118782688B, requires three laser processes, necessitating multiple femtosecond laser devices. These devices are extremely expensive, and since most of these laser processes use ultraviolet lasers, the cost of which is even higher, this undoubtedly increases the production cost of TBC cells. Furthermore, these three laser processes can cause significant damage to the cells, hindering further improvements in their electrical performance and photoelectric conversion efficiency.

[0004] Moreover, as shown in publication numbers CN118782672B and CN119653870B, there is a height difference between the P+ polycrystalline silicon layer and the N+ polycrystalline silicon layer on the back of the TBC cell produced therein. This increases the difficulty of screen printing the metal paste, and makes it easy for short grid phenomena to occur in the subsequent metallization process of the P region and N region, resulting in poor contact, high contact resistivity of the electrode (or grid line), and problems such as poor welding on the back of the photovoltaic module.

[0005] Furthermore, as shown in CN116845140A and CN119653870B, in the fabrication process of TBC cells, the first laser treatment in most cases is to locally treat the BSG layer on the back of the P+ polysilicon layer to expose the local P+ polysilicon layer, followed by cleaning and etching of the local P+ polysi layer. However, etching the highly doped P+ polysi layer is extremely difficult, making it hard to completely remove the local P+ polysi layer. This also hinders further improvement in the electrical performance and photoelectric conversion efficiency of TBC cells. Therefore, there is an urgent need to improve the existing TBC cell fabrication methods. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a TBC battery and its preparation method.

[0007] Based on this, the present invention discloses a method for preparing a TBC battery, comprising the following preparation steps:

[0008] Step 1: Sequentially prepare a tunneling layer and an intrinsic amorphous silicon layer on the back side of the silicon wafer;

[0009] Step 2: Locally fabricate a first barrier layer on the back side of the intrinsic amorphous silicon layer;

[0010] Step 3: Boron diffusion transforms the intrinsic amorphous silicon layer in the non-first barrier layer region into a boron-doped polycrystalline silicon layer, and a borosilicate glass layer is formed on the back side of the boron-doped polycrystalline silicon layer.

[0011] Step 4: Laser patterning removes one end of the first barrier layer near the boron-doped polysilicon layer to expose the intrinsic amorphous silicon layer in the laser region; wet etching is used to remove the intrinsic amorphous silicon layer and tunneling layer in the laser region to form a gap region (isolation region) to expose the silicon wafer, and the borosilicate glass layer is removed to expose the boron-doped polysilicon layer, and the first barrier layer in the non-laser region is removed to expose the intrinsic amorphous silicon layer.

[0012] Step 5: Locally fabricate a second barrier layer on the back side of the silicon wafer and boron-doped polycrystalline silicon layer in the gap region;

[0013] Step 6: Phosphorus diffusion, which transforms the intrinsic amorphous silicon layer in the non-laser region into a phosphorus-doped polycrystalline silicon layer;

[0014] Step 7: Remove the second barrier layer and perform a flocking process;

[0015] Step 8: Prepare passivation antireflection films on the front and back sides of the texturized silicon wafer, and then form the first metal electrode of the ohmic contact boron-doped polycrystalline silicon layer and the second metal electrode of the ohmic contact phosphorus-doped polycrystalline silicon layer by metallization.

[0016] Preferably, before step 1, the process further includes: double-sided polishing of the silicon wafer to remove impurities from the surface of the silicon wafer and forming a polished surface on the back side of the silicon wafer.

[0017] Preferably, in step 1, the tunneling layer is a tunneling silicon oxide layer with a thickness of 2-4 nm; the intrinsic amorphous silicon layer has a thickness of 200-380 nm.

[0018] Preferably, step 2, preparing the first barrier layer, includes: screen printing a first barrier layer paste locally on the back side of the intrinsic amorphous silicon layer, and then sintering to prepare the first barrier layer;

[0019] Step 5, preparing the second barrier layer, includes: screen printing a second barrier layer paste on the back side of the Gap region silicon wafer and the boron-doped polycrystalline silicon layer, and then sintering to prepare the second barrier layer.

[0020] More preferably, in steps 2 and 5, the opening of the screen printing stencil is 400-620μm, and silica paste is printed locally. After printing, it is sintered at a high temperature of 860-900℃ for 3-7 minutes. The first barrier layer and the second barrier layer are both silica barrier layers, and the width of the first barrier layer and the second barrier layer after sintering is 450-640μm, the thickness is 0.2-2μm, and the refractive index is 1.6-1.8.

[0021] Preferably, in step 3, the thickness of the borosilicate glass layer is 45-65 nm, and the doping concentration of the boron-doped polycrystalline silicon is 8e19~2e20 cm⁻¹. -3 .

[0022] Preferably, in step 4, the laser is a green laser with a wavelength of 500-550nm, a power of 60-120W, a scanning rate of 5000-50000mm / s, and a frequency of 250-1000KHz.

[0023] Alternatively, the laser is an infrared laser with a wavelength of 700-1200nm, a power of 70-120W, a scanning rate of 5000-20000mm / s, and a frequency of 250-1000KHz.

[0024] The width of the first barrier layer removed by the laser is 70-120 μm, and the width of the remaining first barrier layer is 380-500 μm.

[0025] More preferably, in step 4, the wet etching includes: first, alkaline etching to remove the intrinsic amorphous silicon layer in the laser region, and then acid etching to remove the tunneling layer in the laser region, the borosilicate glass layer in the non-first barrier layer region, and the first barrier layer in the non-laser region.

[0026] Preferably, in step 6, a 35-55 nm thick phosphorus-silicon glass layer is also formed on the back side of the phosphorus-doped polycrystalline silicon layer; the doping concentration of the phosphorus-doped polycrystalline silicon layer is 1e20~4e20cm. -3 .

[0027] More preferably, step 7 specifically includes: first, acid wet etching to remove the phosphorus silicon glass layer to expose the phosphorus-doped polysilicon layer, and remove the second barrier layer to expose the back side of the Gap region silicon wafer and the boron-doped polysilicon layer; then, alkaline texturing to form a textured surface on the front side of the silicon wafer and the back side of the Gap region silicon wafer.

[0028] The TBC battery fabrication method of the present invention uses two screen printing processes to create a relatively wide barrier layer. First, a relatively wide first barrier layer is locally screen-printed on the back side of the i-polysi layer (intrinsic amorphous silicon layer) using a screen printing plate, so that subsequent boron diffusion can be used to fabricate the P+polysi layer (boron-doped polycrystalline silicon layer). Then, the first barrier layer is locally removed using laser patterning, and the i-polysi layer and tunneling layer in the laser-treated area are removed by wet etching to fabricate the gap region. Second, a relatively wide second barrier layer is locally printed on the back side of the gap region silicon wafer and the P+polysi layer using a screen printing plate, followed by phosphorus diffusion to fabricate the N+polysi layer (phosphorus-doped polycrystalline silicon layer). Therefore, by using two screen-printed barrier layers, combined with one laser patterning + wet etching; (1) the laser treatment of the first barrier layer exposes the i-polysi layer in the laser region, and the difficulty of wet etching of the i-polysi layer (compared to wet etching of the high doping concentration P+polysi layer) is greatly reduced, and the gap region can be easily formed; (2) the first barrier layer can protect the i-polysi layer on its front side from boron doping, and at the same time realize the preparation of the high concentration P+polysi layer in the non-first barrier layer region; while the second barrier layer can protect the P+polysi layer on its front side from phosphorus doping, and at the same time realize the preparation of the high concentration N+polysi layer in the non-second barrier layer region (corresponding to the non-laser region); (3) it can also make the N+polysi layer and P+polysi layer doped in different regions of the same i-polysi layer to ensure that there is no height difference between the N+polysi layer and the P+polysi layer, which is beneficial to subsequent metallization.

[0029] The present invention also discloses a TBC battery, which is prepared by the TBC battery preparation method described above in the present invention.

[0030] Compared with the prior art, the present invention has at least the following beneficial effects:

[0031] The TBC battery fabrication method of the present invention (1) reduces the laser process, which can reduce equipment investment costs and reduce laser damage to the battery, and can form a high-doped P+polysi layer and N+polysi layer on the back side; (2) it can also solve the problem of difficult etching of the high-doped P+ polysilicon layer when wet cleaning and etching of the high-doped P+ polysilicon layer after the first laser as shown in CN119653870B (the present invention performs laser patterning on the first barrier layer, and combines wet etching to remove the i-polysi layer and tunneling layer, which can easily form) Gap region; Compared with wet etching of highly doped P+ polysilicon layers, the difficulty of wet etching of i-polysi layers in this invention is greatly reduced, thus easily forming gap regions); (3) At the same time, N+ polysi layers and P+ polysi layers can be doped and prepared in different regions of the same i-polysi layer, completely avoiding the height difference problem between P+ polysi layers and N+ polysi layers, reducing the difficulty of subsequent metal paste screen printing, reducing the difficulty of metallization, and preventing phenomena such as short grids, poor electrode or grid line contact, and poor welding due to height differences. Therefore, the preparation method of TBC battery in this invention can reduce the production cost of the battery and further improve the FF, Jsc (short-circuit current density), Voc and photoelectric conversion efficiency of the battery.

[0032] Furthermore, the TBC battery preparation method of the present invention, by controlling the laser patterning process, controls the thickness of the barrier layer (to prevent the barrier layer from being too thick, which would lead to uneven diffusion and doping, thereby reducing the passivation effect of the battery; at the same time, to prevent the barrier layer from being too thin, which would weaken the barrier ability and affect the contact resistance and passivation effect), and controls the sintering temperature and sintering time of the barrier layer slurry to control the refractive index and compactness of the sintered barrier layer (this ensures that the barrier layer is not too thick, but still has a strong barrier ability and plays a good barrier role), can further improve the FF, Jsc, Voc and photoelectric conversion efficiency of the battery. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after treatment with S1.

[0034] Figure 2 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after S2 treatment.

[0035] Figure 3 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after S3 treatment.

[0036] Figure 4This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after S4 treatment.

[0037] Figure 5 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after processing with S5.

[0038] Figure 6 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after processing with S6.

[0039] Figure 7 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after processing with S7.

[0040] Figure 8 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after S8 treatment.

[0041] Figure 9 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after processing with S9.

[0042] Figure 10 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after processing in S10.

[0043] Figure 11 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared according to the present invention after processing with S11.

[0044] Reference numerals: 1. Silicon wafer; 2. Tunneling SiOx layer; 3. i-polysi layer; 41. First barrier layer; 42. Second barrier layer; 5. P+polysi layer; 6. BSG layer; 7. N+polysi layer; 8. PSG layer; 9. AlOx film; 10. SiNx film; 11. First metal electrode; 12. Second metal electrode. Detailed Implementation

[0045] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] A method for preparing a TBC battery according to the present invention, see [link to relevant documentation]. Figure 1-11 The preparation steps include the following:

[0047] S1: As Figure 1 As shown, the original silicon wafer 1 is polished on both sides to remove impurities from the surface of the original silicon wafer 1 and to form a polished surface on the back side of the original silicon wafer 1.

[0048] In step S1, the resistivity of the original silicon wafer 1 is 4-10 Ω·cm and the thickness is 130-145 μm.

[0049] In step S1, the double-sided polishing process is as follows: the original silicon wafer 1 is placed in an alkaline polishing tank containing KOH solution and polished on both sides at 75-90℃ for 1-5 minutes.

[0050] S2: As Figure 2 As shown, a tunneling SiOx layer 2 (tunneling silicon oxide layer) and an i-polysi layer 3 (intrinsic amorphous silicon layer) are sequentially deposited on the back side of silicon wafer 1.

[0051] In step S2, the deposition process conditions for tunneling SiOx layer 2 are as follows: the gas flow rate of O2 is 14000-28000 sccm, the reaction temperature is 510-690℃, the reaction time is 890-1800s, and the deposition thickness of tunneling SiOx layer 2 is 2-4nm.

[0052] In step S2, the deposition process conditions for the i-polysi layer 3 are as follows: the i-polysi layer 3 is deposited on the tunneled SiOx layer 2, the gas flow rate of SiH4 is 500-1400 sccm, the reaction temperature is 610-745℃, the reaction time is 1.5-3.5h, the gas pressure is 160-430mTorr, and the deposition thickness of the i-polysi layer 3 is 200-380nm.

[0053] S3: As Figure 3 As shown, a first barrier layer paste (such as SiO2 paste, i.e., silicon oxide paste) is locally printed on the back side of the i-polysi layer 3 using screen printing, and the first barrier layer 41 (such as SiO2 barrier layer, i.e. silicon oxide barrier layer) is prepared by sintering in a high-temperature furnace.

[0054] In step S3, the preparation process conditions of the first barrier layer 41 are as follows: based on P / N = 1.5-1.8 (P / N is the linewidth ratio of the P region to the N region on the back side), the opening of the screen printing plate is 450-600μm, SiO2 paste is printed locally, and after printing, it is passed through a high-temperature furnace with a sintering temperature of 860-900℃ and a sintering time of 3-7min. The width of the SiO2 barrier layer is 460-620μm, the thickness is 0.2-2μm, and the refractive index is 1.6-1.8.

[0055] In step S3, a first barrier layer 41 is formed on the i-polysi layer 3. This not only protects the i-polysi layer 3 on the front side from subsequent boron diffusion doping, but also facilitates the formation of gap regions and the fabrication of the N+ polysi layer 7 by subsequent wet etching. Simultaneously, subsequent boron diffusion can transform the i-polysi layer 3 in areas outside the first barrier layer 41 into a highly doped p+ polysi layer 5. Therefore, the localized fabrication of the first barrier layer 41 on the back side not only protects it from subsequent boron diffusion doping, but also facilitates the formation of gap regions and the fabrication of the N+ polysi layer 7 by subsequent laser patterning combined with wet etching.

[0056] S4: As Figure 4 As shown, boron diffusion is performed on the back side of silicon wafer 1, transforming the i-polysi layer 3 in the non-first barrier layer 41 region into a P+polysi layer 5 (boron-doped polysilicon layer), and a BSG layer 6 (borosilicate glass layer) is generated on the back side of the P+polysi layer 5; while the i-polysi layer 3 in the first barrier layer 41 region can prevent boron atoms from entering the i-polysi layer 3 in the first barrier layer 41 region due to the barrier of the first barrier layer 41 on the boron doping source (such as boron atoms), and the first barrier layer 41 contains boron atoms.

[0057] In step S4, boron diffusion includes a deposition stage, a propagation stage, and an oxidation stage performed sequentially. The process conditions for each stage are as follows:

[0058] During the deposition stage, the deposition temperature was 810-900℃, the deposition time was 1200-3200s, the BCl3 gas flow rate was 64-440sccm, and the O2 gas flow rate was 1000-3400sccm. During the N2 propagation stage, the propagation temperature was 910-930℃, the propagation time was 1200-2100s, and the N2 gas flow rate was 3200-6300sccm. During the O2 oxidation stage, the oxidation temperature was 945-1000℃, the oxidation time was 1200-3300s, and the O2 gas flow rate was 14000-35000sccm. The thickness of BSG layer 6 was 45-65nm.

[0059] S5: As Figure 5As shown, a green laser is used to pattern the left-end local area of ​​the first barrier layer 41 (i.e., the local area near the P+polysi layer 5) to remove the first barrier layer 41 in the left-end local area, exposing the left-end local area of ​​the undoped i-polysi layer 3 (corresponding to the laser area). The i-polysi layer 3 in the laser area is etched away by an alkaline wet etching bath, and then the tunneling SiOx layer 2 in the laser area is removed by an acidic wet etching bath to expose the back surface of the silicon wafer 1 in the laser area to form a gap area. The BSG layer 6 in the area without the first barrier layer 41 is removed to expose the P+polysi layer 5, and the first barrier layer 41 in the non-laser area is removed to expose the i-polysi layer 3 in the non-laser area (corresponding to the N area).

[0060] In step S5, the process conditions for laser patterning are as follows: A green laser or an infrared laser can be used, as long as the first blocking layer 41 in the left-end local area can be removed to facilitate alkaline wet etching. A cheaper infrared laser can be used. When using an infrared laser, the laser wavelength is 700-1200nm, the laser power is 70-120W, the laser scanning rate is 5000-20000mm / s, the laser frequency is 250-1000KHz, and the laser line spacing is 5-15um. When using a green laser, the laser wavelength is 500-550nm, the laser power is 60-120W, the laser scanning rate is 5000-50000mm / s, and the laser frequency is 250-1000KHz. The first barrier layer 41 with a local width of 70-120μm on the left end is removed, exposing the i-polysi layer 3 in the laser region. (Compared to the highly doped P+polysi layer 5, it is very easy to etch the exposed i-polysi layer 3 using an alkaline wet process, and the problem of high etching difficulty and high etching cost of the highly doped P+polysi layer 5 will not occur.) The width of the remaining first barrier layer 41 is 380-500μm.

[0061] In step S5, the process conditions for alkaline wet etching are as follows: the etching temperature of the alkaline solution is 75-90℃, the etching time is 150-200s, the etching depth is 1.2-2.3μm, and a gap region is formed.

[0062] In step S5, the process conditions for acidic wet scrubbing are as follows: the volume ratio of HF solution to nitric acid solution is 1:3-1:5, the concentration of HF solution is 50-75wt%, the concentration of nitric acid solution is 55-65wt%, and the removal time is 100-140s.

[0063] S6: As Figure 6As shown, a second barrier layer paste (such as SiO2 paste) is locally printed on the back surface of the silicon wafer 1 in the Gap area and the P+polysi layer 5 using screen printing, and the second barrier layer 42 (such as SiO2 barrier layer) is prepared by sintering in a high-temperature furnace.

[0064] In step S6, the second barrier layer 42 has a thickness of 0.9 μm and a width of 510 μm.

[0065] In step S6, the preparation process conditions of the second barrier layer 42 are as follows: based on P / N = 1.5-1.8, the opening of the screen printing plate is 480-620μm, SiO2 paste is printed locally, and after printing, it is passed through a high-temperature furnace with a sintering temperature of 860-900℃ and a sintering time of 3-7min. The width of the SiO2 barrier layer is 500-640μm, the thickness is 0.2-2μm, and the refractive index is 1.6-1.8.

[0066] In step S6, a second barrier layer 42 is also formed on the side of the Gap region and the P+polysi layer 5 to prevent subsequent phosphorus diffusion into the silicon wafer 1 and the P+polysi layer 5, thereby improving battery performance.

[0067] S7: As Figure 7 As shown, phosphorus diffusion is performed on the back side of silicon wafer 1, transforming the i-polysi layer 3 in the non-laser region into an N+polysi layer 7 (phosphorus-doped polycrystalline silicon layer), and a PSG layer 8 (phosphosilicate glass layer) is generated on the back side of the N+polysi layer 7; while the P+polysi layer 5 in the second barrier layer 42 region and the back surface of the silicon wafer 1 in the gap region are protected from phosphorus doping sources (such as phosphorus atoms) by the second barrier layer 42, preventing phosphorus atoms from entering the P+polysi layer 5 in the second barrier layer 42 region and the silicon wafer 1 in the gap region, and the second barrier layer 42 contains phosphorus atoms.

[0068] In step S7, phosphorus diffusion includes a deposition stage, a diffusion stage, and an oxidation stage performed sequentially. The process conditions for each stage are as follows: N2 gas flow rate is 7-30 L / min, allowing the liquid dopant source POCl3 to enter the quartz tube, followed by the introduction of O2 gas flow rate of 0.5-3.5 L / min, deposition temperature is 750-810℃, and deposition time is 1000-3000 s; in the diffusion stage, a sufficient amount of N2 gas flow rate of 8-30 L / min and O2 gas flow rate of 0.5-3.5 L / min are introduced, diffusion temperature is 820-920℃, and diffusion time is 500-2000 s; in the oxidation stage, N2 gas flow rate is 8-30 L / min, followed by the introduction of O2 gas flow rate of 0.2-3 L / min, oxidation temperature is 830-880℃, and oxidation time is 600-2000 s; the thickness of PSG layer 8 is 35-55 nm.

[0069] S8: As Figure 8 As shown, the silicon wafer 1 after step S7 is placed in an acidic wet process bath to remove the PSG layer 8 on the back side to expose the N+polysi layer 7, and to remove the phosphorus-containing second barrier layer 42 to expose the P+polysi layer 5 and the back surface of the silicon wafer 1 in the gap area; then it is placed in an alkaline wet process bath to texturize, so as to prepare a pyramid-shaped textured surface on both the back gap area and the front side of the silicon wafer 1.

[0070] In step S8, the process conditions for acidic wet scrubbing are as follows: the volume ratio of HF solution to nitric acid solution is 1:3-1:5, the concentration of HF solution is 50-75wt%, the concentration of nitric acid solution is 55-65wt%, and the removal time is 100-140s.

[0071] In step S8, the process conditions for alkaline wet texturing are as follows: the concentration of KOH solution is 1.2-2.5wt%, the temperature is 75-90℃, and the texturing time is 150-600s, forming a pyramid-shaped textured surface on the back gap area and the front side of silicon wafer 1.

[0072] In this invention, the high doping concentration of the P+polysi layer 5 and the N+polysi layer 7, combined with the thick polysi layer, can effectively resist alkaline wet etching. At the same time, the thickness of the polysi layer can also be controlled by alkaline wet texturing.

[0073] S9: such as Figure 9 As shown, AlOx film 9 (alumina film) is deposited on both the front and back sides of silicon wafer 1 after the process in step S8 as a passivation film.

[0074] In step S9, the AlOx film 9 deposition process conditions are as follows: using ALD (atomic layer deposition), AlOx film 9 with a thickness of 5-12nm is deposited on both the back side of silicon wafer 1 (i.e., the back side of the Gap area, P+polysi layer 5 and N+polysi layer 7) and the front side of silicon wafer 1 by reacting Al(CH3)3 with water vapor. The process temperature is 200-380℃ and the deposition time is 300-1000s.

[0075] S10: SiNx film 10 (silicon nitride film) is deposited on both the front and back sides of AlOx film 9 as passivation and antireflection films.

[0076] In step S10, as Figure 10As shown, the deposition process conditions for SiNx film 10 are as follows: PECVD (plasma-enhanced chemical vapor deposition) is used to prepare front-side SiNx film 10 and back-side SiNx film 10 on the front side of front-side AlOx film 9 and the back side of back-side AlOx film 9, respectively, with a thickness of 65-90 nm for both front-side and back-side SiNx film 10; during the preparation process, the gases inside the tube are SiH4 and NH3, the working pressure is 1200-2200 mTorr, the power is 10000-15000 W, the temperature is 330-500℃, the gas flow rate of SiH4 is 800-12000 sccm, the flow rate of NH3 is 7000-12000 sccm, the silicon-nitrogen ratio is 1:2-1:7, and the deposition time is 10-25 min.

[0077] S11: As Figure 11 As shown, the back side of the silicon wafer 1 after step S10 is metallized to obtain the first metal electrode 11 of the ohmic contact P+polysi layer 5 and the second metal electrode 12 of the ohmic contact N+polysi layer 7.

[0078] In step S11, the metallization process conditions are as follows: screen printing of metal paste (such as Ag paste) with an opening of 10-60 μm; after printing, sintering at 700-900℃ to form the first metal electrode 11 and the second metal electrode 12; after photoinjection, a TBC battery is obtained.

[0079] Specific embodiments and comparative examples are given below.

[0080] Example 1

[0081] This embodiment describes a method for preparing a TBC battery, see [link to relevant documentation]. Figure 1-11 The preparation steps include the following:

[0082] S1: As Figure 1 As shown, the original silicon wafer 1 is polished on both sides to remove impurities from the surface of the original silicon wafer 1 and to form a polished surface on the back side of the original silicon wafer 1.

[0083] In step S1, the original silicon wafer 1 is an N-type silicon wafer with a resistivity of 4Ω·cm, a thickness of 145μm, and dimensions of 182.2mm*183.75mm.

[0084] In step S1, the process conditions for double-sided polishing include: the original silicon wafer 1 is placed in an alkaline polishing bath containing KOH solution, double-sided polishing is performed at 75°C for 5 minutes, the polishing thickness is 3μm, and the thinning amount is 0.34g.

[0085] S2: As Figure 2 As shown, a tunneling SiOx layer 2 (tunneling silicon oxide layer) and an i-polysi layer 3 (intrinsic amorphous silicon layer) are sequentially deposited on the back side of silicon wafer 1.

[0086] In step S2, the deposition process conditions for tunneling SiOx layer 2 are as follows: the gas flow rate of O2 is 25000 sccm, the reaction temperature is 610℃, the reaction time is 1200s, and the deposition thickness of tunneling SiOx layer 2 is 3.5nm.

[0087] In step S2, the deposition process conditions for the i-polysi layer 3 are as follows: the i-polysi layer 3 is deposited on the tunneled SiOx layer 2, the gas flow rate of SiH4 is 880 sccm, the reaction temperature is 738℃, the reaction time is 2.4h, the gas pressure is 320mTorr, and the deposition thickness of the i-polysi layer 3 is 280nm.

[0088] S3: As Figure 3 As shown, a first barrier layer paste (such as SiO2 paste, i.e., silicon oxide paste) is locally printed on the back side of the i-polysi layer 3 using screen printing, and the first barrier layer 41 (such as SiO2 barrier layer, i.e. silicon oxide barrier layer) is prepared by sintering in a high-temperature furnace.

[0089] In step S3, the preparation process conditions of the first barrier layer 41 are as follows: based on P / N = 1.6, the opening of the screen printing plate is 500 μm, SiO2 paste is printed locally, and after printing, it is passed through a high-temperature furnace with a sintering temperature of 890℃ and a sintering time of 4.5 min. The width of the SiO2 barrier layer is 510 μm, the thickness is 0.9 μm, and the refractive index is 1.7.

[0090] S4: As Figure 4 As shown, boron diffusion is performed on the back side of silicon wafer 1, transforming the i-polysi layer 3 in the non-first barrier layer 41 region into a P+polysi layer 5 (boron-doped polysilicon layer), and a BSG layer 6 (borosilicate glass layer) is generated on the back side of the P+polysi layer 5; while the i-polysi layer 3 in the first barrier layer 41 region can prevent boron atoms from entering the i-polysi layer 3 in the first barrier layer 41 region due to the barrier of the first barrier layer 41 on the boron doping source (such as boron atoms), and the first barrier layer 41 contains boron atoms.

[0091] In step S4, boron diffusion includes a deposition stage, a propagation stage, and an oxidation stage performed sequentially. The process conditions for each stage are as follows:

[0092] During the deposition stage, the deposition temperature was 855℃, the deposition time was 2500s, the BCl3 gas flow rate was 350sccm, and the O2 gas flow rate was 3200sccm. During the N2 propagation stage, the propagation temperature was 928℃, the propagation time was 1800s, and the N2 gas flow rate was 4800sccm. During the O2 oxidation stage, the oxidation temperature was 956℃, the oxidation time was 2800s, and the O2 gas flow rate was 28000sccm. The boron doping concentration in the P+polysi layer 5 was 1.2e20cm³. -3 The thickness of BSG layer 6 is 55nm.

[0093] S5: As Figure 5 As shown, a green laser is used to pattern the left-end local area of ​​the first barrier layer 41 (i.e., the local area near the P+polysi layer 5) to remove the first barrier layer 41 in the left-end local area, exposing the left-end local area of ​​the undoped i-polysi layer 3 (corresponding to the laser area). The i-polysi layer 3 in the laser area is etched away by an alkaline wet etching bath, and then the tunneling SiOx layer 2 in the laser area is removed by an acidic wet etching bath to expose the back surface of the silicon wafer 1 in the laser area to form a gap area. The BSG layer 6 in the area without the first barrier layer 41 is removed to expose the P+polysi layer 5, and the first barrier layer 41 in the non-laser area is removed to expose the i-polysi layer 3 in the non-laser area (corresponding to the N area).

[0094] In step S5, the laser patterning process conditions are as follows: laser wavelength is 515nm, laser power is 90W, laser scanning rate is 34500mm / s, laser frequency is 250KHz, laser spot size is 50μm, the first blocking layer 41 with a local width of 100μm at the left end is removed to expose the i-polysi layer 3 in the laser region, and the remaining width of the first blocking layer 41 is 410μm.

[0095] In step S5, the process conditions for alkaline wet etching are as follows: the concentration of KOH solution is 3wt%, the etching temperature is 75℃, the etching time is 180s, the etching depth is 1.8μm, and the width of the gap area is 100μm.

[0096] In step S5, the process conditions for acidic wet scrubbing are as follows: the volume ratio of HF solution to nitric acid solution is 1:4, the concentration of HF solution is 65wt%, the concentration of nitric acid solution is 58wt%, and the removal time is 130s.

[0097] S6: As Figure 6As shown, a second barrier layer paste (such as SiO2 paste) is locally printed on the back surface of the silicon wafer 1 in the P+polysi layer 5 and the Gap region using screen printing, and the second barrier layer 42 (such as SiO2 barrier layer) is prepared by sintering in a high-temperature furnace.

[0098] In step S6, the thickness of the second barrier layer 42 is 0.9 μm and the width is 510 μm. The fabrication process conditions for the second barrier layer 42 in step S6 are the same as those in step S3, and therefore will not be repeated here.

[0099] S7: As Figure 7 As shown, phosphorus diffusion is performed on the back side of silicon wafer 1, transforming the i-polysi layer 3 in the non-laser region into an N+polysi layer 7 (phosphorus-doped polycrystalline silicon layer), and a PSG layer 8 (phosphosilicate glass layer) is generated on the back side of the N+polysi layer 7; while the P+polysi layer 5 in the second barrier layer 42 region and the back surface of the silicon wafer 1 in the gap region are protected from phosphorus doping sources (such as phosphorus atoms) by the second barrier layer 42, preventing phosphorus atoms from entering the P+polysi layer 5 in the second barrier layer 42 region and the silicon wafer 1 in the gap region, and the second barrier layer 42 contains phosphorus atoms.

[0100] In step S7, phosphorus diffusion includes a deposition stage, a diffusion stage, and an oxidation stage performed sequentially. The process conditions for each stage are as follows: N2 gas flow rate is 25 L / min, allowing the liquid dopant source POCl3 to enter the quartz tube, followed by the introduction of O2 gas at a flow rate of 2 L / min; the deposition temperature is 780℃, and the deposition time is 2600 s; in the diffusion stage, a sufficient amount of N2 is introduced at a flow rate of 10 L / min, and O2 gas flow rate is 1 L / min; the diffusion temperature is 835℃, and the diffusion time is 1700 s; in the oxidation stage, N2 gas flow rate is 10 L / min, followed by the introduction of O2 gas at a flow rate of 1 L / min; the oxidation temperature is 874℃, and the oxidation time is 1300 s; the thickness of the PSG layer 8 is 37 nm, and the phosphorus doping concentration in the N+polysi layer 7 is 2.1e20 cm⁻¹. -3 .

[0101] S8: As Figure 8 As shown, the silicon wafer 1 after step S7 is placed in an acidic wet process bath to remove the PSG layer 8 on the back side to expose the N+polysi layer 7, and to remove the phosphorus-containing second barrier layer 42 to expose the P+polysi layer 5 and the back surface of the silicon wafer 1 in the Gap area; then it is placed in an alkaline wet process bath to texturize, so as to prepare a pyramid-shaped textured surface on both the front side of the silicon wafer 1 and the back side of the silicon wafer 1 in the Gap area.

[0102] In step S8, the process conditions for acidic wet scrubbing are as follows: the volume ratio of HF solution to nitric acid solution is 1:4, the concentration of HF solution is 65wt%, the concentration of nitric acid solution is 58wt%, and the removal time is 130s.

[0103] In step S8, the process conditions for texturing in an alkaline wet bath are as follows: the concentration of KOH solution is 1.5wt%, and the texturing is carried out at 82°C for 220s, forming a pyramid-shaped textured surface on the back side and front side of silicon wafer 1 in the Gap area, with a textured surface height of 1.4μm and a width of 1.8μm.

[0104] S9: such as Figure 9 As shown, AlOx film 9 (alumina film) is deposited on both the front and back sides of silicon wafer 1 after the process in step S8 as a passivation film.

[0105] In step S9, the AlOx film 9 deposition process conditions are as follows: using ALD (atomic layer deposition), Al(CH3)3 reacts with water vapor to deposit an AlOx film 9 with a thickness of 5nm on both the back side of silicon wafer 1 (i.e., the back side of the Gap area, P+polysi layer 5 and N+polysi layer 7) and the front side of silicon wafer 1. The process temperature is 250℃ and the deposition time is 300s.

[0106] S10: SiNx film 10 (silicon nitride film) is deposited on both the front and back sides of AlOx film 9 as passivation and antireflection films.

[0107] In step S10, as Figure 10 As shown, the deposition conditions for the SiNx film 10 are as follows: PECVD (plasma-enhanced chemical vapor deposition) is used to prepare the front and back SiNx films 10 on the front and back sides of the front AlOx film 9, respectively, with a thickness of 75 nm for both films. During the preparation process, the gases inside the tube are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 13000 W, the temperature is 460℃, the gas flow rate of SiH4 is 950 sccm, the flow rate of NH3 is 7800 sccm, the silicon-nitrogen ratio is 1:5, and the deposition time is 10 min. The refractive index of the front SiNx film 10 is 1.7, and the refractive index of the back SiNx film 10 is 1.9.

[0108] S11: As Figure 11 As shown, the back side of the silicon wafer 1 after step S10 is metallized to obtain the first metal electrode 11 of the ohmic contact P+polysi layer 5 and the second metal electrode 12 of the ohmic contact N+polysi layer 7.

[0109] In step S11, the metallization process conditions are as follows: screen printing of metal paste (such as Ag paste) with an opening of 40 μm; after printing, sintering at 860°C to form the first metal electrode 11 and the second metal electrode 12; after photoinjection, a TBC battery is obtained.

[0110] Example 2

[0111] The method for preparing a TBC battery in this embodiment is specifically described in Embodiment 1, but the difference between the two is as follows:

[0112] In step S5 of this embodiment, an infrared laser is used instead. The laser wavelength of the infrared laser is 1150nm, the laser power is 70W, the laser scanning rate is 20000mm / s, the laser frequency is 500KHz, and the laser spot size is 60μm. In addition, the etching time of the alkaline wet process tank is changed to 200s.

[0113] Comparative Example 1

[0114] The preparation method of this comparative example of a TBC battery is specifically referred to in Example 1, the difference being that:

[0115] In this comparative example, the thickness of the first barrier layer in step S3 and the second barrier layer in step S6 are both changed to 0.08 μm.

[0116] Comparative Example 2

[0117] The preparation method of this comparative example of a TBC battery is specifically referred to in Example 1, the difference being that:

[0118] In this comparative example, the thickness of the first barrier layer in step S3 and the second barrier layer in step S6 are both changed to 3.5 μm.

[0119] Comparative Example 3

[0120] The preparation method of this comparative example of a TBC battery is specifically referred to in Example 1, the difference being that:

[0121] In this comparative example, the sintering temperature of the first barrier layer slurry in step S3 and the second barrier layer slurry in step S6 were both changed to 855℃ to alter the density of the barrier layer. The sintering yielded a first barrier layer and a second barrier layer with a refractive index of 1.5.

[0122] Comparative Example 4

[0123] The preparation method of this comparative example of a TBC battery is specifically referred to in Example 1, the difference being that:

[0124] In this comparative example, the sintering time of the first barrier layer slurry in step S3 and the second barrier layer slurry in step S6 were both changed to 2.4 min to change the density of the barrier layer. The first barrier layer and the second barrier layer with a refractive index of 1.5 were obtained by sintering.

[0125] Performance testing

[0126] The performance of the TBC batteries from Examples 1-2 and Comparative Examples 1-4 was tested, and the test results are shown in Table 1 below:

[0127] Table 1

[0128] Example 1 26.55 743.81 42.39 84.21 Example 2 26.32 738.27 42.27 84.33 Comparative Example 1 26.22 737.64 42.37 83.89 Comparative Example 2 26.10 736.54 42.18 84.01 Comparative Example 3 26.27 733.44 42.13 85.02 Comparative Example 4 26.25 732.34 42.03 85.28

[0129] In Table 1, Voc is the open-circuit voltage, Jsc is the short-circuit current density, and FF is the fill factor.

[0130] As shown in Table 1:

[0131] (1) The laser and the corresponding alkaline wet etching time in step S5 of Examples 1 and 2 are different, resulting in a 0.23% difference in photoelectric conversion efficiency between the two. This is mainly because the green laser has a smaller thermal impact on the P+polysi layer compared to the infrared laser, and the heavy doping effect is not obvious; while the infrared laser has a larger thermal impact, affecting the doping concentration of the P+polysi layer and the passivation effect of the battery. Secondly, the laser heat affects the crystallization degree of the i-polysi layer. The infrared laser will accelerate the crystallization state of the i-polysi layer, thus affecting the subsequent phosphorus doping of the i-polysi layer.

[0132] Therefore, step S5 preferably uses a green laser to pattern the left end of the first barrier layer, which can further improve the photoelectric conversion efficiency of the battery and shorten the alkaline wet etching time.

[0133] (2) Comparative Example 2 increased the thickness of the barrier layer (such as the first barrier layer and the second barrier layer). Although the barrier layer effectively blocked boron doping and phosphorus doping, a thicker barrier layer had a greater impact on the airflow between wafers (referring to adjacent silicon wafers during the diffusion process) during boron and phosphorus diffusion, resulting in uneven diffusion within the wafer. This further led to uneven doping concentration of the P+polysi layer and N+polysi layer, thereby reducing the passivation effect and other performance of the battery. Consequently, the FF, Jsc, Voc and photoelectric conversion efficiency of the battery in Comparative Example 2 were significantly lower than those in Example 1.

[0134] (3) Comparative Example 1 reduced the thickness of the barrier layers (such as the first barrier layer and the second barrier layer). A barrier layer that is too thin has significantly reduced blocking power, causing boron and phosphorus to diffuse into the i-polysi layer, P+polysi layer, and gap region silicon wafer blocked by the barrier layers. This neutralizes some electrons or holes, adversely affecting the contact resistance and passivation effect of the battery. Therefore, the FF, Voc, and photoelectric conversion efficiency of the battery in Comparative Example 1 are significantly lower than those in Example 1.

[0135] (4) Comparative Examples 3 and 4 obtained low-refractive-index barrier layers (such as the first barrier layer and the second barrier layer) by adjusting the sintering temperature and sintering time of the barrier layer slurry, respectively. The lower the refractive index, the worse the material density, and the worse the barrier effect on the dopant source. This causes boron and phosphorus to diffuse into the i-polysi layer, P+polysi layer, and Gap region silicon wafer blocked by the barrier layer, thereby neutralizing some electrons or holes and adversely affecting the contact resistance and passivation effect of the battery. Therefore, the Jsc, Voc, and photoelectric conversion efficiency of the batteries in Comparative Examples 3 and 4 are significantly lower than those in Example 1.

[0136] In summary, the TBC battery preparation method of the present invention can further improve the FF, Jsc, Voc and photoelectric conversion efficiency of the battery by controlling the laser patterning process (as shown in Examples 1 and 2), controlling the thickness of the barrier layer (as shown in Comparative Examples 1 and 2), and controlling the sintering temperature and sintering time of the barrier layer slurry.

[0137] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0138] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for preparing a TBC battery, characterized in that, The preparation steps include the following: Step 1: Sequentially prepare a tunneling layer and an intrinsic amorphous silicon layer on the back side of the silicon wafer; Step 2: Locally fabricate a first barrier layer on the back side of the intrinsic amorphous silicon layer; Step 3: Boron diffusion transforms the intrinsic amorphous silicon layer in the non-first barrier layer region into a boron-doped polycrystalline silicon layer, and a borosilicate glass layer is formed on the back side of the boron-doped polycrystalline silicon layer. Step 4: Laser patterning removes one end of the first barrier layer near the boron-doped polysilicon layer to expose the intrinsic amorphous silicon layer in the laser region; wet etching is used to remove the intrinsic amorphous silicon layer and tunneling layer in the laser region to form a gap region exposing the silicon wafer, and the borosilicate glass layer is removed to expose the boron-doped polysilicon layer, and the first barrier layer in the non-laser region is removed to expose the intrinsic amorphous silicon layer. Step 5: Locally fabricate a second barrier layer on the back side of the silicon wafer and boron-doped polycrystalline silicon layer in the gap region; Step 6: Phosphorus diffusion, which transforms the intrinsic amorphous silicon layer in the non-laser region into a phosphorus-doped polycrystalline silicon layer; Step 7: Remove the second barrier layer and perform a flocking process; Step 8: Prepare passivation antireflection films on the front and back sides of the texturized silicon wafer, and then form the first metal electrode of the ohmic contact boron-doped polycrystalline silicon layer and the second metal electrode of the ohmic contact phosphorus-doped polycrystalline silicon layer by metallization.

2. The method for preparing a TBC battery according to claim 1, characterized in that, Before step 1, the process also includes: double-sided polishing of the silicon wafer to remove impurities from the surface of the silicon wafer and forming a polished surface on the back of the silicon wafer; In step 1, the tunneling layer is a tunneling silicon oxide layer with a thickness of 2-4 nm; the intrinsic amorphous silicon layer has a thickness of 200-380 nm.

3. The method for preparing a TBC battery according to claim 1, characterized in that, Step 2, preparing the first barrier layer, includes: screen printing a first barrier layer paste locally on the back side of the intrinsic amorphous silicon layer, and then sintering to prepare the first barrier layer; Step 5, preparing the second barrier layer, includes: screen printing a second barrier layer paste on the back side of the Gap region silicon wafer and the boron-doped polycrystalline silicon layer, and then sintering to prepare the second barrier layer.

4. The method for preparing a TBC battery according to claim 3, characterized in that, In steps 2 and 5, the opening of the screen printing stencil is 400-620μm, and silica paste is printed locally. After printing, it is sintered at a high temperature of 860-900℃ for 3-7 minutes. The first barrier layer and the second barrier layer are both silica barrier layers, and the width of the first barrier layer and the second barrier layer after sintering is 450-640μm, the thickness is 0.2-2μm, and the refractive index is 1.6-1.

8.

5. The method for preparing a TBC battery according to claim 1, characterized in that, In step 3, the thickness of the borosilicate glass layer is 45-65 nm and the doping concentration of the boron-doped polysilicon is 8e19~2e20cm -3 .

6. The method for preparing a TBC battery according to claim 1, characterized in that, In step 4, the laser is a green laser with a wavelength of 500-550nm, a power of 60-120W, a scanning rate of 5000-50000mm / s, and a frequency of 250-1000KHz. Alternatively, the laser is an infrared laser with a wavelength of 700-1200nm, a power of 70-120W, a scanning rate of 5000-20000mm / s, and a frequency of 250-1000KHz. The width of the first barrier layer removed by the laser is 70-120 μm, and the width of the remaining first barrier layer is 380-500 μm.

7. A method for preparing a TBC battery according to claim 1 or 6, characterized in that, In step 4, the wet etching includes: first, alkaline etching to remove the intrinsic amorphous silicon layer in the laser region, and then acid etching to remove the tunneling layer in the laser region, the borosilicate glass layer in the non-first barrier layer region, and the first barrier layer in the non-laser region.

8. The method for preparing a TBC battery according to claim 1, characterized in that, In step 6, a 35-55 nm thick phosphorus-silicon glass layer is also formed on the back side of the phosphorus-doped polycrystalline silicon layer; the doping concentration of the phosphorus-doped polycrystalline silicon layer is 1e20~4e20cm. -3 .

9. The method for preparing a TBC battery according to claim 8, characterized in that, Step 7 specifically includes: first, acid wet etching to remove the phosphorus-silicon glass layer to expose the phosphorus-doped polysilicon layer, and then removing the second barrier layer to expose the back side of the Gap region silicon wafer and the boron-doped polysilicon layer; then, alkaline texturing to form a textured surface on the front side of the silicon wafer and the back side of the Gap region silicon wafer.

10. A TBC battery, characterized in that, It is prepared by the method of any one of claims 1-9 for a TBC battery.

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