A method and system for implementing processor memory access optimization for instruction multi-lane concurrency

Abstract

The present disclosure provides a processor memory access optimization implementation method and system for instruction multi-channel concurrency, and relates to the technical field of processor integrated circuits, comprising obtaining Load instructions and Store instructions to be executed; distributing a plurality of memory access instructions to each independent parallel processing memory access channel, each memory access channel comprising a Load memory access channel and a Store memory access channel; setting an independent Load queue and a RAW check queue in the Load memory access channel, and setting an independent Store queue, an STD queue and a Store Buffer queue in the Store memory access channel; the Load instructions sequentially pass through the address generation, TLB parallel query, L1Cache access, RAW check and data push forward and data write back stages in the Load memory access channel; the Store instructions are subjected to address and data separation processing, the address part enters the Store queue, the data part enters the STD queue, then merging is performed, a plurality of Store operations on the same Cache Line are merged into one write, the merged data is written into the Store Buffer queue, and the Store Buffer queue uniformly submits the cache.

Description

Technical Field

[0001] This disclosure relates to the field of processor integrated circuit technology, specifically to a method and system for optimizing processor memory access in multi-channel concurrent instruction processing. Background Technology

[0002] The statements in this section are merely background information relating to this disclosure and do not necessarily constitute prior art.

[0003] With the rise of high-load applications such as big data, cloud computing, and artificial intelligence, the performance bottleneck of processors has gradually shifted from arithmetic operations to the memory access subsystem. Traditional pipelined processors, due to their limited instruction-level parallelism, struggle to meet the high-bandwidth, low-latency access requirements of modern applications. Superscalar and out-of-order execution architectures have become mainstream, improving instruction throughput through multiple issues and dynamic scheduling. However, the memory access unit, as a crucial module connecting the processor core and the memory hierarchy, directly limits the overall system efficiency.

[0004] As an emerging open-source instruction set architecture, RISC-V has become the mainstream ISA widely adopted by academia and industry due to its advantages such as simplicity, modularity, and scalability. The memory access unit of a RISC-V processor is primarily responsible for processing Load / Store type instructions, enabling access to data caches (L1 / L2 cache), TLB, main memory, etc. The key design of the RISC-V processor's memory access unit is crucial for achieving efficient data access.

[0005] Currently, the memory access process implemented in the memory access unit of RISC-V superscalar processors includes address space calculation, address translation, and separate execution of Load / Store instructions: the Load instruction accesses the L1D cache based on the physical address, while simultaneously accessing the data portion of the Store instruction, and finally writes the data back to the physical register based on address overlap. The Store instruction does not directly access the cache, but instead writes back by merging cache lines in a write queue. Corresponding miss queues or write-back queues are designed for cache misses or write-backs to lower-level memory spaces, completing the interaction on a cache line basis.

[0006] However, the existing design solutions described above have the following technical problems:

[0007] 1) Limited parallelism of memory access instructions: The memory access instruction processing capability of most processor memory access units is not matched with core parameters such as out-of-order execution units and issue width, becoming a system bottleneck. The processor memory access unit can only support 1-2 memory access instructions per cycle, which cannot fully utilize the high concurrency advantage brought by out-of-order scheduling. Load and Store instructions compete for resources and queue management, which can easily lead to pipeline blockage and reduce throughput.

[0008] 2) Complex Data Dependency Handling: There is a RAW (Read After Write) dependency between Load and Store instructions. Traditional data forwarding and dependency detection mechanisms generally use queue traversal and flags, which are logically complex and have high latency. For example, serially traversing the Store queue within the Load queue is inefficient and can easily become a performance bottleneck. An imperfect data forwarding mechanism causes Load instructions to wait for the Store to write back to main memory or cache before they can retrieve data, increasing latency.

[0009] 3) Low efficiency in address generation and TLB lookup: Address generation (Agen) and TLB lookup for Load / Store instructions are often executed serially, failing to be parallelized, which increases the total latency of the memory access pipeline. Insufficient application of PIPT (Physical Index Physical Tag) technology means that cache accesses must wait for the TLB to return the physical address, reducing memory access efficiency, increasing pipeline cavitation, and impacting throughput.

[0010] 4) Multi-core / multi-thread support and consistency challenges: With the popularization of multi-core and SMT (Simultaneous Multi-Threading) technologies, memory access units need to support higher concurrency and more complex data consistency protocols (such as MESI, MOESI, etc.), and existing designs are difficult to balance performance and consistency. Summary of the Invention

[0011] To address the aforementioned issues, this disclosure proposes a method and system for optimizing processor memory access with multi-channel concurrent instruction processing. A multi-channel pipeline structure is implemented within the memory access unit, and an independent RAW check queue (RAWQ) is designed to detect read-after-write (RAW) dependencies between Load and Store instructions. The address and data portions of Store instructions are processed separately, and the VIPT (Virtual Index Physical Tag) method is used for address generation. Address generation is performed synchronously with TLB lookup, eliminating pipeline idle waiting, effectively reducing Load-to-use latency, and significantly improving memory access efficiency.

[0012] According to some embodiments, the present disclosure adopts the following technical solutions:

[0013] A method for optimizing processor memory access in a multi-channel concurrent manner includes:

[0014] Retrieve multiple memory access instructions to be executed in each cycle, including Load and Store instructions;

[0015] Based on resource usage and scheduling priority, multiple memory access instructions are allocated to various independent parallel memory access channels, including Load memory access channels and Store memory access channels. The Load memory access channel is equipped with an independent Load queue and RAW check queue, and the Store memory access channel is equipped with an independent Store queue, STD queue and Store Buffer queue.

[0016] The Load instruction sequentially goes through the following stages within the Load memory access channel: address generation, TLB parallel lookup, L1 Cache access, RAW check and data push-forward, and data write-back.

[0017] Store instructions are processed by separating the address and data. The address part enters the Store queue, and the data part enters the STD queue. They are merged according to the instruction ID. The Store Buffer queue merges multiple Store operations on the same Cache Line into a single write. The write to the Cache operation is submitted uniformly by the Store Buffer queue.

[0018] According to some embodiments, the present disclosure adopts the following technical solutions:

[0019] A processor memory access optimization system with instruction multi-channel concurrency includes:

[0020] The address generation unit is configured to obtain multiple memory access instructions to be executed in each cycle. The memory access instructions include Load instructions and Store instructions. The virtual address of the memory access instructions is calculated in the same clock cycle, and address query requests are sent to the TLB and CacheArbiter at the same time.

[0021] The Load instruction execution unit is configured to use independent Load queues and RAW check queues for processing. Load instructions go through address generation, TLB parallel lookup, L1 Cache access, RAW check and data push-forward, and data write-back stages in the Load memory access channel in sequence.

[0022] The Store instruction execution unit is configured to process instructions using independent Store queues, STD queues, and Store Buffer queues. Store instructions are processed by separating address and data. The address part enters the Store queue, and the data part enters the STD queue. The instructions are merged according to the instruction ID. The Store Buffer queue merges multiple Store operations on the same Cache Line into a single write. Cache write operations are submitted uniformly by the Store Buffer queue.

[0023] According to some embodiments, the present disclosure adopts the following technical solutions:

[0024] A computer program product includes a computer program that, when executed by a processor, implements the aforementioned method for optimizing processor memory access with multi-channel concurrent instruction processing.

[0025] According to some embodiments, the present disclosure adopts the following technical solutions:

[0026] A non-transitory computer-readable storage medium is provided for storing computer instructions, which, when executed by a processor, implement the aforementioned method for optimizing processor memory access with multi-channel concurrent instruction processing.

[0027] According to some embodiments, the present disclosure adopts the following technical solutions:

[0028] An electronic device includes a processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory to enable the electronic device to execute a processor memory access optimization method for multi-channel concurrent instruction execution.

[0029] Compared with the prior art, the beneficial effects of this disclosure are as follows:

[0030] This disclosure discloses a processor memory access optimization method for multi-channel concurrent instructions. It employs a multi-channel pipeline structure within the memory access unit, specifically supporting up to four memory access instructions (including Load and Store) entering the execution unit simultaneously per cycle. By dividing the memory access channel into independent Load and Store channels and dynamically balancing hardware resource allocation for the two types of instructions, resource contention within the memory access unit is significantly reduced, improving the parallel processing capability of memory access instructions. The parallel processing capability of memory access instructions is significantly improved, and Load-to-use latency is reduced by 20%.

[0031] This disclosure presents a processor memory access optimization method for multi-channel concurrent instructions. It designs an independent RAW check queue (RAWQ) specifically for detecting read-after-write (RAW) dependencies between Load and Store instructions. The data push-forward mechanism eliminates the need to wait for Store write-back, significantly shortening the critical path of Load instructions and adapting to high-concurrency scenarios such as AI and image processing. Improved data dependency detection efficiency reduces pipeline blocking probability, minimizing pipeline congestion caused by data dependencies and increasing memory access throughput under out-of-order execution, resulting in an overall throughput improvement of 15%. It supports multi-core, multi-threaded high-concurrency scenarios and possesses good scalability and compatibility.

[0032] This disclosure discloses a processor memory access optimization method for multi-channel concurrent instruction access. It innovatively separates the address and data parts of the Store instruction for processing, thereby improving the processing efficiency of the Store instruction. By separating the address and data management of the Store instruction and combining it with the age vector and address merging mechanism, it improves write bandwidth and sequential consistency, and avoids data conflicts caused by out-of-order commits.

[0033] This disclosure discloses a processor memory access optimization method for multi-channel concurrent instruction execution. It adopts the VIPT (Virtual Index Physical Tag) address generation method. In order to shorten the execution path of memory access instructions, address generation and TLB / Cache lookup are carried out in parallel, reducing pipeline cavitation and improving system energy efficiency. Attached Figure Description

[0034] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure.

[0035] Figure 1 This is a block diagram of the optimized memory access unit structure according to an embodiment of the present disclosure;

[0036] Figure 2 This is a schematic diagram of the Load instruction pipeline according to an embodiment of the present disclosure;

[0037] Figure 3 This is a schematic diagram of the Store instruction pipeline according to an embodiment of the present disclosure. Detailed Implementation

[0038] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0039] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0040] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0041] Example 1

[0042] One embodiment of this disclosure provides a processor memory access optimization method for instruction multi-channel concurrent access, including:

[0043] Step 1: Obtain the multiple memory access instructions to be executed in each cycle. The memory access instructions include Load instructions and Store instructions.

[0044] Step 2: Based on resource usage and scheduling priority, allocate multiple memory access instructions to various independent parallel memory access channels, including Load memory access channels and Store memory access channels; set up independent Load queues and RAW check queues in Load memory access channels, and set up independent Store queues, STD queues and Store Buffer queues in Store memory access channels;

[0045] The Load instruction sequentially goes through the following stages within the Load memory access channel: address generation, TLB parallel lookup, L1 Cache access, RAW check and data push-forward, and data write-back.

[0046] Store instructions are processed using separate Store queues, STD queues, and Store Buffer queues. Store instructions are processed by separating the address and data. The address part goes into the Store queue, and the data part goes into the STD queue. They are merged according to the instruction ID. The Store Buffer queue merges multiple Store operations on the same cache line into a single write. Cache write operations are submitted uniformly by the Store Buffer queue.

[0047] As one embodiment, this disclosure presents a processor memory access optimization method for multi-channel concurrent instruction processing. It features a systematic and innovative design across multiple levels, including memory access pipeline structure, data dependency detection and push-forward mechanism, address generation, and TLB / Cache parallel lookup. This method supports multi-channel parallel memory access instruction processing, improving throughput; optimizes the data dependency detection and push-forward mechanism for Load / Store instructions, reducing pipeline congestion and latency; achieves efficient parallelism of address generation and TLB / Cache lookup, shortening the memory access instruction execution path; and supports data consistency and high concurrency in multi-core / multi-threaded environments. It possesses good scalability, verifiability, and industrial application value. The specific details are as follows:

[0048] Step 1: Obtain the multiple memory access instructions to be executed in each cycle, including Load instructions and Store instructions;

[0049] Step 2: Allocate multiple memory access instructions to various independent parallel memory access channels based on resource usage and scheduling priority;

[0050] Specifically, the memory access unit disclosed herein features a multi-channel pipeline structure with four receive channels, supporting up to four memory access instructions (including Load and Store instructions) entering the execution unit simultaneously per cycle. By dividing the memory access channels into independent Load and Store channels and dynamically balancing the allocation of hardware resources for the two types of instructions, resource contention within the memory access unit is significantly reduced, thereby enhancing the parallel processing capability of memory access instructions.

[0051] The system comprises four channels: channel 0, channel 1, channel 2, and channel 3. These channels are divided into independent Load and Store channels. Channels 0 and 2 can receive both Load and Store commands. Channels 1 and 3 can only receive Load commands. In other words, channels 0-3 can all receive Load commands, while channels 0 and 2 can receive Store commands. Command transmission can be scheduled based on the transmission status of the transmission queue.

[0052] The memory access channels include Load memory access channels and Store memory access channels. Each Load channel has an independent Load queue (LDQ) and RAW check queue (RAWQ), which can realize efficient instruction distribution and parallel execution under out-of-order scheduling.

[0053] Each Store channel is equipped with an independent Store Queue (STQ), Data Queue (STD), and Store Buffer (STB), supporting address and data separation processing to improve write bandwidth and efficiency.

[0054] Furthermore, the pipeline structure within the channel includes: Load instructions sequentially pass through address generation, TLB parallel lookup, L1 Cache access, RAW checking and data push-forward, and data write-back stages within the Load memory access channel; Store instructions first perform address and data separation processing within the Store memory access channel, with the address part entering the Store queue (STQ) and the data part entering the STD queue, and then merging them to combine multiple Store operations on the same Cache Line into a single write, after which the merged data is written to the Store Buffer queue (STB), and then the Store Buffer queue (STB) submits the data to the cache in a unified manner.

[0055] As one implementation, the RAW Check Queue (RAWQ) is a dedicated hardware queue specifically designed to detect read-after-write (RAW) dependencies between Load and Store instructions. RAWQ can obtain the address and data status of preceding Store instructions during the Load instruction execution phase, enabling efficient parallel detection. Once the relevant Store data is detected to be in the STQ or STB, the Load instruction can directly retrieve the data via a forwarding mechanism, without waiting for the Store to be written back to main memory or cache, significantly reducing Load execution latency. This mechanism is particularly effective for out-of-order execution scenarios, preventing pipeline congestion and performance degradation caused by data dependencies.

[0056] As one embodiment, the specific process of the multi-channel memory access pipeline and parallel scheduling disclosed herein is as follows:

[0057] (1) Dispatch of memory access instructions

[0058] The out-of-order scheduling unit allocates memory access instructions to each memory access channel based on resource availability and scheduling priority. Each channel can independently process Load / Store instructions, avoiding resource contention.

[0059] Specifically, a dynamic load balancing algorithm is adopted to monitor the queue depth and resource utilization of each channel in real time, and dynamically adjust the allocation strategy according to the instruction type and priority to ensure load balancing and maximized throughput of each channel.

[0060] The system accepts four memory access instructions per cycle, employing a bank-based design with four queues processing instructions in parallel. Due to the out-of-order execution of instructions, the execution speed varies, resulting in some queues being full while others are empty. Therefore, allocation is based on the specific situation; that is, load memory access instructions are allocated according to the queue status. If a queue is relatively full, it is allocated to one of the other queues.

[0061] (2) Each production line executes

[0062] As one example, the Load instruction sequentially goes through stages such as address generation, TLB parallel lookup, L1Cache access, RAW checking and data push-forward, and data write-back. Each channel can execute concurrently without blocking the others.

[0063] Specifically, this disclosure employs the VIPT (Virtual Index Physical Tag) mechanism, which includes virtual indexes and physical tags, to achieve a high degree of parallelism in address generation, TLB lookups, and L1 Cache access. The specific process is as follows:

[0064] 1. Address generation

[0065] The address generation unit (Agen) calculates the virtual address for memory access instructions within the same clock cycle and simultaneously sends address lookup requests to the TLB and Cache Arbiter. The address generation unit separates the index and tag of the virtual address at instruction issuance. The index portion is directly used for L1 Data Cache indexing without waiting for the TLB, while the tag portion waits for the TLB to return the physical address before tag comparison.

[0066] The address generation unit corresponds to Addr gen. This part mainly calculates the address space of memory access instructions, records instruction information such as Load, store, and fence instructions, and determines address characteristics such as non-alignment.

[0067] Index and Tag are the memory access instruction address ranges. Index is the address range [13:6], and Tag corresponds to [47:14].

[0068] 2. TLB Parallel Queries

[0069] Address generation and TLB lookup are performed simultaneously, eliminating pipeline idle waiting and significantly improving memory access efficiency. If the TLB lookup hits, physical address tag matching is immediately completed, achieving a zero-latency path for cache access and reducing pipeline idling. This mechanism effectively reduces load-to-use latency and improves instruction throughput. It is particularly suitable for processor architectures with high issue width and out-of-order execution, improving overall system energy efficiency.

[0070] 3. L1 Cache Access

[0071] Access to the cache requires two arbitrations. The first arbitration determines which modules have access rights; in this design, MQ, WBQ, STB, SNQ, and LDQ all need to access the cache. The priority is STB full > SNQ > LDQ > MQ > STB normal. The second arbitration determines which banks to access. When multiple requests enter the Data Cache to read data, if different requests access the same bank, a bank conflict occurs. Therefore, address arbitration is performed on valid requests in advance. Arbiters do not allow conflicts, ensuring that after arbitration, p0, p1, and p2 are inaccessible to each other.

[0072] 4. RAW inspection and data push-forward

[0073] Due to the complex data dependencies between Load and Store instructions, traditional serial traversal mechanisms are inefficient. This disclosure employs an independent RAW check queue (RAWQ). The RAW check queue within the Load memory access channel is used to detect read-write dependencies between Load and Store instructions. During the Load instruction issuance phase, the address and data status of the preceding Store instruction are known in advance and recorded in real time. Each Load channel can access the RAW check queue in parallel to check for the existence of related Store instructions. When related Store data is detected to be in the Store queue or Store Buffer, the Load instruction directly retrieves the data through a push-forward mechanism, without waiting for the Store data to be written back to main memory or cache, achieving efficient parallel detection and push-forward. The specific process is as follows:

[0074] (1) The parallel detection process includes: when the Load instruction enters the RAWQ, the hardware automatically compares its target address with the address range of all Store instructions in the RAWQ.

[0075] If address overlap exists, further determine whether the Store data has arrived.

[0076] If the data is already available, the Load instruction can directly forward to retrieve the data without waiting for the Store queue to write back to main memory or cache, greatly reducing Load execution latency.

[0077] (2) The push-forward process includes: implementing multi-level push-forward priorities, prioritizing the push-forward of the most recent Store data to ensure data consistency. If multiple Stores are found to hit the same address, an age vector is used to ensure that the Load retrieves the most recently written data. This mechanism significantly reduces Load-to-use latency, reduces pipeline blockage caused by data correlation, and improves memory access throughput under out-of-order execution.

[0078] The age vector refers to the age relationship of Store instructions within the STQ table. During forward checking, when multiple Store instructions overlap with the address of the Load instruction, to ensure data correctness, the youngest Store instruction that is older than the Load instruction but meets the criteria must be identified.

[0079] As one example, such as Figure 2 The diagram shows the execution pipeline for the Load instruction. LD0-3 represents the execution process of the Load instruction, as detailed below:

[0080] Stage 1: Address Generation and Access Permission Check

[0081] In the first stage of the pipeline, the Load instruction enters the address generation unit (AGEN), calculates the target memory access address range, and checks for special cases such as cross-page or unaligned access. During address generation, virtual address calculation and TLB address translation are performed in parallel. After calculation, the address information is simultaneously passed to the following three modules:

[0082] Cache Arbiter: Checks whether the current instruction can obtain access to the L1 Dcache.

[0083] LDQ: Instruction information is stored in the LDQ Entry, recording the acquired physical address and its address attributes. For instructions whose addresses span multiple cache lines, they must be split into two separate instructions after they become the oldest instruction.

[0084] DTLB: Retrieves the physical address information of the page table, checks for address anomalies based on the PMP attribute of the page table, and passes the anomalies to the instruction queue.

[0085] Stage 2: Cache Access and Address Conflict Check

[0086] In the second stage of the pipeline, after acquiring L1 Dcache access, the Load instruction performs tag matching to determine cache line hit status. If a cache line hit occurs, data is directly read from the L1 Dcache, masked, and then sent to the Forward module. If a cache line partially hits, the instruction is temporarily stored in the Load queue, and the STB, STQ, and MQ queues are checked sequentially for overlapping addresses. In the STB, entries are checked for addresses overlapping with the Load instruction address; in the STQ, all entries are traversed for overlapping addresses; and in the MQ, all entries are checked for overlapping addresses. In this case, Load outputs a completion signal, prematurely releasing its temporary physical registers to accelerate the scheduling and execution of subsequent instructions. If a cache line miss occurs, the instruction enters the LDQ and enters the Sleep state, waiting for the Wake-up signal after the MQ is filled.

[0087] Stage 3: Data Forwarding and Cache Reading

[0088] In the third stage of the pipeline, when the data for the Load instruction can be completely forwarded from STB, STQ, MQ, and Cache (i.e., the data source for the Load instruction is determined), if it is detected that only the address is ready in the Store Entry corresponding to STQ, but the data portion is not yet ready, the Load instruction cannot meet the completion condition. In this case, the Cancel signal in the Load instruction's completion signal is set to 1, and the ROB marks it as incomplete upon receiving this completion signal. It is important to note that this stage only completes the data preparation work; the actual data has not yet been written back to the physical registers. After Stage 2 determines the address overlap, the Forward module merges the four data sources (L1 cache, MQ, STB, and STQ) based on the Mask flags fed back by each module.

[0089] Stage 4: Data Write-back

[0090] In the fourth stage of the pipeline, the data merged by the Forward module is written to the physical register file, the LDQ entry is cleared, and the age_vector is cleared of valid flags, in preparation for recording the next Load instruction.

[0091] As one example, regarding Store instructions: In traditional designs, Store instructions often require waiting for both the address and data to arrive before entering the Store queue, resulting in significant latency. This disclosure innovatively separates the address and data portions of the Store instruction for processing. The address information enters the STQ queue, and the data enters the STD queue. Once both portions arrive, they are merged and written to the STB queue, which then submits them to the Cache or main memory. The specific process is as follows:

[0092] 1. Address and data are processed separately. The specific process includes: after the Store instruction is issued, the address and data are separated. The address part is managed independently in the STQ, and the data part is stored independently in the STD queue. The two parts of information can arrive asynchronously, avoiding pipeline blockage due to data waiting.

[0093] 2. The merged write process includes: Once both STQ and STD information are available, address merging logic is used to merge multiple Store operations on the same Cache Line into a single write, reducing the total number of write-backs. The merged data is written to the STB, and then the Store Buffer queue commits it to the cache. The STB uses a circular buffer structure to support high-concurrency writes. Both STQ and STB are equipped with age vectors to record the issuance order of each Store instruction. The commit phase strictly follows the program order to ensure data consistency and avoid data conflicts caused by out-of-order commits. The address merging mechanism supports merging multiple writes to the same Cache Line, reducing write-back pressure.

[0094] After the STB obtains access to the Cache, it writes one line at a time, in units of Cache line (512 bits).

[0095] As one example, such as Figure 3 The execution process of the Store directive involves the following steps:

[0096] Stage 1: Address Generation and Access Permission Check

[0097] In the first stage of the pipeline, the Store instruction enters the address generation unit, calculates the target memory access address range, and checks for special cases such as cross-page or unaligned access. Simultaneously, it queries the TLB to obtain physical address and page table attribute information to determine instruction anomalies. The STD information sent by the IQ is matched with the STQ's table entries for instruction ID matching. If a match is successful, the STD information is recorded in the table entry; otherwise, it is temporarily stored in the STD Queue for later merging.

[0098] Stage 2: Address Write Merging and RAW Correlation Check

[0099] In the second stage of the pipeline, the STQ stores the physical address, write data, and address access permissions of Store instructions. To ensure correct instruction execution, the oldest Store instruction undergoes a RAW dependency check with completed Load instructions. If an address conflict is found, a pipeline flush is triggered, and the Load instruction ID that malfunctioned is marked. If the address, data, RAW dependency, and exception checks for a Store instruction are all complete, the Store instruction can be marked as complete. It should be noted that Store instruction completion does not mean that the data has been written to main memory or cache, but rather that the Store instruction has met the conditions for sequential retirement. Write operations are performed by the STB.

[0100] Stage 3: Data Writing and Cache Access

[0101] After a Store instruction's write operation is marked as complete, it enters the execution phase, where the STB writes it to the cache as a cache line. The STB first allocates or merges the Store instructions sent by the STQ into the corresponding Entry by address, determines the write priority based on the Entry ID, and then sends an access request to the Cache Arbiter. If the target cache line is not found, the STB either writes directly according to the original state of the cache line or waits for the write-back to complete before executing the write operation. When a Store instruction becomes the oldest and meets the retirement criteria, the ROB marks it as retired and updates the oldest instruction ID. The corresponding STQ entry is released, and the Store's entire lifecycle ends.

[0102] Furthermore, this disclosure enables data consistency and concurrency support in multi-core / multi-threaded environments. The memory access unit can be seamlessly integrated into multi-core or multi-threaded processor systems, supports mainstream cache coherency protocols (such as MESI and MOESI), and improves concurrency performance through the following mechanisms:

[0103] (1) Consistency Protocol Interface: The memory access unit interacts with the Cache consistency protocol controller through a dedicated interface, supporting operations such as Cache Line state transition, invalidation notification, and write-back.

[0104] (2) Multi-threaded scheduling support: Each memory access channel can be bound to different threads. The upper-level scheduling unit dynamically adjusts the allocation of memory access resources according to thread priority and load, thereby improving the overall throughput of the multi-threaded system.

[0105] As one example, such as Figure 1 As shown, the specific details of the overall memory access unit architecture of this disclosure are as follows:

[0106] The Load Queue (LDQ) uses a 4-bank parallel architecture to store load instruction information, including the instruction's virtual address, physical address, cache access status, flush status, and exception status. Compared to the C910's approach of using a separate Read Buffer to handle cache misses and cross-cache line requests, this design adds a dedicated Entry to the LDQ outside of existing entries to handle special requests, waiting for the oldest instruction in the cross-cache line to be executed, thus reducing pipeline pressure. This design effectively alleviates the pressure on the Read Buffer in multi-miss scenarios and reduces pipeline congestion.

[0107] The Store Queue (STQ) uses a 2-Bank parallel architecture to store Store instruction information. This design sets up a Store Data Queue (STDQ) to temporarily store Store data, waiting for the address to be sent to the execution unit before merging. When a Store instruction arrives before the address, the C910 memory access unit allocates an Entry to the Store data in the STQ. Without an address, the data dependency check condition is not met, and the Entry is simply occupied. Once the STQ receives the complete Store instruction data and address, it is marked as complete. When the instruction becomes the oldest, it requests the STB to perform a merge operation. After successful merge, it enters the RAWQ for acute address dependency checking. If there are no dependency conflicts, the instructions are retired sequentially. The instruction information recorded in the remaining entries is basically the same as that of the Load instruction.

[0108] The write-back to the store buffer (STB) merges store instructions in units of cache lines (512 bits). It checks address matching; if there's no address overlap, an entry is created; otherwise, it's merged into an existing entry, and the entry's age is updated. After merging, the STB sends a success signal to the STQ. For store instructions accessing the None-Cache (NC) address range, a special entry is used to handle these instructions. NC store instruction data is not written to the L1 Dcache but is directly passed to the WBQ for write-back to the L2 cache. After winning cache access, the STB writes to the L1 Dcache in units of cache lines.

[0109] Snoop Queue (SNQ) is a storage bus consistency request mechanism. To ensure data consistency across multiple core caches, the Interconnect sends requests to other cores to access or modify the same cache line. Upon receiving a request, the SNQ creates an Entry and requests L1 DCache access permissions. It then checks or modifies the CSA status bit of the corresponding cache line. If the cache line's status is Dirty, the cache line must be written back to memory, and other cores must be notified of any data modifications at that address.

[0110] The Cache Arbitration Module (CAB) is responsible for arbitrating access requests to the Data Cache. Due to the characteristics of the hardware design, this design supports a maximum of four read and write requests. These requests include VA address information sent directly from the Age, as well as all instructions in STQ, LDQ, MQ, and SNQ waiting to acquire cache access rights. The CAB makes decisions based on the hardware's preset priority.

[0111] The Data Cache is structured into three parts: Tag, Data, and CSA. The Tag is used to determine cacheline hit status, Data stores the data within the corresponding address space, and the CSA records the cacheline status. Any modification to the cacheline or a Snoop request updates the CSA status. When the cacheline's CSA is in the Dirty / Evict state, if a write or Snoop request is received, the cacheline is first replaced and then passed to WBQ for writing back to memory.

[0112] The Read After Write Queue (RAWQ) is used to check read-after-write dependencies between Load and Store instructions. The C910 checks data dependencies by traversing all LDQ and STQ entries. This means that if an older Store instruction is still pending when a Load instruction completes, the Load instruction will continue to occupy that entry, impacting memory access bandwidth. Therefore, this design creates a separate RAWQ specifically for handling dependency checks.

[0113] The Write Back Queue (WBQ) is used to complete a write operation, which takes at least 4 clock cycles to write back from the L1 Cache to the L2 Cache. To improve write back efficiency, write back operations are completed in units of cache lines. This design sets up a WBQ to manage cache lines written back due to the Dirty / Silence Evict.

[0114] The Miss Queue (MQ) is used to handle cache misses. When a cache line is missing, a read request is sent to the L2 cache, and instructions in the queue that are sleeping are woken up after the data is populated back into the cache. Special entries are set up for instructions accessing the None Cacheable address space. This queue also supports handling bus errors and other bus-related exceptions.

[0115] The forward unit is responsible for handling the data forwarding and merging of Load instructions. In out-of-order execution scenarios, Store instructions may enter a sleep state due to DTLB page table missing issues, cache line backfilling, or other reasons, causing Store instruction data to "linger" in various stages of the pipeline. If older Store instruction data has not yet been written back, the data retrieved by the Load instruction is often incorrect. To solve this problem, a forward mechanism is added to check the Store addresses within each module and determine address overlap. Store instruction data may reside in STQ, MQ, STB, and WBQ. If the Load instruction determines that it can retrieve all the data, it is allowed to complete and feedback is sent to the preceding issue unit to mark the corresponding register as Ready, thereby reducing instruction wait time.

[0116] The Prefetch Queue (PQ) is used to predict the address space that might be accessed when a memory access instruction results in a Cache Miss. It is trained based on the instruction's PC and the missing address, and then initiates a read request in advance based on the confidence level.

[0117] Example 2

[0118] One embodiment of this disclosure provides a processor memory access optimization system with instruction multi-channel concurrency, including:

[0119] The address generation unit is configured to obtain multiple memory access instructions to be executed in each cycle. The memory access instructions include Load instructions and Store instructions. The virtual address of the memory access instructions is calculated in the same clock cycle, and address query requests are sent to the TLB and CacheArbiter at the same time.

[0120] The Load instruction execution unit is configured to use independent Load queues and RAW check queues for processing. Load instructions go through address generation, TLB parallel lookup, L1 Cache access, RAW check and data push-forward, and data write-back stages in the Load memory access channel in sequence.

[0121] The Store instruction execution unit is configured to process instructions using independent Store queues, STD queues, and Store Buffer queues. Store instructions are processed by separating the address and data. The address part enters the Store queue, and the data part enters the STD queue. Then, they are merged to combine multiple Store operations on the same Cache Line into a single write. The merged data is then written to the Store Buffer queue, which then submits the data to the cache.

[0122] As one embodiment, the processor memory access optimization implementation system with multi-channel concurrent instruction proposed in this invention can be widely applied to: high-performance general-purpose processors (such as server and desktop CPUs); embedded processors (such as mobile terminals and IoT chips); dedicated accelerators (such as AI inference, image processing, and encryption chips); and multi-core heterogeneous systems (such as system-on-a-chip (SoC) and cloud data centers).

[0123] Example 3

[0124] One embodiment of this disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the aforementioned method for optimizing processor memory access with multi-channel concurrent instruction processing.

[0125] Example 4

[0126] One embodiment of this disclosure provides a non-transitory computer-readable storage medium for storing computer instructions. When the computer instructions are executed by a processor, they implement the aforementioned method for optimizing processor memory access with multi-channel concurrent instruction processing.

[0127] Example 5

[0128] One embodiment of this disclosure provides an electronic device, including a processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory to enable the electronic device to execute a processor memory access optimization implementation method for multi-channel concurrent instruction execution.

[0129] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0130] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0131] While the specific embodiments of this disclosure have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of this disclosure. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of this disclosure are still within the scope of protection of this disclosure.

Claims

1. A method for optimizing processor memory access in a multi-channel concurrent manner, characterized in that, include: Retrieve multiple memory access instructions to be executed in each cycle, including Load and Store instructions; Based on resource usage and scheduling priority, multiple memory access instructions are allocated to various independent parallel memory access channels. Specifically, the memory access unit is set up with a multi-channel pipeline structure, with a total of 4 receive channels, namely channel 0, channel 1, channel 2 and channel 3. The 4 channels are divided into independent Load channels and Store channels. Channels 0 and 2 can receive both Load instructions and Store instructions; channels 1 and 3 can only receive Load instructions. That is, channels 0-3 can all receive Load instructions, and channels 0 and 2 can receive Store instructions. Instruction transmission can be scheduled according to the transmission status of the transmit queue. Each memory access channel independently processes Load and Store instructions; a dynamic load balancing algorithm is used to monitor the queue depth and resource utilization of each memory access channel in real time, and dynamically adjust the allocation strategy according to resource consumption, instruction type and priority to ensure load balancing of each memory access channel. The memory access channels include Load memory access channels and Store memory access channels. The Load memory access channel has an independent Load queue and a RAW check queue, while the Store memory access channel has an independent Store queue, STD queue, and Store Buffer queue. The RAW check queue in the Load memory access channel is used to detect read-write dependencies between Load and Store instructions. During the Load instruction issuance phase, the address and data status of the preceding Store instruction are known in advance and recorded in real time. Each Load channel can access the RAW check queue in parallel to check for the existence of related Store instructions. When related Store data is detected in the Store queue or Store Buffer, the Load instruction directly retrieves the data through a push-forward mechanism without waiting for the Store data to be written back to main memory or the cache. The specific process is as follows: The parallel detection process includes: when the Load instruction enters the RAWQ, the hardware automatically compares its target address with the address range of all Store instructions in the RAWQ; If address overlap exists, further determine whether the Store data has arrived; If the data is already available, the Load instruction can directly retrieve the data without waiting for the Store queue to be written back to main memory or cache, greatly reducing Load execution latency. The push-forward process includes: implementing multi-level push-forward priorities, prioritizing the push-forward of the most recent Store data to ensure data consistency; if multiple Stores are found to hit the same address, an age vector is used to ensure that the Load retrieves the most recently written data; The age vector refers to the age relationship of Store instructions within the STQ table entry. During forward checking, when multiple Store instructions overlap with the address of the Load instruction, to ensure data correctness, the youngest Store instruction that is older than the Load instruction but meets the conditions must be found. The Load instruction sequentially goes through the following stages within the Load memory access channel: address generation, TLB parallel lookup, L1 Cache access, RAW check and data push-forward, and data write-back. Access to the cache requires two arbitrations. The first arbitration determines the access permission, with priority STB full > SNQ > LDQ > MQ > STB normal. The second arbitration determines access to the bank. If different requests access the same bank, address arbitration is performed on valid requests in advance. Store instructions are processed by separating the address and data. The address part goes into the Store queue and the data part goes into the STD queue. Then they are merged to combine multiple Store operations on the same Cache Line into a single write. After merging, the data is written to the Store Buffer queue, and then the Store Buffer queue submits the data to the cache in a unified manner.

2. The processor memory access optimization implementation method for instruction multi-channel concurrency as described in claim 1, characterized in that, The address and data portions of a Store instruction are processed separately. The address portion is managed independently by the Store queue, while the data portion is stored independently through the STD queue. Once both portions of the Store instruction are in place, the merged data is written to the Store Buffer queue using a merging mechanism and managed by an age vector to ensure that Store instructions are submitted in order. The address merging mechanism supports merging multiple writes to the same Cache Line, reducing write-back pressure.

3. The processor memory access optimization implementation method for instruction multi-channel concurrency as described in claim 1, characterized in that, The address generation unit completes the virtual address calculation and TLB lookup for Load and Store instructions within the same clock cycle. The VIPT mechanism is used to achieve a high degree of parallelism between address generation, TLB lookup, and L1 cache access. The virtual address is separated into Index and Tag at instruction issue. The Index part is directly used for L1 Data Cache indexing, and the Tag part waits for the TLB to return the physical address before tag comparison. Address generation and TLB lookup are performed synchronously without serial waiting. If the TLB finds the address, the physical address tag comparison is completed immediately, realizing a zero-latency path for cache access.

4. The processor memory access optimization implementation method for instruction multi-channel concurrency as described in claim 1, characterized in that, The Store Buffer queue adopts a circular buffer structure, which supports high-concurrency writing and sequential commit, improves write bandwidth, and ensures program sequential consistency.

5. A processor memory access optimization implementation system with multi-channel instruction execution employs the processor memory access optimization implementation method with multi-channel instruction execution as described in any one of claims 1-4, characterized in that, include: The address generation unit is configured to obtain multiple memory access instructions to be executed in each cycle. The memory access instructions include Load instructions and Store instructions. The virtual address of the memory access instructions is calculated in the same clock cycle, and address query requests are sent to the TLB and CacheArbiter at the same time. The Load instruction execution unit is configured to use independent Load queues and RAW check queues for processing. Load instructions go through address generation, TLB parallel lookup, L1 Cache access, RAW check and data push-forward, and data write-back stages in the Load memory access channel in sequence. The Store instruction execution unit is configured to process instructions using independent Store queues, STD queues, and Store Buffer queues. Store instructions are processed by separating the address and data. The address part enters the Store queue, and the data part enters the STD queue. Then, they are merged to combine multiple Store operations on the same Cache Line into a single write. The merged data is then written to the Store Buffer queue, which then submits the data to the cache.

6. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the processor memory access optimization method for multi-channel concurrent instruction access as described in any one of claims 1-4.

7. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium is used to store computer instructions, which, when executed by a processor, implement a processor memory access optimization method for multi-channel concurrent instruction access as described in any one of claims 1-4.

8. An electronic device, characterized in that, include: The device includes a processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory to enable the electronic device to implement the processor memory access optimization method for instruction multi-channel concurrency as described in any one of claims 1-4.

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