A method for improving the yield compatibility of copper plating and board electrical process

Abstract

The application discloses a method for improving the adaptability of copper plating and plate electrical process yield, comprising the following steps: copper plating pretreatment: adopting bipolar micro-etching process to control the hole wall roughness at 0.2-0.5 mu m; copper plating; carrying out three-stage drying process on the circuit board after copper plating; storing the dried circuit board in a crystal phase regulation storage room for 6-12 hours to improve the copper crystal face (111) orientation ratio to more than 75%; self-adaptive plate electricity, automatically adjusting the initial current of plate electricity based on the storage time of the circuit board: when the storage time t is less than or equal to 8H, the initial current is 4.2+ / -0.3A / dm2; when the storage time t is greater than 8H, the initial current is 3.8+ / -0.2A / dm2. The method for improving the adaptability of copper plating and plate electrical process yield provided by the application prolongs the storage time of the circuit board by optimizing the processing technology after copper plating, solves the production capacity loss caused by the mismatch between copper plating and plate electrical maintenance, thereby improving the production efficiency and reducing the production cost.

Description

Technical Field

[0001] This invention relates to the field of circuit board manufacturing technology, and specifically to a method for improving the adaptability of copper plating and board electroplating processes to production output. Background Technology

[0002] Printed circuit boards (PCBs) achieve electrical connections between layers through hole metallization. The hole metallization process includes chemical copper plating (immersion copper), full-board electroplating (board electroplating), and electroplating. Immersion copper plating utilizes chemical reactions to deposit a copper layer of approximately 0.3μm-0.5μm on the walls of drilled holes, making the originally insulating resin and fiberglass surfaces conductive. This lays the foundation for subsequent board electroplating and electroplating, playing a crucial role in connecting the layers. Because the immersion copper layer is very thin, it is highly susceptible to oxidation when exposed to air. After being washed away with chemicals, it can detach, creating voids that prevent subsequent copper plating on the hole walls, resulting in open circuits and posing significant quality risks to the PCB. To prevent this oxidation, the current industry practice is to immerse the copper-plated board in a curing bath containing dilute acid, strictly controlling the resting time (generally ≤4 hours), before proceeding with board electroplating.

[0003] Immersing circuit boards in a curing tank can effectively mitigate the oxidation of the copper plating layer, but it also presents other problems. In actual production processes, the copper plating process is used more frequently and for longer periods than the board electroplating process. When copper plating is needed, the board electroplating process has to stop due to a lack of boards, resulting in lost production capacity and wasted costs.

[0004] Therefore, it is necessary to provide a new method to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this invention is to provide a method to improve the adaptability of copper plating and board electroplating processes. By optimizing the post-copper plating processing, the downtime of the circuit board is increased, which solves the problem of capacity loss caused by the mismatch between copper plating and board electroplating maintenance, thereby improving production efficiency and reducing production costs.

[0006] The technical solution of the present invention is as follows: A method for improving the compatibility of copper plating with plate electroplating processes includes the following steps: Step S1, Copper plating pretreatment: Using bipolar micro-etching process, the circuit board is first soaked in sulfuric acid-hydrogen peroxide solution, and then soaked in organic acid activator to control the roughness of the hole wall at 0.2-0.5μm; Step S2, copper plating; Step S3: The circuit board after copper plating undergoes a three-stage drying process until no moisture remains in the holes. The drying process is as follows: The first stage involves drying with hot air at 75-80℃, with a wind speed of 8-10m / s, for 3-5 minutes. The second stage involves infrared equilibrium drying at 60-65℃, with a wavelength of 2.5-5μm, for 8-12 minutes. The third stage involves circulating air cooling at 40-45℃, with circulating air humidity ≤15%. Step S4: Store the dried circuit board in a crystal phase control storage chamber for 6-12 hours to increase the proportion of copper crystal plane (111) orientation to over 75%. The storage conditions are as follows: A weak magnetic field of 0.5-1.2T is applied, with its direction parallel to the plate surface; The storage room temperature fluctuates periodically under a cycle of 25±3℃ / 2H. Step S5, adaptive board circuitry, includes: Automatically adjust the initial current of the board based on the board's storage time: When the storage time t≤8H, ​​the initial current is 4.2±0.3A / dm²; When the storage time t > 8 hours, the initial current is 3.8 ± 0.2 A / dm².

[0007] Furthermore, in step S1, the sulfuric acid concentration in the sulfuric acid-hydrogen peroxide solution is 5-8 wt%, the hydrogen peroxide concentration is 3-5 wt%, and the circuit board is soaked in the sulfuric acid-hydrogen peroxide solution for 30-60 seconds.

[0008] Furthermore, in step S1, the organic acid activator is a citric acid-tartaric acid composite solution with a pH value of 4.5-5.5.

[0009] Furthermore, step S3 also includes an online real-time moisture monitoring step to automatically determine the end point of the drying step.

[0010] Furthermore, step S5 also includes: real-time monitoring of the coating thickness and feedback adjustment of pulse parameters.

[0011] Furthermore, the pulse parameters include: duty cycle 70-80%, frequency 12-50Hz.

[0012] Compared with existing technologies, the method for improving the adaptability of copper plating and electroplating processes provided by this invention has the following advantages: The method for improving the adaptability of copper plating and board electroplating processes provided by this invention can extend the storage time of circuit boards by optimizing the storage environment of circuit boards after copper plating, thus solving the capacity loss caused by the mismatch between copper plating and board electroplating maintenance. The production line cycle matching degree has been increased from 70% to more than 95%, and the delay time window of board electroplating process can be extended to 24-36 hours, thereby improving production efficiency and reducing production costs.

[0013] II. The method for improving the adaptability of copper plating and plate-mount processes provided by this invention optimizes the pretreatment process before copper plating, the drying conditions after copper plating, the storage environment, and the plate-mount process. This improves the uniformity of the plating layer (Tp value) within the holes by 15%, the tensile strength of the plating layer is ≥350 MPa, and the pass rate of the thermal stress test (288°C) is ≥99.85%. Consequently, the scrap rate of the copper plating / plate-mount process and the scrap rate of copper-free holes in the copper plating / plate-mount process are reduced. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a graph showing the test results of the backlight quality of the circuit board corresponding to different resting times after copper plating in this invention. Figure 2 These are the test results of the appearance quality of the circuit board after electroplating, corresponding to different resting times after copper plating in this invention. Figure 3 This is a graph showing the thermal shock test results of the test board after different storage times following copper plating in this invention. Figure 4 This is a product quality trend chart produced using the method of this invention. Detailed Implementation

[0016] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, and to make the above-mentioned objectives, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below.

[0017] It should be noted that the descriptions of these embodiments are for the purpose of aiding understanding the present invention, but do not constitute a limitation thereof. Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. Example 1

[0018] A method for improving the compatibility of copper plating with plate electroplating processes includes the following steps: Step S1, Copper plating pretreatment: Using bipolar micro-etching process, the circuit board is first soaked in sulfuric acid-hydrogen peroxide solution, and then soaked in organic acid activator to control the roughness of the hole wall at 0.2-0.5μm; The sulfuric acid-hydrogen peroxide solution contains 5-8 wt% sulfuric acid and 3-5 wt% hydrogen peroxide, and the circuit board is immersed in the solution for 30-60 seconds. The organic acid activator is a citric acid-tartaric acid composite solution with a pH of 4.5-5.5. A copper layer anchoring structure is established through gradient etching, and surface activation treatment is combined to improve the adhesion of the copper layer, increasing the adhesion by 40%.

[0019] Step S2, copper plating; Step S3: The circuit board after copper plating undergoes a three-stage drying process until no moisture remains in the holes. The drying process is as follows: The first stage involves drying with hot air at 80℃, with a wind speed of 8-10m / s, for 3-5 minutes to quickly remove surface moisture. The second stage involves infrared equilibrium drying at 65℃ with a wavelength of 2.5-5μm for 8-12 minutes to eliminate internal stress. The third stage involves 40°C circulating air cooling with a circulating air humidity of ≤15% to stabilize the substrate structure. The process also involves real-time online moisture monitoring to automatically determine the endpoint of the drying step.

[0020] Step S4: Store the dried circuit board in a crystal phase control storage chamber for 6-12 hours to increase the orientation ratio of the copper crystal plane (111) to over 75% in order to reduce the internal stress of subsequent electroplating. The storage conditions are as follows: A weak magnetic field of 0.5-1.2T is applied, with its direction parallel to the plate surface; The storage room temperature fluctuates periodically under a cycle of 25±3℃ / 2H. Step S5, adaptive board circuitry, includes: Automatically adjust the initial current of the board based on the board's storage time: When the storage time t≤8H, ​​the initial current is 4.2±0.3A / dm²; When the storage time t > 8 hours, the initial current is 3.8 ± 0.2 A / dm². The coating thickness is monitored in real time, and the pulse parameters are adjusted accordingly. These pulse parameters include a duty cycle of 70-80% and a frequency of 12-50Hz. The specific method is as follows: Using an X-ray fluorescence thickness gauge (XRF) or eddy current thickness gauge, the thickness of the plating layer on the hole wall or surface is measured online (the thickness gauge is installed in the electroplating tank, one for each electroplating tank, flush with the nozzle). Multiple sampling points are taken in key areas (such as the four corners of square slot holes) to ensure data representativeness. Data feedback frequency: data is collected every 10-30 seconds and transmitted to the electroplating control system via an industrial bus (such as Modbus). The electroplating control system adjusts the pulse parameters based on the real-time copper thickness data.

[0021] Specifically, the relationship between coating thickness and pulse parameters is as follows: Pulse current density: Current density is positively correlated with metal deposition rate (deposition amount per unit time = current density × electrochemical equivalent). When the coating thickness does not meet the target, the current density needs to be increased to accelerate deposition; conversely, it needs to be decreased.

[0022] Pulse on-time (Ton) and off-time (Toff): Ton: The longer the conduction time, the greater the deposition amount per pulse and the faster the thickness growth; Toff: The turn-off time affects the ion diffusion recovery capability. Too short a Toff will lead to concentration polarization and affect the uniformity of the coating.

[0023] Duty Cycle (Ton / (Ton+Toff)): The higher the duty cycle, the greater the equivalent average current density and the higher the deposition rate.

[0024] Frequency: High-frequency pulses (short Ton+Toff cycle) can refine grains and improve coating density, but need to be adjusted in conjunction with current density to avoid overload.

[0025] Waveform (e.g., reverse pulse): Reverse pulse can dissolve coating protrusions, improve flatness, and indirectly optimize the effective thickness distribution.

[0026] The post-copper plating resting times were set to 6h, 8h, 10h, and 12h, respectively. The test boards were characterized and their performance compared through backlight testing, appearance testing, outer layer AOI testing, four-wire testing, and thermal shock testing to verify the feasibility of the solution. The specific test board process is as follows: Negative film board: Pre-process → Drilling → Copper plating (after copper plating, drying and storage) → Board electroplating → Outer layer negative pattern → Negative etching → Four-line testing → Post-process Positive film board: Pre-process → Drilling → Copper plating (after copper plating, drying and storage) → Board electroplating → Outer layer positive film pattern → Pattern electroplating → Etching → Four-line testing → Post-process Copper plating backlight test results: Test results of backlight quality of circuit boards after copper plating and different resting times are as follows: Figure 1 As shown, where Figure 1 (a) indicates the backlight effect of copper plating after 6 hours of storage. Figure 1 (b) indicates the backlight effect after parking for 6 hours; Figure 1 (c) indicates the backlight effect of copper plating after 8 hours of storage. Figure 1 (d) indicates the backlight effect after parking for 8 hours; Figure 1 (e) indicates the backlight effect of copper plating after 10 hours of storage. Figure 1(f) indicates the backlight effect after parking for 10 hours; Figure 1 (g) represents the backlight effect of copper plating after 12 hours of storage. Figure 1 (h) indicates the backlight effect after 12 hours of storage. After copper plating and storage for 6-12 hours, the backlight level is ≥9, which meets production requirements.

[0027] Results of appearance quality test after plate charging: The test results of the appearance quality of the circuit board after electroplating for different resting times after copper plating are as follows: Figure 2 As shown, where Figure 2 (a) shows the appearance of the circuit board surface before the circuit board is powered on, corresponding to a 6-hour parking period. Figure 2 (b) shows the effect of the circuit board surface after being powered on under the condition of being parked for 6 hours; Figure 2 (c) indicates the appearance of the circuit board surface before the circuit board is powered on, corresponding to a 8-hour parking period. Figure 2 (d) shows the circuit board surface effect after 8 hours of parking; Figure 2(e) shows the circuit board surface effect before 10 hours of parking. Figure 2 (f) indicates the circuit board surface effect after 10 hours of parking; Figure 2 (g) indicates the surface condition of the circuit board before it is powered on, corresponding to a 12-hour parking period. Figure 2 (h) indicates the circuit board surface finish after 12 hours of storage. Figure 2 It can be seen that after copper plating and resting for 6-12 hours, the surface of the board after electroplating is bright, without roughness or watermarks.

[0028] The outer AOI test results are shown in Table 1: Table 1: Test results of outer AOI for different parking times ; The results of the four-line test are shown in Table 2: Table 2: Four-line test results for different parking times ; Thermal shock test verification: (1) Testing process Four samples were immersed in copper, dried, and stored in the environment described in this invention. They were placed in the air for 6 hours, 8 hours, 10 hours, and 12 hours, respectively, and then subjected to board electrolysis with parameters of 1.6ASD*60min. All processes of the final step were completed under the same conditions, and then a thermal shock test was performed. (2) Testing equipment: oven, solder pot, thermometer, stopwatch, rosin, desiccant, etc.; (3) Test methods; a. Set the oven to 140℃, place the sample under the gong in the oven and bake for 6 hours. After baking, place it in a desiccator to cool to room temperature. b. Raise the temperature of the tin furnace to 288℃ and clean the dross off the tin surface; c. Immerse the sample completely in flux for 5-10 seconds, then remove it and let it drip vertically for 60 seconds; d. Use stainless steel clips to hold the sample and let it float freely on the tin surface for 10 seconds (10 seconds required). +1 Remove from the water after 0 seconds (0 seconds), do not vibrate, and allow to cool to room temperature. e. Repeat steps c and d twice, clean and dry the surface, visually inspect and slice to observe the condition of the well wall.

[0029] (4) Test parameters: Solder pot temperature 288±5℃, immersion time 10 +1 0 seconds, tinning 3 times; (5) Inspection standards: After thermal shock, each sample is sliced ​​to confirm the presence of quality problems such as no copper in the through hole, broken copper on the hole wall, plating separation, and plating cracks.

[0030] (6) Test results: The thermal shock test results of the test boards after different resting times after copper plating are as follows: Figure 3 As shown, where Figure 3 (a) shows the overall effect of the thermal shock test on the test plate under the condition of 6 hours of storage. Figure 2 (b) A partial view of the thermal shock test effect of the test plate under the condition of 6 hours of storage; Figure 3 (c) shows the overall effect of the thermal shock test on the test plate under the condition of 8 hours of storage. Figure 3 (d) shows a partial view of the thermal shock test effect of the test plate under the condition of 8 hours of storage; Figure 3 (e) shows the overall effect of the thermal shock test on the test plate under the condition of 10 hours of storage. Figure 3 (f) shows a partial view of the thermal shock test effect of the test plate under the condition of 10h parking; Figure 3 (g) shows the overall effect of the thermal shock test on the test plate under the condition of 12h storage. Figure 3 (h) represents a partial view of the thermal shock test results of the test plate under the condition of 12 hours of storage. (From...) Figure 3 It can be seen that the sample slices have quality problems such as no holes or copper, broken copper on the hole walls, plating separation, and plating cracks.

[0031] The results of the above test board backlight, appearance, outer layer AOI, four-line test and thermal shock test show that the extended pre-electrode rest time after copper plating results in qualified production board quality, which preliminarily demonstrates the feasibility of the process of the present invention.

[0032] Mass production of the above processes will be implemented, and the scrap rate of the copper plating / electrode plating process and the scrap rate of copper-free vias in the copper plating / electrode plating process will be monitored. Product quality trends will be as follows: Figure 4 As shown. By Figure 4 It can be seen that by using the process of the present invention, the scrap rate of the copper plating / electrode plating process and the scrap rate of copper-free vias in the copper plating / electrode plating process are both reduced, indicating that the process of the present invention can improve the yield of circuit boards. Furthermore, tests show that the process of the present invention improves the uniformity of the plating layer inside the vias (Tp value) by 15%, the tensile strength of the plating layer is ≥350 MPa, and the pass rate of the thermal stress test (288°C) is ≥99.85%.

[0033] The technical advantages of the process of this invention compared with the existing copper plating-plate electroplating process are shown in Table 3: ; Meanwhile, the process method of the present invention can increase production capacity and reduce costs, as shown in the following statistics: Table 4: Impact of prolonged dwell time before electroplating after copper plating on output ; According to calculations, this can save 846,000 yuan per year in costs.

[0034] The embodiments of the present invention have been described in detail above, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions, and variations made to these embodiments without departing from the principles and spirit of the present invention still fall within the protection scope of the present invention.

Claims

1. A method for improving the adaptability of copper plating and electroplating processes to production yield, characterized in that, Includes the following steps: Step S1, Copper plating pretreatment: Using bipolar micro-etching process, the circuit board is first soaked in sulfuric acid-hydrogen peroxide solution, and then soaked in organic acid activator to control the roughness of the hole wall at 0.2-0.5μm; Step S2, copper plating; Step S3: The circuit board after copper plating undergoes a three-stage drying process until no moisture remains in the holes. The drying process is as follows: The first stage involves drying with hot air at 75-80℃, with a wind speed of 8-10m / s, for 3-5 minutes. The second stage involves infrared equilibrium drying at 60-65℃, with a wavelength of 2.5-5μm, for 8-12 minutes. The third stage involves circulating air cooling at 40-45℃, with circulating air humidity ≤15%. Step S4: Store the dried circuit board in a crystal phase control storage chamber for 6-12 hours to increase the proportion of copper crystal plane (111) orientation to over 75%. The storage conditions are as follows: A weak magnetic field of 0.5-1.2T is applied, with its direction parallel to the plate surface; The storage room temperature fluctuates periodically under a cycle of 25±3℃ / 2H. Step S5, adaptive board circuitry, includes: Automatically adjust the initial current of the board based on the board's storage time: When the storage time t≤8H, ​​the initial current is 4.2±0.3A / dm²; When the storage time t > 8 hours, the initial current is 3.8 ± 0.2 A / dm².

2. The method for improving the adaptability of copper plating and electroplating processes according to claim 1, characterized in that, In step S1, the sulfuric acid concentration in the sulfuric acid-hydrogen peroxide solution is 5-8 wt%, the hydrogen peroxide concentration is 3-5 wt%, and the circuit board is soaked in the sulfuric acid-hydrogen peroxide solution for 30-60 seconds.

3. The method for improving the adaptability of copper plating and electroplating processes according to claim 2, characterized in that, In step S1, the organic acid activator is a citric acid-tartaric acid composite solution with a pH value of 4.5-5.

5.

4. The method for improving the adaptability of copper plating and electroplating processes according to claim 1, characterized in that, Step S3 also includes an online real-time moisture monitoring step to automatically determine the end point of the drying step.

5. The method for improving the adaptability of copper plating and electroplating processes according to claim 1, characterized in that, Step S5 also includes: real-time monitoring of the coating thickness and feedback adjustment of pulse parameters.

6. The method for improving the adaptability of copper plating and electroplating processes according to claim 5, characterized in that, Pulse parameters include: duty cycle 70-80%, frequency 12-50Hz.

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