基于Gem5平台的RISC-V超标量处理器性能优化方法及系统
By optimizing the RISC-V superscalar processor in modules using the Gem5 platform, the problems of coarse simulation granularity and high verification cost in the existing technology are solved, and the processor performance is significantly improved and the energy efficiency is high.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG LINGNENG ELECTRONIC TECH CO LTD
- Filing Date
- 2025-05-29
- Publication Date
- 2026-07-17
AI Technical Summary
Existing RISC-V processor performance optimization methods suffer from coarse-grained simulation, difficulty in fine-grained microarchitectural behavior modeling, inability to effectively analyze inter-module relationships and performance bottlenecks, and high verification costs, making it difficult to meet the needs of high-performance applications.
The Gem5 platform was used to optimize the RISC-V superscalar processor in modules. By dividing it into front-end, mid-end and back-end modules, a progressive multi-level optimization process was set up, including local parameter fine-tuning, algorithm optimization, module linkage modification and overall pipeline adjustment, to optimize the processor architecture.
The processor's instruction throughput, response speed, and energy efficiency have been improved to meet the needs of high-performance application scenarios. The optimized pipeline structure reduces bubbles and data conflicts, and improves the collaborative performance between modules.
Smart Images
Figure CN120803532B_ABST