FPGA-based DDR4 multi-channel data arbitration transmission method, system, device and medium

Abstract

This invention discloses an FPGA-based DDR4 multi-channel data arbitration transmission method, comprising: S1, designing a multi-channel architecture to form N independent data transmission channels; S2, setting up a buffer; S3, AD sampling and buffering; S4, writing data to the DDR4 memory through write arbitration logic, finding the channel with the largest sampled data volume that meets the write conditions, with only that channel writing data to the DDR4 memory each time; S5, locating readable channels through interrupt management logic; and S6, reading data from the DDR4 memory through read channel management logic, sequentially reading data from all readable channels. This invention also discloses a system, device, and medium for implementing the DDR4 multi-channel data arbitration transmission method. This invention fully exploits the bandwidth potential of DDR4 memory and significantly improves the parallel processing capability of data transmission.

Description

Technical Field

[0001] This invention relates to the field of digital processing technology, and in particular to a method, system, device and medium for DDR4 multi-channel data arbitration transmission based on FPGA. Background Technology

[0002] In the rail transit sector, the edge-cloud integration model is becoming increasingly prevalent, and terminal data acquisition and control systems are becoming more common. Typically, terminals utilize multi-channel simultaneous sampling of various data types. With continuous technological advancements, data requirements are becoming increasingly stringent, demanding wider bandwidth, faster sampling frequencies, more diverse sampling types, and a dramatic increase in data processing volume. For high-speed data processing systems, the performance of the memory subsystem becomes a key factor limiting overall system performance. DDR4 memory (Double Data Rate Synchronous Dynamic Random Access Memory), with its high bandwidth, low power consumption, and large capacity, has become an important choice for improving system performance. FPGA (Field Programmable Gate Array), as a flexible programmable logic device, can easily interface with DDR4 and effectively control data transmission. Therefore, FPGAs are often used to implement sampling control logic for external high-speed AD (Analog-to-Digital Converter), video acquisition systems, and radar, while simultaneously using DDR4 for data storage or processing.

[0003] Achieving efficient storage under multi-channel, high-frequency, and high-bandwidth data sampling conditions is crucial. Designing DDR4 multi-data channels based on FPGA is significant for improving the overall performance of data processing systems, but existing technologies have two main problems:

[0004] 1. Insufficient DDR4 memory bandwidth utilization affects data transfer rates. The theoretical bandwidth of DDR4 is limited by physical interface and timing constraints. When multiple channels are written concurrently, the lack of an efficient scheduling mechanism results in actual bandwidth utilization being far lower than the theoretical value. Especially when the total channel bandwidth demand approaches or exceeds the DDR4 peak bandwidth, severe data backlog occurs, failing to meet real-time requirements.

[0005] 2. The lack of a channel arbitration mechanism makes congestion prone to occur when multiple data channels are running in parallel. Existing FPGA storage architectures often use fixed priority or round-robin scheduling strategies, which are difficult to dynamically adapt to sudden traffic surges in each channel. For example, a high-priority channel may occupy the bus for a long time, causing data loss in low-priority channels. When multiple channels initiate requests simultaneously, conflicts occur frequently, requiring multiple retries and increasing latency.

[0006] Therefore, there is an urgent need for a multi-channel data transmission scheme that can maximize memory bandwidth utilization and achieve conflict-free multi-channel arbitration to meet the needs of high-speed data acquisition systems for rail transit.

[0007] The statements herein provide only background information in relation to this invention and do not necessarily constitute prior art. Summary of the Invention

[0008] The purpose of this invention is to provide a method, system, device and medium for DDR4 multi-channel data arbitration transmission based on FPGA, so as to solve the problems of insufficient bandwidth utilization of DDR4 memory and easy congestion of multi-channels, which affects the data transmission efficiency.

[0009] To achieve the above objectives, this invention provides an FPGA-based DDR4 multi-channel data arbitration transmission method. This method is implemented based on a DDR4 multi-channel data arbitration transmission system, which includes: an FPGA; multiple AD sampling chips, all connected to the FPGA; multiple DDR4 chips, all connected to the FPGA; and a host computer connected to the FPGA. The DDR4 multi-channel data arbitration transmission method includes: S1, designing a multi-channel architecture to form N data transmission channels, wherein the N data transmission channels are independent of each other; and S2, setting up a buffer area.

[0010] S3. AD sampling and caching; S4. Write data to DDR4 through write arbitration logic, find the channel with the largest amount of sampled data and meet the write conditions, and only that channel writes data to DDR4 each time; S5. Locate the readable channel through interrupt management logic; S6. Read data in DDR4 through read channel management logic, and read data from all readable channels in sequence.

[0011] Optionally, the FPGA-based DDR4 multi-channel data arbitration transmission method includes designing a DDR4 read / write state machine for read / write control. The DDR4 read / write state machine includes the following states: Idle state (IDLE), in which the read / write status is monitored in real time, and the corresponding read / write process is entered according to different state transition conditions; Write address state (MEM_WRITE_ADDR), in which the write address in DDR4 is identified before the write operation; Write data state (MEM_WRITE_DATA), in which data is written to DDR4; Read wait state (MEM_READ_ADDR_WAIT), in which the host computer waits for the channel to become idle after initiating a read operation; Read address state (MEM_READ_ADDR), in which the corresponding address in DDR4 is identified before the read operation; Read data state (MEM_READ_DATA), in which DDR4 data at the corresponding address is read.

[0012] Optionally, step S1 specifically involves: dividing the storage space of the multiple DDR4 chips into N memory segments, corresponding to N AD sampling chips, forming N one-to-one data transmission channels; designing N independent DDR4 controllers on the FPGA, and connecting them to different memory segments in the DDR4 storage space, with each DDR4 controller managing its respective channel independently.

[0013] Optionally, step S2 specifically involves adding a WR_FIFO to each AD sampling chip, and multiple DDR4s sharing a unified RD_FIFO, which is added to the FPGA and connected to all DDR4s.

[0014] Optionally, step S3 specifically includes the following steps: S3.1, acquiring data through the AD sampling chip; S3.2, when AD sampling is successful, controlling the WR_FIFO of the corresponding channel to open, and writing the sampled data into the WR_FIFO for buffering.

[0015] Optionally, step S3.1 specifically includes the following steps: S3.1.1 After the host computer issues a sampling start command and sets the sampling length requirement, the AD sampling chip changes from the initial state AD_SPI_IDLE to the sampling wait state AD_SPI_WAIT, and simultaneously sends a reply signal to the host computer, indicating that sampling can be started; S3.1.2 After sending the reply signal, the AD sampling chip enters the ready-to-send command code state. In this state, the host computer sets the parameters of the AD sampling chip and sends a sampling setting command. Subsequently, the AD sampling chip enters the send command code state, in which the sampling setting command is written; S3.1.3 The AD sampling chip enters the ready-to-receive-data state AD_SPI_START_DATA. Then, the host computer starts AD sampling, and the AD sampling chip enters the receive-data state AD_SPI_DATA, reading back the sampled data via SPI.

[0016] Optionally, the parameter setting in step S3.1.2 is completed in two steps, specifically as follows: After sending the reply signal, the AD sampling chip enters the state of preparing to send the first command code, AD_SPI_START_01. At this time, the host computer receives the reply signal, clears the sampling start command, and prepares to send the sampling setting command. In this state, the host computer sets the functional parameters of the AD sampling chip. After the setting is completed, the host computer sends the sampling setting command, and the AD sampling chip enters the state of sending the first command code, AD_SPI_CMD_01, and begins to write the corresponding sampling setting command via SPI. The AD sampling chip starts the state of preparing to send the second command code, AD_SPI_START_02. In this state, the host computer performs identity recognition and hardware module management and control on the AD sampling chip. Subsequently, the AD sampling chip enters the state of sending the second command code, AD_SPI_CMD_02, and starts writing the second sampling setting command via SPI.

[0017] Optionally, step S4 specifically includes the following steps: S4.1, during the data preparation stage, the DDR4 is in the IDLE state, and the WR_FIFO status is monitored through the write arbitration logic to monitor the readable data volume given in the N-channel WR_FIFO in real time; S4.2, the channel with the largest sampled data volume is found, and the channel number max_index and the readable data volume max_value of the channel with the largest data volume are obtained; S4.3, it is determined whether the selected channel with the largest sampled data volume meets the write condition. If the write condition is met, proceed to step S4.4; if the write condition is not met, proceed directly to step S4.5; S4.4, the write address of the selected channel's data in the DDR4 is determined and the data is written to that write address in the DDR4, and the starting position of the next data write of the channel is tracked in real time; S4.5, steps S4.1-S4.4 are repeated to form a loop until the stop write condition is met, and the DDR4 returns to the IDLE state.

[0018] Optionally, finding the channel with the largest amount of sampled data specifically means: if the channel is not full, select the channel with the largest amount of data; and if there is more than one channel with the largest amount of data, select the channel with the smaller channel number.

[0019] Optionally, step S4.3 specifically involves: based on the channel number max_index and the readable data volume max_value of the currently selected channel output in step S4.2, determining whether max_value is greater than or equal to the burst length wr_burst_len. If max_value is greater than or equal to the burst length, it indicates that the readable data volume of the current maximum data volume channel meets the write condition, and then proceeding to step S4.4, the DDR4 changes from the IDLE state to the MEM_WRITE_ADDR state; if the readable data volume max_value of the maximum data volume channel is less than the burst length wr_burst_len, it indicates that there is currently no channel with sufficient data volume for a burst write, the DDR4 remains in the IDLE state, and directly proceeding to step S4.5; wherein, the burst length is the amount of data continuously transmitted in a burst transmission, calculated based on the number of data units transmitted in each transmission (set to a fixed value) and the bit width of the DDR4.

[0020] Optionally, the data writing to DDR4 adopts a burst mode, writing a burst length of data at once; the real-time tracking of the starting position of the next data write of the channel specifically involves: if there is still residual data in the WR_FIFO of the channel, the next write address of the channel needs to be updated. Each write address needs to be offset according to the burst length. next_wr_burst_addr[i] is used to record the starting address of the next burst write of the corresponding channel. The address offset corresponding to the burst length wr_burst_len is added to next_wr_burst_addr[i] to ensure that the next write operation starts from the correct address; at the same time, the channel write completion status flag wr_ddr4_over[i] is set to the first level, indicating that the DDR4 write operation of the channel has not yet been completed.

[0021] Optionally, satisfying the stop-write condition means that the amount of data in all channels is less than the length of a single burst.

[0022] Optionally, in step S4.5, when DDR4 is in the IDLE state, if the WR_FIFO of some channels is empty, it means that the channel has been completed. Then, the address and status variables related to the channel are reset through a reset operation, so that the channel can restart a new sampling and writing operation. Specifically, next_wr_burst_addr[i] is reset to its initial value, and the channel write completion status flag wr_ddr4_over[i] is set to the second level, indicating that the write operation of the channel has been completed.

[0023] Optionally, step S5 specifically includes the following steps: S5.1, the channel that has completed the write operation sends a signal to the interrupt manager, which is set in the FPGA; S5.2, the interrupt manager outputs an interrupt signal to notify the host computer that a channel has completed the write operation; S5.3, after receiving the interrupt signal, the host computer locates the readable channel through the FPGA and then starts the memory read operation of the corresponding channel.

[0024] Optionally, step S6 specifically involves: reading data from the memory segment of the readable channel, writing it into the corresponding RD_FIFO, and then using DMA to read the data of the channel; the read operation adopts a burst mode, performing multiple burst reads continuously within a channel, and after reading the data of the channel at once, reading data from all readable channels in sequence until all readable channels have completed the read operation, and the DDR4 returns to the idle state IDLE.

[0025] This invention also provides an FPGA-based DDR4 multi-channel data arbitration transmission system for implementing the aforementioned arbitration transmission method. The arbitration transmission system includes: an FPGA; N AD sampling chips, all connected to the FPGA; multiple DDR4 chips, all connected to the FPGA; and a host computer connected to the FPGA. The storage space of the multiple DDR4 chips is divided into N memory segments, corresponding to the N AD sampling chips, forming N one-to-one data transmission channels. The FPGA includes N independent DDR4 controllers, each connected to a different memory segment within the DDR4 storage space.

[0026] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the FPGA-based DDR4 multi-channel data arbitration transmission method.

[0027] The present invention also provides a computer-readable storage medium storing at least one piece of program code, which is loaded and executed by a processor to implement the FPGA-based DDR4 multi-channel data arbitration transmission method.

[0028] Compared with existing technologies, the FPGA-based DDR4 multi-channel data arbitration transmission method, system, device, and medium provided by this invention have at least the following advantages and beneficial effects:

[0029] 1. Multi-channel architecture design: This invention adopts a multi-channel parallel architecture, where each channel can independently perform data read and write operations. By dividing the DDR4 memory space into multiple memory segments, multiple independent DDR4 controllers are designed in the FPGA and connected to different DDR4 memory segments, achieving efficient multi-channel data transmission. Each channel's DDR4 controller independently manages a series of key operations such as address generation, command sending, and data caching. This multi-channel architecture can fully exploit the bandwidth potential of DDR4, greatly improving the parallel processing capability of data transmission and significantly increasing data processing efficiency.

[0030] 2. Data Allocation and Scheduling: Proper data allocation and scheduling are crucial in the operation of a multi-channel system. During the data writing phase, this invention employs arbitration logic to distribute data systematically across different channels, ensuring balanced load on each channel. During the data reading phase, data is precisely retrieved from the appropriate channel based on its address information. This efficient data allocation and scheduling algorithm not only comprehensively improves the overall system performance but also effectively avoids potential conflicts between channels, ensuring stable system operation.

[0031] 3. Interrupt Mechanism: In multi-channel architecture systems, the completion status of each channel is difficult for the host computer to know in advance. This invention employs an interrupt mechanism, which accurately notifies the host computer which channel has completed sampling via an interrupt signal, enabling the host computer to promptly perform data reading operations. Simultaneously, it can quickly restart the sampling process for that channel. This interrupt mechanism significantly improves the utilization efficiency of the host computer's CPU. While the host computer operates efficiently, the FPGA can also smoothly complete continuous sampling tasks, greatly enhancing the overall system efficiency.

[0032] 4. Caching Mechanism: This invention further improves data transmission efficiency by designing a dedicated data buffer FIFO for each channel. During data writing, the data is first cached in the AD's FIFO buffer, and then the DDR4 controller writes the data from the buffer to the DDR4. During data reading, the DDR4 controller first reads the data from the DDR4 into the buffer, then initiates DMA so that other modules can read data from the buffer. This caching mechanism significantly reduces the number of direct data transfers between the FPGA and DDR4, effectively reducing data transmission latency and thus greatly improving the system's response speed, making the system more efficient and smoother during data processing. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the FPGA-based DDR4 multi-channel data arbitration transmission system of the present invention;

[0034] Figure 2This is a flowchart of the FPGA-based DDR4 multi-channel data arbitration transmission method of the present invention;

[0035] Figure 3 This is a schematic diagram of the state machine of the AD sampling chip of the present invention;

[0036] Figure 4 This is a schematic diagram of the DDR4 read / write state machine of the present invention;

[0037] Figure 5 This is a schematic diagram of the arbitration logic of the present invention;

[0038] Figure 6 This is a schematic diagram of the interrupt logic and read channel management logic of the present invention. Detailed Implementation

[0039] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the FPGA-based DDR4 multi-channel data arbitration transmission method, system, device, and medium proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0040] This invention provides a FPGA-based DDR4 multi-channel data arbitration transmission method, which is based on... Figure 1 The illustrated DDR4 multi-channel data arbitration transmission system includes: an FPGA as the main control chip; multiple AD sampling chips, all connected to the FPGA, used to convert analog signals into digital signals for processing and analysis by the FPGA; multiple DDR4 chips, all connected to the FPGA; and a host computer connected to the FPGA, with PCIe (Peripheral Component Interconnect Express) 3.0 as the transmission channel between them.

[0041] In this preferred embodiment, 30 AD sampling chips are used, employing high-speed 16-bit AD sampling chips, with each AD sampling chip having a sampling frequency of 4MHz. Four DDR4 chips are used, totaling 2GB of memory, employing DDR4 with a sampling frequency of 200MHz and a 128-bit bus width. The DDR4 multi-channel data arbitration transmission method will be described subsequently using this preferred embodiment.

[0042] Based on the aforementioned DDR4 multi-channel data arbitration transmission system, such as Figure 2 As shown, the FPGA-based DDR4 multi-channel data arbitration transmission method provided by this invention includes the following steps:

[0043] S1. Design a multi-channel architecture, dividing the storage space of the multiple DDR4 chips into N memory segments, corresponding to N AD sampling chips, forming N one-to-one data transmission channels (hereinafter referred to as channels). The total number of memory segments is consistent with the number of AD sampling chips. Design N independent DDR4 controllers on the FPGA and connect them to different memory segments in the DDR4 storage space.

[0044] Each memory segment is labeled as memory segment n, and each channel number is labeled as channel n, where 0 ≤ n < N.

[0045] Each channel's DDR4 controller independently manages a series of critical operations such as address generation, command sending, and data buffering for that channel, thereby achieving independence between channels.

[0046] In this preferred embodiment, the four DDR4 chips are divided into 30 memory segments, which are sequentially labeled as memory segment 0 to memory segment 29, corresponding to 30 AD sampling chips, forming 30 data transmission channels, with channel numbers sequentially labeled as 0 to 29.

[0047] S2. Set up a buffer area. Add a WR_FIFO (write first-in-first-out queue) to each AD sampling chip. Multiple DDR4s share a unified RD_FIFO (read first-in-first-out queue). This RD_FIFO is added to the FPGA and connected to all DDR4s.

[0048] Each AD sampling chip's WR_FIFO is used for buffering during data writing, which eliminates the impact of data flow discontinuity caused by DDR4 read / write characteristics and solves the problem of speed, protocol, and bit width mismatch between AD sampling chips and DDR4. Each WR_FIFO is marked as WR_FIFO_CHANn, where n is the channel number of the channel where the WR_FIFO is located.

[0049] RD_FIFO is used to cache data during reading, which can eliminate the impact of data flow discontinuity caused by the read and write characteristics of DDR4, and solve the problem of speed and demand mismatch between DDR4 and the host computer processor.

[0050] S3, AD sampling and buffering.

[0051] S3.1. Data is acquired through an AD sampling chip to achieve AD sampling.

[0052] AD sampling refers to the process by which an AD sampling chip captures the instantaneous values ​​of an analog signal at fixed time intervals and then converts the continuous analog signal into a discrete digital signal. The AD sampling chip used is a 4MHz sampling rate, 16-bit wide AD sampling chip. Since one AD sampling chip contains two channels, the actual sampling bit width is 32 bits.

[0053] The AD sampling logic mainly includes a state machine, such as Figure 3 As shown, the specific steps include the following:

[0054] S3.1.1 The initial state of the AD sampling chip is AD_SPI_IDLE. After the host computer issues the sampling start command and sets the sampling length requirement, the AD sampling chip enters the sampling wait state AD_SPI_WAIT and sends a reply signal to the host computer, indicating that sampling can be started and waiting for the next command from the host computer.

[0055] S3.1.2 After sending the reply signal, the AD sampling chip enters the state of preparing to send the command code. In this state, the host computer sets the parameters of the AD sampling chip and sends the sampling setting command. Then the AD sampling chip enters the state of sending the command code, in which the sampling setting command is written.

[0056] Specifically, the parameter settings are completed in two steps:

[0057] After sending the reply signal, the AD sampling chip enters the state of preparing to send the first command code (AD_SPI_START_01). At this time, the host computer receives the reply signal, clears the sampling start command, and prepares to send the sampling setting command. In this state, the host computer sets the functional parameters of the AD sampling chip, including setting the bit width, whether to include filtering, and whether to include CRC code. If the default selection is selected, it will prepare to send the default sampling setting command. After the setting is completed, the host computer sends the sampling setting command, and the AD sampling chip enters the state of sending the first command code (AD_SPI_CMD_01) and begins to write the corresponding sampling setting command through SPI (Serial Peripheral Interface).

[0058] The AD sampling chip starts up in the preparation state of sending the second command code AD_SPI_START_02. In this state, the host computer performs identification and hardware module management and control of the AD sampling chip, including assigning identifiers to each AD sampling chip, managing the reset switch, configuring pin modes, etc. Then the AD sampling chip enters the state of sending the second command code AD_SPI_CMD_02 and starts writing the second sampling setting command through SPI.

[0059] S3.1.3 The AD sampling chip enters the data receiving state AD_SPI_START_DATA. Then, the AD sampling is started by the host computer. The AD sampling chip enters the data receiving state AD_SPI_DATA. In the AD_SPI_DATA state, the AD sampling chip reads back 16 bits of sampled data each time via SPI.

[0060] S3.2 When AD sampling is successful, control the WR_FIFO of the corresponding channel to open and write the sampled data into the WR_FIFO for buffering.

[0061] Specifically, the sampled data of the nth AD sampling chip is written into the WR_FIFO of the corresponding channel, i.e., WR_FIFO_CHANn. Since an AD contains two channels, the 16-bit sampled data needs to be concatenated into 32-bit data before being written into the corresponding FIFO. After writing the sampled data into the corresponding WR_FIFO, the AD sampling chip completes sampling and sequentially enters the transmit end state AD_SPI_START_END and the end state AD_SPI_END.

[0062] The WR_FIFO consists of three sub-modules: the IP core design of WR_FIFO (a pre-designed circuit module), the write logic of WR_FIFO, and the read logic of WR_FIFO.

[0063] The WR_FIFO IP core design adopts an asynchronous FIFO design using primitives, which facilitates program portability. Key parameters of the IP core design include: a FIFO depth of 1024, and the use of a block (memory block) approach for unified resource allocation scheduling.

[0064] Reading from the WR_FIFO is delayed by one clock cycle, a setting that affects subsequent DDR4 control logic. Additionally, since the AD sampling bit width is 32 bits while the DDR4 portion is 128 bits, this also needs to be configured. Therefore, the WR_FIFO read and write operations employ asynchronous logic. The clock frequency for writing sampled data to the WR_FIFO is 4MHz, while the WR_FIFO read clock uses the DDR4 clock, which has a frequency of 200MHz. Read and write control must be designed based on the FIFO characteristics.

[0065] S4. Write data to DDR4 through the arbitration logic.

[0066] On the one hand, DDR4's read / write speed can reach up to 3200MT / s. This embodiment uses a 200MHz user clock and a 128-bit wide DDR4, while the AD sampling chip has a frequency of 4MHz and a bit width of 32 bits. Clearly, the overall bandwidth of DDR4's 30 channels is far greater than the bandwidth required by all AD sampling chips. On the other hand, all 30 channels are sampled simultaneously, and the sampled data is continuously stored in the corresponding WR_FIFO, while writing to DDR4 is a single-threaded operation. Based on this logic, appropriate arbitration logic needs to be designed to meet the requirements.

[0067] Since DDR4 can only perform read or write operations on the same address at a time, a DDR4 read / write state machine must first be designed to control read and write operations. The DDR4 read / write state machine is as follows: Figure 4 As shown.

[0068] In this context, IDLE represents the DDR4 idle state. During this state, read / write status is monitored in real time, and the appropriate read / write process is initiated based on different state transition conditions. The logic for writing to DDR4 is the write arbitration logic, and the logic for reading from DDR4 is the read DDR4 management logic.

[0069] MEM_WRITE_ADDR represents the write address state. DDR4 write operations require writing to the corresponding address first, i.e., identifying the address in the DDR4 before proceeding with subsequent write operations. MEM_WRITE_DATA represents the write data state. After writing a block of data at once, the DDR4 returns to the IDLE state, which will be explained in detail later in conjunction with the write arbitration logic.

[0070] Among them, MEM_READ_ADDR_WAIT is the read wait state. After the host computer initiates a read operation, it waits for the channel to become idle. At this time, DDR4 enters MEM_READ_ADDR_WAIT. MEM_READ_ADDR is the read address state. Before the read operation, the corresponding address in DDR4 is written, that is, the corresponding address in DDR4 is identified. MEM_READ_DATA is the read data state, which reads the DDR4 data at the corresponding address.

[0071] In terms of DDR4's operating logic, to save resources and fully utilize bandwidth, a burst mode is used for read and write operations, meaning that multiple data blocks at consecutive addresses are written in a single operation. The burst depth (the number of data units transferred in each read / write operation) is set to a fixed value, currently 128 times. Since DDR4 is 128-bit, the amount of data written in one burst is 128 times × (128 bits / time / 8 bits / Byte) = 2048 Bytes = 2Kb.

[0072] The following details the arbitration logic. Since 30 channels are sampled simultaneously, the sampled data is continuously stored in the corresponding WR_FIFO. However, the DDR4 write operation is a single-threaded operation, requiring arbitration logic to determine which channel performs the DDR4 write operation at any given time. The basic idea is: first, monitor the WR_FIFO status of the 30 AD sampling chips in real time to find the channel with the largest amount of sampled data; second, write the sampled data from the channel with the largest data volume to the corresponding DDR4 memory address, writing a burst length (the amount of data continuously transmitted in a single burst, in bytes) of data at once.

[0073] like Figure 5 As shown, the process of writing data into DDR4 via write arbitration logic specifically includes the following steps:

[0074] S4.1 During the data preparation phase, DDR4 is in the IDLE state. The WR_FIFO status is monitored through the write arbitration logic, and the readable data volume fifo_rd_count given in the 30-channel WR_FIFO is monitored in real time.

[0075] S4.2 Find the channel with the largest amount of sampled data.

[0076] The 30-channel operation is designed in a pipelined manner. The DDR4 operating clock is 200MHz. However, the logic for finding the channel with the largest data volume among the 30 channels is complex and cannot be completed within a single clock cycle. Therefore, each operation performs a maximum value lookup on 3 or 2 channels, completing the process in 4 pipeline steps, ultimately yielding the channel with the largest data volume to be operated on. This process requires continuous monitoring to obtain the channel number `max_index` and the readable data volume `max_value` of the channel with the largest data volume.

[0077] The pipeline is completed in four steps: First, the 30 channels are divided into 10 groups (3 channels per group), and each group performs a 3-to-1 comparison in parallel; Second, the results of the 10 groups are further divided into groups (9 are divided into 3 groups, and the remaining 1 goes directly to the next step), and 4 candidate channels are output; Third, the 4 candidate channels are divided into 2 groups, and each group performs a 2-to-1 comparison, and 2 candidate channels are output; Fourth, a final 2-to-1 comparison is performed to obtain the channel with the largest amount of data.

[0078] During each filtering step, if the channel is not full, the channel with the largest data volume is selected; if there is more than one channel with the largest data volume, the channel with the smaller channel number is selected. Under these conditions, at any given time, only one channel with the largest data volume will be selected by the write arbitration logic, and the data in that channel will be written to DDR4 through subsequent steps.

[0079] An example method for finding the channel with the largest amount of sampled data is as follows:

[0080]

[0081]

[0082]

[0083]

[0084]

[0085] S4.3 Determine whether the channel with the largest selected sampled data volume meets the write conditions.

[0086] Specifically, based on the channel number max_index and the readable data volume max_value of the currently selected channel output in step S4.2, it is determined whether max_value is greater than or equal to the burst length wr_burst_len. If max_value is greater than or equal to the burst length, it means that the readable data volume of the current maximum data volume channel meets the conditions for burst writing. Then, the channel ready flag fifo_one_chan_rdy is set to high level, and the selected channel number burst_fifo_chan is set to max_index, that is, the channel number to be burst written is determined. Then, step S4.4 is entered. At this time, DDR4 enters write mode and changes from IDLE state to MEM_WRITE_ADDR state.

[0087] If the readable data size (max_value) of the maximum data size channel is less than the burst transmission length (wr_burst_len), it means that there is currently no channel with enough data for a burst write. In this case, the channel ready flag (fifo_one_chan_rdy) is set to low, indicating that no channel is ready; the selected channel number (burst_fifo_chan) is also set to low, indicating that there is no valid channel, and DDR4 remains idle, which satisfies the stop write condition, and proceeds directly to step S4.5.

[0088] An example method for step S4.3 is as follows:

[0089]

[0090]

[0091] In the example method described above, the critical state variables of the system are precisely controlled and updated within the logic process triggered by the rising edge of the clock signal mem_clk. When the reset signal rst is valid, it signifies that the system has entered the initialization phase. At this time, the channel ready flag fifo_one_chan_rdy is set to a low level of 1'b0, indicating that no channel is currently ready for burst data transmission; the actual burst data length burst_fifo_count is cleared to 8'b0 to empty the burst data count; and the selected channel number burst_fifo_chan is set to 5'b0, indicating that no channel is currently selected.

[0092] When the DDR4 is in an idle state (STATE_CUR == IDLE) and the readable data volume (max_value) of the maximum data volume channel is detected to be greater than or equal to the burst transfer length (wr_burst_len), it means that there is currently a channel whose data volume meets the conditions for burst writing. At this time, the channel ready flag (fifo_one_chan_rdy) is set to high level 1'b1 to indicate that a channel is ready for burst data transmission; the actual burst data length (burst_fifo_count) is updated to max_value, recording the readable data volume of the currently selected channel; and the selected channel number (burst_fifo_chan) is set to max_index to determine the channel number to be used for burst writing.

[0093] If the DDR4 is in an idle state (STATE_CUR == IDLE), but the readable data size (max_value) of the maximum data volume channel is less than the burst transfer length (wr_burst_len), it means that there is currently no channel with enough data for a burst write. In this case, the channel ready flag (fifo_one_chan_rdy) is set to low (1'b0), indicating that no channel is ready; the actual burst data length (burst_fifo_count) is cleared to zero (8'b0); and the selected channel number is set to 5'b0, indicating that there is no valid channel.

[0094] When DDR4 is in write address state (STATE_CUR == MEM_WRITE_ADDR), regardless of the previous state, the channel ready flag fifo_one_chan_rdy is set to low level 1'b0 to prevent unnecessary channel preparation signal interference during the write address phase.

[0095] S4.4 Determine the write address of the selected channel's data in DDR4 and write the data to that write address in DDR4, and track the starting position of the next data write for that channel in real time.

[0096] Specifically, the write address is the starting position of each data write in each channel. The initial write address of each channel starts from the set initial value ZERO. After the write address is determined, the data in the channel that meets the write conditions is selected in step S4.2 and determined in step S4.3 and written to the corresponding write address in DDR4. The burst mode is used to write a burst length of data at once.

[0097] At the same time, the starting position of the next data write for this channel is tracked in real time. If there is still residual data in the WR_FIFO of this channel, that is, the sampled data of this channel has not been completely written to DDR4, the next write address of this channel needs to be updated.

[0098] Since the length of data written in one operation is the burst length, which does not fill a full DDR4 memory segment, when performing a write operation in DDR4, in order to ensure that the data is written to the memory segment continuously and in an orderly manner, the address of each write operation needs to be offset according to the burst length to determine the starting position of the next burst write.

[0099] Specifically, `next_wr_burst_addr[i]` is used to record the starting address of the next burst write for the corresponding channel. When DDR4 is in write address state (STATE_CUR == MEM_WRITE_ADDR), and the currently processed channel i happens to be the channel with the largest data volume (i == burst_fifo_chan), the next burst write address for that channel needs to be updated. Specifically, `next_wr_burst_addr[i]` is added to the address offset `BURST_SIZE[ADDR_BITS-1:0]` corresponding to the burst transfer length `wr_burst_len` to ensure that the next write operation starts from the correct address. Simultaneously, the channel write completion status flag `wr_ddr4_over[i]` is set to the first level. In this preferred embodiment, the first level is specifically a low level 1'b0, indicating that the DDR4 write operation for that channel has not yet been completed.

[0100] S4.5 After the channel in step S4.4 completes one data write, steps S4.1-S4.4 are repeated to form a loop until the write stop condition is met and DDR4 returns to the idle state.

[0101] The stop-write condition is met when the amount of data in all channels is less than the length of a single burst. When the stop-write condition is met, DDR4 enters the IDLE state. When DDR4 is in the IDLE state, the state of all channels may be as follows: some channels have completed their writes and WR_FIFO is empty; some channels still have residual data (wr_ddr4_over[i] is low), but there is not enough data to trigger a transmission.

[0102] If the WR_FIFO of a certain channel is empty at this time, with no residual data, it means that all the sampled data of that channel has been written to DDR4, indicating that the channel meets the reset conditions and a reset operation is required.

[0103] After a complete sampling and writing process is completed, a reset operation resets the address and status variables related to the channel, enabling the channel to restart a new sampling and writing operation. The reset operation requires not only that the channel has completed sampling and writing, but also system confirmation of the status. Specifically, the following conditions must be met simultaneously: the system is in an idle state (STATE_CUR == IDLE) (i.e., no other channels are being written to), the channel's WR_FIFO is empty (fifo_empty[i] == 1'b1), and the channel's sampling synchronization signal is not started (fifo_start_sync[i] == 1'b0). When the above three conditions are met, next_wr_burst_addr[i] is reset to its initial value ZERO, and wr_ddr4_over[i] is set to the second level. In this preferred embodiment, the second level is specifically a high level 1'b1, indicating that the writing operation of the channel has been completed.

[0104] At this point, a complete sampling and writing process has been completed, and data from all channels that meet the writing conditions has been written to DDR4.

[0105] The idle state (IDLE) is maintained until a new sampling begins. When the data collected by a certain channel reaches the write condition, DDR4 re-enters the write address state (MEM_WRITE_ADDR) and the write data state (MEM_WRITE_DATA). At this time, only one channel is writing data. In other words, after a new sampling begins, the process from steps S4.1 to S4.5 is completed.

[0106] In summary, by writing arbitration logic, the arbitration task of writing DDR4 data can be completed in complex scenarios of multi-channel acquisition, ensuring that the data is accurately and efficiently stored in the corresponding memory address.

[0107] In terms of memory allocation strategy, the distribution of 30-channel AD sampling data in DDR4 memory uses the high 5 bits of the address to distinguish different channels. Since `burst_fifo_chan` represents the channel number with the largest data volume, it occupies 5 address bits. Data from different channels is completely isolated in terms of physical address, thus avoiding data interference between channels. Through explicit partitioning of channel numbers, data in any channel can be located very quickly. Simultaneously, the final write burst address `wr_burst_addr` is formed by concatenating the channel number `burst_fifo_chan` and the starting address of the next burst write for that channel, `next_wr_burst_addr[burst_fifo_chan]`, i.e., `wr_burst_addr <= {burst_fifo_chan, next_wr_burst_addr[burst_fifo_chan]}`. This ensures the continuity of data in the same channel in memory during burst writes, fully utilizing the burst transfer characteristics of DDR4 and improving transfer efficiency. In this way, ordered storage and efficient management of multi-channel data in DDR4 memory are achieved.

[0108] S5. Locate the readable channel through interrupt management logic.

[0109] Before initiating a read operation on each channel, the host computer needs to know precisely whether each channel has completed sampling and writing operations. This requires the FPGA to promptly notify the host computer after completing data sampling and storing it in DDR4. To achieve this, interrupt management logic is used. When a channel completes data sampling and writing operations, a corresponding interrupt signal is triggered to notify the host computer. Upon receiving the interrupt signal, the host computer enters the interrupt service routine and reads the data from the corresponding channel's DDR4, thus successfully completing the entire data transmission process. The workflow of interrupt management and channel read management is as follows: Figure 6 As shown.

[0110] The interrupt management logic specifically includes the following steps:

[0111] S5.1 The channel that has completed the write operation sends a signal to the interrupt manager, which is set in the FPGA;

[0112] Specifically, the system has 30 channels corresponding to 30 interrupts. When a channel completes a write operation, the corresponding bit of the wr_ddr4_over signal is set to high to indicate that the write task for that channel is complete. Subsequently, this signal is sent to the interrupt manager in the FPGA.

[0113] S5.2 The interrupt manager outputs an interrupt signal to notify the host computer that a channel has completed a write operation.

[0114] The interrupt manager is responsible for the centralized management and scheduling of interrupt signals from each channel, playing a crucial role in the entire system. Since there are 30 interrupts corresponding to 30 channels, and the interrupt lines of the host computer typically cannot provide so many interrupt logics, a single general interrupt signal is sent to the host computer via the interrupt manager.

[0115] The interrupt is triggered by a level, and the effective level is high. This setting ensures reliable transmission and accurate identification of the interrupt signal.

[0116] S5.3 After receiving the interrupt signal, the host computer sends a command to the processor in the FPGA. The processor queries the status parameters of the interrupt manager to accurately locate the channel number n of the channel that triggered the interrupt, that is, to locate the readable channel. Then, it notifies the host computer to start the memory read operation of the corresponding channel.

[0117] A specific example of step S5.3 is as follows, which implements how to handle interrupt signals and initiate data reading of the corresponding channel:

[0118]

[0119] After querying the interrupt manager's status parameters, the processor iterates through all channels, checking each channel for interrupt requests. If an interrupt request is found, it sequentially performs interrupt confirmation, increments the interrupt counter (recording the number of interrupts), prints debug information, and sets the data ready flag (ad_ch_flag[i] = 1). Finally, the function returns 0. Upon receiving the data ready flag signal, the host computer initiates the memory read operation for the corresponding channel.

[0120] S6. Read data from DDR4 through the read channel management logic.

[0121] DDR4 read and write operations are managed by the same state machine, and the specific state transition logic is as follows: Figure 4 As shown, the read and write parts of this DDR4 read / write state machine are parallel. When a channel completes a write operation (wr_ddr4_over[i] is high), the host computer receives an interrupt signal and initiates a read operation. The read data wait state MEM_READ_ADDR_WAIT is interrupted, and DDR4 sequentially enters the read data address state MEM_READ_ADDR and the read data state MEM_READ_DATA.

[0122] Reading DDR4 data is the reverse of writing. However, in a read operation, complex arbitration logic is not required; instead, all data in the corresponding channel is read at once. Due to the large data volume, a single read operation may take a considerable amount of time. Therefore, DMA (Direct Memory Access) is used for data reading. This method can significantly reduce the resource consumption of the host computer's CPU, as the CPU only needs to wait for the DMA to complete the data transfer before proceeding with subsequent data processing.

[0123] The DMA is configured to write data to the host computer's memory, so it is an S2MM direction, which is a write direction. The internal data stream width is set to 128 bits, which is consistent with the width of the FPGA's memory read, thus improving communication efficiency.

[0124] To better integrate with DMA and improve data transfer efficiency, a FIFO (First-In, First-Out) approach is used for data caching. The DDR4 management logic reads data from the memory segment of the corresponding readable channel and writes it into the corresponding RD_FIFO. Finally, the user initiates DMA via PCIe to read data from the corresponding channel.

[0125] The read operation also uses a burst method, with each burst reading 128 × 16 = 2048 bytes. Similar to the write operation, the address needs to be offset by a corresponding length after each burst read to ensure continuous and accurate data reading. The difference between the read and write operations is that the read operation performs multiple burst reads continuously within a channel. After reading all the data in that channel at once, it begins reading the data from the next channel that has completed a write operation.

[0126] After reading the data of a certain channel, according to the number of interrupts recorded by the interrupt counter in step S5, data is read from all readable channels that triggered interrupts in sequence until all readable channels have completed the read operation, and DDR4 returns to the idle state IDLE.

[0127] In summary, the overall system logic is as follows: Figure 2 As shown.

[0128] exist Figure 2 In all channels, the data flow process is consistent. User data is written to WR_FIFO_CHAN_n in the form of WR_FIFO, and then enters the DDR4 address segment n inside the DDR4 memory via the DDR4 arbitration logic. Subsequently, the data is read from the corresponding memory segment by the DDR4 read management logic and written to the corresponding RD_FIFO. Finally, the user initiates DMA via PCIe to read the data from the corresponding channel.

[0129] Meanwhile, the DDR4 write arbitration logic needs to send a write completion signal to the interrupt manager. After a channel completes AD sampling and write operations, an interrupt for the corresponding channel is triggered, and the interrupt manager sends an interrupt signal to the host computer. Upon receiving the interrupt signal, the host computer queries the status parameters of the interrupt manager to determine the corresponding channel number and reads the data from the memory of that channel.

[0130] In this invention, DDR4 is divided into 30 channels, which indirectly enables simultaneous reading and writing of 30 channels, which were originally unable to be read and written at the same time. That is, when one channel is writing data, another channel can be reading data. Each channel can start reading operation as soon as it completes the write operation, without being affected by other channels. This method greatly improves the data throughput of DDR4 and significantly improves the utilization rate of DDR4.

[0131] The following test cases were used during laboratory testing:

[0132] Test conditions: 30-channel A / D converter, 4MHz sampling rate, each A / D converter has two channels, each 16-bit, and the number of samples per pass is set to 0x800000 = 8,388,608. Therefore, the amount of data generated per pass is approximately 30 × 2 × 16 / 8 × 8388608 = 1,006,632,960, which means each pass generates 1GB of data. The data sampled per second is 30 × 4 × 2 × 16 / 8 = 420MB.

[0133] Through experimental testing, performance data for DDR4 multi-data channels were obtained. Multi-channel read / write speed test results show that each channel can achieve a high data transfer rate, meeting design requirements. Multi-channel parallel read / write test results show that as the number of channels increases, the overall data transfer rate of the system significantly improves, realizing the advantages of parallel data transfer. Simultaneously, the accuracy of data transfer was guaranteed under different data volumes and read / write frequencies, verifying the reliability of the design.

[0134] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores at least one instruction, at least one program, code set or instruction set, and the at least one instruction, the at least one program, the code set or instruction set is loaded and executed by the processor to implement the FPGA-based DDR4 multi-channel data arbitration transmission method.

[0135] The present invention also provides a computer-readable storage medium storing at least one piece of program code, which is loaded and executed by a processor to implement the FPGA-based DDR4 multi-channel data arbitration transmission method.

[0136] In summary, this invention provides a method, system, device, and medium for DDR4 multi-channel data arbitration transmission based on FPGA, aiming to handle complex situations with large data volumes. This invention innovatively integrates multi-channel data with DDR4 memory, realizing data transmission and reception functions for corresponding channels. Through a carefully designed and reasonable arbitration strategy, combined with an interrupt handling mechanism, bandwidth resources are fully utilized to complete the coordinated work of various modules. This invention deeply explores the potential performance of FPGA, thereby achieving efficient collaborative operation between modules, comprehensively achieving efficient acquisition, stable storage, and high-speed transmission of multi-channel data.

[0137] Taking this preferred embodiment as an example, each AD sampling chip has a sampling rate set to 4MHz, contains two sampling channels, and each channel has a bit width of 16 bits. Calculations show that a single AD sampling chip can collect up to 16MB of data per second. When there are 30 such channels in the system, the amount of data generated per second will rise to 480MB. Therefore, it can be deduced that an AD sampling board can generate as much as 4.8GB of data in 10 seconds. Such a massive amount of data is difficult to store directly on a conventional hard drive or other common storage spaces; therefore, using DDR4 memory for data processing becomes a necessary and efficient choice.

[0138] Under the architecture of this invention, all channels can simultaneously initiate sampling operations, and then the sampled data is stored efficiently and rationally in their respective storage spaces. Each channel operates independently, with no inter-channel interference. Furthermore, the system can quickly respond to read requests initiated by the host computer, effectively solving the challenging problems posed by massive data volumes and bandwidth sharing. This invention employs a multi-channel parallel architecture, where each channel can independently perform data read and write operations. By designing independent DDR4 controllers within the FPGA and establishing connections with different AD sampling channels, smooth transmission of multi-channel data is successfully achieved. All control processes related to acquisition, storage, and transmission require no external intervention and do not rely on CPU intervention in internal operations. The CPU only needs to issue start commands and respond to termination interrupts. Therefore, each channel's controller bears the responsibility of managing a series of key operations such as address generation, command sending, and data caching for its respective channel. This innovative architecture fully leverages the bandwidth potential of DDR4 memory, significantly improving the parallel processing capability of data transmission.

[0139] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0140] In the description of this invention, it should be understood that the terms "center," "height," "thickness," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0141] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0142] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0143] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. An FPGA-based DDR4 multi-lane data arbitration transmission method, which is implemented based on a DDR4 multi-lane data arbitration transmission system, the DDR4 multi-lane data arbitration transmission system comprising: FPGA; Multiple AD sampling chips are provided, all of which are connected to the FPGA; Multiple DDR4 chips are configured, all connected to the FPGA. A host computer is connected to the FPGA; characterized in that it includes: S1. Design a multi-channel architecture to form N data transmission channels, wherein the N data transmission channels are independent of each other; S2. Set the cache area; S3, AD sampling and buffering; S4. Write data to DDR4 through the write arbitration logic, find the channel with the largest sampled data volume and meet the write conditions, and only this channel writes data to DDR4 in each write operation; wherein, meeting the write conditions means that the readable data volume of the channel is greater than or equal to the burst length, and the burst length is the amount of data continuously transmitted in a burst transmission. S5. Locate the readable channel through interrupt management logic; S6. Read data from DDR4 through the read channel management logic, and read data from all readable channels in sequence.

2. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 1, characterized in that, This includes designing a DDR4 read / write state machine for read / write control, wherein the DDR4 read / write state machine includes the following states: The IDLE state is used to monitor read and write status in real time and enter the corresponding read and write process based on different state transition conditions. The write address status MEM_WRITE_ADDR identifies the write address in DDR4 before the write operation; The write data state is MEM_WRITE_DATA, in which data is written to DDR4; The read wait state MEM_READ_ADDR_WAIT indicates that after the host computer initiates a read operation, it waits for the channel to become available. The read address status is MEM_READ_ADDR, which identifies the corresponding address in DDR4 before the read operation. The data read status is MEM_READ_DATA, which reads DDR4 data from the corresponding address.

3. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 2, characterized in that, Step S1 specifically involves: The storage space of the multiple DDR4 chips is divided into N memory segments, corresponding to N AD sampling chips, forming N one-to-one data transmission channels; N independent DDR4 controllers are designed on the FPGA, and each controller is connected to a different memory segment in the DDR4 storage space. Each DDR4 controller manages its own channel independently.

4. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 3, characterized in that, Step S2 specifically involves: Each AD sampling chip has a WR_FIFO added to it, and multiple DDR4s share a unified RD_FIFO, which is added to the FPGA and connected to all DDR4s.

5. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 4, characterized in that, Step S3 specifically includes the following steps: S3.

1. Data is acquired through an AD sampling chip; S3.2 When AD sampling is successful, control the WR_FIFO of the corresponding channel to open and write the sampled data into the WR_FIFO for buffering.

6. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 5, characterized in that, Step S3.1 specifically includes the following steps: S3.1.1 After the host computer issues the sampling start command and sets the sampling length requirement, the AD sampling chip enters the sampling wait state AD_SPI_WAIT from the initial state AD_SPI_IDLE, and sends a reply signal to the host computer to indicate that sampling can be started. S3.1.2 After sending the reply signal, the AD sampling chip enters the state of preparing to send the command code. In this state, the host computer sets the parameters of the AD sampling chip and sends the sampling setting command. Then the AD sampling chip enters the state of sending the command code, in which the sampling setting command is written. S3.1.3, the AD sampling chip enters the data reception state AD_SPI_START_DATA, and then the host computer starts AD sampling. The AD sampling chip enters the data reception state AD_SPI_DATA and reads back the sampled data via SPI.

7. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 6, characterized in that, The parameter setting in step S3.1.2 is completed in two steps, specifically as follows: After sending a response signal, the AD sampling chip enters the state of preparing to send the first command code (AD_SPI_START_01). At this time, the host computer receives the response signal, clears the sampling start command, and prepares to send the sampling setting command. In this state, the host computer sets the functional parameters of the AD sampling chip. After the setting is completed, the host computer sends the sampling setting command, and the AD sampling chip enters the state of sending the first command code (AD_SPI_CMD_01) and begins to write the corresponding sampling setting command via SPI. The AD sampling chip starts up in the preparation state AD_SPI_START_02 to send the second command code. In this state, the host computer performs identification and hardware module management and control of the AD sampling chip. Subsequently, the AD sampling chip enters the state of sending the second command code AD_SPI_CMD_02 and starts SPI to write the second sampling setting command.

8. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 4, characterized in that, Step S4 specifically includes the following steps: S4.1, During the write data preparation stage, DDR4 is in the idle state (IDLE). The WR_FIFO status is monitored through the write arbitration logic, and the amount of readable data given in the N-way WR_FIFO is monitored in real time. S4.2 Find the channel with the largest amount of sampled data, and obtain the channel number max_index and the readable data size max_value of the channel with the largest amount of data. S4.3 Determine whether the channel with the largest amount of selected sampled data meets the writing conditions. If the writing conditions are met, proceed to step S4.

4. If the writing conditions are not met, proceed directly to step S4.

5. S4.4 Determine the write address of the selected channel's data in DDR4 and write the data to that write address in DDR4, and track the starting position of the next data write for that channel in real time; S4.

5. Repeat steps S4.1-S4.4 to form a loop until the write stop condition is met, and DDR4 returns to the idle state (IDLE).

9. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 8, characterized in that, The specific steps for finding the channel with the largest amount of sampled data are: If a channel is not full, select the channel with the largest data volume; if there is more than one channel with the largest data volume, select the channel with the smaller channel number.

10. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 8, characterized in that, Step S4.3 specifically includes: Based on the channel number max_index and the readable data volume max_value of the currently selected channel output in step S4.2, determine whether max_value is greater than or equal to the burst length wr_burst_len. If max_value is greater than or equal to the burst length, it means that the readable data volume of the current maximum data volume channel meets the write condition. Then proceed to step S4.4, and DDR4 changes from IDLE state to MEM_WRITE_ADDR state. If the maximum data volume of the channel is less than the burst length wr_burst_len, it means that there is no channel with enough data to perform a burst write. DDR4 remains in the idle state IDLE and proceeds directly to step S4.

5. The burst length is calculated based on the number of data units transmitted in each transmission, which is set to a fixed value, and the bit width of DDR4.

11. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 8, characterized in that, The data is written to DDR4 using a burst method, writing a burst length of data at once. The specific details of tracking the starting position of the next data write to this channel in real time are as follows: If there is still residual data in the WR_FIFO of the channel, the next write address of the channel needs to be updated. Each write address needs to be offset according to the burst length. next_wr_burst_addr[i] is used to record the starting address of the next burst write of the corresponding channel. Add the address offset corresponding to the burst length wr_burst_len to next_wr_burst_addr[i] to ensure that the next write operation starts from the correct address. At the same time, set the channel write completion status flag wr_ddr4_over[i] to the first level to indicate that the DDR4 write operation of the channel has not yet been completed.

12. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 8, characterized in that, The condition for stopping writing is met when the amount of data in all channels is less than the length of a single burst.

13. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 8, characterized in that, In step S4.5, when DDR4 is in the IDLE state, if the WR_FIFO of some channels is empty, it means that the channel has been completed. Then, the address and status variables related to the channel are reset through a reset operation, so that the channel can restart a new sampling and writing operation. Specifically, next_wr_burst_addr[i] is reset to its initial value, and the channel write completion status flag wr_ddr4_over[i] is set to the second level, indicating that the write operation of the channel has been completed.

14. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 4, characterized in that, Step S5 specifically includes the following steps: S5.1 The channel that has completed the write operation sends a signal to the interrupt manager, which is set in the FPGA; S5.2 The interrupt manager outputs an interrupt signal to notify the host computer that a channel has completed the write operation; S5.3 After receiving the interrupt signal, the host computer locates the readable channel through the FPGA and then starts the memory read operation of the corresponding channel.

15. The FPGA-based DDR4 multi-channel data arbitration transmission method as described in claim 4, characterized in that, Step S6 specifically involves: Data is read from the memory segment of the readable channel, written to the corresponding RD_FIFO, and then DMA is used to read the data from that channel. The read operation adopts a burst mode, performing multiple burst reads continuously within a channel. After reading all the data in the channel at once, data is read from all readable channels in sequence until all readable channels have completed the read operation, at which point the DDR4 returns to the IDLE state.

16. A DDR4 multi-channel data arbitration transmission system based on FPGA, characterized in that, For implementing the arbitration transmission method as described in any one of claims 1 to 15, the arbitration transmission system comprises: an FPGA; N AD sampling chips, all connected to the FPGA; multiple DDR4 chips, all connected to the FPGA; and a host computer connected to the FPGA. The storage space of the multiple DDR4 chips is divided into N memory segments, corresponding to N AD sampling chips, forming N one-to-one data transmission channels; the FPGA includes N independent DDR4 controllers, which are respectively connected to different memory segments in the DDR4 storage space.

17. A computer device, characterized in that, The method includes a memory and a processor, wherein the memory stores at least one instruction, at least one program, a code set, or an instruction set, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the FPGA-based DDR4 multi-channel data arbitration transmission method as described in any one of claims 1 to 15.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one piece of program code, which is loaded and executed by a processor to implement the FPGA-based DDR4 multi-channel data arbitration transmission method as described in any one of claims 1 to 15.

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