Register access signal conversion and transmission methods, chips and on-chip systems

Abstract

This disclosure relates to a register access signal conversion and transmission method, a chip, and a system-on-a-chip (SoC). The method includes: receiving a register access request timing signal from the APB interface of a local chip; generating a UCIe sideband register access request data packet based on the register access request timing signal; and sending the UCIe sideband register access request data packet to a destination layer. The chip includes a conversion module located in the chip's protocol layer, used for: receiving the register access request timing signal from the APB interface; generating a UCIe sideband register access request data packet based on the register access request timing signal; and sending the UCIe sideband register access request data packet. This disclosure facilitates SoC integration, improves the compatibility of SoCs composed of chiplets, enables SoCs to easily perform register access within local chiplets and across chips, and implements the functions specified by the UCIe protocol sideband.

Description

Technical Field

[0001] This disclosure relates to the field of chip data transmission technology, and in particular to a register access signal conversion and transmission method, a chip, and a system-on-a-chip. Background Technology

[0002] As Moore's Law slows down, chiplet technology has become an important technological approach to continuously improve the integration and computing power of System on Chip (SoC).

[0003] A system-on-a-chip (SoC) integrates multiple functional modules onto a single chip, while chiplet technology breaks these functional modules down into multiple chiplets, which are then integrated together using advanced packaging techniques. Due to their independent design, the individual chiplets that make up a SoC may have different communication protocols. The incompatibility between these different communication protocols limits the application of chiplet technology in SoCs and hinders SoC design. Summary of the Invention

[0004] In view of this, this disclosure provides a register access signal conversion and transmission method, a chip, and a system-on-a-chip to improve the compatibility of the chip's communication connection protocol, thereby helping to reduce the design difficulty of the system-on-a-chip.

[0005] The technical solution disclosed herein is implemented as follows: According to one aspect of the embodiments of this disclosure, a register access signal conversion and transmission method is provided, including: Receive APB protocol register access request timing signals from the APB interface of the local chip; Based on the APB protocol register access request timing signal, generate a UCIe sideband register access request data packet; Send the UCIe sideband register access request data packet to the destination layer; Receive and parse the UCIe sideband register access complete data packet, and generate an APB protocol register access complete timing signal based on the UCIe sideband register access complete data packet. The UCIe sideband register access complete data packet is associated with the UCIe sideband register access request data packet. The UCIe sideband register access complete data packet is associated with the APB protocol register access request timing signal. The UCIe sideband register access complete data packet and the UCIe sideband register access request data packet belong to the same data packet corresponding to the same APB protocol access. The APB protocol register access completion timing signal is sent through the APB interface.

[0006] In one possible implementation, the destination register of the APB protocol register access request timing signal is any one of the local chip adaptation layer register, the local chip physical layer register, the remote chip physical layer register, and the remote chip adaptation layer register.

[0007] In one possible implementation, when the destination register of the APB protocol register access request timing signal is the local chip adaptation layer register, sending the UCIe sideband register access request data packet to the destination layer includes: The UCIe sideband register access request data packet is sent to the local chip's adaptation layer via the FDI interface.

[0008] In one possible implementation, when the destination register of the APB protocol register access request timing signal is the local chip physical layer register, sending the UCIe sideband register access request data packet to the destination layer includes: The UCIe sideband register access request data packet is sent to the local chip's adaptation layer via the FDI interface, and the adaptation layer forwards the UCIe sideband register access request data packet to the local chip's physical layer via the RDI interface.

[0009] In one possible implementation, when the destination register of the APB protocol register access request timing signal is the remote chip physical layer register or the remote chip adaptation layer register, sending the UCIe sideband register access request data packet to the destination layer includes: Write the UCIe sideband register access request data packet into the mailbox register for remote chip register access.

[0010] In one possible implementation, the mailbox register is located in the adapter layer of the local chip.

[0011] In one possible implementation, when the destination register of the APB protocol register access request timing signal is a local chip protocol layer register, the method further includes: The local chip protocol layer registers can be accessed directly through the APB interface.

[0012] In one possible implementation, the local chip includes a protocol layer, an adaptation layer, and a physical layer as defined by the UCIe protocol. The APB interface is connected to the protocol layer; The protocol layer and the adaptation layer communicate through the FDI interface of the UCIe protocol, and the adaptation layer and the physical layer communicate through the RDI interface of the UCIe protocol.

[0013] In one possible implementation, the destination register address in the UCIe sideband register access request data packet is consistent with the destination register address in the APB protocol register access request timing signal, and the data information in the UCIe sideband register access request data packet is consistent with the data information in the APB protocol register access request timing signal.

[0014] According to another aspect of embodiments of this disclosure, a chip is provided, the chip including a UCIe interface defined by the UCIe protocol and an APB interface defined by the APB protocol; wherein... The chip also includes: The conversion module, located in the protocol layer of the UCIe interface, is used for: Receives APB protocol register access request timing signals from the APB interface; generates UCIe sideband register access request data packets based on the APB protocol register access request timing signals; and sends the UCIe sideband register access request data packets; and In response to the reception of the UCIe sideband register access complete data packet, an APB protocol register access complete timing signal is generated based on the UCIe sideband register access complete data packet, wherein the UCIe sideband register access complete data packet is associated with the UCIe sideband register access request data packet; the APB protocol register access complete timing signal is sent through the APB interface.

[0015] According to another aspect of the embodiments of this disclosure, an on-chip system is provided, comprising: At least one small chip in an integrated package; Wherein, at least one of the at least one small chip uses the chip described above.

[0016] As can be seen from the above scheme, the register access signal conversion and transmission method, chip, and system-on-a-chip disclosed herein simplify the complexity of the data link design for a system-on-a-chip composed of chiplets based on the APB protocol by converting the APB protocol register access request timing signals received by the APB interface of the local chip into UCIe sideband register access request data packets for transmission. This helps reduce the design difficulty of the data link, thereby reducing the design difficulty of the system-on-a-chip and improving the compatibility of the APB and UCIe protocols within the same system-on-a-chip. When different chiplets within the system-on-a-chip are designed independently by different design teams and the chiplets support the UCIe protocol, the register access signal conversion and transmission method disclosed herein can be used in specific chiplets within the system-on-a-chip according to design requirements, thus helping to leverage the advantages of both the APB and UCIe protocols simultaneously within the system-on-a-chip. Furthermore, using the chip disclosed herein, only a conversion module responsible for translating and converting signals between the APB protocol and the UCIe protocol needs to be set in the protocol layer defined by the chip's UCIe protocol. This enables the APB protocol to send register access requests to the local chip even when the APB protocol only accesses the protocol layer. At the same time, based on the UCIe protocol, the local chip can also send register access requests to a remote chip via the APB protocol. Because the chip's APB protocol only accesses the protocol layer defined by the UCIe protocol and not the adaptation layer and physical layer defined by the UCIe protocol, the chip does not need to design related links for APB protocol access to the adaptation layer and physical layer. This helps to reduce the complexity and difficulty of data link design within the chip, thereby reducing the design difficulty of the chip. It also enables the on-chip system to easily perform register access for local chips and across chips, and implement the functions specified by the UCIe protocol sideband. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the chip structure of the UCIe protocol in related technologies; Figure 2 This is a schematic flowchart illustrating a register access signal conversion and transmission method according to an illustrative embodiment; Figure 3 This is a schematic diagram of register access timing for the APB interface according to an illustrative embodiment; Figure 4 This is a schematic diagram of the UCIe sideband register access request packet format according to an illustrative embodiment; Figure 5 This is a schematic diagram illustrating the UCIe sideband register access completion packet format according to an illustrative embodiment; Figure 6This is a schematic diagram of the remote chip register access process of the UCIe protocol; Figure 7 This is a schematic diagram of a specific scenario using the register access signal conversion and transmission method according to an embodiment of this disclosure; Figure 8 This is a timing diagram of local chip register access, taking a read operation as an example; Figure 9 This is a schematic diagram illustrating the detailed process of register access for a remote chip according to an illustrative embodiment. Figure 10 This is a schematic diagram of a chip according to an illustrative embodiment; Figure 11 This is a schematic diagram of the register access method of the APB protocol in related technologies. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0020] In a system-on-a-chip, register configuration is required to implement the corresponding chip functions, and register access is achieved using a specific protocol.

[0021] The APB (Advanced Peripheral Bus) protocol is a bus protocol used in on-chip systems, commonly for register access between various modules. The APB protocol is part of the AMBA (Advanced Microcontroller Bus Architecture) protocol and is primarily used to connect low-speed peripherals (such as UART (Universal Asynchronous Receiver-Transmitter)). 2 In a system-on-a-chip (SoC) bus system (such as C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), etc.), it enables the connection between master and slave devices through a simple interface design. In SoCs, the APB protocol is also commonly used for register access in various modules.

[0022] UCIe (Universal Chipplet Interconnect Express) is a protocol for communication between chiplets, designed to achieve high-speed, efficient communication between chiplets within a package. It supports various upper-layer protocols, such as PCIe (Peripheral Component Interconnect Express), CXL (Compute Express Link), and custom streaming protocols, to meet different communication needs. Notably, UCIe proposes a novel method using sidebands for information exchange between the protocol layer, adaptation layer, and physical layer, as well as between dies. This includes register access via sidebands, enabling hierarchical register access within the local die and cross-die register access. This facilitates the configuration and management of registers at different levels without consuming main link data bandwidth.

[0023] Figure 1 This is a schematic diagram of the chip structure for the UCIe protocol in related technologies. For example... Figure 1 As shown, the UCIe protocol specifies that a chip contains a three-layer structure consisting of a protocol layer, an adapter layer, and a physical layer.

[0024] The protocol layer, the top layer of the UCIe protocol architecture, primarily defines the rules and protocol formats for data exchange, ensuring seamless interoperability between chiplets from different manufacturers. The protocol layer supports multiple mainstream protocols, including PCIe 6.0, CXL 2.0 / 3.0, and user-defined streaming protocols. These protocols transmit data via Flit mode for efficient, low-latency communication. The protocol layer ensures compatibility between different protocols by encapsulating data into Flits for efficient transmission between the adaptation and physical layers. In streaming mode, the protocol layer is entirely user-defined. The protocol layer interacts with the adaptation layer through the FDI (Flit-aware D2D Interface), passing the encapsulated Flit data to the adaptation layer. The protocol layer participates in protocol capability negotiation during link initialization, determining the supported protocols and modes. By supporting multiple protocols and custom modes, the protocol layer provides flexibility and compatibility for chiplet interconnection, enabling chiplets with different functionalities to communicate efficiently within a standardized framework.

[0025] The adaptation layer is a logical layer in the UCIe protocol, located between the protocol layer and the physical layer. Its main function is to adapt data fragments encapsulated by the protocol layer to the physical layer for transmission, while also managing link state, power management, and parameter negotiation. The adapter is the concrete implementation of the adaptation layer, which can be understood as its physical entity. The adapter is responsible for handling various functions of the adaptation layer, such as CRC calculation, retransmission mechanisms, and link state management. In actual system configurations, one adaptation layer can support multiple protocol stacks. These stacks can share the same adapter through arbitration and multiplexing mechanisms (Arb / Mux) within the adaptation layer. For example, one adapter can bridge multiple protocol stacks and support multiple physical layer modules. In multi-module configurations, the adapter's functionality can be extended to multiple modules.

[0026] The physical layer is the lowest layer responsible for implementing die-to-die (D2D) electrical connections and data transmission. Its main function is to convert the data signals provided by the adapter layer into electrical signals suitable for transmission over the physical link, and then restore these signals to data at the receiving end. The physical layer is responsible for converting the data signals provided by the adapter layer into electrical signals suitable for transmission over the physical link. It handles signal encoding, modulation, demodulation, and decoding operations, and also manages signal integrity, including timing, amplitude, and noise control. The physical layer initializes and trains the link during startup to ensure its reliability and performance, including: electrical parameter negotiation (negotiating the link's electrical characteristics, such as voltage swing and pre-emphasis); clock recovery (restoring the clock signal from the transmitting end at the receiving end); and link training (calibrating the link's electrical characteristics through training sequences to ensure data transmission accuracy). The physical layer supports multiple low-power states to reduce power consumption, such as L1 / L2 low-power states: when not transmitting data, the physical layer can enter a low-power mode to save energy. The protocol and adaptation layers also support low-power states. When there is no data transmission, all three layers of UCIe support low-power states and need to negotiate with the peer die. Once it is confirmed that neither the local nor the peer is transmitting data, the physical layer, adaptation layer, and protocol layer sequentially enter low-power modes. Dynamic power management: dynamically adjusts the power state based on link usage. The physical layer supports parallel transmission of multiple physical links to improve data transmission bandwidth and efficiency. The physical layer is a key part of the UCIe architecture for implementing chip-to-chip interconnection. It is directly responsible for the transmission of electrical signals and the reliability of the links, ensuring that data can be transmitted efficiently and accurately between different chips. The design and implementation of the physical layer directly affect the performance, power consumption, and reliability of the entire system. The implementation of the physical layer typically depends on specific packaging technologies and electrical characteristics. For example, standard packaging and advanced packaging, such as 2.5D and 3D packaging technologies, can provide higher bandwidth and lower power consumption. The design of the physical layer needs to consider a variety of factors, including signal integrity, power consumption, packaging technology and cost. By optimizing the physical layer design, the performance and reliability of UCIe systems can be significantly improved.

[0027] Specifically, the protocol layer and the adaptation layer communicate and transmit data through the FDI (Flit-aware D2D Interface, chip-to-chip interconnection interface) interface, while the adaptation layer and the physical layer communicate and transmit data through the RDI (Raw D2D Interface, raw chip-to-chip interconnection interface) interface.

[0028] The FDI interface, defined in the UCIe standard, sits between the protocol layer and the adaptation layer. It supports different fragmentation sizes, such as 68B and 256B, to accommodate various transmission requirements. The FDI interface supports mainband data transmission signals, sideband data transmission signals, and control handshake signals. It allows multiple protocol stacks to share the same D2D adapter, achieving time-division multiplexing of the adapter and physical layer through arbitration and multiplexing mechanisms. The FDI interface plays a crucial bridging role in the UCIe architecture, enabling efficient data transmission between the protocol layer and the adaptation layer, and improving system flexibility and energy efficiency by supporting fragmentation transmission and link state management for multiple protocols.

[0029] The RDI interface is an interface defined in the UCIe standard, located between the adaptation layer and the physical layer. The RDI interface is responsible for transmitting data from the adaptation layer to the physical layer and receiving data from the physical layer. The RDI interface primarily processes raw data streams and does not involve protocol-aware operations; that is, it does not handle the specific protocol format of the data but transmits the data directly in its raw form. The RDI interface is designed to achieve low-latency and high-bandwidth data transmission to meet the needs of inter-chip interconnection.

[0030] The RDI interface supports mainband data transmission signals, sideband data transmission signals, and control handshake signals. The RDI interface is one of the key interfaces in the UCIe architecture for achieving efficient chip-to-chip interconnection. Through close cooperation with the adaptation layer and physical layer, it ensures fast and reliable data transmission between different chips.

[0031] Although the three-layer structure of protocol layer, adaptation layer, and physical layer is a logical layer in the UCIe architecture, each layer in a UCIe chip contains different registers. These registers have distinct functions. Protocol layer registers primarily manage protocol-related configuration and status information, including: Status management: tracking the protocol layer's state, such as whether the link is active or has any outstanding transactions; Register access: the protocol layer can access the adaptation and physical layers via sideband mechanisms to perform cross-layer configuration and status queries. Adaptor layer registers focus on link management and data transmission configuration, including: Link state management: managing the link's state, such as whether the link is in initialization, training, or low-power states; Protocol adaptation parameters: storing protocol adaptation-related parameters, such as Flit size and protocol conversion parameters, which are exchanged with the peer chip via sideband; Register access: adaptor layer registers can be accessed by the protocol layer via sideband mechanisms, and the adaptor layer can also access physical layer registers via sideband mechanisms. Physical layer registers are primarily used to manage the electrical characteristics and link status of physical links, including: electrical parameter configuration: storing electrical parameters related to the physical link, such as voltage swing, pre-emphasis, clock recovery, etc.; link training and management: storing link training status information, such as training sequences, link quality, etc.; link status management: performing link initialization, link training, low-power management, etc.; register access: physical layer registers can be accessed by the adaptation layer and protocol layer through sideband mechanisms for link initialization, debugging, and status querying. The sideband mechanism in the UCIe architecture is used to transmit register access requests and link management messages between different layers. Through sidebands, the protocol layer, adaptation layer, and physical layer can achieve cross-layer register access and link management.

[0032] Currently, the APB protocol is widely used in digital chips for register access. Its advantages lie in its simplicity, versatility, and mature design and implementation. However, its disadvantage is that it requires the allocation of all register addresses within the SoC during the SoC design phase, accessing registers via addressing. However, on Chiplet, the APB protocol cannot directly access registers on other dies across different dies. In an SoC, if different dies are produced by different design and manufacturing entities, it's difficult to uniformly plan all registers at the system level during design, making it impossible to obtain the address allocation information for all registers within the SoC. In this case, the SoC cannot directly access registers at all levels within each die through the APB interface.

[0033] In the UCIe protocol, local chip adapter layer registers and local chip physical layer registers can be accessed via sidebands by sending dedicated sideband data packets from the protocol layer. The UCIe protocol stipulates that protocol layer registers do not support access via sidebands; protocol layer registers are limited to internal access within the local chip and cannot be directly accessed via sidebands. If access to remote chip protocol layer registers is required, it must be achieved indirectly through a mailbox mechanism. Different chips can achieve register access at different levels and across chips via sidebands as long as they meet the UCIe protocol specifications. However, the implementation is complex and not convenient for direct use at the SoC system level.

[0034] The mailbox mechanism in the UCIe protocol is a mechanism for indirectly accessing remote chip registers. In the UCIe protocol, the protocol layer cannot directly access the registers of a remote chip via sidebands; instead, it achieves this indirectly through the mailbox mechanism. The mailbox mechanism allows one chip, such as the master die, to send a register access request to another chip, such as the slave die, and receive a response. The working principle of the mailbox mechanism is as follows: 1. Request Initiation: The local chip protocol layer (master chip protocol layer) writes content to the mailbox register of the local chip adapter layer (master chip adapter layer) through the FDI sideband interface, according to the request type. The request includes information such as the type of register access (e.g., read or write) and the target address; 2. Adapter Layer Processing: After recognizing the content written to the mailbox register, the local chip adapter layer generates a remote chip sideband register access request data packet and sends the request to the local chip physical layer through the RDI sideband interface. The local chip physical layer receives and converts the request into serial data, which is then transmitted via the UCIe link sideband (UCIe Link). The process is as follows: 1. **Sideband (Slave Chip) Link:** The data is sent to the remote chip via the sideband link. 2. **Remote Processing:** The remote chip's physical layer receives the serial data and converts it into a remote chip sideband register access request data packet. Then, it transmits the remote chip sideband register access request data packet to the remote chip adaptation layer via the RDI sideband interface. The remote chip adaptation layer accesses the corresponding registers according to the remote chip sideband register access request data packet and returns the access result to the remote chip physical layer. 3. **Result Return:** The remote chip physical layer converts the access result into serial data and sends it back to the master chip via the UCIe link sideband link. The local chip physical layer (master chip physical layer) receives the serial data and parses it into sideband packet data representing the access result. Then, it transmits the sideband packet data to the local chip adaptation layer via the RDI sideband interface. The local chip adaptation layer writes the sideband packet data into the mailbox register and notifies the local chip protocol layer via the FDI sideband interface. The UCIe protocol specifies that the key mailbox registers involved in the mailbox mechanism include the Sideband Mailbox Index register, the Sideband Mailbox Data register, the Mailbox Status register, and the Mailbox Control register. The sideband mailbox index register is used to specify the access type (e.g., 32 / 64-bit, memory / configuration, read / write), address, etc. The sideband mailbox data register is used to store the data to be written or the result of the read operation. The sideband status register indicates the status of the access result, such as success or access failure. The mailbox control register is used to trigger sideband register access requests.The characteristics of the Mailbox mechanism include: 1. No external system intervention required in UCIe, such as the CPU (Central Processing Unit), improving communication efficiency; 2. High efficiency and flexibility: The Mailbox mechanism enables efficient access to remote chip registers while maintaining system flexibility. The Mailbox mechanism is a key technology in the UCIe protocol for achieving cross-chip register access. Through the collaborative work of the adaptation layer and the physical layer, it enables indirect access to remote chip registers. Accessing remote chip registers via the Mailbox mechanism also avoids consuming mainband resources, reducing mainband load and improving communication efficiency.

[0035] APB and UCIe each have their own characteristics. The APB protocol is simple, with concise control logic. Read and write operations can be completed in as little as two clock cycles, without the need for complex wait cycles and response signals. Due to its simplicity, the APB interface is easy to implement and verify, making it suitable for connecting various low-speed peripherals. The UCIe protocol represents the trend in chiplet technology, but it is more complex. The register access method specified by UCIe is implemented using more complex sideband data packets and includes complex mechanisms such as cross-layer credit management, making its implementation more complex than APB and less conducive to on-chip system integration.

[0036] However, because APB relies on the allocation of all register addresses in the on-chip system during the design phase and accesses registers through addressing, if it is difficult to uniformly plan all registers at the system level during the design phase and thus cannot obtain the allocation information of all register addresses in the on-chip system, the on-chip system will not be able to directly access the registers in all levels of each die through the APB interface, resulting in the limitation of the APB interface.

[0037] As seen above, the APB protocol is used for register access, while the UCIe protocol is used for chiplet interconnection. If all register addresses in the on-chip system can be allocated during the design phase, then it is possible to access all UCIe-related registers using the APB protocol. However, as the scale of the on-chip system increases and the number of chiplets grows, it becomes increasingly difficult to allocate all register addresses in the on-chip system in advance during the design phase. Therefore, it becomes increasingly difficult to achieve access to all registers in the on-chip system using only the APB protocol. Thus, it is more recommended to use UCIe sideband register access to complete register access within UCIe.

[0038] In view of this, embodiments of the present disclosure provide a register access signal conversion and transmission method, a chip, and a system-on-a-chip to realize the conversion of sideband register access signals of the APB protocol and the UCIe protocol, so as to help improve the compatibility of the chip's communication connection protocol and at the same time help reduce the design difficulty of the system-on-a-chip.

[0039] Figure 2 This is a schematic flowchart illustrating a register access signal conversion and transmission method according to an illustrative embodiment. Figure 2 As shown, the register access signal conversion and transmission method mainly includes the following steps 201 to 203.

[0040] Step 201: Receive the APB protocol register access request timing signal from the APB interface of the local chip; Step 202: Generate a UCIe Sideband Register Access Request Packet based on the APB protocol register access request timing signal. Step 203: Send the UCIe sideband register access request data packet to the destination layer.

[0041] In an illustrative embodiment, the target layer includes at least one of the following: an adaptation layer of the local chip, a physical layer of the local chip, a physical layer of the remote chip, and a protocol layer of the remote chip.

[0042] Figure 3 This is a schematic diagram illustrating the register access timing of the APB interface according to an exemplary embodiment. Figure 3 As shown, in the register access timing of the APB interface: PCLK is the global clock signal. In this illustrative embodiment, PCLK is sampled on its rising edge. Figure 3 In the PENABLE signal, T0, T1, T2, T3, T4, T5, and T6 represent the rising edge positions of each PCLK cycle; PADDR is the target address signal used to specify the target address to be accessed. It remains stable during transmission and is ready when the PENABLE signal is active, ensuring the address is correctly identified during transmission. The PADDR signal plays a crucial role in both write and read operations and is a core component of the APB bus communication. PADDR represents a 32-bit address bus, supporting a maximum of 2... 32 Address space, Figure 3In this context, Addr1 represents the address content; PWRITE is the write control signal, used to indicate whether the current transfer operation is a write or read operation. PWRITE=1 indicates that the current operation is a write operation, and PWRITE=0 indicates that the current operation is a read operation; PSEL is the slave device select signal, used to indicate the target slave device of the current transfer operation. When the PSEL signal is high, it indicates that the master device is initiating a new transfer operation and the target is a slave device. In the APB bus system, there may be multiple slave devices connected to the bus. The PSEL signal, combined with the address range of the slave devices, can specify which slave device the current operation is targeting; PENABLE is the transfer enable signal, used to indicate whether the transfer operation has entered the data transmission phase. When PENABLE is low, it indicates that the current... During the Setup phase, the master device is preparing for a transfer operation, setting parameters such as PADDR (destination address) and PWRITE (transfer operation type). When PENABLE is high, it indicates that the device has entered the Access phase, and the master and slave devices begin actual data transfer. A high PENABLE signal marks the start of a new transfer operation. PWDATA is the write data signal, used to transfer data from the master to the slave device during a write operation in the APB protocol. The PWDATA signal is typically 32 bits wide, but the actual data width used can be adjusted according to specific design requirements. For example, some systems may use 8-bit, 16-bit, or 32-bit data widths. During a write operation, the PWDATA signal provides the data to be written simultaneously with the high PENABLE signal. Figure 3 Data1 represents the data content; PREADY is the ready signal, used by the slave device to indicate to the master device whether it is ready to complete the current read or write operation. If the PREADY signal is high, it means that the slave device is ready and the data transmission can be completed. If the PREADY signal is low, it means that the slave device is not ready and the master device needs to wait. The PREADY signal works in conjunction with the PENABLE signal to ensure that the data transmission between the master device and the slave device is synchronized.

[0043] remove Figure 3In addition to the signals shown, the APB interface signals also include PRDATA and PSLVERR. PRDATA is the read data signal, used to transfer data from the slave device to the master device during a read operation in the APB protocol. The width of the PRDATA signal is usually the same as the PWDATA signal, typically 32 bits, but can be adjusted to other widths (such as 8 bits, 16 bits, etc.) according to specific design requirements. During a read operation, the PRDATA signal provides the data read from the target address while the PREADY signal is high. PSLVERR is the slave device error signal, used by the slave device to report to the master whether an error occurred during the current transmission operation. If the PSLVERR signal is high, it indicates that the slave device detected an error, such as illegal address access, timeout, or other abnormal conditions. If the PSLVERR signal remains low, it indicates that the transmission operation was completed normally and no error was detected. The master device can decide whether to re-initiate the transmission operation or take other error handling measures based on the state of the PSLVERR signal.

[0044] In an illustrative embodiment, the timing signal interaction process of the APB interface when receiving a register access request may include the following: Write operation timing: First stage, Setup stage (T1 to T2): PSEL signal is pulled high to indicate the initiation of a new transmission, PWRITE signal is pulled high to indicate that this operation is a write operation, PADDR and PWDATA signals place the target address and the data to be written respectively, and PENABLE signal remains low; Second stage, Access stage (T2 to T3): PENABLE signal is pulled high to indicate the start of the data transmission stage, PREADY signal is pulled high by the slave device to indicate that the slave device is ready to receive data, and the data transmission is completed at time T3; Third stage, End stage (T3 and after): After the transmission is completed, PSEL and PENABLE signals are pulled low. If continuous transmission is required and the target slave device is the same, PSEL signal can remain high.

[0045] Read operation timing: Phase 1, Setup phase (T1 to T2): The PSEL signal goes high, indicating a new transfer is initiated; the PWRITE signal goes low, indicating this is a read operation; the PADDR signal sets the target address; and the PENABLE signal remains low. Phase 2, Access phase (T2 to T3): The PENABLE signal goes high, indicating the start of data transmission; the PREADY signal is pulled high by the slave device, indicating the slave device is ready to send data; the PRDATA signal provides valid data simultaneously with or after the PREADY signal goes high. Phase 3, End phase (T3 and later): After the transfer is complete, the PSEL and PENABLE signals go low. Error response: In write or read operations, if an error occurs (such as illegal address access or timeout), the slave device can indicate transmission failure by pulling the PSLVERR signal high in the last cycle of the transfer.

[0046] It can be seen that the timing design of the APB protocol is relatively simple, each transmission requires at least two clock cycles, and it does not support pipelined operation.

[0047] Figure 4 This is a schematic diagram illustrating the UCIe sideband register access request packet format according to an illustrative embodiment. For example... Figure 4 As shown, the fields mainly include Opcode, SrcID, DstID, CP, DP, Addr, BE, EP, Tag, and Data.

[0048] The Opcode field, or opcode field, is 5 bits wide and is used to indicate the data packet type and data width (e.g., 32-bit or 64-bit). For example: an Opcode field value of "00000" corresponds to a "32-bit memory read" type, indicating that 32 bits of data are read from the specified address; an Opcode field value of "00001" corresponds to a "32-bit memory write" type, indicating that 32 bits of data are written to the specified address; an Opcode field value of "00100" corresponds to a "32-bit configuration read" type, indicating that 32 bits of data are read from the configuration register; an Opcode field value of "00101" corresponds to a "32-bit configuration write" type, indicating that 32 bits of data are written to the configuration register; an Opcode field value of "01000" corresponds to a "64-bit memory read" type, indicating that 64 bits of data are read from the specified address; an Opcode field value of "01001 ... "Memory Write" indicates writing 64 bits of data to the specified address; an Opcode field value of "01100" corresponds to the type "64-bit Configuration Read", indicating reading 64 bits of data from the configuration register; an Opcode field value of "01101" corresponds to the type "64-bit Configuration Write", indicating writing 64 bits of data to the configuration register; an Opcode field value of "10000" corresponds to the type "Complete with No Data"; an Opcode field value of "10001" corresponds to the type "Complete with 32 Bits of Data"; an Opcode field value of "10010" corresponds to the type "Message with No Data"; an Opcode field value of "11001" corresponds to the type "Complete with 64 Bits of Data"; an Opcode field value of "11011" corresponds to the type "Message with 64 Bits of Data"; other values ​​for the Opcode field are reserved or extended operations for future expansion or other special operations.

[0049] The SrcID field, or source identifier field, is 3 bits wide. A SrcID field value of "000" indicates "Stack 0 Protocol Layer"; a SrcID field value of "001" indicates "D2D Adapter"; a SrcID field value of "100" indicates "Stack 1 Protocol Layer"; other values ​​of the SrcID field are reserved.

[0050] The DstID field, or Target Identifier field, is 3 bits wide. A DstID field value of "001" indicates "Inter-chip Adaptation Layer"; a DstID field value of "010" indicates "Physical Layer"; other values ​​of the DstID field are reserved.

[0051] The CP field, or Control Parity field, controls parity. It has a width of 1 bit and is the even parity field for all header parts except for the DP and CP fields.

[0052] The DP field, or Data Parity field, is a 1-bit field used to perform parity checks on the data payload of a data packet to verify the correctness of the data content.

[0053] The Addr field, also known as the Address field, is a 24-bit field. Different opcodes use this field differently; please refer to the relevant UCIe specification for details.

[0054] The BE field, or Byte Enables field, is the requested byte enable field. It is 8 bits wide. The BE field does not need to be contiguous. If the opcode is used for a 32-bit request, then BE[7:4] is reserved.

[0055] The EP field, or Error Poison field, is a data poisoning field with a width of 1 bit. If poisoning forwarding is enabled, the completer can poison the data when there is an internal error.

[0056] The Tag field, or tag field, is a 5-bit field used to uniquely identify each incomplete request. The Tag field is a 5-bit field generated by the requester, and it must be unique for all incomplete requests that require completion. The original requester uses the tag to associate the returned completion with the original request.

[0057] The Data field, also known as the data payload, has a width of 32 bits or 64 bits. It is the portion of the data packet used to transmit the actual data and is the core of the data packet. The Data field can also be called the payload, and its width can be either 32 bits or 64 bits depending on the opcode.

[0058] For example, in a UCIe system, if the sender needs to write 32-bit data "0x12345678" to a register on the receiver, the sender sets the Opcode field of the UCIe data packet to "00001" (indicating a 32-bit memory write), fills the data "0x12345678" into the Data field of the UCIe data packet, and sends the data packet. Upon receiving the data packet, the receiver recognizes this as a 32-bit write operation based on the Opcode field and writes the data from the Data field into the register at the target address. The Data field, by supporting various data widths and flexible data content, ensures efficient and flexible data transmission.

[0059] From the register access timing of the APB interface and the UCIe sideband register access request data packet described above, it can be seen that the APB signal contains the target address information corresponding to the PADDR signal, the transmission operation type information corresponding to the PWRITE signal, the write data content corresponding to PWDATA, and the read data content corresponding to PRDATA. Furthermore, the UCIe sideband register access request data packet contains the data packet type corresponding to the Opcode field, the address information corresponding to the Addr field, and the data content corresponding to the Data field. Therefore, the content of the PWRITE signal can be associated with the content of the Opcode field, the content of the PADDR signal can be associated with the content of the Addr field, and the content of the PWDATA and PRDATA signals can be associated with the content of the Data field. Based on this, the content of the APB interface received register access request timing signal can be translated into the content of the UCIe sideband register access request data packet and sent using the UCIe protocol. Therefore, in the illustrative embodiment, step 202 can further include: generating a corresponding UCIe sideband register access request data packet containing the same information content based on the information content carried in the APB protocol register access request timing signal.

[0060] In an illustrative embodiment, when the APB protocol register access request timing signal is a register write request, that is, when the PWRITE signal in the APB protocol register access request timing signal received by the APB interface is "1", a corresponding UCIe sideband register access request data packet containing the same information content is generated based on the information content carried in the APB protocol register access request timing signal. For example, this may specifically include: The transmission operation type information is obtained from the PWRITE signal in the APB protocol register access request timing signal (i.e., the APB protocol register write request timing signal) received from the APB interface, and the Opcode field content in the UCIe sideband register access request data packet is generated based on the transmission operation type information. The target address information is obtained from the PADDR signal in the APB protocol register access request timing signal (i.e., the APB protocol register write request timing signal) received from the APB interface, and the Addr field content in the UCIe sideband register access request data packet is generated based on the target address information. The write data content is obtained from the PWDATA signal in the APB protocol register access request timing signal (i.e., APB protocol register write request timing signal) received from the APB interface, and the Data field content in the UCIe sideband register access request data packet is generated based on the write data content. According to the UCIe protocol rules, generate the other field contents of the UCIe sideband register access request data packet. This UCIe sideband register access request data packet is a UCIe sideband register write request data packet.

[0061] In an illustrative embodiment, when the APB protocol register access request timing signal is a register read request, i.e., when the PWRITE signal in the APB protocol register access request timing signal received by the APB interface is "0", a corresponding UCIe sideband register access request data packet containing the same information content is generated based on the information content carried in the APB protocol register access request timing signal. This can specifically include, for example: The transmission operation type information is obtained from the PWRITE signal in the APB protocol register access request timing signal (i.e., the APB protocol register read request timing signal) received from the APB interface, and the Opcode field content in the UCIe sideband register access request data packet is generated based on the transmission operation type information. The target address information is obtained from the PADDR signal in the APB protocol register access request timing signal (i.e., the APB protocol register read request timing signal) received from the APB interface, and the Addr field content in the UCIe sideband register access request data packet is generated based on the target address information. According to the UCIe protocol rules, generate the contents of other fields in the UCIe sideband register access request data packet.

[0062] In an illustrative embodiment, step 202 can be implemented in hardware. In this illustrative embodiment, the UCIe sideband register access request data packet generated by the local chip is temporarily stored in the local chip's buffer. The local chip's buffer can be a hardware buffer implemented with hardware logic that conforms to the UCIe protocol requirements, and the local chip's buffer can be used to temporarily store the sideband data packet to be sent.

[0063] In an illustrative embodiment, sending the UCIe sideband register access request packet to the destination layer in step 203 is implemented based on the UCIe protocol.

[0064] The register access signal conversion and transmission method of this disclosure allows for the use of the APB protocol in one part of the on-chip system and the UCIe protocol in another part. An intermediate translation module or conversion module is used between the two to translate and convert the signals of these two protocols. This achieves compatibility between the two protocols on the same on-chip system, while leveraging the respective advantages of both the APB and UCIe protocols. This improves the compatibility of the chip's communication connection protocols and helps reduce the design complexity of the on-chip system.

[0065] In an illustrative embodiment, the destination register for the APB protocol register access request timing signal is any one of the local chip adapter layer register, the local chip physical layer register, the remote chip physical layer register, or the remote chip adapter layer register.

[0066] In the illustrative embodiment, the aforementioned APB protocol register access request timing signal does not include a register access request timing signal for accessing a local chip protocol layer register. Therefore, if the destination register for the APB protocol register access request timing signal received from the local chip's APB interface is a local chip protocol layer register, the register access signal conversion and transmission method of this disclosure embodiment further includes: directly accessing the local chip protocol layer register via the APB interface.

[0067] In this illustrative embodiment, the destination register of the APB protocol register access request timing signal does not include the remote chip protocol layer register. Therefore, if the destination register of the APB protocol register access request timing signal received from the local chip's APB interface is a remote chip protocol layer register, an error message is directly returned through the APB interface.

[0068] In an illustrative embodiment, the register access signal conversion and transmission method of this disclosure can be executed in the protocol layer of the local chip. In this illustrative embodiment, the APB interface is connected to the protocol layer of the local chip, but not to the adapter layer or the physical layer of the local chip. Based on the UICe protocol, the protocol layer, adapter layer, and physical layer of the local chip communicate through the FDI and RDI interfaces of the UCIe protocol. This approach simplifies the local chip's register access interface and reduces integration design complexity by eliminating the physical connection path between the APB interface and the adapter and physical layers of the local chip. Furthermore, it is compatible with the UCIe protocol, enabling the collaborative operation of the local chip's APB and UCIe protocols. This improves the compatibility of the chip's communication connection protocols and reduces the design complexity of the system-on-a-chip.

[0069] In an illustrative embodiment, the destination register to be accessed is determined by the PADDR signal in the APB protocol register access request timing signal. If the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of a local chip protocol layer register, then the destination register accessed by the APB protocol register access request timing signal is a local chip protocol layer register; if the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of a local chip adaptation layer register, then the destination register accessed by the APB protocol register access request timing signal is a local chip adaptation layer register; if the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of a local chip physical layer register, then the destination register accessed by the APB protocol register access request timing signal is a local chip physical layer register. If the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of a remote chip physical layer register, then the destination register accessed by the APB protocol register access request timing signal is a remote chip physical layer register; if the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of a remote chip adaptation layer register, then the destination register accessed by the APB protocol register access request timing signal is a remote chip adaptation layer register; if the target address information corresponding to the PADDR signal in the APB protocol register access request timing signal is the address of a remote chip protocol layer register, then the destination register accessed by the APB protocol register access request timing signal is a remote chip protocol layer register.

[0070] In an illustrative embodiment, after generating the UCIe sideband register access request data packet, the UCIe sideband register access request data packet is transmitted and parsed based on the UCIe protocol.

[0071] In an illustrative embodiment, when the destination register of the APB protocol register access request timing signal is a local chip adapter layer register, step 203 of sending the UCIe sideband register access request data packet to the destination layer may include: sending the UCIe sideband register access request data packet to the local chip adapter layer through the FDI interface.

[0072] In an illustrative embodiment, when the destination register of the APB protocol register access request timing signal is a local chip physical layer register, step 203 of sending the UCIe sideband register access request data packet to the destination layer includes: sending the UCIe sideband register access request data packet to the local chip's adaptation layer through the FDI interface, and having the local chip's adaptation layer forward the UCIe sideband register access request data packet to the local chip's physical layer through the RDI interface.

[0073] In an illustrative embodiment, when the destination register of the APB protocol register access request timing signal is a remote chip physical layer register or a remote chip adaptation layer register, the UCIe sideband register access request data packet is sent based on the mailbox mechanism of the UCIe protocol.

[0074] Based on this, in the illustrative embodiment, when the destination register of the APB protocol register access request timing signal is a remote chip physical layer register or a remote chip adaptation layer register, step 203 of sending the UCIe sideband register access request data packet to the destination layer includes: writing the UCIe sideband register access request data packet into the mailbox register for remote chip register access.

[0075] The specific process of writing the UCIe sideband register access request data packet into the mailbox register accessible by the remote chip register can include: Multiple UCIe sideband register access request data packets are generated. The local chip protocol layer writes these multiple UCIe sideband register access request data packets sequentially from the sideband to the mailbox register in the local chip's adapter layer via the FDI interface.

[0076] In an illustrative embodiment, based on the UCIe specification, the mailbox register is located in the local chip's adaptation layer.

[0077] In this illustrative embodiment, the destination register address in the UCIe sideband register access request data packet is consistent with the destination register address in the APB protocol register access request timing signal, and the data information in the UCIe sideband register access request data packet is consistent with the data information in the APB protocol register access request timing signal. This ensures that the APB protocol register access request received by the APB interface can be accurately implemented through the UCIe protocol.

[0078] Whether it's a read or write request, the initiating end of the access request needs to receive corresponding access feedback to ensure the accuracy of the access execution. For example, the initiating end of a read request needs to receive the data content to be read, and the initiating end of a write request needs to receive write confirmation feedback. Therefore, after completing step 203 of sending the UCIe sideband register access request data packet to the destination layer, a subsequent process of obtaining relevant feedback information is still required. Figure 2 As shown, in the illustrative embodiment, in addition to steps 201 to 203 described above, steps 204 to 205 following step 203 are also included.

[0079] Step 204: Receive and parse the UCIe Sideband Register Access Completion Packet. Based on the UCIe Sideband Register Access Completion Packet, generate the APB protocol register access completion timing signal. The UCIe Sideband Register Access Completion Packet is associated with the UCIe Sideband Register Access Request Packet. The UCIe Sideband Register Access Completion Packet and the UCIe Sideband Register Access Request Packet belong to the same APB protocol access packet. Step 205: Send the APB protocol register access completion timing signal through the APB interface.

[0080] Figure 5 This is a schematic diagram illustrating the UCIe sideband register access completion packet format according to an illustrative embodiment, such as... Figure 5 As shown, the format of this UCIe sideband register access completion packet is similar to that of the UCIe sideband register access request packet. The difference lies in that the UCIe sideband register access completion packet includes an rsvd field and a Status field, while the UCIe sideband register access request packet includes an Addr field. The rsvd field, or Reserved field, can be used to extend and improve compatibility. The Status field indicates whether the register access operation was successful.

[0081] Because the UCIe sideband register access completion data packet contains the packet type corresponding to the Opcode field and the data content corresponding to the Data field, and the APB signal contains the transmission operation type information corresponding to the PWRITE signal, the write data content corresponding to PWDATA, and the read data content corresponding to PRDATA, the content of the Opcode field can be associated with the content of the PWRITE signal, and the content of the Data field can be associated with the content of the PWDATA signal and / or the PRDATA signal. Therefore, based on this, the content of the UCIe sideband register access completion data packet can also be translated into the APB protocol register access completion timing signal and sent back to the sender of the APB protocol register access request timing signal through the APB interface.

[0082] Through steps 201 to 203 and steps 501 to 502 described above, a complete interactive process in an on-chip system can be completed. This process involves the requesting end sending a register access request based on the APB protocol, translating the APB protocol register access request into a UCIe protocol sideband register access request, sending the UCIe protocol sideband register access request, receiving the UCIe protocol sideband register access completion message, translating the UCIe protocol sideband register access completion message back into an APB protocol sideband register access completion message, and finally sending the APB protocol sideband register access completion message back to the sending end. This process realizes the conversion between the APB protocol and the UCIe protocol, ensuring that in the on-chip system, the data path based on the APB protocol only accesses the chip's UCIe protocol layer, and the protocol layer handles the translation between the APB protocol and the UCIe protocol. The APB protocol data path no longer needs to access the adaptation layer and physical layer, thus simplifying the APB protocol data link network, reducing the design difficulty of the data link network for each chip in the on-chip network, and improving the compatibility between the APB protocol and the UCIe protocol.

[0083] Figure 6 This is a schematic diagram of the remote chip register access process of the UCIe protocol, such as... Figure 6 As shown, the process mainly includes the following steps 601 to 611.

[0084] Step 601: The protocol layer of the local chip sends the mailbox target request information to the adaptation layer of the local chip through the FDI interface.

[0085] This step may include the local chip's protocol layer sending a UCIe sideband register access request data packet to the local chip's adapter layer via the FDI interface, and writing information to the local chip's adapter layer's mailbox.

[0086] Step 602: The local chip's adapter layer checks the creditworthiness of the remote chip's adapter and generates a remote chip access request.

[0087] Step 603: The local chip's adaptation layer sends a remote chip access request to the local chip's physical layer through the RDI interface.

[0088] Step 604: The physical layer of the local chip sends a remote chip access request to the physical layer of the remote chip through the UCIe sideband.

[0089] Step 605: The physical layer of the remote chip sends a remote chip access request to the adaptation layer of the remote chip through the RDI interface.

[0090] Step 606: The adaptation layer of the remote chip decodes the remote chip access request to the physical layer of the remote chip through the RDI interface and executes the transaction for the remote chip access request.

[0091] Step 607: The adaptation layer of the remote chip sends a response to the physical layer of the remote chip for the remote chip access request through the RDI interface.

[0092] Step 608: The physical layer of the remote chip sends a response to the physical layer of the local chip for the remote chip access request via the UCIe sideband.

[0093] Step 609: The physical layer of the local chip sends a response sideband data packet to the adapter layer of the local chip via the RDI interface in response to the remote chip access request.

[0094] Step 610: The local chip adapter layer updates the mailbox in the local chip adapter layer with the information of the side packet of the remote chip access request.

[0095] Step 611: After the email address in the local chip's adaptation layer is updated, the local chip's protocol layer obtains the email request completion information from the local chip's adaptation layer through the FDI interface.

[0096] This step may include the local chip's protocol layer obtaining information from the mailbox in the local chip's adaptation layer.

[0097] When the register access request timing signal received from the APB interface of the local chip is for accessing the registers of a remote chip, the register access request of the APB protocol (APB protocol register access request timing signal) can be translated into the UCIe protocol sideband register access request (UCIe sideband register access request data packet). Then, combined with the UCIe protocol remote chip register access process in steps 601 to 611 above, the access to the remote chip register is realized. The access feedback information of the UCIe protocol (such as the UCIe sideband register access completion data packet) is translated into the access feedback information of the APB protocol (such as the APB protocol register access completion timing signal) and sent to the requester of the register access request through the APB interface.

[0098] Figure 7 This is a schematic diagram of a specific scenario using the register access signal conversion and transmission method of this disclosure embodiment, which is a sideband register access process for converting the APB protocol to the UCIe protocol. Figure 7 As shown, this scenario mainly includes the following steps 701 to 709.

[0099] Step 701: During chip design, plan the on-chip system-level address space in advance, including the addresses of registers at each level, and then execute step 702.

[0100] Step 702: The on-chip system initiates a register access request through the APB interface, and then executes step 703.

[0101] Step 703: The local chip's protocol layer analyzes the read / write type and address information of the register access request of the APB interface, and then executes one of steps 704 to 707 based on the analysis results.

[0102] Step 704: If the register access request is to access the local chip protocol layer register, the local chip protocol layer register is accessed directly through the APB interface, and then the process ends.

[0103] Step 705: If the register access request is to access the adapter layer register or the physical layer register of the local chip, convert the register access request of the APB interface into a UCIe sideband register access request data packet and send it to the adapter layer register or the physical layer register of the local chip, and then execute step 708.

[0104] Step 706: If the register access request is to access the adapter layer register or physical layer register of the remote chip, generate multiple UCIe sideband register access request data packets, write them to the mailbox, and then execute step 709.

[0105] Step 707: If the register access request is to access the protocol layer register of a remote chip, reply with an error message to the on-chip system through the APB interface, and then end the process.

[0106] Because the mailbox mechanism of the UCIe protocol does not support access to the protocol layer of remote chips, step 707 is set to respond to an error.

[0107] Step 708: After receiving the UCIe sideband register access completion data packet, convert the UCIe sideband register access completion data packet back to the APB interface signal and reply to the on-chip system, and then end the process.

[0108] Step 709: After waiting for the remote chip to reply, the local chip's protocol layer reads the mailbox information, generates a UCIe sideband register access completion data packet, converts it back to the APB interface signal and replies to the on-chip system, and then ends the process.

[0109] Based on the register access signal conversion and transmission method of this disclosure, each chip in the system-on-a-chip only needs to connect its own protocol layer to the APB interface, and use the UCIe protocol between its own protocol layer and the adaptation layer and physical layer, as well as between each chip, and perform translation between the APB protocol and the UCIe protocol at the protocol layer, so as to achieve compatibility between the two protocols of the entire system-on-a-chip and simplify the APB protocol data link of each chip.

[0110] Figure 8This is a timing diagram of local chip register access, taking a read operation as an example. Here, clk is the clock signal; fdi_lp_cfg_vld is the lp_cfg_vld signal in the FDI interface, used to indicate whether the sideband information sent from the protocol layer to the adaptation layer is valid. When fdi_lp_cfg_vld is high, it indicates that the sideband information sent by the protocol layer is valid, and the adaptation layer will then process the received sideband information. The fdi_lp_cfg_vld signal is independently set to 1 at different stages of data transmission. During the continuous data transmission phase of the same data packet, the fdi_lp_cfg_vld signal needs to be continuously set to 1 for several hours. During clock cycles, when accessing data packets in registers, the protocol layer uses the fdi_lp_cfg_vld signal to ensure the adaptation layer correctly receives and processes the data; fdi_lp_cfg[31:0] is the sideband interface in the FDI interface from the protocol layer to the adaptation layer, used to transmit sideband data packet content from the protocol layer to the adaptation layer, and [31:0] indicates that this signal is a 32-bit signal; fdi_pl_cfg[31:0] is the sideband interface in the FDI interface from the adaptation layer to the protocol layer, used to transmit sideband data packet content from the adaptation layer to the protocol layer, and [31:0] indicates that this signal is a 32-bit signal. The fdi_pl_cfg[31:0] signal corresponds to the fdi_lp_cfg[31:0] signal, realizing bidirectional communication between the protocol layer and the adaptation layer. This bidirectional communication mechanism allows for effective data exchange between the protocol layer and the adaptation layer, thereby ensuring the normal operation of the entire UCIe link; rdi_lp_cfg_vld is the lp_cfg_vld signal in the RDI interface, used to indicate whether the sideband information sent by the adaptation layer to the physical layer is valid. When the rdi_lp_cfg_vld signal is high, it indicates that the sideband information sent by the adaptation layer is valid. The processing layer needs to handle the received sideband information; PSel is the slave device selection signal of the APB protocol; PEnable is the transmission enable signal of the APB protocol; PWrite is the write control signal of the APB protocol; PAddr[31:0] is the target address signal of the APB protocol, [31:0] represents 32 bits; PWData[31:0] is the write data signal of the APB protocol, [31:0] represents 32 bits; PRData[31:0] is the read data signal of the APB protocol, [31:0] represents 32 bits; PReady is the ready signal of the APB protocol.

[0111] like Figure 8As shown in the timing diagram of the read access scenario, at position 1, the system initiates a read operation through the APB interface. The protocol layer generates a UCIe sideband register access request data packet at position 2 and sends it to the adaptation layer through the FDI port. After the adaptation layer replies at position 3, the PReady signal of the APB interface is raised at position 4, and the read data is updated to the PRDATA signal. The system reads the data through the APB interface and completes the read operation.

[0112] Figure 9 This is a schematic diagram illustrating a detailed process for accessing registers in a remote chip, based on an illustrative embodiment. For example... Figure 9 As shown, the detailed process status mainly includes the following status stages.

[0113] 1. The initial reset state of the mailbox, also known as the MAILBOX_INIT state, is in the stage of waiting for the APB interface to initiate a remote chip register access request. After receiving the remote chip register access request, it jumps to the state of writing mailbox index 0.

[0114] 2. Write Mailbox Index 0 state, also known as WR_MAILBOX_INDDEX0 state. In this state, the protocol layer writes the Opcode field, BE field, and low-order address information (bits 0 to 18) to the AdapterSideband Mailbox Index Low register through the local chip UCIe sideband register access request data packet. After receiving the local chip UCIe sideband register access completion data packet returned by the adapter layer, it jumps to the Write Mailbox Index 1 state. If the local chip UCIe sideband register access completion data packet is not received after the timeout, or if the UCIe sideband register access completion data packet with error information is received, it enters the mailbox error state. 3. Write Mailbox Index 1 state, also known as WR_MAILBOX_INDDEX1 state. In this state, the protocol layer writes the high bits (bits 19 to 23) of the adapter layer's sideband mailbox index high register through the local chip UCIe sideband register access request data packet. After receiving the local chip UCIe sideband register access completion data packet returned by the adapter layer, it jumps to the write mailbox data state. If the mailbox status register information is a timeout error state, or if a UCIe sideband register access completion data packet with error information is received, it enters the mailbox error state. 4. Write Mailbox Data State, also known as WR_MAILBOX_DATA State: In this state, the protocol layer writes write data information (i.e., the content of the PWDATA signal) of the APB interface to the adapter layer's sideband mailbox data register through the local chip UCIe sideband register access request data packet. If the register access request timing signal of the APB interface is a read operation signal, this state can be skipped. After receiving the local chip UCIe sideband register access completion data packet returned by the adapter layer, the process jumps to the write mailbox target state. If the local chip UCIe sideband register access completion data packet is not received after the timeout, or if a UCIe sideband register access completion data packet with error information is received, the process enters the mailbox error state. 5. Write Mailbox Target Status, also known as WR_MAILBOX_TRG status. In this status phase, the protocol layer sets the write / read trigger signal or control bit of the adapter layer's sideband mailbox control register to 1 through the local chip's UCIe sideband register access request data packet, informing the adapter layer that all information has been written. After receiving the local chip's UCIe sideband register access completion data packet returned by the adapter layer, it waits for the adapter layer to send the register access information in the mailbox to the remote chip. If the local chip's UCIe sideband register access completion data packet is not received after a timeout, or if a UCIe sideband register access completion data packet with error information is received, the mailbox status register will display an error message. In this status, the adapter layer's sideband mailbox control register can be read periodically. After the write / read trigger signal changes from 1 to 0, or after the adapter layer returns a mailbox process end signal to the protocol layer, the reply information in the mailbox can be read, and the process can jump to the mailbox reading status. 6. Reading the mailbox status, also known as the RD_MAILBOX_STATUS state, involves the protocol layer reading the adapter sideband mailbox status register through the local chip's UCIe sideband register access request data packet. If the read information is "Success," the access is successful, and the process jumps to the mailbox data reading state. If the read information is CA (Completer Abort, indicating that the completer has aborted the operation, usually because the completer cannot complete the requested operation or encountered an error during processing) or UR (Unsupported Request, indicating that the request is not supported, usually because the request type, format, or parameters exceed the capability range), the access is abnormal, and the mailbox status register displays an error message. If no local chip UCIe sideband register access completion data packet is received after the timeout, or if a UCIe sideband register access completion data packet with error information is received, the process enters the mailbox error state. 7. The mailbox data reading state, also known as the RD_MAILBOX_DATA state, corresponds to the execution of a register read request when the register access request timing signal received by the APB interface is received. The protocol layer reads the adapter layer sideband mailbox data register through the local chip's UCIe sideband register access request data packet, sends the read data to the PRDATA signal interface of the APB interface, and pulls the PReady signal of the APB interface high. After that, the process ends and returns to the mailbox initial reset state. If no local chip UCIe sideband register access completion data packet is received after the timeout, or if a UCIe sideband register access completion data packet with error information is received, the mailbox enters the mailbox error state. If the register access request timing signal received by the APB interface is a register write request, the adapter layer sideband mailbox data register is not read in the mailbox data reading state. Only the PReady signal of the APB interface is pulled high, and then the process ends and returns to the mailbox initial reset state. 8. Mailbox Error Status, also known as MAILBOX_ERROR Status, indicates that the access to the register has timed out or is abnormal. It directly replies with error information to the system that issued the register access request timing signal through the PSLVERR signal of the APB interface, informing that the register access has failed. Then the process ends and returns to the initial reset status of the mailbox.

[0115] The register access signal conversion and transmission method of this disclosure simplifies the design complexity of the data link based on the APB protocol in a system-on-a-chip (SoC) composed of chiplets by converting the APB protocol register access request timing signal received by the APB interface of the local chip into a UCIe sideband register access request data packet for transmission. This reduces the complexity of the data link design, thereby reducing the design difficulty of the SoC and improving the compatibility of the APB and UCIe protocols within the same SoC. When different chiplets within the SoC are designed independently by different design teams and support the UCIe protocol, the register access signal conversion and transmission method of this disclosure can be used in specific chiplets within the SoC according to design requirements, thus helping to leverage the advantages of both the APB and UCIe protocols simultaneously within the SoC.

[0116] Figure 10 This is a schematic diagram of a chip according to an illustrative embodiment, such as... Figure 10 As shown, the chip includes a UCIe interface defined by the UCIe protocol and an APB interface defined by the APB protocol. The chip also includes a conversion module located in the protocol layer of the UCIe interface, used for: receiving APB protocol register access request timing signals from the APB interface; generating UCIe sideband register access request data packets based on the APB protocol register access request timing signals; and sending the UCIe sideband register access request data packets.

[0117] In an illustrative embodiment, the conversion module is further configured to: in response to the reception of a UCIe sideband register access completion data packet, generate an APB protocol register access completion timing signal based on the UCIe sideband register access completion data packet, wherein the UCIe sideband register access completion data packet is associated with a UCIe sideband register access request data packet; and send the APB protocol register access completion timing signal through the APB interface.

[0118] Figure 11 This is a schematic diagram of the register access method of the APB protocol in related technologies, such as... Figure 11 As shown, accessing registers using the APB protocol in a chip requires designing the routing structure of registers in various parts of the chip for the APB protocol, including the routing structures of registers within the protocol layer, registers within the adaptation layer, and registers within the physical layer for the APB protocol.

[0119] from Figure 10 and Figure 11The comparison shows that the chip using the embodiments of this disclosure only needs to set up a conversion module in the chip's protocol layer to handle the translation and conversion of signals between the APB protocol and the UCIe protocol. This enables the chip to send register access requests to the local chip via the APB protocol when the APB protocol only accesses the protocol layer. At the same time, based on the UCIe protocol, the local chip can also send register access requests to a remote chip via the APB protocol. Since the APB protocol in the chip only accesses the protocol layer and not the adaptation layer and physical layer, the chip does not need to design related links for the APB protocol to access the adaptation layer and physical layer, thus helping to reduce the design difficulty of the chip.

[0120] In an illustrative embodiment, a system-on-a-chip (SoC) is also provided, comprising at least one integrated-package chiplet. At least one of the at least one chiplet employs the chip described in the above embodiments.

[0121] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A register access signal conversion and transmission method, comprising: Receive APB protocol register access request timing signals from the APB interface of the local chip; Based on the APB protocol register access request timing signal, generate a UCIe sideband register access request data packet; Send the UCIe sideband register access request data packet to the destination layer; Receive and parse the UCIe sideband register access complete data packet, and generate an APB protocol register access complete timing signal based on the UCIe sideband register access complete data packet. The UCIe sideband register access complete data packet is associated with the UCIe sideband register access request data packet. The UCIe sideband register access complete data packet and the UCIe sideband register access request data packet belong to the same data packet corresponding to the same APB protocol access. The APB protocol register access completion timing signal is sent through the APB interface; The destination register address in the UCIe sideband register access request data packet is consistent with the destination register address in the APB protocol register access request timing signal, and the data information in the UCIe sideband register access request data packet is consistent with the data information in the APB protocol register access request timing signal.

2. The register access signal conversion and transmission method according to claim 1, characterized in that: The destination register for the APB protocol register access request timing signal can be any one of the following: local chip adaptation layer register, local chip physical layer register, remote chip physical layer register, or remote chip adaptation layer register.

3. The register access signal conversion transmission method according to claim 2, wherein, When the destination register of the APB protocol register access request timing signal is the local chip adaptation layer register, sending the UCIe sideband register access request data packet to the destination layer includes: The UCIe sideband register access request data packet is sent to the local chip's adaptation layer via the FDI interface.

4. The register access signal conversion transmission method according to claim 2, wherein, When the destination register of the APB protocol register access request timing signal is the local chip physical layer register, sending the UCIe sideband register access request data packet to the destination layer includes: The UCIe sideband register access request data packet is sent to the local chip's adaptation layer via the FDI interface, and the adaptation layer forwards the UCIe sideband register access request data packet to the local chip's physical layer via the RDI interface.

5. The register access signal conversion and transmission method according to claim 2, characterized in that, When the destination register of the APB protocol register access request timing signal is the physical layer register of the remote chip or the adaptation layer register of the remote chip, sending the UCIe sideband register access request data packet to the destination layer includes: Write the UCIe sideband register access request data packet into the mailbox register for remote chip register access.

6. The register access signal conversion and transmission method according to claim 5, characterized in that: The mailbox register is located in the adapter layer of the local chip.

7. The register access signal conversion and transmission method according to claim 1, characterized in that, When the destination register of the APB protocol register access request timing signal is a local chip protocol layer register, the method further includes: The local chip protocol layer registers can be accessed directly through the APB interface.

8. The register access signal conversion and transmission method according to claim 1, characterized in that: The local chip includes the protocol layer, adaptation layer, and physical layer defined by the UCIe protocol; The APB interface is connected to the protocol layer; The protocol layer and the adaptation layer communicate through the FDI interface of the UCIe protocol, and the adaptation layer and the physical layer communicate through the RDI interface of the UCIe protocol.

9. A chip, characterized in that: The chip includes a UCIe interface defined by the UCIe protocol and an APB interface defined by the APB protocol; wherein... The chip also includes: The conversion module, located in the protocol layer of the UCIe interface, is used for: Receives APB protocol register access request timing signals from the APB interface; generates UCIe sideband register access request data packets based on the APB protocol register access request timing signals; and sends the UCIe sideband register access request data packets; and In response to the reception of a UCIe sideband register access complete data packet, an APB protocol register access complete timing signal is generated based on the UCIe sideband register access complete data packet, wherein the UCIe sideband register access complete data packet is associated with the UCIe sideband register access request data packet; the APB protocol register access complete timing signal is sent through the APB interface. The destination register address in the UCIe sideband register access request data packet is consistent with the destination register address in the APB protocol register access request timing signal, and the data information in the UCIe sideband register access request data packet is consistent with the data information in the APB protocol register access request timing signal.

10. A system-on-a-chip, characterized in that, include: At least one small chip in an integrated package; Wherein, at least one of the at least one small chip is a chip as described in claim 9.

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