Display device and display panel thereof

Abstract

The present disclosure relates to the technical field of display, and mainly relates to a display device and a display panel thereof; the display panel has a display area and a non-display area; in the display area, the display panel has a plurality of panel input ports, and the panel input ports are used for inputting an initialization voltage; in the non-display area, the display panel has a source driving circuit, and the source driving circuit comprises a source driver and an integrated voltage dividing module; the source driver has a plurality of driver output ports, and the driver output ports are used for outputting the initialization voltage; the number of the driver output ports is less than the number of the panel input ports, and the integrated voltage dividing module is configured to electrically connect any one of the driver output ports with at least one of the panel input ports; the display panel can improve the picture quality without changing the original source driver structure (without developing a new source driver), and without increasing the cost.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display device and its display panel. Background Technology

[0002] Due to differences in materials and manufacturing processes, different sub-pixels have different activation characteristics. If all sub-pixels use the same reset voltage, it will cause problems in image quality adjustment, such as common issues like ghosting and color cast.

[0003] In related technologies, the method of setting the initialization voltage of each sub-pixel individually can improve problems such as ghosting and color shift. However, this solution is limited by the number of output ports of the source driver (driver IC).

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display device and its display panel that can improve image quality without changing the original source driver structure (without developing a new source driver) and without increasing costs.

[0006] According to one aspect of this disclosure, a display panel is provided having a display area and a non-display area; In the display area, the display panel has multiple panel input ports, which are used to input initialization voltage; In the non-display area, the display panel has a source drive circuit, which includes a source driver and an integrated voltage divider module; The source driver has multiple driver output ports, which are used to output initialization voltage; the number of driver output ports is less than the number of panel input ports, and the integrated voltage divider module is configured such that any one of the driver output ports is electrically connected to at least one of the panel input ports.

[0007] In one embodiment of this disclosure, the display panel in the display area has a plurality of display units; The display unit includes sub-pixels and a pixel driving circuit that drives the sub-pixels to emit light. The pixel driving circuit has at least one initialization connection port. The same initialization connection port of each pixel driving circuit of the sub-pixels with the same luminous color is connected to the same panel input port.

[0008] In one embodiment of this disclosure, the number of integrated voltage divider modules is one.

[0009] In one embodiment of this disclosure, the source driver has a lookup table, and the source driver is configured to invoke the lookup table and output an initialization voltage through the driver output port.

[0010] In one embodiment of this disclosure, the source driver has at least two lookup tables, each of which corresponds to a different display mode of the display panel; The source driver is configured to call the corresponding lookup table based on different display modes of the display panel, and output the initialization voltage through the driver output port.

[0011] In one embodiment of this disclosure, in the non-display area, the display panel is bonded to a flexible circuit board; the integrated voltage divider module is disposed on the flexible circuit board; A voltage regulator is also provided on the flexible circuit board. The output terminal of the integrated voltage divider module is electrically connected to the input terminal of the voltage regulator, and the output terminal of the voltage regulator is electrically connected to the panel input port. The voltage regulator is configured to regulate the initial voltage output by the integrated voltage divider module and output the regulated initial voltage to the panel input port.

[0012] In one embodiment of this disclosure, the display panel has two sets of panel input port groups, each set of panel input port groups including the plurality of panel input ports; The output terminal of the voltage regulator is electrically connected to the two sets of panel input ports respectively; the voltage regulator is configured to regulate the initial voltage output by the integrated voltage divider module and output the regulated initial voltage to the two sets of panel input ports.

[0013] In one embodiment of this disclosure, the number of integrated voltage divider modules is at least two, and each integrated voltage divider module has an enable control unit configured to control the integrated voltage divider module to turn on or off, and the source driver is configured to control each of the enable control units to turn on or off. Any two of the integrated voltage divider modules form a module pair, which has at least one adjustment interface corresponding to the module pair. The driver output port connected to one of the modules in the module pair through the adjustment interface is different from the driver output port connected to the other module in the module pair. The adjustment interface is one of the panel input ports.

[0014] In one embodiment of this disclosure, the number of integrated voltage divider modules is two, and each pixel driving circuit has a first initialization connection port and a second initialization connection port; The source driver has four driver output ports, and the display panel has six panel input ports; the sub-pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In one of the integrated voltage divider modules, the panel input port connected to the first initialization connection port corresponding to the first sub-pixel and the panel input port connected to the second initialization connection port corresponding to the second sub-pixel are connected to the same driver output port through the integrated voltage divider module; the panel input port connected to the first initialization connection port corresponding to the third sub-pixel and the panel input port connected to the second initialization connection port corresponding to the first sub-pixel are connected to the same driver output port through the integrated voltage divider module. In another integrated voltage divider module, the panel input port connected to the first initialization connection port corresponding to the first sub-pixel and the panel input port connected to the second initialization connection port corresponding to the third sub-pixel are connected to the same driver output port through the integrated voltage divider module; the panel input port connected to the first initialization connection port corresponding to the second sub-pixel and the panel input port connected to the second initialization connection port corresponding to the first sub-pixel are connected to the same driver output port through the integrated voltage divider module.

[0015] According to another aspect of this disclosure, a display device is provided having the aforementioned display panel.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0019] Figure 2 This is a schematic diagram of the pixel driving circuit in one embodiment of the present disclosure.

[0020] Figure 3This is a schematic diagram of the pixel driving circuit in one embodiment of the present disclosure.

[0021] Figure 4 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0022] Figure 5 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0023] Figure 6 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0024] Figure 7 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0026] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0027] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0028] In this application, unless otherwise expressly specified and limited, the term "connection" shall be interpreted broadly. For example, "connection" may be a fixed connection, a detachable connection, or an integral part; it may be a direct connection or an indirect connection through an intermediate medium.

[0029] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region refers to the region through which current primarily flows.

[0030] In embodiments of this disclosure, the functions of the "source electrode" and "drain electrode" are sometimes interchanged in cases where transistors with opposite polarities are used or where the current direction changes during circuit operation. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged. In embodiments of this disclosure, for any transistor, one of the "source electrode" and the "drain electrode" is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor, and the gate is referred to as the control electrode of the transistor. The first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode.

[0031] Structural layer A is located on the side of structural layer B that faces away from the substrate. This can be understood as structural layer A being formed on the side of structural layer B that faces away from the substrate. When structural layer B is a patterned structure, some structures of structural layer A may also be located at the same physical height as structural layer B or at a lower physical height than structural layer B, where the substrate serves as the height reference.

[0032] This disclosure provides a display device including a display panel (PNL).

[0033] See Figure 1 The display panel PNL includes a display area AA and a non-display area BB located on at least one side of the display area AA.

[0034] The display panel PNL includes multiple display units arranged in an array within its display area AA. Each display unit comprises a sub-pixel (PIX) and a pixel driving circuit (PDC) that drives the sub-pixel. The display panel PNL has multiple scan lines GL arranged along the row direction DH in the display area AA, with each scan line GL corresponding to a row of display units; each scan line GL is connected to a pixel driving circuit (PDC) in its corresponding row. The display panel PNL also has multiple data lines DL arranged along the column direction DV in the display area AA, with each data line DL corresponding to a column of display units; each data line DL is connected to a pixel driving circuit (PDC) in its corresponding column. Thus, each display unit's pixel driving circuit (PDC) is connected to one scan line GL and one data line DL. When a strobe signal is applied to the scan line GL, the data voltage applied to the data line DL is applied to the pixel driving circuit (PDC), allowing the PDC to control the brightness of the sub-pixel based on the applied driving voltage.

[0035] In one embodiment of this disclosure, the display panel may further include an initialization signal line, which is used to connect to the initialization connection port of the pixel driving circuit PDC and apply an initialization voltage to the pixel driving circuit PDC.

[0036] Optionally, the sub-pixel PIX can be a current-driven self-emissive element, such as any one of OLED, PLED, QLED, Micro LED, Mini LED, etc. In this embodiment, the sub-pixel PIX can include multiple sub-pixel PIXs of different colors, such as a first sub-pixel PIX1 (a red sub-pixel for emitting red light), a second sub-pixel PIX2 (a green sub-pixel for emitting green light), and a third sub-pixel PIX3 (a blue sub-pixel for emitting blue light).

[0037] In one embodiment of this disclosure, the display panel PNL may include a substrate (not shown), a driving layer (not shown), and a pixel layer (not shown) stacked sequentially. The pixel layer contains light-emitting elements (not shown), which can serve as sub-pixels (PIXs), and the driving layer contains a pixel driving circuit (PDC) for driving the light-emitting elements (sub-pixels). Each light-emitting element (sub-pixel) emits light under the drive of the pixel driving circuit (PDC) to display an image. Furthermore, the display panel PNL also includes a thin-film encapsulation layer located on the side of the pixel layer away from the substrate, which encapsulates and protects the pixel layer.

[0038] Optionally, the substrate can be an inorganic material substrate or an organic material substrate; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrates. For example, in some embodiments of this disclosure, the substrate material can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of this disclosure, the substrate material can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate can also be a flexible substrate, for example, the substrate material may include polyimide.

[0039] Optionally, in the driving layer DRL, any pixel driving circuit PDC may include a thin-film transistor (TFT) and a storage capacitor. Further, the TFT can be selected from top-gate, bottom-gate, or dual-gate TFTs; the active layer of the TFT can be made of amorphous silicon, low-temperature polycrystalline silicon, metal-oxide-semiconductor, organic semiconductor, carbon nanotube, or other types of semiconductor materials; the TFT can be an N-type or P-type TFT.

[0040] It is understood that any two transistors in a pixel driver circuit (PDC) can be of the same or different types. Exemplarily, in some embodiments, some transistors in a PDC can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in other embodiments, in a PDC, the active layer material of some transistors can be low-temperature polycrystalline silicon (LTPS) semiconductor material, and the active layer material of some transistors can be metal-oxide-semiconductor (MODS) semiconductor material. In some embodiments of this disclosure, the thin-film transistor is a LPS transistor. In other embodiments of this disclosure, some thin-film transistors are LPS transistors, and some thin-film transistors are MODS transistors.

[0041] Optionally, the pixel driving circuit PDC includes at least a data writing transistor, a driving transistor, and a storage capacitor. The gate of the driving transistor can be electrically connected to one electrode plate of the storage capacitor. The source of the data writing transistor can be electrically connected to the data line DL, and the gate of the data writing transistor can be electrically connected to the scan line GL. The pixel driving circuit PDC is configured such that when a scan signal is applied to the scan line GL, the data writing transistor is turned on, thereby causing the driving voltage on the data line DL to be written to the gate of the driving transistor and the storage capacitor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It is understood that the pixel driving circuit PDC of this disclosure embodiment may also include other transistors or capacitors to give the pixel driving circuit PDC better driving performance. For example, the pixel driving circuit PDC can be a 7T1C (7 thin film transistors and one storage capacitor), an 8T1C (8 thin film transistors and one storage capacitor), or a pixel driving circuit with other architectures.

[0042] Optionally, in the non-display area BB, the display panel PNL has a source drive circuit. The source drive circuit provides drive current (or voltage) to the light-emitting element. The magnitude of the current directly determines the brightness of the light-emitting element, thereby realizing the brightness control of the pixel.

[0043] Optionally, in the non-display area BB, the display panel PNL is also bonded with a flexible circuit board (FPC), which is used to realize the electrical connection between the host computer and the source drive circuit. In this embodiment, the source drive circuit can be bonded to the flexible circuit board (FPC).

[0044] Due to differences in materials and processes, the activation status of different sub-pixels varies. If all sub-pixels use the same reset voltage, it will cause problems in image quality adjustment, such as the common problem of ghosting and color cast. The root cause is the different activation levels of the pixels. Under the same initialization voltage, when switching from black to white, for example, if the red and green sub-pixels are not activated, the ghosting effect will be bluish.

[0045] In related technologies, the initialization voltage of each sub-pixel can be set individually to improve problems such as ghosting and color shift. However, this solution is limited by the number of output ports of the source driver (driver IC).

[0046] To address this technical problem, this disclosure optimizes the structure of the source driver circuit, thereby improving issues such as ghosting and color distortion, and enhancing display quality without altering the source driver IC.

[0047] In one embodiment of this disclosure, the pixel driving circuit PDC has multiple initialization connection ports Vinit, which are used to apply an initialization voltage to the pixel driving circuit PDC. For example, a pixel driving circuit PDC based on 7T1C has two initialization connection ports Vinit (a first initialization connection port Vinit1 and a second initialization connection port Vinit2). As another example, a pixel driving circuit PDC based on 8T1C has three initialization connection ports Vinit (a first initialization connection port Vinit1, a second initialization connection port Vinit2, and a third initialization connection port Vinit3).

[0048] See Figure 2 , Figure 2 The pixel driving circuit PDC is presented as having an 8T1C architecture (8 thin-film transistors and one storage capacitor), which includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst. The pixel driving circuit PDC has three initialization connection ports, namely the first initialization connection port Vinit1, the second initialization connection port Vinit2, and the third initialization connection port Vinit3. Each of these three initialization connection ports is used to connect to the corresponding initialization voltage.

[0049] See Figure 3 , Figure 3 The pixel driving circuit PDC is presented as having a 7T1C architecture (7 thin-film transistors and one storage capacitor), which includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst. The pixel driving circuit PDC has two initialization connection ports, namely the first initialization connection port Vinit1 and the second initialization connection port Vinit2, both of which are used to connect the corresponding initialization voltage.

[0050] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 4 , Figure 6 and Figure 7The same initialization connection port (Vinit) of the PDCs of the pixel driving circuits for sub-pixels of the same emitting color is connected to the same panel input port. In other words, the same initialization connection port (Vinit) of the PDCs of the pixel driving circuits for sub-pixels of the same color is interconnected, while different initialization connection ports (Vinit) are not interconnected. Furthermore, the initialization connection ports (Vinit) of the PDCs of pixel driving circuits for sub-pixels of different colors are not interconnected. Under this connection method, when the PDC is 7T1C, the display panel PNL has six panel input ports. When the PDC is 8T1C, the display panel PNL has nine panel input ports.

[0051] Taking the 8T1C pixel drive circuit PDC as an example, see Figure 4 Each first sub-pixel PIX1 has its first initialization connection port Vinit1 of all pixel driving circuit PDCs connected to the same panel input port; its second initialization connection port Vinit2 of all pixel driving circuit PDCs connected to the same panel input port; and its third initialization connection port Vinit3 of all pixel driving circuit PDCs connected to the same panel input port. These three panel input ports are different from each other. The same applies to the second sub-pixel PIX2 and the third sub-pixel PIX3, and will not be described further in this disclosure. See [link to relevant documentation] Figure 6 and Figure 7 The initialization connection ports Vinit of the first sub-pixel PIX1, the second sub-pixel PIX2, and the third sub-pixel PIX3 are connected to different panel input ports. Under these conditions, based on the 8T1C pixel drive circuit PDC, the display panel PNL has nine panel input ports.

[0052] Taking the pixel driving circuit PDC 7T1C as an example, see [link / reference]. Figure 3 and Figure 5The pixel driver circuit PDC has a first initialization connection port Vinit1 and a second initialization connection port Vinit2. Each first sub-pixel PIX1 corresponds to a pixel driver circuit PDC whose first initialization connection port Vinit1 is connected to the same panel input port (first panel input port Vinit1-R). Each first sub-pixel PIX1 corresponds to a pixel driver circuit PDC whose second initialization connection port Vinit2 is connected to the same panel input port (second panel input port Vinit2-R). Each second sub-pixel PIX2 corresponds to a pixel driver circuit PDC whose first initialization connection port Vinit1 is connected to the same panel input port (third panel input port Vinit1-G). Each second sub-pixel PIX2 corresponds to a pixel driver circuit PDC whose second initialization connection port Vinit2 is connected to the same panel input port (fourth panel input port Vinit2-G). Each third sub-pixel PIX3 corresponds to a pixel driver circuit PDC whose first initialization connection port Vinit1 is connected to the same panel input port (fifth panel input port Vinit1-B). Each third sub-pixel PIX3 corresponds to a pixel driver circuit PDC whose second initialization connection port Vinit2 is connected to the same panel input port (sixth panel input port Vinit2-B). Thus, the display panel PNL has six panel input ports.

[0053] In this disclosure, the initialization voltage of each sub-pixel PIX is controlled individually. During display, the activation control of a single pixel can be achieved by adjusting the initialization voltage. For example, the second initialization voltage of the first sub-pixel PIX1 (red sub-pixel) and the second sub-pixel PIX2 (green sub-pixel) is positively biased to precharge them in advance so that they reach the same level as the third sub-pixel PIX3 (blue sub-pixel) when they are activated, thereby improving the problem of ghosting and color shift.

[0054] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 7 A dual-side driving approach can be adopted to initialize the pixel drive circuit (PDC). In this example, the display panel (PNL) can have two sets of panel input port groups, each containing multiple panel input ports. Both sets of panel input port groups are electrically connected to the corresponding initialization connection port (Vinit). In this disclosure, dual-side driving significantly shortens the signal transmission path. Compared to single-side driving (where the signal needs to be transmitted from one end to the other), dual-side driving reduces signal delay and attenuation, enabling faster pixel switching control. Especially in high refresh rate panels (such as gaming monitors and high-end displays), it effectively reduces ghosting and improves the smoothness of dynamic images.

[0055] Taking the pixel driver circuit PDC as an example (8T1C), each group of panel input ports includes nine panel input ports. Each first sub-pixel PIX1 corresponds to the first initialization connection port Vinit1 of the pixel driver circuit PDC, which is connected to the same two panel input ports (the first panel input port in the first group of panel input ports and the first panel input port in the second group of panel input ports). Each first sub-pixel PIX1 corresponds to the second initialization connection port Vinit2 of the pixel driver circuit PDC, which is connected to the same two panel input ports (the second panel input port in the first group of panel input ports and the second panel input port in the second group of panel input ports). Each first sub-pixel PIX1 corresponds to the third initialization connection port Vinit3 of the pixel driver circuit PDC, which is connected to the same two panel input ports (the second panel input port in the first group of panel input ports and the third panel input port in the second group of panel input ports). Each second sub-pixel PIX2 corresponds to a pixel driver circuit PDC whose first initialization connection port Vinit1 is connected to the same two panel input ports (the fourth panel input port in the first group of panel input ports and the fourth panel input port in the second group of panel input ports). Each second sub-pixel PIX2 corresponds to a pixel driver circuit PDC whose second initialization connection port Vinit2 is connected to the same two panel input ports (the fifth panel input port in the first group of panel input ports and the fifth panel input port in the second group of panel input ports). Each second sub-pixel PIX2 corresponds to a pixel driver circuit PDC whose third initialization connection port Vinit3 is connected to the same two panel input ports (the sixth panel input port in the first group of panel input ports and the sixth panel input port in the second group of panel input ports). Each third sub-pixel PIX3 corresponds to a pixel driver circuit PDC whose first initialization connection port Vinit1 is connected to the same two panel input ports (the seventh panel input port in the first group of panel input ports and the seventh panel input port in the second group of panel input ports). Each third sub-pixel PIX3 corresponds to a pixel driver circuit PDC whose second initialization connection port Vinit2 is connected to the same two panel input ports (the eighth panel input port in the first group of panel input ports and the eighth panel input port in the second group of panel input ports). Each third sub-pixel PIX3 corresponds to a pixel driver circuit PDC whose third initialization connection port Vinit3 is connected to the same two panel input ports (the ninth panel input port in the first group of panel input ports and the ninth panel input port in the second group of panel input ports).

[0056] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 5 and Figure 7 The source drive circuit has a source driver IC, wherein the source driver IC has multiple driver output ports Q (see...). Figure 5 The source driver IC generates an initialization voltage through its internal voltage processing circuit and outputs it through the driver output ports Q1, Q2, Q3 and Q4.

[0057] Optionally, when the number of driver output ports Q is not less than the number of panel input ports in each group of panel input ports, the driver output ports Q are connected one-to-one with the panel input ports to enable the source driver IC to apply initialization voltage to the panel input ports (initialization connection port Vinit).

[0058] Optional, see Figure 5 When the number of driver output ports Q is less than the number of panel input ports in each panel input port group, to avoid redeveloping the source driver IC, this disclosure proposes an integrated voltage divider module QM. The integrated voltage divider module QM is configured such that any one driver output port Q is electrically connected to at least one panel input port. It is understood that a driver output port Q can be connected to one panel input port, or it can be connected to two panel input ports. Of course, a driver output port Q can also be connected to three, four, or other panel input ports, depending on the requirements.

[0059] In this disclosure, when the initialization voltage is the same, electrical connection can be made by connecting the same driver output port Q. "Same" in this disclosure means that all values ​​within a certain range of difference are considered the same.

[0060] In one embodiment of this disclosure, the source driver IC further has an enable interface KQ, and the integrated voltage divider module QM has an enable control unit SN. The enable interface KQ is electrically connected to the enable control unit SN, and the enable control unit SN is configured to control the integrated voltage divider module QM to turn on or off. The source driver IC is also configured to control the enable control unit SN to turn on or off. In other words, the source driver IC is further configured to control the integrated voltage divider module QM to turn on or off via the enable control unit SN.

[0061] In one embodiment of this disclosure, the number of integrated voltage divider modules QM is at least one. For example, the number of integrated voltage divider modules QM is one. Alternatively, the number of integrated voltage divider modules QM is at least two. When multiple integrated voltage divider modules QM are present, the source driver IC can drive the corresponding integrated voltage divider module QM to turn on or off by controlling the enable control unit SN of the integrated voltage divider module QM. Of course, which integrated voltage divider module QM is specifically activated depends on actual requirements.

[0062] In one embodiment of this disclosure, any two integrated voltage divider modules QM forming a module pair have at least one adjustment interface corresponding to that module pair. The at least one adjustment interface is different from the driver output port Q connected to one module in the module pair through the driver output port Q connected to the other module in the module pair; the adjustment interface is one of the various panel input ports. It is understood that when there are two integrated voltage divider modules QM, there is one module pair. When there are three integrated voltage divider modules QM, there are three module pairs. When there are four integrated voltage divider modules QM, there are six module pairs, and so on.

[0063] In one embodiment of this disclosure, the integrated voltage divider module QM can achieve its functions using switches and corresponding connection wiring. Of course, the same functions can also be achieved in other ways.

[0064] In one embodiment of this disclosure, the integrated voltage divider module QM can be integrated onto the source driver IC. Alternatively, it can be configured independently or integrated into other structures.

[0065] In this example, taking the pixel driver circuit PDC as a 7T1C structure, the different configuration methods of each integrated voltage divider module QM when there are multiple integrated voltage divider modules QM are explained: See Figure 3 and Figure 5 The system integrates two voltage divider modules (QM). Each pixel driver circuit (PDC) has a first initialization connection port (Vinit1) and a second initialization connection port (Vinit2). The source driver IC has four driver output ports (Q1, Q2, Q3, Q4), and the display panel (PNL) has six panel input ports (Vinit1-R, Vinit2-R, Vinit1-G, Vinit2-G, Vinit1-B, Vinit2-B). The sub-pixel (PIX) includes a first sub-pixel (PIX1), a second sub-pixel (PIX2), and a third sub-pixel (PIX3); wherein the first sub-pixel (PIX1) is a red sub-pixel, the second sub-pixel (PIX2) is a green sub-pixel, and the third sub-pixel (PIX3) is a blue sub-pixel.

[0066] See Figure 5In the first integrated voltage divider module QM1, the panel input port Vinit1-R, which connects to the first initialization connection port Vinit1 corresponding to the first sub-pixel PIX1, and the panel input port Vinit2-G, which connects to the second initialization connection port Vinit2 corresponding to the second sub-pixel PIX2, are connected to the same driver output port Q1 through the first integrated voltage divider module QM1; the panel input port Vinit1-B, which connects to the first initialization connection port Vinit1 corresponding to the third sub-pixel PIX3, and the panel input port Vinit2-R, which connects to the second initialization connection port Vinit2 corresponding to the first sub-pixel PIX1, are connected to the same driver output port Q3 through the first integrated voltage divider module QM1; the panel input port Vinit1-G, which connects to the first initialization connection port Vinit1 corresponding to the second sub-pixel PIX2, is connected to the driver output port Q2 through the first integrated voltage divider module QM1; and the panel input port Vinit2-B, which connects to the second initialization connection port Vinit2 corresponding to the third sub-pixel PIX3, is connected to the driver output port Q4 through the first integrated voltage divider module QM1.

[0067] In the second integrated voltage divider module QM2, the panel input port Vinit1-R, which connects to the first initialization connection port Vinit1 corresponding to the first sub-pixel PIX1, and the panel input port Vinit2-B, which connects to the second initialization connection port Vinit2 corresponding to the third sub-pixel PIX3, are connected to the same driver output port Q1 through the second integrated voltage divider module QM2; the panel input port Vinit1-G, which connects to the first initialization connection port Vinit1 corresponding to the second sub-pixel PIX2, and the panel input port Vinit2-R, which connects to the second initialization connection port Vinit2 corresponding to the first sub-pixel PIX1, are connected to the same driver output port Q2 through the second integrated voltage divider module QM2. The panel input port Vinit1-B, which connects to the first initialization connection port Vinit1 corresponding to the third sub-pixel PIX3, is connected to the driver output port Q3 through the second integrated voltage divider module QM2; the panel input port Vinit2-G, which connects to the second initialization connection port Vinit2 corresponding to the second sub-pixel PIX2, is connected to the driver output port Q4 through the second integrated voltage divider module QM2.

[0068] The connection method of the pixel driving circuit PDC based on 8T1C can be adapted to actual needs by designing and adjusting the corresponding integrated voltage divider module QM.

[0069] Of course, in other implementations, the number of integrated voltage divider modules (QM) can be set according to requirements.

[0070] In one embodiment of this disclosure, the source driver IC has a lookup table (LUT), which can retrieve the lookup table and output the corresponding initialization voltage.

[0071] In one example, the number of query table LUTs is one.

[0072] In another example, see Figure 5 The number of lookup tables (LUTs) is at least two (in one example, there are two LUTs, namely LUT1 and LUT2), and each LUT corresponds to a different display mode of the display panel PNL; each LUT can output an initialization voltage through the driver output port Q. The source driver IC is configured to call the corresponding LUT based on the different display modes of the display panel PNL and output the initialization voltage through the driver output port Q.

[0073] In one embodiment of this disclosure, the integrated voltage divider module QM can be disposed on a flexible circuit board (FPC) (not shown in the figure).

[0074] See in this example. Figure 7 ( Figure 7 The diagram only shows the connection method of the panel input port corresponding to the third initialization connection port Vinit3 of the 8T1C pixel driving circuit. A voltage regulator WT can be set on the flexible circuit board (FPC), and the initialization voltages output by the integrated voltage divider module QM are output after passing through the voltage regulator WT. In other words, the voltage regulator WT is electrically connected to the integrated voltage divider module QM, and at the same time, the voltage regulator WT is electrically connected to the panel input port, thereby sending the regulated initialization voltage to the panel input port. In this disclosure, setting the voltage regulator WT to output the regulated initialization voltage can avoid the problem of initialization voltage deviation caused by voltage drop and internal circuit loss of the source driver IC. It can be understood that the output terminal of the integrated voltage divider module QM is connected to the voltage regulator WT through the flexible circuit board (FPC), and the voltage regulator WT outputs the regulated initialization voltage through the flexible circuit board (FPC).

[0075] In other embodiments of this disclosure, the integrated voltage divider module QM can also be integrated onto the source driver.

[0076] In summary, this disclosure proposes an additional integrated voltage divider module QM, which, without altering the existing source driver IC structure, enables individual control of the initialization voltage of each sub-pixel (PIX). It allows for the selection of initialization voltages with similar characteristics for multiplexing output (using the same driver output interface), eliminating the limitation on the number of driver output interfaces of the source driver IC. This makes the source driver IC suitable for different display panel PNLs and different display modes, significantly reducing costs and improving the flexibility of display panel PNL design (the source driver IC can flexibly control the output of the initialization voltage through the integrated voltage divider module QM). Furthermore, by adopting the scheme in this disclosure, the initialization voltage is independently controlled according to the characteristics of the sub-pixel (PIX), optimizing image quality and making the output of the initialization voltage more stable.

[0077] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized in that, It has a display area and a non-display area; In the display area, the display panel has multiple panel input ports, which are used to input initialization voltage; In the non-display area, the display panel has a source drive circuit, which includes a source driver and an integrated voltage divider module; The source driver has multiple driver output ports, which are used to output initialization voltage. The number of driver output ports is less than the number of panel input ports, and the integrated voltage divider module is configured such that any one of the driver output ports is electrically connected to at least one of the panel input ports; The number of integrated voltage divider modules is at least two, and each integrated voltage divider module has an enable control unit. The enable control unit is configured to control the integrated voltage divider module to turn on or off, and the source driver is configured to control each of the enable control units to turn on or off. Any two of the integrated voltage divider modules form a module pair, which has at least one adjustment interface corresponding to the module pair. The driver output port connected to one of the modules in the module pair through the adjustment interface is different from the driver output port connected to the other module in the module pair. The adjustment interface is one of the panel input ports.

2. The display panel according to claim 1, characterized in that, In the display area, the display panel has multiple display units; The display unit includes sub-pixels and a pixel driving circuit that drives the sub-pixels to emit light. The pixel driving circuit has at least one initialization connection port. The same initialization connection port of each pixel driving circuit of the sub-pixels with the same luminous color is connected to the same panel input port.

3. The display panel according to claim 2, characterized in that, The source driver has a lookup table, and the source driver is configured to call the lookup table and output an initialization voltage through the driver output port.

4. The display panel according to claim 3, characterized in that, The source driver has at least two lookup tables, each lookup table corresponding to a different display mode of the display panel; The source driver is configured to call the corresponding lookup table based on different display modes of the display panel, and output the initialization voltage through the driver output port.

5. The display panel according to claim 4, characterized in that, In the non-display area, the display panel is bonded to a flexible circuit board; the integrated voltage divider module is disposed on the flexible circuit board; A voltage regulator is also provided on the flexible circuit board. The output terminal of the integrated voltage divider module is electrically connected to the input terminal of the voltage regulator, and the output terminal of the voltage regulator is electrically connected to the panel input port. The voltage regulator is configured to regulate the initial voltage output by the integrated voltage divider module and output the regulated initial voltage to the panel input port.

6. The display panel according to claim 5, characterized in that, The display panel has two sets of panel input port groups, and each set of panel input port groups includes the plurality of panel input ports; The output terminal of the voltage regulator is electrically connected to the two sets of panel input ports respectively; the voltage regulator is configured to regulate the initial voltage output by the integrated voltage divider module and output the regulated initial voltage to the two sets of panel input ports.

7. The display panel according to claim 6, characterized in that, The number of integrated voltage divider modules is two, and each pixel driving circuit has a first initialization connection port and a second initialization connection port; The source driver has four driver output ports, and the display panel has six panel input ports; the sub-pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In one of the integrated voltage divider modules, the panel input port connected to the first initialization connection port corresponding to the first sub-pixel and the panel input port connected to the second initialization connection port corresponding to the second sub-pixel are connected to the same driver output port through the integrated voltage divider module; the panel input port connected to the first initialization connection port corresponding to the third sub-pixel and the panel input port connected to the second initialization connection port corresponding to the first sub-pixel are connected to the same driver output port through the integrated voltage divider module. In another integrated voltage divider module, the panel input port connected to the first initialization connection port corresponding to the first sub-pixel and the panel input port connected to the second initialization connection port corresponding to the third sub-pixel are connected to the same driver output port through the integrated voltage divider module; the panel input port connected to the first initialization connection port corresponding to the second sub-pixel and the panel input port connected to the second initialization connection port corresponding to the first sub-pixel are connected to the same driver output port through the integrated voltage divider module.

8. A display device, characterized in that, It has a display panel as described in any one of claims 1-7.

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