Driving circuit of display panel and display device

Abstract

The application provides a driving circuit of a display panel and a display device, wherein the driving circuit of the display panel comprises a gate driving circuit and a compensation circuit; the compensation circuit comprises an OR gate circuit, an inverting circuit and a digital-to-analog conversion circuit; the OR gate circuit performs OR operation on signals on a plurality of gate connection lines, thereby outputting corresponding level signals; the inverting circuit and the digital-to-analog conversion circuit sequentially perform inversion and digital-to-analog conversion on the level signals, thereby outputting corresponding row opening signals and row closing signals to scan lines connected with abnormal gate connection lines, signal compensation is realized, one or more abnormal gate connection lines or gate driving units can be determined through OR operation, and through the setting of the inverting circuit and the digital-to-analog conversion circuit, the signals on the abnormal gate connection lines can be directly converted into compensation signals and provided to corresponding scan lines, signal compensation is realized, thereby avoiding the appearance of dark lines or weak lines and improving display effect.

Description

Technical Field

[0001] This invention belongs to the field of display panel technology, and particularly relates to a driving circuit and display device for a display panel. Background Technology

[0002] The driving circuit of a display panel typically includes a gate driving circuit, which includes multiple cascaded gate driving units connected to the scan lines of the display panel. During scanning, the cascaded gate driving units output line scan signals line by line to scan the display panel line by line.

[0003] The gate driving unit is connected to the scan lines of the display panel via gate connection lines. Due to manufacturing process limitations, the connection lines between the gate driving unit and the scan lines of the display panel may experience open circuits or poor contact, leading to display defects such as bright spots, dark spots, and flashes. Gate driving unit-related defects account for a relatively high percentage. Short circuits in the gate connection lines can prevent the thin-film transistors of the current row of pixel units from turning on properly, resulting in dark or weak lines on the display panel. If these abnormal display conditions cannot be repaired, they will cause significant economic losses. Summary of the Invention

[0004] The purpose of this invention is to provide a driving circuit for a display panel, which aims to solve the problem of dark or weak lines appearing on the display screen when there are poor connection lines in the traditional gate driving unit.

[0005] A first aspect of this invention provides a driving circuit for a display panel, comprising:

[0006] The gate driving circuit includes a plurality of gate driving units connected in sequence. The plurality of gate driving units are connected to a plurality of scan lines of the display panel through a plurality of gate connection lines. The plurality of gate driving units are used to output line scan signals line by line.

[0007] The compensation circuit includes:

[0008] An OR gate circuit is connected to multiple gate connection lines respectively. The OR gate circuit is used to perform an OR operation on the signals on the multiple gate connection lines and output multiple level signals in sequence, including high level signals and / or low level signals.

[0009] An inverting circuit, connected to the OR gate circuit, is used to sequentially invert multiple level signals and sequentially output the inverted level signals;

[0010] A digital-to-analog converter circuit, connected to the inverting circuit and the target scan line, is used to perform digital-to-analog conversion on the inverted high-level signal and convert it into the row enable signal, or to perform digital-to-analog conversion on the inverted low-level signal into the row disable signal, and output the row enable signal or the row disable signal to the target scan line accordingly. The target scan line is a scan line connected to the disconnected gate connection line or a scan line connected to the abnormal gate driving unit.

[0011] Optionally, the OR gate circuit includes a plurality of first diodes;

[0012] The anode of each first diode is connected to a gate connection line, and the cathodes of the plurality of first diodes are connected to form the output terminal of the OR gate circuit.

[0013] Optionally, the OR gate circuit includes a plurality of thin-film transistors;

[0014] The drain and gate of each of the thin-film transistors are connected to a gate connection line, and the source connections of the plurality of thin-film transistors form the output of the OR gate circuit.

[0015] Optionally, the inverting circuit includes a first resistor, a transistor, and a second diode;

[0016] The first end of the first resistor is connected to the positive voltage terminal, the second end of the first resistor, the collector of the transistor, and the anode of the second diode are connected, the cathode of the second diode constitutes the output terminal of the inverting circuit, the base of the transistor constitutes the input terminal of the inverting circuit, and the emitter of the transistor is grounded.

[0017] Optionally, the compensation circuit further includes:

[0018] A voltage divider circuit is connected to the output terminal of the OR gate circuit and the first reference voltage terminal. The voltage divider circuit is used to proportionally divide the voltage difference between the output signal of the OR gate circuit and the first reference voltage terminal, and output the divided voltage signal to the inverting circuit. The first reference voltage is less than the voltage of the row enable signal and greater than the voltage of the row disable signal.

[0019] Optionally, the voltage divider circuit includes a second resistor, a third resistor, and a capacitor;

[0020] The first end of the second resistor and the first end of the capacitor are connected to form the input terminal of the voltage divider circuit. The second end of the second resistor, the second end of the capacitor and the first end of the third resistor are connected to form the output terminal of the voltage divider circuit. The second end of the third resistor is connected to the reference voltage terminal.

[0021] Optionally, the digital-to-analog converter circuit includes:

[0022] The comparator has its non-inverting input terminal forming the input terminal of the digital-to-analog converter circuit, its inverting input terminal being used to input a second reference voltage, its positive power supply terminal being used to input the row enable signal, its negative power supply terminal being used to input the row disable signal, and its output terminal forming the output terminal of the digital-to-analog converter circuit. The second reference voltage is less than the voltage of the row enable signal.

[0023] The first repair line is connected to the output of the comparator and the first end of the target scan line.

[0024] Optionally, the digital-to-analog converter circuit further includes:

[0025] The second repair line is connected to the output of the comparator and the second end of the target scan line.

[0026] Optionally, the compensation circuit further includes:

[0027] The digital-to-analog converter circuit is connected to multiple scan lines via multiple switches. Each switch is turned on by a first switch signal and turned off by a second switch signal.

[0028] A switch control circuit is connected to the OR gate circuit and the plurality of switches respectively. The switch control circuit is used for:

[0029] The scanning time of each frame is divided into multiple unit time periods, each unit time period corresponds to the output time period of the line start signal, and the output signal of the OR gate circuit in each unit time period is detected when the frame start signal is received.

[0030] When a high-level signal is detected in the i-th unit time period, multiple second switch signals are output to the multiple switches;

[0031] When a low-level signal is detected in the i-th unit time period, the first switch signal is continuously output to the switch connected to the i-th gate drive unit within the unit time period, and multiple second switch signals are output to other switches.

[0032] A second aspect of the present invention provides a display device, including a display panel and a driving circuit for the display panel as described above, wherein the driving circuit for the display panel is connected to the display panel.

[0033] The beneficial effects of the present invention compared with the prior art are as follows: The driving circuit of the above-mentioned display panel includes a gate driving circuit and a compensation circuit. The compensation circuit includes an OR gate circuit, an inverting circuit, and a digital-to-analog converter circuit. The gate driving circuit includes multiple gate driving units cascaded in sequence. The gate driving units are connected to the scan lines of the display panel through gate connection lines. The OR gate circuit performs an OR operation on the signals on multiple gate connection lines to output corresponding level signals. The inverting circuit and the digital-to-analog converter circuit sequentially invert and convert the level signals to digital-to-analog, thereby outputting corresponding row enable signals and row disable signals to the scan lines connected to the abnormal gate connection lines to achieve signal compensation. Through the OR gate operation, multiple gate connection lines and corresponding gate driving units can be synchronously operated to determine one or more abnormal gate connection lines or gate driving units. Furthermore, by setting the inverting circuit and the digital-to-analog converter circuit, the signals on the abnormal gate connection lines can be directly converted into compensation signals and provided to the corresponding scan lines to achieve signal compensation, thereby avoiding dark lines or weak lines and improving the display effect. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a first structure of the display panel and the driving circuit of the display panel provided in Embodiment 1 of the present invention;

[0035] Figure 2 This is a schematic diagram of a second structure of the display panel and the driving circuit of the display panel provided in Embodiment 1 of the present invention;

[0036] Figure 3 This is a waveform timing diagram of the row scanning signal provided in Embodiment 1 of the present invention;

[0037] Figure 4 This is a schematic diagram of the signals on the gate connection line provided in Embodiment 1 of the present invention;

[0038] Figure 5 This is a schematic diagram of the output signal of the OR gate circuit provided in Embodiment 1 of the present invention;

[0039] Figure 6 This is a schematic diagram of the first type of OR gate circuit provided in Embodiment 1 of the present invention;

[0040] Figure 7 This is a second circuit diagram of the OR gate circuit provided in Embodiment 1 of the present invention;

[0041] Figure 8 This is a circuit diagram of the inverting circuit provided in Embodiment 1 of the present invention;

[0042] Figure 9 This is a schematic diagram of the compensation circuit provided in Embodiment 1 of the present invention;

[0043] Figure 10 This is a circuit diagram of the voltage divider circuit and the inverter circuit provided in Embodiment 1 of the present invention;

[0044] Figure 11 This is a circuit diagram of the digital-to-analog converter circuit provided in Embodiment 1 of the present invention;

[0045] Figure 12 This is a schematic diagram of a third structure of the display panel and the driving circuit of the display panel provided in Embodiment 1 of the present invention;

[0046] Figure 13 This is a schematic diagram of the structure of the display panel and the driving circuit of the display panel provided in Embodiment 2 of the present invention;

[0047] Figure 14 This is a schematic diagram of the structure of the display device provided in Embodiment 3 of the present invention.

[0048] The figures in the diagram are labeled as follows:

[0049] 1. Flexible circuit board; 2. Chip-on film; 100. Display panel; 200. Driving circuit of display panel; 210. Gate driving circuit; 220. Compensation circuit; 211. Gate driving unit; 221. OR gate circuit; 222. Inverting circuit; 223. Digital-to-analog converter circuit; 224. Voltage divider circuit; 225. Switching control circuit;

[0050] L1, gate connection line; L2, first repair line; L3, second repair line; D1, first diode; D11, second diode; R1, first resistor; R2, second resistor; R3, third resistor; C1, capacitor; K1, transistor; T1, thin-film transistor; Q1, switch; U1, comparator;

[0051] Vgh, Horizontal Array Enable signal; Vgl, Horizontal Array Disable signal; Vout1, Output signal of OR gate circuit; Vout2, Output signal of inverter circuit; Vout3, Output signal of digital-to-analog converter circuit; Vref1, First reference voltage; Vref2, Second reference voltage. Detailed Implementation

[0052] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0053] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0054] Example 1

[0055] A first aspect of this invention provides a driving circuit 200 for a display panel, such as... Figure 1 and Figure 2 As shown, it includes:

[0056] The gate driving circuit 210 includes a plurality of gate driving units 211 connected in sequence. The plurality of gate driving units 211 are connected to a plurality of scan lines of the display panel 100 through a plurality of gate connection lines L1. The plurality of gate driving units 211 are used to output line scan signals line by line.

[0057] Compensation circuit 220, the compensation circuit 220 includes:

[0058] OR gate circuit 221 is connected to multiple gate connection lines L1 respectively. OR gate circuit 221 is used to perform OR operation on the signals on multiple gate connection lines L1 and output multiple level signals in sequence. The multiple level signals include high level signals and / or low level signals.

[0059] Inverting circuit 222, connected to OR gate circuit 221, is used to sequentially invert multiple level signals and output the inverted level signals sequentially.

[0060] The digital-to-analog converter circuit 223 is connected to the inverting circuit 222 and the target scan line. It is used to convert the inverted high-level signal into a digital-to-analog signal and convert it into a row enable signal Vgh, or to convert the inverted low-level signal into a digital-to-analog signal Vgl and output the corresponding row enable signal Vgh or row disable signal Vgl to the target scan line. The target scan line is a scan line connected to the disconnected gate connection line L1 or a scan line connected to the abnormal gate drive unit 211.

[0061] In this embodiment, the gate driving circuit 210 is a GOA (Gate Driver on Array) circuit. The GOA circuit integrates the TFT (Thin Film Transistor) in the gate driving circuit 210 onto the array substrate, thereby eliminating the gate driving integrated circuit part that was originally set outside the array substrate, reducing the cost of the product from both material cost and process steps.

[0062] When a GOA circuit is used, the GOA circuit is bonded to the non-display area of ​​the display panel 100. The display area 110 of the display panel 100 is provided with multiple data lines, multiple scan lines and multiple array-arranged pixel units. Each pixel unit is connected to a corresponding data line and a scan line. Each pixel unit is composed of a corresponding thin-film transistor T1, a liquid crystal capacitor and a storage capacitor.

[0063] The display panel driving circuit 200 may further include a source driving circuit and a timing controller. The timing controller outputs control signals to the source driving circuit and the gate driving circuit 210 to control the source driving circuit to output data signals and control the gate driving circuit 210 to output line scanning signals.

[0064] like Figure 1 As shown, the source drive circuit can be composed of multiple flip-chip thin films 2. Each flip-chip thin film 2 is provided with a drive chip and a transmission channel. The flip-chip thin film 2 can also be connected to the flexible circuit board 1. The flexible circuit board 1 can be provided with a corresponding timing controller and power management integrated circuit.

[0065] The gate driving circuit 210 includes multiple cascaded gate driving units 211. The gate driving units 211 can be structures such as shift registers, and the multiple cascaded gate driving units 211 output row scanning signals line by line.

[0066] The gate drive circuit 210 can be adopted as follows: Figure 1 The dual-side drive shown or using, for example Figure 2 As shown in the single-sided driving and dual-sided driving, gate driving circuits 210 are respectively provided on both sides of the display panel 100, and row scanning signals are generated simultaneously, which can improve the driving capability. When single-sided driving is used, gate driving circuit 210 is provided on one side of the display panel 100, and row scanning signals are output line by line.

[0067] The row scanning signal consists of a row enable signal Vgh and a row disable signal Vgl. When scanning a row, the corresponding gate driving unit 211 outputs the row enable signal Vgh through the gate connection line L1 to the scan line of that row. The thin film transistors T1 of each pixel unit in that row are turned on and input data signals. The pixel units in that row display the corresponding display information. Other gate driving units 211 output the row disable signal Vgl through the gate connection line L1 to the scan lines of other rows. The thin film transistors T1 of each pixel unit in other rows are turned off and no display information is displayed.

[0068] In each frame, the line enable signal Vgh is output line by line, thereby enabling the pixel units of each line and displaying the current frame's display screen.

[0069] Among them, such as Figure 3As shown, each frame can be divided into multiple unit time periods t0 according to the output period of the row enable signal Vgh. Each unit time period t0 corresponds to the output period of the row enable signal Vgh. When the gate drive unit 211 normally outputs each row scan signal, the phases of each row scan signal differ by one unit phase. The row scan signal of the previous stage gate drive unit 211 leads the gate drive unit 211 of the next stage, and the output duration of each row scan signal is the same, and the time of the unit phase is equal to the output duration of each row scan signal.

[0070] During manufacturing or use, there may be a break in the gate connection line L1 or an abnormality in the gate drive unit 211, such as... Figure 4 As shown in the waveform diagram on the left, when the gate driving unit 211 is normal and the gate connection line L1 is not broken or short-circuited, the gate driving unit 211 outputs a row scan signal composed of the row enable signal Vgh and the row disable signal Vgl to the scan line. When the gate driving unit 211 malfunctions, as ... the gate driving unit 211 outputs a row scan signal composed of the row enable signal Vgh and the row disable signal Vgl to the scan line. Figure 4 As shown in the waveform diagrams in the middle and on the right, there may be insufficient or no output voltage, which may cause the pixel units in the corresponding row of the display panel 100 to malfunction, thus causing the display panel 100 to display abnormally.

[0071] To solve this problem, the display panel driving circuit 200 is also equipped with a compensation circuit 220, which uses signal detection, signal compensation and voltage compensation methods to perform compensation output.

[0072] First, the OR gate circuit 221 connects each gate connection line L1 and performs an OR operation on the multiple signals output by the multiple gate driving units 211 to identify the target scan line that needs to be compensated. When each gate driving unit 211 outputs a row scan signal normally and the gate connection line L1 is not disconnected, one of the gate driving units 211 outputs a row enable signal Vgh, and the other gate driving units 211 maintain the output of a row disable signal Vgl. The OR gate circuit 221 then outputs a high-level signal sequentially during line-by-line scanning.

[0073] When one of the gate drive units 211 malfunctions or one of the gate connection lines L1 is disconnected, when the row is scanned to that row, the voltage of the corresponding gate connection line L1 is insufficient or low level, and the remaining gate drive units 211 maintain the output of the row turn-off signal Vgl, or the gate circuit 221 outputs a low level signal when the row is scanned to that row.

[0074] For example, assuming the abnormal output occurs in line 82, when scanning line by line from line 1 to line 81, OR gate circuit 221 outputs a high-level signal sequentially according to the unit time period t0. When scanning to line 82, OR gate circuit 221 outputs a low-level signal. The gate connection line L1 or gate driving unit 211 corresponding to line 82 is the module to be repaired or replaced, and line 82 is the object to be compensated for.

[0075] The location of the abnormality can be determined by the OR gate circuit 221, and then the abnormal signal is filtered and compensated by the inverting circuit 222 and the digital-to-analog converter circuit 223 in the compensation stage.

[0076] In order to achieve normal output, an inverter circuit 222 is used to invert the level signal output by the front-end OR gate circuit 221, converting the high-level signal output by the OR gate circuit 221 into a low-level signal, and converting the low-level signal output by the OR gate circuit 221 into a high-level signal, thereby filtering out the abnormal signals that need to be processed.

[0077] The output of OR gate 221 or inverter 222 can also be connected to a corresponding processor or display. Based on the output signal Vout1 of OR gate 221 or the output signal Vout2 of inverter 222, maintenance personnel can determine the abnormal gate connection line L1 or the abnormal gate drive unit 211. For example, when a low-level signal is obtained from the output of OR gate 221, or when a high-level signal is obtained from the output of inverter 222, the abnormal location can be determined based on the display information or time information.

[0078] Then, maintenance personnel can connect the analog-to-digital converter circuit 223 to the corresponding scan line using methods such as laser scanning, for example... Figure 5 As shown, assuming Gm is the scan line of row 82, and the gate connection line L1 connected to the scan line is broken, the gate connection line L1 is first disconnected from the scan line by laser, where × represents the disconnection point, and the output terminal of the digital-to-analog converter circuit 223 is connected to the scan line by laser or other means.

[0079] When the gate connection line L1 in row 82 is disconnected, the OR gate circuit 221 outputs a low-level signal when scanning to row 82, and the inverter circuit 222 inverts the output to a high-level signal. The high-level signal is converted into a row enable signal Vgh by the digital-to-analog converter circuit 223 and output to the scan line of row 82 to achieve signal compensation. The row enable signal Vgh is normally output to the thin-film transistor T1 of the pixel unit corresponding to row 82. The thin-film transistor T1 is turned on and displays normally, thereby avoiding dark or weak lines in row 82 and improving the display effect.

[0080] Then, when scanning to other rows, the OR gate circuit 221 normally outputs a high-level signal, the inverting circuit 222 inverts and outputs a low-level signal, and converts it through the digital-to-analog converter circuit 223 to output a row turn-off signal Vgl. The row turn-off signal Vgl is output to the scan line of the 82nd row. The row turn-off signal Vgl is normally output to the thin-film transistor T1 of the pixel unit corresponding to the 82nd row. The thin-film transistor T1 is turned off, and the pixel unit corresponding to the 82nd row can normally receive the row scanning signal and display and stop display normally.

[0081] The OR gate circuit 221 can be made of corresponding logic gates, components, etc. In an optional embodiment, such as... Figure 6 As shown, the OR gate circuit 221 includes a plurality of first diodes D1;

[0082] The anode of each first diode D1 is connected to a gate connection line L1, and the cathodes of multiple first diodes D1 are connected to form the output terminal of OR gate circuit 221.

[0083] In this embodiment, when the corresponding gate driving unit 211 and the corresponding gate connection line L1 are normal, during line-by-line scanning, one of the gate driving units 211 outputs a line-on signal Vgh, and the other gate driving units 211 output a line-off signal Vgl. Then, after multiple first diodes D1 are connected in parallel, multiple first diodes D1 output a high-level signal.

[0084] Alternatively, when one of the gate drive units 211 malfunctions or the connected gate connection line L1 is disconnected, when scanning to that row, the corresponding first diode D1 outputs a low-level signal, and the other first diodes D1 also output a low-level signal. Then, the multiple first diodes D1 connected in parallel output low-level signals. The location of the malfunctioning gate drive unit 211 or the malfunctioning gate connection line L1 can be determined according to the timing of the low-level signals.

[0085] like Figure 7 As shown, in another alternative embodiment, the OR gate circuit 221 includes a plurality of thin-film transistors T1;

[0086] The drain and gate of each thin-film transistor T1 are connected to a gate connection line L1, and the source connections of multiple thin-film transistors T1 form the output terminal of OR gate circuit 221.

[0087] In this embodiment, when the corresponding gate driving unit 211 and the corresponding gate connection line L1 are normal, during line-by-line scanning, one of the gate driving units 211 outputs a line-on signal Vgh, and the other gate driving units 211 output a line-off signal Vgl. Then, after multiple first diodes D1 are connected in parallel, multiple first diodes D1 output a high-level signal.

[0088] Alternatively, when one of the gate drive units 211 malfunctions or the connected gate connection line L1 is disconnected, when scanning to that row, the corresponding first diode D1 outputs a low-level signal, and the other first diodes D1 also output a low-level signal. Then, the multiple first diodes D1 connected in parallel output low-level signals. The location of the malfunctioning gate drive unit 211 or the malfunctioning gate connection line L1 can be determined according to the timing of the low-level signals.

[0089] The inverting circuit 222 can be composed of an inverter and a corresponding switching circuit. In an optional embodiment, such as... Figure 8 As shown, the inverter circuit 222 includes a first resistor R1, a transistor K1, and a second diode D11;

[0090] The first end of the first resistor R1 is connected to the positive voltage terminal. The second end of the first resistor R1, the collector of the transistor K1, and the anode of the second diode D11 are connected. The cathode of the second diode D11 forms the output terminal of the inverting circuit 222. The base of the transistor K1 forms the input terminal of the inverting circuit 222. The emitter of the transistor K1 is grounded.

[0091] In this embodiment, Vout1 is the output signal of OR gate 221, and Vout2 is the output signal of inverter 222. When OR gate 221 outputs a high level, transistor K1 in inverter 222 is turned on and outputs a low level signal to digital-to-analog converter 223. When OR gate 221 outputs a low level, transistor K1 in inverter 222 is turned off, and inverter 222 maintains the output of a high level signal to digital-to-analog converter 223.

[0092] The second diode D11 enables unidirectional transmission of the level signal, which can prevent the digital-to-analog converter circuit 223 from transmitting the signal in reverse to the inverting circuit 222, thus avoiding damage to the device.

[0093] Furthermore, when the gate drive unit 211 malfunctions, its output voltage is insufficient, but it may still cause the OR gate circuit 221 to output a high-level signal. At this time, the high-level signal may still trigger the transistor K1 to conduct, causing the inverter circuit 222 to output a low-level signal, thus making it impossible to identify the valid abnormal signal and determine the abnormal location.

[0094] Therefore, such as Figure 9 As shown, in an optional embodiment, the compensation circuit 220 further includes:

[0095] Voltage divider circuit 224 is connected to the output terminal of OR gate circuit 221 and the first reference voltage Vref1 terminal. Voltage divider circuit 224 is used to proportionally divide the voltage difference between the output signal Vout1 of OR gate circuit 221 and the first reference voltage Vref1 terminal, and output the divided voltage signal to inverter circuit 222. The first reference voltage Vref1 is less than the voltage of the horizontal enable signal Vgh and greater than the voltage of the horizontal disable signal Vgl.

[0096] In this embodiment, the voltage divider circuit 224 outputs a high-level signal to the output signal Vout1 of the OR gate circuit 221 and the first reference voltage Vref1. When the output voltage of the gate driving unit 211 is insufficient and less than the row enable signal Vgh, the OR gate circuit 221 still outputs a high-level signal. At this time, the voltage of the high-level signal is equal to the output voltage of the abnormal gate driving unit 211. After voltage division, the voltage signal received by the transistor K1 is less than the threshold voltage, and the transistor K1 cannot be turned on. The inverter circuit 222 can output a high-level signal normally. Thus, the abnormal position can be determined according to the output signal Vout2 of the inverter circuit 222.

[0097] The voltage divider circuit 224 can use corresponding voltage divider resistors, such as... Figure 10 As shown, in an optional embodiment, the voltage divider circuit 224 includes a second resistor R2, a third resistor R3, and a capacitor C1;

[0098] The first end of the second resistor R2 and the first end of the capacitor C1 are connected to form the input terminal of the voltage divider circuit 224. The second end of the second resistor R2, the second end of the capacitor C1 and the first end of the third resistor R3 are connected to form the output terminal of the voltage divider circuit 224. The second end of the third resistor R3 is connected to the reference voltage terminal.

[0099] In this embodiment, the second resistor R2 and the third resistor R3 form a voltage divider circuit 224, which divides the voltage difference between the output signal Vout1 of the OR gate circuit 221 and the first reference voltage Vref1, thereby identifying the abnormal gate drive unit 211.

[0100] Meanwhile, capacitor C1 is connected in parallel across the second resistor R2. When the OR gate 221 outputs a level signal, the level signal can be quickly fed back to transistor K1 and the third resistor R3 by utilizing the principle that the voltage across capacitor C1 cannot change abruptly, thus reducing the time delay of compensation circuit 220.

[0101] The digital-to-analog converter circuit 223 can employ a corresponding digital-to-analog converter, comparator, etc. In an optional embodiment, such as... Figure 2 and Figure 11 As shown, the digital-to-analog converter circuit 223 includes:

[0102] Comparator U1 has its non-inverting input terminal forming the input terminal of digital-to-analog converter circuit 223, its inverting input terminal being used to input the second reference voltage Vref2, its positive power supply terminal being used to input the row enable signal Vgh, its negative power supply terminal being used to input the row disable signal Vgl, and its output terminal forming the output terminal of digital-to-analog converter circuit 223. The second reference voltage Vref2 is less than the voltage of the row enable signal Vgh.

[0103] The first repair line L2 is connected to the output of comparator U1 and the first end of the target scan line.

[0104] In this embodiment, Vout3 is the output signal of the digital-to-analog converter circuit 223. When the OR gate circuit 221 inputs a high-level signal, the inverter circuit 222 outputs a low-level signal with zero voltage. This signal cannot be used as the row turn-off signal Vgl to drive the pixel unit to turn off. Therefore, a comparator U1 and a first repair line L2 are also provided between the inverter circuit 222 and the corresponding scan line of the display panel 100. Similarly, when the OR gate circuit 221 inputs a low-level signal, the inverter circuit 222 outputs a high-level signal with a positive voltage. This voltage may not be equal to the voltage of the row turn-on signal Vgh, causing the pixel unit to fail to turn on normally.

[0105] To this end, a comparator U1 is also provided for signal conversion. When one of the gate connection lines L1 is disconnected, the OR gate circuit 221 outputs a low-level signal and the inverting circuit 222 outputs a high-level signal of positive voltage. At this time, the high-level signal is greater than the second reference voltage Vref2. The comparator U1 outputs the row enable signal Vgh at the positive power supply terminal to the first repair line L2 and transmits it to the scan line at the corresponding abnormal position through the first repair line L2.

[0106] When scanning to other normal rows, the OR gate circuit 221 outputs a high-level signal, and the inverter circuit 222 outputs a low-level signal with zero voltage to the comparator U1. Since the low-level signal is less than the second reference voltage Vref2, the comparator U1 outputs a row-off signal Vgl at the negative power supply terminal to the first repair line L2, and transmits it to the corresponding scan line through the first repair line L2, so that the scan line receives the normal row-on signal Vgh and row-off signal Vgl.

[0107] Furthermore, in order to improve driving capabilities, such as Figure 1 As shown, the digital-to-analog converter circuit 223 also includes:

[0108] The second repair line L3 is connected to the output of comparator U1 and the second end of the target scan line.

[0109] In this embodiment, the gate driving circuit 210 adopts dual-side driving and is respectively set on both sides of the display area 110. The output terminal of the comparator U1 is connected to the first repair line L2 and the second repair line L3 respectively. The first repair line L2 is connected to the first end of the scan line corresponding to the abnormal position, and the second repair line L3 is connected to the second end of the scan line corresponding to the abnormal position. After the laser disconnects the scan line and the gate connection line L1, the comparator U1 outputs the normal row open signal Vgh and row close signal Vgl to the two ends of the corresponding scan line of the display panel 100, and realizes dual-side driving.

[0110] The beneficial effects of this invention embodiment compared with the prior art are as follows: The driving circuit 200 of the display panel mentioned above includes a gate driving circuit 210 and a compensation circuit 220. The compensation circuit 220 includes an OR gate circuit 221, an inverter circuit 222, and a digital-to-analog converter circuit 223. The gate driving circuit 210 includes a plurality of gate driving units 211 cascaded in sequence. The gate driving units 211 are connected to the scan lines of the display panel 100 through gate connection lines L1. The OR gate circuit 221 performs an OR operation on the signals on the plurality of gate connection lines L1, thereby outputting a corresponding level signal. The inverter circuit 222 and the digital-to-analog converter circuit 223 sequentially perform an OR operation on the level signal. The circuit employs inversion and digital-to-analog conversion to output corresponding row enable signals Vgh and row disable signals Vgl to the scan lines connected to the abnormal gate connection lines L1, thereby achieving signal compensation. Through OR gate operation, multiple gate connection lines L1 and their corresponding gate drive units 211 can be synchronously operated to identify one or more abnormal gate connection lines L1 or gate drive units 211. Furthermore, by setting up an inversion circuit 222 and a digital-to-analog conversion circuit 223, the signal on the abnormal gate connection line L1 can be directly converted into a compensation signal and provided to the corresponding scan line to achieve signal compensation, thereby avoiding dark or weak lines and improving the display effect.

[0111] Example 2

[0112] When using the solution of Embodiment 1, there is a limitation that signal compensation cannot be performed on gate connection lines L1 at multiple abnormal locations. For example, when gate connection lines L1 are broken in both rows 82 and 100, and the compensation circuit 220 is connected to the scan lines of rows 82 and 100 through repair lines, when scanning line by line to row 82, the digital-to-analog converter 223 outputs a row enable signal Vgh to the scan lines of rows 82 and 100, causing the pixel unit of row 100 to start displaying prematurely, resulting in horizontal lines on the screen. Then, when scanning line by line to row 100, the digital-to-analog converter 223 outputs a row enable signal Vgh to the scan lines of rows 82 and 100, causing the pixel unit of row 82 to start displaying again, resulting in abnormal screen display.

[0113] To solve this problem, such as Figure 13 As shown, in an optional embodiment, the compensation circuit 220 further includes:

[0114] Multiple switches Q1 are connected to multiple scan lines through the digital-to-analog converter circuit 223. The switches Q1 are turned on by the first switch signal and turned off by the second switch signal.

[0115] The switch control circuit 225 is connected to the OR gate circuit 221 and multiple switches Q1 respectively. The switch control circuit 225 is used for:

[0116] The scanning time of each frame is divided into multiple unit time periods t0. Each time period corresponds to the output time period of the line start signal Vgh. When the frame start signal is received, the output signal Vout1 of the OR gate circuit 221 in each unit time period t0 is detected.

[0117] When a high-level signal is detected in the i-th unit time period t0, multiple second switch signals are output to multiple switches Q1;

[0118] When a low-level signal is detected in the i-th unit time period t0, a first switch signal is continuously output to the switch Q1 connected to the i-th gate drive unit 211 within the unit time period t0, and multiple second switch signals are output to other switches Q1.

[0119] In this embodiment, the switching signal can divide each frame time into multiple unit time periods t0 according to the frame time and the number of gate driving units 211. Each time period outputs a line start signal Vgh, and the frame start signal is used as a trigger signal to realize the detection of each signal and the control of the switch Q1.

[0120] When the i-th gate driving unit 211 malfunctions or the connection line connected to the scan line malfunctions, the switch control circuit 225 detects a low-level signal through the OR gate circuit 221 in the i-th time period. At this time, it outputs a first switch signal to control the switch Q1 corresponding to the i-th gate driving unit 211 to turn on, and outputs a second switch signal to control the other switches Q1 to turn off. The row enable signal Vgh converted and output by the digital-to-analog converter circuit 223 is normally output to the scan line of the i-th row through the switch Q1, while the scan lines of other rows are provided with row disable signals Vgl by other gate driving units 211.

[0121] For example, if the gate connection line L1 of row 82 and row 100 is abnormal, a low-level signal is detected in the 82nd time period. The switch control circuit 225 controls the switch Q1 corresponding to the 82nd gate drive unit 211 to be turned on, and controls other switches Q1 to be turned off. The row enable signal Vgh converted and output by the digital-to-analog converter circuit 223 is normally output to the scan line of row 82 through switch Q1, and will not be output to the scan line of row 100.

[0122] When a low-level signal is detected in the 100th time period, the switch control circuit 225 controls the switch Q1 corresponding to the 100th gate drive unit 211 to be turned on, and controls other switches Q1 to be turned off. The row enable signal Vgh converted by the digital-to-analog converter circuit 223 is normally output to the scan line of the 100th row through the switch Q1, and will not be output to the scan line of the 82nd row, thereby avoiding affecting other rows, and can realize signal compensation for all abnormal gate drive units 211 or gate connection lines L1.

[0123] Each switch Q1 can be set on the display panel 100 or on the flexible circuit board 1, and the specific setting position is not limited.

[0124] The switch control circuit 225 can employ a corresponding timer and detection unit. In an optional embodiment, the switch control circuit 225 is a timing controller. The timing controller performs signal detection and switch Q1 control on the one hand, and outputs control signals to the source drive circuit and the gate drive circuit 210 on the other hand, so as to control the source drive circuit to output data signals and control the gate drive circuit 210 to output row scan signals.

[0125] Example 3

[0126] A second aspect of the present invention provides a display device, such as... Figure 14 As shown, the display device includes a display panel 100 and a driving circuit 200 for the display panel. The specific structures of the display panel 100 and the driving circuit 200 are as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The driving circuit 200 for the display panel is connected to the display panel 100.

[0127] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A driving circuit for a display panel, characterized in that, include: The gate driving circuit includes a plurality of gate driving units connected in sequence. The plurality of gate driving units are connected to a plurality of scan lines of the display panel through a plurality of gate connection lines. The plurality of gate driving units are used to output line scan signals line by line. The compensation circuit includes: An OR gate circuit is connected to multiple gate connection lines respectively. The OR gate circuit is used to perform an OR operation on the signals on the multiple gate connection lines and output multiple level signals in sequence, including high level signals and / or low level signals. An inverting circuit, connected to the OR gate circuit, is used to sequentially invert multiple level signals and sequentially output the inverted level signals; A digital-to-analog converter circuit, connected to the inverting circuit and the target scan line, is used to perform digital-to-analog conversion on the inverted high-level signal and convert it into a row enable signal, or to perform digital-to-analog conversion on the inverted low-level signal into a row disable signal, and output the row enable signal or the row disable signal to the target scan line accordingly. The target scan line is a scan line connected to the disconnected gate connection line or a scan line connected to the abnormal gate driving unit.

2. The driving circuit for the display panel as described in claim 1, characterized in that, The OR gate circuit includes a plurality of first diodes; The anode of each first diode is connected to a gate connection line, and the cathodes of the plurality of first diodes are connected to form the output terminal of the OR gate circuit.

3. The driving circuit for the display panel as described in claim 1, characterized in that, The OR gate circuit includes multiple thin-film transistors; The drain and gate of each of the thin-film transistors are connected to a gate connection line, and the source connections of the plurality of thin-film transistors form the output of the OR gate circuit.

4. The driving circuit for the display panel as described in claim 1, characterized in that, The inverting circuit includes a first resistor, a transistor, and a second diode; The first end of the first resistor is connected to the positive voltage terminal, the second end of the first resistor, the collector of the transistor, and the anode of the second diode are connected, the cathode of the second diode constitutes the output terminal of the inverting circuit, the base of the transistor constitutes the input terminal of the inverting circuit, and the emitter of the transistor is grounded.

5. The driving circuit for the display panel as described in claim 1, characterized in that, The compensation circuit further includes: A voltage divider circuit is connected to the output terminal of the OR gate circuit and the first reference voltage terminal. The voltage divider circuit is used to proportionally divide the voltage difference between the output signal of the OR gate circuit and the first reference voltage terminal, and output the divided voltage signal to the inverting circuit. The first reference voltage is less than the voltage of the row enable signal and greater than the voltage of the row disable signal.

6. The driving circuit for the display panel as described in claim 5, characterized in that, The voltage divider circuit includes a second resistor, a third resistor, and a capacitor; The first end of the second resistor and the first end of the capacitor are connected to form the input terminal of the voltage divider circuit. The second end of the second resistor, the second end of the capacitor and the first end of the third resistor are connected to form the output terminal of the voltage divider circuit. The second end of the third resistor is connected to the reference voltage terminal.

7. The driving circuit for the display panel as described in claim 1, characterized in that, The digital-to-analog converter circuit includes: The comparator has its non-inverting input terminal forming the input terminal of the digital-to-analog converter circuit, its inverting input terminal being used to input a second reference voltage, its positive power supply terminal being used to input the row enable signal, its negative power supply terminal being used to input the row disable signal, and its output terminal forming the output terminal of the digital-to-analog converter circuit. The second reference voltage is less than the voltage of the row enable signal. The first repair line is connected to the output of the comparator and the first end of the target scan line.

8. The driving circuit for the display panel as described in claim 7, characterized in that, The digital-to-analog converter circuit also includes: The second repair line is connected to the output of the comparator and the second end of the target scan line.

9. The driving circuit for the display panel as described in any one of claims 1 to 8, characterized in that, The compensation circuit further includes: Multiple switches are provided, and the digital-to-analog conversion circuit is connected to multiple scan lines through the multiple switches respectively. The switches are turned on by a first switch signal and turned off by a second switch signal. A switch control circuit is connected to the OR gate circuit and the plurality of switches respectively. The switch control circuit is used for: The scanning time of each frame is divided into multiple unit time periods, each unit time period corresponds to the output time period of the line start signal, and the output signal of the OR gate circuit in each unit time period is detected when the frame start signal is received. When a high-level signal is detected in the i-th unit time period, multiple second switch signals are output to the multiple switches; When a low-level signal is detected in the i-th unit time period, the first switch signal is continuously output to the switch connected to the i-th gate drive unit within the unit time period, and multiple second switch signals are output to other switches.

10. A display device, characterized in that, It includes a display panel and a driving circuit for the display panel as described in any one of claims 1 to 9, wherein the driving circuit for the display panel is connected to the display panel.

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