Semiconductor package and manufacturing method thereof

Abstract

The invention provides a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a first redistribution layer; a second redistribution layer; a glass substrate between the first redistribution layer and the second redistribution layer, the glass substrate including a through glass via configured to connect the first redistribution layer and the second redistribution layer; a first semiconductor chip and a second semiconductor chip on a second surface of the second redistribution layer; and a bridge chip included in the glass substrate and configured to connect the first semiconductor chip and the second semiconductor chip.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure relate to a method of manufacturing a semiconductor package having a glass interposer and a bridge chip and an apparatus thereof. BACKGROUND

[0002] According to the development of the electronic industry and the needs of users, electronic devices are becoming smaller and lighter. As electronic devices become smaller and lighter, semiconductor packages used in electronic devices are also becoming smaller and lighter, and are required to have high reliability as well as high performance and high capacity. According to the high performance and high capacity of semiconductor packages, power consumption in semiconductor packages increases. Accordingly, the importance of a structure of a semiconductor package that stably supplies power to the semiconductor package in response to the size / performance of the semiconductor package increases. SUMMARY

[0003] One or more example embodiments provide a method of manufacturing a semiconductor package having a glass interposer and a bridge chip and an apparatus thereof.

[0004] According to an aspect of one or more embodiments, there is provided a semiconductor package including: a first redistribution layer; a second redistribution layer; a glass substrate between the first redistribution layer and the second redistribution layer, the glass substrate including a through-glass via configured to connect the first redistribution layer and the second redistribution layer; a first semiconductor chip and a second semiconductor chip on a second surface of the second redistribution layer; and a bridge chip included in the glass substrate and configured to connect the first semiconductor chip and the second semiconductor chip.

[0005] According to another aspect of one or more embodiments, there is provided a method of manufacturing a semiconductor package, the method including: providing a first redistribution layer on a carrier substrate, the first redistribution layer including a first redistribution insulating layer, a first wiring pattern, and a first via connected to the first wiring pattern; providing a glass substrate including a through-glass via on the first redistribution layer, the glass substrate configured to be electrically connected to the first redistribution layer; providing a bridge chip; providing a second redistribution layer configured to be electrically connected to the glass substrate on the glass substrate, the second redistribution layer including a second redistribution insulating layer, a second wiring pattern, and a second via connected to the second wiring pattern; and providing a first semiconductor chip and a second semiconductor chip on the second redistribution layer, wherein the bridge chip is configured to electrically connect the first semiconductor chip and the second semiconductor chip.

[0006] According to yet another aspect of one or more embodiments, a semiconductor package is provided that includes a first redistribution layer including a first redistribution insulating layer, a first wiring pattern, and a first via connected to the first wiring pattern; a second redistribution layer including a second redistribution insulating layer, a second wiring pattern, and a second via connected to the second wiring pattern; a glass substrate between the first redistribution layer and the second redistribution layer, the glass substrate including a through-glass via configured to connect the first redistribution layer and the second redistribution layer; a first semiconductor chip and a second semiconductor chip on a second surface of the second redistribution layer; a bridge chip included in the glass substrate and electrically connected to the first semiconductor chip and the second semiconductor chip, the bridge chip configured to electrically connect the first semiconductor chip and the second semiconductor chip; and an external terminal on the first redistribution layer, the external terminal configured to connect the semiconductor package to a structure external to the semiconductor package. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and / or other aspects, features, and advantages of the example embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 A plan view of a panel-level glass-based semiconductor package according to one or more embodiments is shown;

[0009] Figure 2 A cross-sectional view taken along line A-A' of the panel-level glass-based semiconductor package of Figure 1

[0010] Figure 3A A cross-sectional view of forming a first redistribution layer in a method of manufacturing a panel-level glass-based semiconductor package according to one or more embodiments is shown;

[0011] Figure 3B A cross-sectional view of laminating a photosensitive film in a method of manufacturing a panel-level glass-based semiconductor package according to one or more embodiments is shown;

[0012] Figure 3C A cross-sectional view of forming a glass interposer in a method of manufacturing a panel-level glass-based semiconductor package according to one or more embodiments is shown;

[0013] Figure 3D A cross-sectional view of forming a bridge chip in a method of manufacturing a panel-level glass-based semiconductor package according to one or more embodiments is shown;

[0014] Figure 3E and Figure 3F ​A cross-sectional view showing formation of a second redistribution layer in a method of manufacturing a panel-level glass-based semiconductor package according to one or more embodiments is shown;

[0015] Figure 3G A cross-sectional view showing formation of a semiconductor chip in a method of manufacturing a panel-level glass-based semiconductor package according to one or more embodiments is shown;

[0016] Figure 3H A cross-sectional view showing formation of a mold layer is shown; Figure 3I A cross-sectional view showing formation of an external terminal in a method of manufacturing a panel-level glass-based semiconductor package according to one or more embodiments is shown;

[0017] Figure 4 A panel-level glass-based semiconductor package according to one or more other embodiments is shown;

[0018] Figure 5 A flow diagram of a method of manufacturing a panel-level glass-based semiconductor package including a bridge chip according to one or more embodiments is shown;

[0019] Figure 6 A semiconductor package architecture that can incorporate a semiconductor package according to one or more embodiments is shown; and

[0020] Figure 7 A schematic block diagram of an electronic system according to one or more embodiments is shown. DETAILED DESCRIPTION

[0021] The embodiments described herein are examples or example embodiments, and as such, the present disclosure is not limited thereto, but can be embodied in various other forms. Each of the embodiments provided in the following description are not mutually exclusive from one or more features associated with another example or another embodiment provided herein or not provided herein but consistent with the present disclosure. For example, matters described in a particular example or embodiment can be understood to be related to or combined with a different example or embodiment, even if not described in the description of the different example or embodiment, unless otherwise mentioned.

[0022] Furthermore, it is to be understood that the description of principles, aspects, examples and embodiments is intended to encompass structural and functional equivalents. Furthermore, it is to be understood that such equivalents include not only currently known equivalents but also equivalents developed in the future that perform the same function, regardless of a different structure.

[0023] It will be understood that, when an element, component, layer, pattern, structure, region, or the like (hereinafter “element”) is referred to as being “on”, “above”, “on top of”, “under”, “below”, “underneath”, “connected to”, or “coupled to” another element, it can be directly on, above, on top of, under, below, underneath, connected to, or coupled to the other element, or one or more intervening elements can also be present. In contrast, when an element is referred to as being “directly on”, “directly above”, “directly on top of”, “directly under”, “directly below”, “directly underneath”, “directly connected to”, or “directly coupled to” another element, there are no intervening elements present. Like reference numerals refer to like elements throughout the present disclosure.

[0024] For ease of description, spatial terms, such as “over”, “above”, “on”, “up”, “under”, “below”, “down”, “top”, and “bottom”, among others, can be used herein to describe one element’s relationship to another element as illustrated in the Figures. It will be understood that the spatial terms are intended to encompass different orientations of the semiconductor device in use or operation, in addition to the orientation depicted in the Figures. For example, if the semiconductor device in the figures is turned over, an element described as “under” or “below” another element would then be oriented “above” the other element. Thus, the term “under” can encompass both an up and down orientation. The semiconductor device can be oriented in other ways (rotated 90 degrees, or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0025] As used herein, expressions such as “at least one of”, when preceding a list of two or more elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression “at least one of a, b, and c” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, the term “same” when used to compare dimensions of two or more elements can encompass “substantially the same” dimensions.

[0026] It will be understood that, although the terms“first,”“second,”“third,”“fourth,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0027] It will also be understood that even if a certain step or operation is described late in the process, that step or operation can be performed earlier without departing from the teachings of the present disclosure.

[0028] Various implementations are described herein with reference to cross-sectional illustrations that are schematic illustrations of illustrative embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in regions between the buried region and a surface through which implantation occurs. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present disclosure. Furthermore, in the drawings, the dimensions and relative dimensions of layers and regions are exaggerated for clarity.

[0029] For the sake of brevity, general elements of a semiconductor device can or can not be described in detail herein.

[0030] Due to the demand for higher performance computing, more semiconductor chips are being included in a semiconductor package, which results in memory latency and more severe warpage.

[0031] To reduce memory latency and more severe warpage, one or more embodiments provide a semiconductor package including a glass interposer for increasing structural rigidity to reduce warpage and a bridge chip included in the glass interposer to connect semiconductor chips so that the semiconductor chips can be formed closer to each other.

[0032] Figure 1 A plan view of a semiconductor package according to one or more embodiments is shown; Figure 2 A cross-sectional view taken along line A-A’ of the semiconductor package of Figure 1 is shown.

[0033] Reference is made to Figure 1 andFigure 2 The semiconductor package 1 can include first, second, and third semiconductor chips 10, 20, and 30, a bridge chip 40 connecting the semiconductor chips, a first redistribution layer 100 connecting the semiconductor chips to elements outside of the semiconductor package 1, a glass interposer 200 providing connection between the redistribution layers, a photosensitive film 180, and a second redistribution layer 300 connecting the semiconductor chips to the glass interposer 200, and the first, second, and third semiconductor chips 10, 20, and 30 can be, for example, logic chips, memory chips, or the like.

[0034] Here, a direction parallel to a main surface (upper surface or lower surface) of the first redistribution layer 100 can be referred to as a horizontal direction (X direction and / or Y direction), and a direction perpendicular to and orthogonal to the horizontal direction (X direction and / or Y direction) can be referred to as a vertical direction (Z direction).

[0035] The semiconductor package 1 can include a package having a fan-out structure in which the size of a connection layer such as a redistribution layer is expanded beyond the periphery of one or more semiconductor chips in the horizontal direction. The size of the first redistribution layer 100 and the size of the second redistribution layer 300 can be greater than the size of the first, second, and third semiconductor chips 10, 20, and 30 in the horizontal direction. The size of the first redistribution layer 100 and the second redistribution layer 300 can be the same as the size of the entire semiconductor package 1 in the horizontal direction.

[0036] The first redistribution layer 100 can include first redistribution insulating layers 110, first wiring patterns 120, and first vias 130. The first redistribution insulating layers 110 can be stacked in the vertical direction (Z direction). The first redistribution insulating layers 110 can include an insulating material such as a photoimageable dielectric (PID) resin prepared by combining an epoxy resin and a photoinitiator, and can further include a photosensitive polyimide and / or an inorganic filler, without being limited thereto.

[0037] The first wiring patterns 120 and the first vias 130 can be electrically conductive and can be provided in the first redistribution insulating layers 110. The first wiring patterns 120 can be provided to extend in the horizontal direction (X direction and / or Y direction) in the first redistribution insulating layers 110. The first vias 130 can penetrate one or more of the first redistribution insulating layers 110 in the vertical direction (Z direction) to contact and electrically connect some of the first wiring patterns 120.

[0038] According to an embodiment, at least some of the first wiring patterns 120 can be integrally provided with some of the first vias 130. For example, the first wiring patterns 120 and the first vias 130 in contact with the upper surface of the first wiring patterns 120 can be integrally formed as a single structure.

[0039] According to embodiments, the first via 130 can have any suitable shape, including, for example, a tapered shape in which a horizontal width of the first via 130 decreases in a vertical direction (Z direction) away from the first semiconductor chip 10 and the second semiconductor chip 20, which can facilitate manufacturing processes.

[0040] The first wiring pattern 120 and the first via 130 can include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and alloys thereof, but are not limited thereto.

[0041] The semiconductor package 1 can further include an under bump metal (UBM) layer 150. The UBM layer 150 can include a copper layer, a nickel layer, and a copper-nickel-tin intermetallic compound layer between the copper layer and the nickel layer. The UBM layer 150 can be electrically and / or physically connected to at least one of the first wiring pattern 120 and the first via 130, and can electrically connect the first redistribution layer 100 with other components of the semiconductor package 1, such as an external connection terminal 170 that connects the semiconductor package 1 to an element outside of the semiconductor package 1, such as, for example, a printed circuit board (PCB). In addition, the UBM layer 150 can prevent the external connection terminal 170 from being damaged (such as cracking) due to thermal shock between the external connection terminal 170 and the first redistribution layer 100, thereby improving the reliability of the semiconductor package 1. The UBM layer 150 can include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof.

[0042] The semiconductor package 1 can further include an external connection terminal 170 provided on a first surface of the UBM layer 150. The external connection terminal 170 can be configured to electrically and physically connect the first redistribution layer 100 and an external device. According to embodiments, the external connection terminal 170 can include, for example, solder balls, conductive bumps, and flip chip connection structures having a grid array such as a pin grid array, a ball grid array, and a land grid array. The external connection terminal 170 can be electrically connected to the UBM layer 150, and can be electrically connected to an external device, such as a module substrate, a system board, and a printed circuit board.

[0043] A glass interposer 200 can be provided on the second surface of the first redistribution layer 100 to electrically and / or physically connect the first redistribution layer 100 to the second redistribution layer 300 and the semiconductor chip. The glass interposer 200 can include a glass substrate 210 and through-glass vias 220 that penetrate the glass substrate 210 vertically.

[0044] The interposer made of glass can increase the structural rigidity of the overall package to reduce warpage of the semiconductor package. In addition, glass has tunable modulus and coefficient of thermal expansion (CTE) to enable greater form factor packages, improved dimensional stability for feature scaling, lower loss for high speed signal transfer between the semiconductor package 1 and external elements, and higher temperature stability, which can improve the performance of the semiconductor package as a whole.

[0045] The through-glass vias 220 can be provided between the first redistribution layer 100 and the second redistribution layer 300 and provide an electrical connection path between the first redistribution layer 100 and the second redistribution layer 300. The plurality of through-glass vias 220 can include an electrically conductive material including, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof.

[0046] The through-glass vias 220 can have a first surface and a second surface spaced apart from each other in a vertical direction (Z direction). The second surface of the through-glass vias 220 can be coplanar with the second surface of the glass substrate 210, and the first surface of the through-glass vias 220 can be coplanar with the first surface of the glass substrate 210. The through-glass vias 220 can at least partially contact at least one of the first vias 130 and the first wiring pattern 120 exposed on the second surface of the first redistribution insulating layer 110 on the uppermost side. For example, the first surface of the through-glass vias 220 can be bonded and connected to the second surface of at least one of the first vias 130 and the first wiring pattern 120.

[0047] Each of the through-glass vias 220 can have, for example, a cylindrical shape. The diameter of each of the through-glass vias 220 can be constant in a horizontal direction (X or Y direction). In another embodiment, the plurality of through-glass vias 220 can have a tapered shape having a diameter that varies along the vertical direction (Z direction) according to a manufacturing condition in the horizontal direction (X or Y direction).

[0048] The second redistribution layer 300 can be provided on the glass interposer 200. The second redistribution layer 300 can include one or more second redistribution insulating layers 310 and second vias 330. The second redistribution layer 300 can further include a second wiring pattern connected to the second vias 330 to provide an electrical connection between the glass interposer 200 and the semiconductor chip.

[0049] The second redistribution insulating layers 310 can be stacked in the vertical direction (Z direction) to provide insulation between the wiring patterns and the vias that are not connected to each other. The second redistribution insulating layers 310 can include an insulating material such as a photoimageable dielectric (PID) resin prepared by combining an epoxy resin and a photoinitiator, and can further include a photosensitive polyimide and / or an inorganic filler, without being limited thereto.

[0050] The second wiring patterns and the second vias 330 can be electrically conductive, and can be provided in the second redistribution insulating layers 310. The second wiring patterns can be provided to extend in the horizontal direction (X direction and / or Y direction) in the second redistribution insulating layers 310. The second vias 330 can penetrate one or more of the second redistribution insulating layers 310 in the vertical direction (Z direction), thereby contacting and electrically connecting to some of the second wiring patterns.

[0051] According to an embodiment, at least some of the second wiring patterns can be integrally provided with some of the second vias 330. For example, the second wiring patterns and the second vias 330 in contact with the second surface of the second wiring patterns can be integrally formed as a single structure.

[0052] According to an embodiment, the second vias 330 can have a tapered shape in which the horizontal width of the second vias 330 decreases in the vertical direction (Z direction) away from the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30, which can facilitate a manufacturing process.

[0053] The second wiring patterns and the second vias 330 can include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and alloys thereof, without being limited thereto.

[0054] The first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 can be provided on the second surface of the second redistribution layer 300 and electrically connected to a structure outside the semiconductor package 1 through the second redistribution layer 300, the glass interposer 200, and the first redistribution layer 100. The first surface of the first semiconductor chip 10, the first surface of the second semiconductor chip 20, and the first surface of the third semiconductor chip 30 can be surfaces including connection pads that electrically connect the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 to the second redistribution layer 300.

[0055] For example, the first semiconductor chip 10 and the second semiconductor chip 20 can be high bandwidth memory (HBM) chips, and the third semiconductor chip 30 can be a system on chip (SOC) or an application specific integrated circuit (ASIC) chip. However, embodiments are not limited thereto. For example, the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 can be memory chips such as dynamic random access memory (DRAM) chips and NAND chips, or logic chips such as central processing unit (CPU), graphics processing unit (GPU), and field programmable gate array (FPGA) chips, etc.

[0056] The mold layer 410 can be provided on the second surface of the second redistribution layer 300 and around the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 to seal the semiconductor package 1 and protect the semiconductor package 1 from physical and chemical impact. The mold layer 410 is an epoxy molding compound, and can include, for example, an epoxy molding resin including a silicon filler.

[0057] The semiconductor package 1 can further include a bridge chip 40. The bridge chip 40 can be provided to be embedded in the glass substrate 210. A second surface of the bridge chip 40 can be substantially coplanar with a second surface of the glass substrate 210. The bridge chip 40 can be provided as an electrical connection path between the semiconductor chips. For example, the bridge chip 40 can provide an electrical connection path between the first semiconductor chip 10 and the third semiconductor chip 30 disposed on the second redistribution layer 300, and an electrical connection path between the second semiconductor chip 20 and the third semiconductor chip 30 disposed on the second redistribution layer 300. For example, the first semiconductor chip 10 and the third semiconductor chip 30 can be electrically connected to each other through a bridge circuit in the bridge chip 40. As shown, each of the first semiconductor chip 10 and the third semiconductor chip 30 can overlap at least a portion of the bridge chip 40 in a vertical direction (Z direction). Similarly, for example, the second semiconductor chip 20 and the third semiconductor chip 30 can be electrically connected to each other through a bridge circuit in the bridge chip 40, and each of the second semiconductor chip 20 and the third semiconductor chip 30 can overlap at least a portion of the bridge chip 40 in the vertical direction (Z direction). Figure 1

[0058] The bridge chip 40 can include a bridge substrate and a bridge circuit. The bridge chip 40 can be spaced apart from the first redistribution layer 100, but can be electrically and indirectly connected to the first redistribution layer 100 through the through-glass via 220 and the second redistribution layer 300.

[0059] ​The second surface of the bridge chip 40 can include a connection member 43 electrically connecting the bridge chip 40 to the second redistribution layer 300. The bridge chip 40 can include a semiconductor material such as silicon (Si). However, embodiments are not limited thereto. For example, the bridge chip 40 can include a semiconductor material that is a Group IV semiconductor material, a Group III-V semiconductor material, a Group II-VI semiconductor material, and combinations thereof.

[0060] The connection member 43 can be provided between the bridge chip 40 and the second redistribution layer 300. The connection member 43 can contact the second wiring pattern and / or the second via 330, and can electrically connect the second redistribution layer 300 to the bridge chip 40. For example, the connection member 43 can include a conductive pillar. For example, the connection member 43 can have a single cylindrical shape. Accordingly, the connection member 43 can have a constant diameter along the vertical direction (Z direction). In another embodiment, the connection member 43 can have a tapered shape in which the diameter varies along the vertical direction (Z direction), which can facilitate a manufacturing process. For example, the connection member 43 can include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof.

[0061] Figures 3A to 31 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more embodiments. For brevity, descriptions overlapping with the previous drawings will be omitted, and only differences will be mainly described. The glass interposer and the first and second redistribution layers manufactured in the method described below can be or correspond to Figure 1 The glass interposer 200 and the first and second redistribution layers 100 and 300 illustrated in Figure 1 the same reference numerals as illustrated in

[0062] Referring to Figure 3A The first redistribution layer 100 can be formed on the carrier substrate 1000. The first redistribution layer 100 can include a first redistribution insulating layer 110, a first wiring pattern 120, and a first via 130. The first redistribution insulating layer 110 can be stacked in the vertical direction (Z direction). The first redistribution insulating layer 110 can include an insulating material such as a photoimageable dielectric (PID) resin prepared by combining an epoxy resin and a photoinitiator, and can further include a photosensitive polyimide and / or an inorganic filler, without being limited thereto.

[0063] The first wiring pattern 120 and the first via 130 can be electrically conductive, and can be provided in the first redistribution insulating layer 110. The first wiring pattern 120 can be provided to extend in a horizontal direction (X direction and / or Y direction) in the first redistribution insulating layer 110. The first via 130 can penetrate one or more first redistribution insulating layers 110 in a vertical direction (Z direction) to contact and electrically connect with some of the first wiring pattern 120.

[0064] According to an embodiment, at least some of the first wiring pattern 120 can be integrally provided with some of the first via 130. For example, the first wiring pattern 120 and the first via 130 in contact with the second surface of the first wiring pattern 120 can be integrally formed as a single structure.

[0065] According to an embodiment, the first via 130 can have a tapered shape in which a horizontal width of the first via 130 decreases in a vertical direction (Z direction) away from the first semiconductor chip 10 and the second semiconductor chip 20, which can facilitate a manufacturing process.

[0066] The first wiring pattern 120 and the first via 130 can include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and an alloy thereof, but are not limited thereto.

[0067] According to an embodiment, an under bump metal (UBM) layer 150 can also be formed on the lowermost first redistribution insulating layer 110. The UBM layer 150 can be formed to connect to at least one of the first wiring pattern 120 and the first via 130. The UBM layer 150 can include an electrically conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and a combination thereof.

[0068] Referring to Figure 3B A photosensitive film 180 can be laminated on the second surface of the first redistribution layer 100.

[0069] Referring to Figure 3C A glass interposer 200 including a glass substrate 210 and a through-glass via 220 can be formed on the second surface of the photosensitive film 180. The glass interposer 200 can include a cavity 41 on the second surface of the glass substrate. The glass substrate 210 can be prefabricated to include the through-glass via and the cavity 41, which can simplify a manufacturing process of the glass interposer.

[0070] The through-glass via 220 can include an electrically conductive material including, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof.

[0071] The through-glass via 220 can be formed to at least partially contact at least one of the first via 130 and the first wiring pattern 120 exposed on the second surface of the first redistribution insulating layer 110 on the uppermost side. For example, the first surface of the through-glass via 220 can be bonded and connected to the second surface of at least one of the first via 130 and the first wiring pattern 120.

[0072] Referring to Figure 3D The bridge chip 40 can be embedded in the cavity 41 formed on the glass substrate 210. The bridge chip 40 can include a bridge substrate and a bridge circuit. The connection member 43 can be provided on the second surface of the bridge chip 40. For example, the connection member 43 can include an electrically conductive pillar. For example, the connection member 43 can have a single cylindrical shape. Accordingly, the connection member 43 can have a constant diameter along the vertical direction (Z direction). In another embodiment, the connection member 43 can have a tapered shape in which the diameter varies along the vertical direction (Z direction), which can facilitate a manufacturing process. For example, the connection member 43 can include an electrically conductive material such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof.

[0073] The glass substrate 210, the through-glass via 220, and the connection member 43 can be polished such that the second surfaces of the glass substrate 210, the through-glass via 220, and the connection member 43 are substantially coplanar.

[0074] Referring to Figure 3E and Figure 3F A second redistribution layer 300 can be provided on the glass mediator 200. The second redistribution layer 300 can include one or more second redistribution insulating layers 310 and second vias 330. The second redistribution layer 300 can further include a second wiring pattern. The second wiring pattern and / or the second vias 330 can be connected to the through-glass via 220 and the connection member 43. The connection member 43 can electrically connect the second redistribution layer 300 to the bridge chip 40.

[0075] The second redistribution insulating layers 310 can be stacked in the vertical direction (Z direction). The second redistribution insulating layers 310 can include an insulating material such as a photoimageable dielectric (PID) resin prepared by combining an epoxy resin and a photoinitiator, and can further include a photosensitive polyimide and / or an inorganic filler, without being limited thereto.

[0076] The second wiring pattern and the second via 330 can be electrically conductive and can be provided in the second redistribution insulating layer 310. The second wiring pattern can be provided to extend in a horizontal direction (X direction and / or Y direction) in the second redistribution insulating layer 310. The second via 330 can penetrate one or more second redistribution insulating layers 310 in a vertical direction (Z direction), thereby contacting and electrically connecting with some of the second wiring pattern.

[0077] According to an embodiment, at least some of the second wiring pattern can be integrally provided with some of the second via 330. For example, the second wiring pattern and the second via 330 in contact with the second surface of the second wiring pattern can be integrally formed as a single structure.

[0078] According to an embodiment, the second via 330 can have a tapered shape in which a horizontal width of the second via 330 decreases in a vertical direction (Z direction) away from the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30, which can facilitate a manufacturing process.

[0079] The second wiring pattern and the second via 330 can include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and an alloy thereof, but is not limited thereto.

[0080] Reference Figure 3G The first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 can be provided on the second surface of the second redistribution layer 300. The first surface of the first semiconductor chip 10, the first surface of the second semiconductor chip 20, and the first surface of the third semiconductor chip 30 can include connection pads that electrically connect the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 to the second redistribution layer 300.

[0081] The connection member 43 of the bridge chip 40 can be connected to the first semiconductor chip 10 and the third semiconductor chip 30 via the second wiring pattern and / or the second via, and provide an electrical connection path between the first semiconductor chip 10 and the third semiconductor chip 30. The connection member 43 of the other bridge chip 40 can be connected to the second semiconductor chip 20 and the third semiconductor chip 30 via the second wiring pattern and / or the second via, and provide an electrical connection path between the second semiconductor chip 20 and the third semiconductor chip 30. Each of the first semiconductor chip 10 and the third semiconductor chip 30 can be formed to overlap at least a portion of the bridge chip 40 in a vertical direction (Z direction). Each of the second semiconductor chip 20 and the third semiconductor chip 30 can be formed to overlap at least a portion of the bridge chip 40 in a vertical direction (Z direction).

[0082] Referring to Figure 3H The mold layer 410 can be provided on the second surface of the second redistribution layer 300 and surround the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30. The mold layer 410 is an epoxy molding compound, and can include, for example, an epoxy molding resin including a silicon filler.

[0083] Referring to Figure 3I The carrier substrate 1000 can be removed, and an external connection terminal 170 can be formed on the first surface of the UBM layer 150. The external connection terminal 170 can be configured to electrically and physically connect the first redistribution layer 100 and an external device. The external connection terminal 170 can include, for example, solder balls, conductive bumps, and flip-chip connection structures having a grid array such as a pin grid array, a ball grid array, and a land grid array. The external connection terminal 170 can be electrically connected to the UBM layer 150, and can be electrically connected to an external device such as a module substrate, a system board, and a printed circuit board.

[0084] Figure 4 A semiconductor package according to one or more other embodiments is illustrated.

[0085] Referring to Figure 4 The semiconductor package 1 can include a first semiconductor chip 10', a second semiconductor chip 20', a third semiconductor chip 30', a bridge chip 40, a first redistribution layer 100, a glass interposer 200, and a second redistribution layer 300.

[0086] The semiconductor package 1' can include a package having a fan-out structure. The size of the first redistribution layer 100 and the size of the second redistribution layer 300 can be greater than the size of the first semiconductor chip 10', the second semiconductor chip 20', and the third semiconductor chip 30'. The size of the first redistribution layer 100 and the second redistribution layer 300 can be the same as the size of the semiconductor package 1'.

[0087] The first redistribution layer 100 can include first redistribution insulating layers 110, first wiring patterns 120, and first vias 130. The first redistribution insulating layers 110 can be stacked in a vertical direction (Z direction). The first redistribution insulating layers 110 can include an insulating material such as a photoimageable dielectric (PID) resin prepared by combining an epoxy resin and a photoinitiator, and can further include a photosensitive polyimide and / or an inorganic filler, without being limited thereto.

[0088] The first wiring patterns 120 and the first vias 130 can be electrically conductive and can be provided in the first redistribution insulating layers 110. The first wiring patterns 120 can be provided to extend in a horizontal direction (X direction and / or Y direction) in the first redistribution insulating layers 110. The first vias 130 can penetrate one or more of the first redistribution insulating layers 110 in a vertical direction (Z direction) to contact and electrically connect with some of the first wiring patterns 120.

[0089] According to an embodiment, at least some of the first wiring patterns 120 can be integrally provided with some of the first vias 130. For example, the first wiring patterns 120 and the first vias 130 in contact with the second surfaces of the first wiring patterns 120 can be integrally formed as a single structure.

[0090] According to an embodiment, the first vias 130 can have a tapered shape in which a horizontal width of the first vias 130 decreases in a vertical direction (Z direction) away from the first semiconductor chip 10 and the second semiconductor chip 20, which can facilitate a manufacturing process.

[0091] The first wiring patterns 120 and the first vias 130 can include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and alloys thereof, without being limited thereto.

[0092] The semiconductor package 1' can further include an under bump metal (UBM) layer 150. The UBM layer 150 can include a copper layer, a nickel layer, and a copper-nickel-tin intermetallic compound layer between the copper layer and the nickel layer. The UBM layer 150 can be connected to at least one of the first wiring pattern 120 and the first via 130, and can electrically connect the first redistribution layer 100 with other components of the semiconductor package 1', such as external connection terminals 170. In addition, the UBM layer 150 can prevent the external connection terminals 170 from being broken due to a thermal shock between the external connection terminals 170 and the first redistribution layer 100, thereby improving the reliability of the semiconductor package 1'. The UBM layer 150 can include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof.

[0093] The semiconductor package 1' can further include external connection terminals 170 provided on a first surface of the UBM layer 150. The external connection terminals 170 can be configured to electrically and physically connect the first redistribution layer 100 and an external device. According to embodiments, the external connection terminals 170 can include, for example, solder balls, conductive bumps, and flip-chip connection structures having a grid array such as a pin grid array, a ball grid array, and a land grid array. The external connection terminals 170 can be electrically connected to the UBM layer 150, and can be electrically connected to an external device, such as a module substrate, a system board, and a printed circuit board.

[0094] A glass interposer 200 can be provided on a second surface of the first redistribution layer 100. The glass interposer 200 can include a glass substrate 210 and through-glass vias 220 that vertically penetrate the glass substrate 210.

[0095] The through-glass vias 220 can be provided between the first redistribution layer 100 and a second redistribution layer 300, and provide an electrical connection path between the first redistribution layer 100 and the second redistribution layer 300. The plurality of through-glass vias 220 can include a conductive material including, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof.

[0096] The through-glass via 220 can have a first surface and a second surface spaced apart from each other in a vertical direction (Z direction). The second surface of the through-glass via 220 can be coplanar with the second surface of the glass substrate 210, and the first surface of the through-glass via 220 can be coplanar with the first surface of the glass substrate 210. The through-glass via 220 can at least partially contact at least one of the first via 130 and the first wiring pattern 120 exposed on the second surface of the first redistribution insulating layer 110 on the uppermost side. For example, the first surface of the through-glass via 220 can be bonded and connected to the second surface of at least one of the first via 130 and the first wiring pattern 120.

[0097] Each through-glass via 220 can have, for example, a cylindrical shape. The diameter of each through-glass via 220 can be constant in a horizontal direction (X or Y direction). In another embodiment, the plurality of through-glass vias 220 can have a tapered shape having a diameter that varies in a vertical direction (Z direction) along a horizontal direction (X or Y direction), which can facilitate a manufacturing process.

[0098] A second redistribution layer 300 can be provided on the glass interposer 200. The second redistribution layer 300 can include one or more second redistribution insulating layers 310 and second vias 330. The second redistribution layer 300 can further include a second wiring pattern 320.

[0099] The second redistribution insulating layers 310 can be stacked in a vertical direction (Z direction). The second redistribution insulating layers 310 can include an insulating material such as a photoimageable dielectric (PID) resin prepared by combining an epoxy resin and a photoinitiator, and can further include a photosensitive polyimide and / or an inorganic filler, without being limited thereto.

[0100] The second wiring pattern 320 and the second via 330 can be electrically conductive and can be provided in the second redistribution insulating layer 310. The second wiring pattern 320 can be provided to extend in a horizontal direction (X direction and / or Y direction) in the second redistribution insulating layer 310. The second via 330 can penetrate one or more second redistribution insulating layers 310 in a vertical direction (Z direction), thereby contacting and electrically connecting to some of the second wiring pattern 320.

[0101] According to an embodiment, at least some of the second wiring pattern 320 can be integrally provided with some of the second via 330. For example, the second wiring pattern 320 and the second via 330 in contact with the second surface of the second wiring pattern 320 can be integrally formed as a single structure.

[0102] According to an embodiment, the second via 330 can have a tapered shape in which a horizontal width of the second via 330 decreases in a vertical direction (Z direction) away from the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30, which can facilitate a manufacturing process.

[0103] The second wiring pattern 320 and the second via 330 can include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and alloys thereof, but are not limited thereto.

[0104] The first semiconductor chip 10', the second semiconductor chip 20', and the third semiconductor chip 30' can be provided on the second surface of the second redistribution layer 300. The first surface of the first semiconductor chip 10', the first surface of the second semiconductor chip 20', and the first surface of the third semiconductor chip 30' can include connection members 11 and connection pads 13 that electrically connect the first semiconductor chip 10', the second semiconductor chip 20', and the third semiconductor chip 30' to the second redistribution layer 300. For example, the first semiconductor chip 10' can be electrically connected to the second redistribution layer 300 through the connection members 11 and the connection pads 13. The underfill layer 12 can be provided adjacent to and surrounding the connection members 11 and the connection pads 13 between the first semiconductor chip 10' and the second redistribution layer 300. The connection members 11 and the connection pads 13 can be provided between the first surface of the second semiconductor chip 20' and the second redistribution layer 300. The second semiconductor chip 20' can be electrically connected to the second redistribution layer 300 through the connection members 11 and the connection pads 13. The underfill layer 12 can be provided adjacent to and surrounding the connection members 11 between the second semiconductor chip 20' and the second redistribution layer 300. The connection members 11 and the connection pads 13 can be provided between the first surface of the third semiconductor chip 30' and the second redistribution layer 300. The third semiconductor chip 30' can be electrically connected to the second redistribution layer 300 through the connection members 11 and the connection pads 13. The underfill layer 12 can be provided adjacent to and surrounding the connection members 11 between the third semiconductor chip 30' and the second redistribution layer 300. The underfill layer 12 can include an inclined outer surface. The underfill layer 12 can include an epoxy or two or more silicon hybrid materials.

[0105] For example, the first semiconductor chip 10' and the second semiconductor chip 20' can be logic chips and the third semiconductor chip 30' can be a high bandwidth memory (HBM) chip. However, embodiments are not limited thereto.

[0106] The semiconductor package 1' can further include a bridge chip 40. The bridge chip 40 can be provided to be embedded in the glass substrate 210. A second surface of the bridge chip 40 can be substantially coplanar with a second surface of the glass substrate 210. The bridge chip 40 can be provided as an electrical connection path between the semiconductor chips. For example, the bridge chip 40 can provide an electrical connection path between the first semiconductor chip 10' and the second semiconductor chip 20' disposed on the second redistribution layer 300, and an electrical connection path between the second semiconductor chip 20' and the third semiconductor chip 30' disposed on the second redistribution layer 300. For example, the first semiconductor chip 10' and the second semiconductor chip 20' can be electrically connected to each other through a bridge circuit in the bridge chip 40. As shown in FIG. 1, each of the first semiconductor chip 10' and the second semiconductor chip 20' can overlap at least a portion of the bridge chip 40 in a vertical direction (Z direction). Similarly, for example, the second semiconductor chip 20' and the third semiconductor chip 30' can be electrically connected to each other through a bridge circuit in the bridge chip 40, and each of the second semiconductor chip 20' and the third semiconductor chip 30' can overlap at least a portion of the bridge chip 40 in the vertical direction (Z direction). Figure 4

[0107] The bridge chip 40 can include a bridge substrate and a bridge circuit. The bridge chip 40 can be spaced apart from the first redistribution layer 100, but can be electrically and indirectly connected to the first redistribution layer 100 through the through-glass via 220 and the second redistribution layer 300.

[0108] The second surface of the bridge chip 40 can include a connection member 43 electrically connecting the bridge chip 40 to the second redistribution layer 300. The bridge chip 40 can include a semiconductor material such as silicon (Si). However, embodiments are not limited thereto. For example, the bridge chip 40 can include a semiconductor material that is a Group IV semiconductor material, a Group III-V semiconductor material, a Group II-VI semiconductor material, and combinations thereof.

[0109] The connection member 43 can be provided between the bridge chip 40 and the second redistribution layer 300. The connection member 43 can contact the second wiring pattern and / or the second via 330, and can electrically connect the second redistribution layer 300 to the bridge chip 40. For example, the connection member 43 can include a conductive pillar. For example, the connection member 43 can have a single cylindrical shape. Accordingly, the connection member 43 can have a constant diameter along the vertical direction (Z direction). In another embodiment, the connection member 43 can have a tapered shape in which the diameter varies along the vertical direction (Z direction), which can facilitate a manufacturing process. For example, the connection member 43 can include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof.

[0110] ​A mold layer 410 can be provided on a second surface of the second redistribution layer 300 and around the first semiconductor chip 10', the second semiconductor chip 20', the third semiconductor chip 30', and the underfill layer 12 to seal the semiconductor package 1' and protect the semiconductor package 1' from physical and chemical impact. The mold layer 410 is an epoxy molding compound, and can include an epoxy molding resin including a silicon filler, for example.

[0111] Figure 5 A flowchart of manufacturing a semiconductor package according to one or more embodiments is illustrated.

[0112] In operation S110, a first redistribution layer can be formed on a carrier substrate. A first redistribution insulating layer is provided on the carrier substrate, and a first wiring pattern is formed on the first redistribution insulating layer. By patterning the first redistribution insulating layer with a photoresist, a first via is formed to penetrate the first redistribution insulating layer, and can connect the first wiring pattern provided at different vertical levels. An additional layer of the first redistribution insulating layer having the first wiring pattern and the first via can be formed on a first surface of the first redistribution insulating layer. An under bump metal (UBM) layer can be formed at the lowermost first redistribution insulating layer, and an external connection terminal can be formed on the UBM layer to connect the semiconductor package to an external device.

[0113] In operation S120, a glass interposer including a glass substrate and a through glass via penetrating the glass substrate is formed. The glass substrate can be prefabricated to include the through glass via and a cavity on a second surface of the glass substrate. However, embodiments are not limited thereto, and the glass substrate can be laser processed to form the cavity on the second surface of the glass substrate, and a portion of the glass substrate can be wet-etched or dry-etched to form a through glass tunnel penetrating the glass substrate. The through glass tunnel can be filled with a metal material to form the through glass via. The metal material can include a conductive material including, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof, but embodiments are not limited thereto. A bridge chip can be formed in the cavity.

[0114] In operation S130, a second redistribution layer is formed on a second surface of the glass interposer. A second redistribution insulating layer is provided on the second surface of the glass substrate, and a second wiring pattern is formed on the second redistribution insulating layer by patterning the second redistribution insulating layer with a photoresist. A second via is formed to penetrate the second redistribution insulating layer, and can connect the second wiring pattern provided at different vertical levels. An additional layer of the second redistribution insulating layer having the second wiring pattern and the second via can be formed on the second surface of the second redistribution insulating layer.

[0115] At operation S140, a semiconductor chip can be provided. For example, the semiconductor chip can be provided on a second surface of a second redistribution layer. A connection member can be formed to connect the semiconductor chip and a second wiring pattern included in the second redistribution layer. A bridge chip can connect adjacent semiconductor chips through the second redistribution layer. An underfill layer can fill a space between the connection members. The semiconductor chip can be a logic chip, an HBM chip, a SOC chip, or the like. However, embodiments are not limited thereto.

[0116] At operation S150, an external terminal can be formed to contact the UBM layer to electrically and physically connect the first redistribution layer 100 and an external device.

[0117] Figure 6 A semiconductor package architecture that can incorporate a semiconductor package according to one or more embodiments is illustrated.

[0118] Reference Figure 6 A semiconductor package architecture 2000 according to an example embodiment can include a processor 2200 and a semiconductor device 2300 mounted on a substrate 2100. The processor 2200 and / or the semiconductor device 2300 can include one or more of the semiconductor packages described in the above embodiments.

[0119] Figure 7 A schematic block diagram of an electronic system according to one or more embodiments is illustrated.

[0120] Reference Figure 7 An electronic system 3000 according to an embodiment can include a microprocessor 3100, a memory 3200, and a user interface 3300 that perform data communication using a bus 3400. The microprocessor 3100 can include a central processing unit (CPU) or an application processor (AP). The electronic system 3000 can further include a random access memory (RAM) 3500 that directly communicates with the microprocessor 3100. The microprocessor 3100 and / or the RAM 3500 can be implemented in a single module or package. The user interface 3300 can be used to input data to the electronic system 3000, or output data from the electronic system 3000. For example, the user interface 3300 can include a keyboard, a touchpad, a touchscreen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a micro light emitting device (LED), an organic light emitting diode (OLED) device, an active matrix light emitting diode (AMOLED) device, a printer, a lighting device, or various other input / output devices, but is not limited thereto. The memory 3200 can store an operation code of the microprocessor 3100, data processed by the microprocessor 3100, or data received from an external device. The memory 3200 can include a memory controller, a hard disk, or a solid state drive (SSD).

[0121] At least the microprocessor 3100, the memory 3200, and / or the RAM 3500 in the electronic system 3000 can include a semiconductor package as described in the example embodiments above.

[0122] It is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments.

[0123] While implementations have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims.

[0124] Cross Reference to Related Applications

[0125] This application is based on, and claims the benefit of, U.S. Provisional Application No. 63 / 632,284, filed April 10, 2024, in the United States Patent and Trademark Office, the disclosure of which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package comprising: a first redistribution layer; a second redistribution layer; a glass substrate between the first redistribution layer and the second redistribution layer, the glass substrate comprising a through-glass via configured to connect the first redistribution layer and the second redistribution layer; a first semiconductor chip and a second semiconductor chip on a second surface of the second redistribution layer; as well as A bridge chip is included in the glass substrate and is configured to connect the first semiconductor chip and the second semiconductor chip.

2. The semiconductor package according to claim 1, wherein The first redistribution layer includes a first redistribution insulating layer, a first wiring pattern, and a first via connected to the first wiring pattern, and The second redistribution layer includes a second redistribution insulation layer, a second wiring pattern, and a second via connected to the second wiring pattern.

3. The semiconductor package according to claim 2, wherein The bridge chip is provided to face the second redistribution layer and is configured to be electrically connected to the second redistribution layer.

4. The semiconductor package according to claim 2 , further comprising a first connection member on the second surface of the bridge chip, in, The first connection member is connected to at least one of the second wiring pattern and the second via, and is configured to connect the bridge chip to the first semiconductor chip and the second semiconductor chip.

5. The semiconductor package according to claim 4, wherein The bridge chip electrically connects the first semiconductor chip and the second semiconductor chip through the second redistribution layer. 6 . The semiconductor package according to claim 1 , further comprising a mold layer on the second surface of the second redistribution layer and surrounding the first semiconductor chip and the second semiconductor chip, the mold layer being configured to seal the first semiconductor chip and the second semiconductor chip. The semiconductor package according to claim 1 , wherein the bridge chip is spaced apart from the through-glass via.

8. The semiconductor package according to claim 2, wherein The first redistribution layer further includes an under bump metallurgy layer, and The semiconductor package further includes an external terminal on the underbump metallurgy layer, wherein the external terminal is configured to connect the semiconductor package to a structure outside the semiconductor package.

9. The semiconductor package according to claim 1, wherein The bridge chip overlaps a portion of the first semiconductor chip and a portion of the second semiconductor chip in a vertical direction. 10 . The semiconductor package according to claim 1 , further comprising second connection members and connection pads between the first and second semiconductor chips and the second redistribution layer.

11. A method for manufacturing a semiconductor package, the method comprising: providing a first redistribution layer on a carrier substrate, the first redistribution layer comprising a first redistribution insulating layer, a first wiring pattern, and a first via connected to the first wiring pattern; providing a glass substrate including a through-glass via on the first redistribution layer, the glass substrate being configured to be electrically connected to the first redistribution layer; Provide bridge chip; providing a second redistribution layer configured to be electrically connected to the glass substrate on the glass substrate, the second redistribution layer including a second redistribution insulating layer, a second wiring pattern, and a second via connected to the second wiring pattern; as well as providing a first semiconductor chip and a second semiconductor chip on the second redistribution layer, The bridge chip is configured to electrically connect the first semiconductor chip and the second semiconductor chip. 12 . The method according to claim 11 , further comprising providing a first connection member on the second surface of the bridge chip to be connected to at least one of the second wiring pattern and the second via.

13. The method according to claim 11, wherein The bridge chip is provided to overlap a portion of the first semiconductor chip and a portion of the second semiconductor chip in a vertical direction.

14. A semiconductor package comprising: a first redistribution layer comprising a first redistribution insulating layer, a first wiring pattern, and a first via connected to the first wiring pattern; a second redistribution layer comprising a second redistribution insulating layer, a second wiring pattern, and a second via connected to the second wiring pattern; a glass substrate between the first redistribution layer and the second redistribution layer, the glass substrate comprising a through-glass via configured to connect the first redistribution layer and the second redistribution layer; a first semiconductor chip and a second semiconductor chip on a second surface of the second redistribution layer; a bridge chip included in the glass substrate and electrically connecting the first semiconductor chip and the second semiconductor chip, the bridge chip being configured to electrically connect the first semiconductor chip and the second semiconductor chip; as well as External terminals are on the first redistribution layer, the external terminals being configured to connect the semiconductor package to a structure external to the semiconductor package.

15. The semiconductor package according to claim 14, wherein The bridge chip is provided to face the second redistribution layer and is configured to be electrically connected to the second redistribution layer.

16. The semiconductor package according to claim 14, further comprising a first connection member on the second surface of the bridge chip, in, The first connection member is connected to at least one of the second wiring pattern and the second via, and is configured to connect the bridge chip to the first semiconductor chip and the second semiconductor chip. 17 . The semiconductor package according to claim 14 , further comprising a mold layer on the second surface of the second redistribution layer and surrounding the first semiconductor chip and the second semiconductor chip, the mold layer being configured to seal the first semiconductor chip and the second semiconductor chip.

18. The semiconductor package according to claim 14, wherein The bridge chip is spaced apart from the through-glass via.

19. The semiconductor package according to claim 14, wherein The first redistribution layer further includes an under bump metallurgy layer, and Wherein, the external terminal is on the under bump metal layer.

20. The semiconductor package according to claim 14, wherein The bridge chip overlaps a portion of the first semiconductor chip and a portion of the second semiconductor chip in a vertical direction.

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