A trigger signal acquisition circuit, an ADC sampling device and a sampling method

Abstract

The application discloses a kind of trigger signal acquisition circuit, ADC sampling device and sampling method, trigger signal acquisition circuit includes comparison module, buffer module, data acquisition module and clock module;Clock module outputs at least two first clock signals, the number of first clock signal is greater than two, the phase difference of two first clock signals of adjacent phase in multiple first clock signals is equal;Comparison module is accessed first trigger signal and trigger threshold, and comparison module exports second trigger signal according to first trigger signal and trigger threshold;Buffer module is connected comparison module, and buffer module is copied according to second trigger signal and exports at least two third trigger signals, wherein, the number of third trigger signal is equal to the number of first clock signal;Data acquisition module is collected according to first clock signal to third trigger signal and converts and exports fourth trigger signal.The trigger signal acquisition circuit provided by the application can realize the high-precision extraction of trigger signal.

Description

Technical Field

[0001] This invention relates to the field of signal acquisition technology, and in particular to a trigger signal acquisition circuit, an ADC sampling device, and a sampling method. Background Technology

[0002] ADC (Analog-to-Digital Converter) sampling primarily converts continuously changing analog signals into discrete digital signals. In practical applications, the trigger signal precisely determines when the ADC sampling device begins sampling. In high-precision trigger acquisition, the accuracy of each captured trigger signal must be greater than the ADC's sampling accuracy.

[0003] As the sampling rate of high-speed ADCs increases, the accuracy of capturing trigger signals also increases. Currently, the clock of FPGA (Field Programmable Gate Array) is generally used to capture trigger signals directly, but the accuracy of capturing trigger signals is low and cannot meet the needs of high-precision trigger acquisition. Summary of the Invention

[0004] This invention provides a trigger signal acquisition circuit, an ADC sampling device, and a sampling method to solve the problem that the acquisition accuracy of trigger signals in the prior art is low and cannot meet the requirements of high-precision trigger acquisition.

[0005] According to one aspect of the present invention, a trigger signal acquisition circuit is provided, including a comparison module, a buffer module, a data acquisition module, and a clock module;

[0006] The clock module is used to output at least two first clock signals. When the number of first clock signals is greater than two, the phase difference between two adjacent first clock signals in the multiple first clock signals is equal.

[0007] The comparison module receives a first trigger signal and a trigger threshold, and the comparison module is used to output a second trigger signal based on the first trigger signal and the trigger threshold.

[0008] The buffer module is connected to the comparison module. The buffer module is used to copy and output at least two third trigger signals according to the second trigger signal, wherein the number of third trigger signals is equal to the number of the first clock signals.

[0009] The data acquisition module is connected to the buffer module and the clock module. The data acquisition module is used to acquire the third trigger signal according to the first clock signal and convert it to output a fourth trigger signal.

[0010] Optionally, the trigger signal acquisition circuit further includes a control chip, the data acquisition module and the clock module are disposed inside the control chip, the control chip is connected to the buffer module, and the control chip is used to perform delay control on multiple third trigger signals so that the delay of multiple third trigger signals is the same.

[0011] Optionally, the data acquisition module includes at least two serial-to-parallel conversion units, which are connected to the buffer module and the clock module. The serial-to-parallel conversion units are used to acquire and convert the third trigger signal according to the first clock signal.

[0012] Optionally, the multiple first clock signals output by the clock module have the same frequency.

[0013] According to another aspect of the present invention, an ADC sampling device is provided, including the trigger signal acquisition circuit, an analog-to-digital conversion module, and a data reconstruction module. The analog-to-digital conversion module is used to convert an input analog signal into a digital signal. The data reconstruction module is connected to the trigger signal acquisition circuit and the analog-to-digital conversion module. The data reconstruction module is used to reconstruct the digital signal according to a fourth trigger signal output by the trigger signal acquisition circuit.

[0014] Optionally, the ADC sampling device further includes a front-end processing module, which is connected to the analog-to-digital conversion module and is used to filter the analog signal before inputting it into the analog-to-digital conversion module.

[0015] According to another aspect of the present invention, an ADC sampling method is provided, performed by the ADC sampling device, the method comprising:

[0016] The comparison module outputs a second trigger signal based on the first trigger signal and the trigger threshold.

[0017] The buffer module replicates and outputs at least two third trigger signals according to the second trigger signal;

[0018] The clock module outputs at least two first clock signals;

[0019] The data acquisition module acquires the third trigger signal based on the first clock signal and converts it to output a fourth trigger signal;

[0020] The analog-to-digital converter module converts the received analog signal into a digital signal;

[0021] The data reconstruction module reconstructs the digital signal according to the fourth trigger signal.

[0022] Optionally, the trigger signal acquisition circuit includes a control chip, and before the clock module outputs at least two first clock signals, it further includes: the clock module outputs at least two second clock signals, wherein the multiple second clock signals have the same frequency and the same phase; the control chip calibrates the delay of the multiple third trigger signals to be the same.

[0023] Optionally, the data acquisition module acquires and converts the third trigger signal according to the first clock signal and outputs the fourth trigger signal, including: performing serial-to-parallel conversion on the data of multiple third trigger signals.

[0024] Optionally, the serial-to-parallel conversion of the data from the multiple third trigger signals includes: concatenating the data from the multiple third trigger signals; and extracting the concatenated data to obtain the fourth trigger signal.

[0025] The technical solution of this invention provides a trigger signal acquisition circuit, including a comparison module, a buffer module, a data acquisition module, and a clock module. The clock module outputs at least two first clock signals. The comparison module outputs a second trigger signal based on the first trigger signal and a trigger threshold. The buffer module copies and outputs multiple third trigger signals based on the second trigger signal, wherein the number of third trigger signals is equal to the number of first clock signals. The data acquisition module acquires and converts the third trigger signals based on the first clock signals and outputs a fourth trigger signal. When the number of first clock signals is greater than two, the phase difference between two adjacent first clock signals is equal, meaning the clock module can output multiple clock signals with equally spaced phases. The data acquisition module samples each clock signal, increasing the sampling point density compared to sampling a single clock signal. By sequentially acquiring multiple third trigger signals with equally spaced phases based on multiple first clock signals, the accuracy of trigger signal acquisition is improved, solving the problem of low acquisition accuracy in the prior art, which cannot meet the requirements of high-precision trigger acquisition.

[0026] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a trigger signal acquisition circuit provided in an embodiment of the present invention;

[0029] Figure 2 This is a circuit diagram of the data acquisition module provided in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the structure of an ADC sampling device provided in an embodiment of the present invention;

[0031] Figure 4 This is a flowchart of an ADC sampling method provided in an embodiment of the present invention;

[0032] Figure 5 This is a flowchart of another ADC sampling method provided in an embodiment of the present invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] This invention provides a trigger signal acquisition circuit. Figure 1 This is a schematic diagram of a trigger signal acquisition circuit provided in an embodiment of the present invention, as shown below. Figure 1As shown, the trigger signal acquisition circuit 100 includes a comparison module 110, a buffer module 120, a data acquisition module 130, and a clock module 140. The clock module 140 outputs at least two first clock signals S, wherein when the number of first clock signals S is greater than two, the phase difference between adjacent phases of the multiple first clock signals S is equal. The comparison module 110 receives a first trigger signal a1 and a trigger threshold c, and outputs a second trigger signal a2 based on the first trigger signal a1 and the trigger threshold c. The buffer module 120 is connected to the comparison module 110, and is used to copy and output multiple third trigger signals a3 based on the second trigger signal a2, wherein the number of third trigger signals a3 is equal to the number of first clock signals S. The data acquisition module 130 is connected to the buffer module 120 and the clock module 140, and is used to acquire and convert the third trigger signals a3 based on the first clock signal S, and output a fourth trigger signal a4.

[0036] In this embodiment, the trigger signal acquisition circuit 100 is the circuit that acquires the trigger signal, which has a significant impact on the ADC sampling effect. Working in conjunction with ADC sampling, it can accurately acquire analog signals that meet the requirements. The comparison module 110 is a module that quickly compares the input signal with a reference value. For example, in the field of high-precision triggering, the comparison module 110 uses a high-speed comparator, with a processing speed typically reaching the nanosecond level, suitable for high-speed signal processing applications. The buffer module 120 is a module that buffers and copies the input signal. For example, the buffer module 120 includes a buffer that copies the second trigger signal to obtain multiple third trigger signals. The data acquisition module 130 is a module that acquires the third trigger signals based on the first clock signal output by the clock module 140. The number of first clock signals is the same as the number of third trigger signals. The clock module 140 is a module that provides a time reference, ensuring that the various parts of the system can execute in a predetermined time sequence. When the number of multiple first clock signals output by the clock module 140 is greater than two, the phase difference between two adjacent first clock signals is equal.

[0037] In this embodiment, the comparison module 110 outputs a second trigger signal after comparing the input first trigger signal with a trigger threshold. For example, the first trigger signal is a square wave signal. When the first trigger signal is less than the trigger threshold, the comparison module 110 outputs a low-level signal; when the first trigger signal is higher than the trigger threshold, the comparison module 110 outputs a high-level signal. The buffer module 120 copies the second trigger signal and outputs multiple third trigger signals. The data acquisition module 130 acquires the multiple third trigger signals sequentially according to equal-interval phases based on multiple first clock signals, and performs data conversion processing on the acquired data. For example, the acquired third trigger signals are converted from serial to parallel to obtain a fourth trigger signal.

[0038] The technical solution of this invention provides a trigger signal acquisition circuit, including a comparison module, a buffer module, a data acquisition module, and a clock module. The clock module outputs at least two first clock signals. The comparison module outputs a second trigger signal based on the first trigger signal and a trigger threshold. The buffer module copies and outputs multiple third trigger signals based on the second trigger signal, wherein the number of third trigger signals is equal to the number of first clock signals. The data acquisition module acquires and converts the third trigger signals based on the first clock signals and outputs a fourth trigger signal. When the number of first clock signals is greater than two, the phase difference between two adjacent first clock signals is equal, meaning the clock module can output multiple clock signals with equally spaced phases. The data acquisition module samples each clock signal, increasing the sampling point density compared to sampling a single clock signal. By sequentially acquiring multiple third trigger signals with equally spaced phases based on multiple first clock signals, the accuracy of trigger signal acquisition is improved, solving the problem of low acquisition accuracy in the prior art, which cannot meet the requirements of high-precision trigger acquisition.

[0039] Figure 2 This is a circuit diagram of the data acquisition module provided in an embodiment of the present invention, such as... Figure 2 As shown, the data acquisition module 130 includes at least two serial-to-parallel conversion units. Each serial-to-parallel conversion unit is connected to a buffer module and a clock module. The serial-to-parallel conversion unit is used to acquire a third trigger signal based on a first clock signal and then perform serial-to-parallel conversion. The first clock signal and the third trigger signal correspond one-to-one with the serial-to-parallel conversion unit, and one serial-to-parallel conversion unit acquires one third trigger signal based on one first clock signal.

[0040] In this embodiment of the invention, the serial-to-parallel conversion unit is a unit that converts serial data into parallel data. It enables high-speed acquisition of trigger signals and conversion into low-frequency, multi-bit-width signals. For example, the serial-to-parallel conversion unit internally includes circuit structures such as shift registers. Serial data sequentially enters the shift register, and according to a first clock signal, all bits of data stored in the shift register are simultaneously output at a specific time, completing the conversion to parallel data. In many devices requiring high-speed data processing, parallel data transmission is often used to improve data transmission efficiency when transferring data between the processor and components such as memory. The serial-to-parallel conversion unit converts serial data into a parallel data format, facilitating subsequent rapid data computation, storage, and other operations.

[0041] Continue to refer to Figure 2The trigger signal acquisition circuit also includes a control chip 210, a data acquisition module 130 and a clock module 140, which are located inside the control chip 210. The control chip 210 is connected to the buffer module 120. The control chip 210 is used to perform delay control on multiple third trigger signals so that the delay of multiple third trigger signals is the same.

[0042] In this embodiment of the invention, the control chip 210 plays a crucial role in ADC sampling. The control chip 210 has functions such as ADC sampling timing control, data processing and buffering, and implementation of complex logic and algorithms. For example, the control chip 210 performs delay control on multiple third trigger signals. The control chip 210 uses an FPGA and has a built-in delay function to control the delay of multiple third trigger signals, ensuring that multiple third trigger signals are transmitted to the control chip 210 simultaneously. For example, the clock module 140 first outputs multiple clock signals with the same frequency and phase. The control chip 210 detects the multiple third trigger signals. If the delays of the multiple third trigger signals arriving at the control chip are different, the control chip 210 adjusts the internal delay to make the delays of the multiple third trigger signals the same. This eliminates the delay inconsistencies caused by different external signal input circuits and circuit board wiring, allowing multiple third trigger signals to be transmitted to the input terminal of the data acquisition module 130 simultaneously.

[0043] Based on the above embodiments, the clock module 140 outputs multiple first clock signals with the same frequency. When the number of first clock signals is greater than two, the phase difference between two adjacent first clock signals in the multiple first clock signals is equal. For example, if the number of first clock signals is six, the counting unit divides the phase of the first clock signals into six equal parts. The phases of the first clock signal S1 to the sixth first clock signal S6 are 0°~60°, 60°~120°, 120°~180°, 180°~240°, 240°~300°, and 300°~360°, respectively. The phase difference between two adjacent signals is 60°, and the frequency of each first clock signal is equal. By dividing the clock phase equally, there can be multiple sampling moments with different phases within one clock cycle. This allows for the capture of subtle changes in the third trigger signal within a shorter time interval. Compared to relying solely on single-phase sampling, this method can collect richer and more accurate data, improving sampling accuracy.

[0044] In this embodiment of the invention, the trigger signal acquisition circuit 100 compares the first trigger signal and the trigger threshold through the comparison module 110 and outputs the second trigger signal. The buffer module 120 copies the second trigger signal and outputs multiple third trigger signals. For example, the number of third trigger signals is N, and the number of first clock signals is also N. The data acquisition module 130 acquires N third trigger signals according to the N first clock signals, with equal phase intervals (360°*(1 / N)), and converts the acquired N third trigger signals to obtain the fourth trigger signal. Since the clock module 140 outputs the first clock signal with equal phase division, that is, multiple sampling times with different phases are set within one clock cycle, high-precision extraction of the trigger signal is achieved, providing a basis for the reordering of the digital signal after the analog signal is converted by the ADC.

[0045] This invention also provides an ADC sampling device. Figure 3 This is a schematic diagram of the structure of an ADC sampling device provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the ADC sampling device in this embodiment includes the trigger signal acquisition circuit 100 in the above embodiment, as well as the analog-to-digital conversion module 310 and the data reconstruction module 320. The analog-to-digital conversion module 310 is used to convert the input analog signal A into a digital signal D. The data reconstruction module 320 is connected to the trigger signal acquisition circuit 100 and the analog-to-digital conversion module 310. The data reconstruction module 320 is used to reconstruct the digital signal according to the fourth trigger signal output by the trigger signal acquisition circuit 100.

[0046] In this embodiment of the invention, the analog-to-digital converter (ADC) module 310 converts analog signals into digital signals. In the field of high-precision trigger acquisition, the ADC module 310 includes a high-speed ADC, which has the advantages of fast conversion rate and high sampling frequency, and can process high-speed signals, making it suitable for application scenarios with extremely high requirements for signal digitization speed. The data reconstruction module 320 is a module that rearranges and integrates the sampled data output by the ADC module 310 according to specific rules based on the trigger signal output by the trigger signal acquisition circuit 100. The data reconstruction module 320 is located inside the control chip 210. By reconstructing the digital signals, the data reconstruction module 320 makes the data organization form more in line with the requirements of subsequent processing (such as digital signal processing, storage, transmission, etc.).

[0047] Continue to refer to Figure 3The ADC sampling device 100 also includes a front-end processing module 330, which is connected to the analog-to-digital conversion module 310. The front-end processing module 330 filters the analog signal A before inputting it to the analog-to-digital conversion module 310. The front-end processing module 330 is a module that preprocesses the input analog signal. Its main purpose is to shape the original analog signal into a form more suitable for accurate and efficient sampling and conversion by the ADC. For example, the preprocessing of the analog signal by the front-end processing module 330 includes signal amplification and signal filtering.

[0048] This invention also provides an ADC sampling method, executed by the ADC sampling device in any of the above embodiments. Figure 4 This is a flowchart of an ADC sampling method provided in an embodiment of the present invention, such as... Figure 4 As shown, the ADC sampling methods include:

[0049] S10. The comparison module outputs a second trigger signal based on the first trigger signal and the trigger threshold.

[0050] S20, the buffer module copies and outputs at least two third trigger signals according to the second trigger signal.

[0051] S30, the clock module outputs at least two first clock signals.

[0052] S40. The data acquisition module acquires the third trigger signal based on the first clock signal and converts it to output the fourth trigger signal.

[0053] The S50 analog-to-digital converter module converts the input analog signal into a digital signal.

[0054] S60, The data reconstruction module reconstructs the digital signal according to the fourth trigger signal.

[0055] In this embodiment of the invention, a comparison module compares the first trigger signal and the trigger threshold, then outputs a second trigger signal. This process is fast and highly accurate, ensuring the reliability and efficiency of data processing. A buffer module copies the second trigger signal and outputs multiple third trigger signals. The number of first clock signals output by the clock module corresponds to the number of third trigger signals. The data acquisition module, based on the multiple first clock signals, sequentially acquires the multiple third trigger signals at equal phase intervals, and then processes the acquired data to obtain a fourth trigger signal. By setting multiple sampling times with different phases within one clock cycle, high-precision extraction of the trigger signal is achieved. The data reconstruction module, based on the fourth trigger signal, rearranges and integrates the digital signal according to specific rules, making the data organization more suitable for subsequent processing requirements.

[0056] Referring to the above embodiments, the trigger signal acquisition circuit further includes a control chip. Figure 5 This is a flowchart of another ADC sampling method provided in an embodiment of the present invention, such as... Figure 5 As shown, before the clock module outputs at least two first clock signals, it also includes:

[0057] S11. The clock module outputs at least two second clock signals, wherein the frequency and phase of the multiple second clock signals are the same.

[0058] S12, the delay of the control chip calibration multiple third trigger signals is the same.

[0059] In this embodiment of the invention, multiple second clock signals are in phase and frequency. The clock module first outputs multiple clock signals in phase and frequency. The control chip detects multiple third trigger signals. If the delays of the multiple third trigger signals arriving at the control chip are different, the control chip has a built-in delay function. The control chip adjusts the internal delay to ensure that the delays of the third trigger signals are the same, that is, multiple third trigger signals arrive at the data acquisition module at the same time. The purpose of using the delay function is to eliminate the inconsistency in delay caused by different external signal input circuits and circuit board wiring.

[0060] Based on the above embodiments, the data acquisition module acquires and converts the third trigger signal according to the first clock signal and outputs the fourth trigger signal, including: performing serial-to-parallel conversion on the data of multiple third trigger signals. Specifically, performing serial-to-parallel conversion on the data of multiple third trigger signals includes: concatenating the multiple parallel data streams; and extracting the concatenated data to obtain the fourth trigger signal. For example, in devices requiring high-speed data processing, when transmitting data between the processor and components such as memory, parallel data transmission is often used to improve data transmission efficiency. This involves converting serial data into a parallel data format to facilitate subsequent rapid data processing, storage, and other operations.

[0061] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0062] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A trigger signal acquisition circuit, characterized in that, It includes a comparison module, a buffer module, a data acquisition module, and a clock module; The clock module is used to output at least two first clock signals. When the number of first clock signals is greater than two, the phase difference between two adjacent first clock signals in the multiple first clock signals is equal, and the frequency of the multiple first clock signals output by the clock module is the same. The comparison module receives a first trigger signal and a trigger threshold, and the comparison module is used to output a second trigger signal based on the first trigger signal and the trigger threshold. The buffer module is connected to the comparison module. The buffer module is used to copy and output at least two third trigger signals according to the second trigger signal. The number of third trigger signals is equal to the number of first clock signals, and the delay of the multiple third trigger signals is the same. The data acquisition module is connected to the buffer module and the clock module. The data acquisition module is used to acquire the third trigger signal according to the first clock signal and convert it to output a fourth trigger signal.

2. The trigger signal acquisition circuit according to claim 1, characterized in that, It also includes a control chip, the data acquisition module and the clock module are disposed inside the control chip, the control chip is connected to the buffer module, and the control chip is used to perform delay control on multiple third trigger signals so that the delay of multiple third trigger signals is the same.

3. The trigger signal acquisition circuit according to claim 1, characterized in that, The data acquisition module includes at least two serial-to-parallel conversion units, which are connected to the buffer module and the clock module. The serial-to-parallel conversion units are used to acquire the third trigger signal according to the first clock signal and perform serial-to-parallel conversion.

4. An ADC sampling device, characterized in that, The system includes the trigger signal acquisition circuit, analog-to-digital conversion module, and data reconstruction module as described in any one of claims 1-3. The analog-to-digital conversion module is used to convert the input analog signal into a digital signal. The data reconstruction module is connected to the trigger signal acquisition circuit and the analog-to-digital conversion module. The data reconstruction module is used to reconstruct the digital signal according to the fourth trigger signal output by the trigger signal acquisition circuit.

5. The ADC sampling device according to claim 4, characterized in that, It also includes a front-end processing module, which is connected to the analog-to-digital conversion module. The front-end processing module is used to filter the analog signal and then input it to the analog-to-digital conversion module.

6. An ADC sampling method, characterized in that, Performed by the ADC sampling device of claim 4, the method includes: The comparison module outputs a second trigger signal based on the first trigger signal and the trigger threshold. The buffer module replicates and outputs at least two third trigger signals according to the second trigger signal; The clock module outputs at least two first clock signals; The data acquisition module acquires the third trigger signal based on the first clock signal and converts it to output a fourth trigger signal; The analog-to-digital converter module converts the received analog signal into a digital signal; The data reconstruction module reconstructs the digital signal according to the fourth trigger signal.

7. The ADC sampling method according to claim 6, characterized in that, The trigger signal acquisition circuit includes a control chip, and before the clock module outputs at least two first clock signals, it also includes: The clock module outputs at least two second clock signals, wherein the multiple second clock signals have the same frequency and the same phase. The control chip calibrates the delay of multiple third trigger signals to be the same.

8. The ADC sampling method according to claim 6, characterized in that, The data acquisition module acquires the third trigger signal based on the first clock signal and converts and outputs the fourth trigger signal, including: The data of the multiple third trigger signals are converted from serial to parallel.

9. The ADC sampling method according to claim 8, characterized in that, The serial-to-parallel conversion of the data from the multiple third trigger signals includes: Data splicing is performed on the multiple third trigger signals; The spliced ​​data is extracted to obtain the fourth trigger signal.

Images