Clamp voltage generation circuit

Abstract

This invention discloses a clamping voltage generation circuit, comprising an operational amplifier, PMOS transistors M20 and M21, NMOS transistors M22 and M23, and a constant current source. The source terminals of PMOS transistors M20 and M21 are connected to the operating voltage. The gate terminal of PMOS transistor M20 is connected to the output terminal of the operational amplifier. The drain terminal of PMOS transistor M20 is connected to a first output node. The gate terminal of NMOS transistor M22, and the gate and drain terminals of NMOS transistor M23 are all shorted to the first output node. The source terminal of NMOS transistor M23 is grounded. The gate and drain terminals of PMOS transistor M21 are connected to the drain terminal of NMOS transistor M22. The source terminal of NMOS transistor M22 is connected to the negative input terminal of the operational amplifier. The positive input terminal of the operational amplifier is used to connect to a reference voltage. The constant current source is connected between the source terminal of NMOS transistor M22 and ground. This clamping voltage generation circuit can output a stable clamping voltage, and the clamping voltage builds up quickly.

Description

Technical Field

[0001] This invention relates to semiconductor circuit technology, and in particular to a clamping voltage generating circuit. Background Technology

[0002] Sensitive amplifiers are primarily used in non-volatile memories to distinguish between "0" and "1" data by comparing the current of the memory cell being read with a reference current.

[0003] Read operations on non-volatile memory are achieved by measuring the current of the selected memory cell. With the word line voltage known, a preset voltage is applied to the bit line of the selected memory cell, and the current of the memory cell is read. The read current is then compared with a reference current to determine the phase state of the memory cell. The sensitive amplifier is a crucial module in the readout circuit, and read speed is a key performance indicator for the circuit.

[0004] There are two types of bit line voltage clamping methods used in Nor flash (flash memory) sensitive amplifiers: voltage clamping and current clamping. Voltage clamping determines the bit line voltage by controlling the gate terminal of the NMOS switch, while current clamping determines the bit line voltage by using current to pass through the NMOS switch.

[0005] A common type of sensitive amplifier is... Figure 1 As shown, one input terminal is used to connect to the clamping voltage Vout, one input terminal is used to connect to the read current Icell of the memory cell, and one input terminal is used to connect to the reference current Iref.

[0006] The clamping voltage generation circuit is used to generate the clamping voltage Vout, which is output to the clamping voltage input terminal of the sensitive amplifier.

[0007] A common clamping voltage generation circuit is as follows: Figure 2 As shown, due to the influence of the process, there is a deviation in the resistance, and the current deviation of the main branch of the operational amplifier is relatively large. After the traditional Miller compensation is used and the zero-point compensation pole is inserted, the stability deviation of the wide voltage working loop is relatively large after the process deviation is superimposed. At the same time, it also affects the establishment speed of the clamping voltage to a certain extent.

[0008] Existing tail current generation circuits for clamping voltage generation circuits, such as Figure 3 As shown, its self-biased current mirror is mainly achieved by making the NMOS transistor M10 to the saturation region and by modifying the size of the NMOS transistor M10 to generate a suitable bias current. This bias current is then mirrored to the operational amplifier control terminal of the clamping voltage generation circuit as the input tail current of the operational amplifier. Typically, the NMOS transistor M10 needs a relatively large length (3-5 times or more of the minimum process length) to reduce the influence of the channel length modulation effect on the NMOS transistor M10 branch circuit.

[0009] The main deviation in the bias current generated by the wide-voltage operation tail current generation circuit is caused by the difference in the drain-source voltage VDS of NMOS transistor M10. During wide-voltage operation, the difference in the drain-source voltage VDS of NMOS transistor M10 is relatively large, which leads to a large deviation in the tail current at the control terminal of the operational amplifier in the clamping voltage generation circuit. When the enable signal EN=1, the circuit is inactive. When the enable (EN) switches, the first bias voltage node bgbiasn is established downward from the operating voltage VDD. The tail current of the operational amplifier A1 in the clamping voltage generation circuit is established from small to large. The slow establishment speed affects the overall establishment time of the operational amplifier in the clamping voltage generation circuit. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide a clamping voltage generating circuit that can output a stable clamping voltage.

[0011] To solve the above-mentioned technical problems, the clamping voltage generation circuit provided by the present invention includes an operational amplifier A1, a PMOS transistor M20, a PMOS transistor M21, an NMOS transistor M22, an NMOS transistor M23, and a constant current source;

[0012] The source terminals of PMOS transistors M20 and M21 are connected to the operating voltage VDD.

[0013] The gate terminal of the PMOS transistor M20 is connected to the output terminal of the operational amplifier A1;

[0014] The drain terminal of the PMOS transistor M20 is connected to the first output node Vout1;

[0015] The gate terminal of NMOS transistor M22, the gate terminal and the drain terminal of NMOS transistor M23 are all shorted to the first output node Vout1;

[0016] The source terminal of the NMOS transistor M23 is grounded;

[0017] The gate and drain of the PMOS transistor M21 are connected to the drain of the NMOS transistor M22.

[0018] The source terminal of the NMOS transistor M22 is connected to the negative input terminal of the operational amplifier A1;

[0019] The positive input terminal of the operational amplifier A1 is used to connect to the reference voltage Vref;

[0020] The constant current source is connected between the source terminal of the NMOS transistor M22 and ground.

[0021] Preferably, the clamping voltage generation circuit serves as the bit line voltage clamping circuit of the sensitive amplifier, used to generate a clamping voltage output to the clamping voltage input terminal of the sensitive amplifier.

[0022] Preferably, the sensitive amplifier is a sensitive amplifier applied to Nor flash;

[0023] The sensitive amplifier has one input terminal for connecting to the clamping voltage, one input terminal for connecting to the read current Icell of the storage cell, and one input terminal for connecting to the reference current Iref.

[0024] Preferably, the clamping voltage generation circuit further includes an NMOS transistor M25;

[0025] The source terminal of the NMOS transistor M23 is connected to the drain terminal of the NMOS transistor M25;

[0026] The NMOS transistor M25 has its gate terminal connected to the first output node Vout1 and its source terminal grounded.

[0027] Preferably, the clamping voltage generating circuit further includes a resistor R1, a capacitor C1, and a capacitor C2;

[0028] The resistor R1 and capacitor C1 are connected in series between the output terminal of the operational amplifier A1 and ground.

[0029] The capacitor C2 is connected between the first output node Vout1 and the negative input terminal of the operational amplifier A1.

[0030] Preferably, the clamping voltage generation circuit further includes an NMOS transistor M24;

[0031] The NMOS transistor M24 has its drain terminal shorted to the first output node Vout1, its source terminal grounded, and its gate terminal connected to the negative input terminal of the operational amplifier A1.

[0032] Preferably, the aspect ratio of the NMOS transistor M24 is less than 5.

[0033] Preferably, the threshold voltage Vth of the NMOS transistor M22 decreases with increasing temperature, and the constant current source current Ir decreases with increasing temperature.

[0034] Preferably, the clamping voltage generating circuit further includes PMOS transistors M30, M31, M41, M32, M33, M36, M42, and M43.

[0035] The source terminals of PMOS transistors M30, M31, and M41 are connected to the operating voltage VDD.

[0036] The gate of the PMOS transistor M31 is connected to the gate of the PMOS transistor M21, and its drain is connected to the drain of the NMOS transistor M32.

[0037] The gate of the NMOS transistor M32 is connected to the first output node Vout1, and its source is connected to the drain of the NMOS transistor M36.

[0038] The gate terminal of the PMOS transistor M30 is connected to the output terminal of the operational amplifier A1, and its drain terminal is connected to the second output node Vout2.

[0039] The gate and drain terminals of NMOS transistor M33 and the gate terminal of NMOS transistor M42 are all shorted to the second output node Vout2;

[0040] The gate and drain of the PMOS transistor M41 are connected to the drain of the NMOS transistor M42.

[0041] The source terminal of the NMOS transistor M42 is connected to the drain terminal of the NMOS transistor M43;

[0042] The gate terminal of the NMOS transistor M43 is connected to the gate terminal of the NMOS transistor M36 and the drain terminal of the NMOS transistor M32.

[0043] The source terminals of NMOS transistors M36, M33, and M43 are grounded.

[0044] Preferably, the clamping voltage generation circuit further includes an NMOS transistor M35;

[0045] The drain terminal of the NMOS transistor M35 is connected to the source terminal of the NMOS transistor M33, the gate terminal is connected to the second output node Vout2, and the source terminal is grounded.

[0046] Preferably, the clamping voltage generation circuit further includes an NMOS transistor M34;

[0047] The NMOS transistor M34 has its source terminal grounded, its drain terminal shorted to the second output node Vout2, and its gate terminal connected to the source terminal of the NMOS transistor M42.

[0048] Preferably, the control terminal of the operational amplifier A1 is externally connected to a tail current generating circuit;

[0049] The tail current generating circuit includes PMOS transistors M12, M13, M14, M15, NMOS transistors M10, M11, M16, M17, and M18.

[0050] The source terminals of PMOS transistors M13 and M14 are connected to the operating voltage VDD.

[0051] The gate terminals of PMOS transistor M13, M14, M12, M11, and M16 are all connected to the first bias voltage node bgbiasn.

[0052] The drain terminal of the PMOS transistor M13 is connected to the source terminal of the PMOS transistor M12;

[0053] The source terminal of the NMOS transistor M11 is connected to the drain terminal of the NMOS transistor M10;

[0054] The drain terminal of the PMOS transistor M14 is connected to the source terminal of the PMOS transistor M15.

[0055] The source terminal of the PMOS transistor M15, the drain and gate terminals of the NMOS transistor M17, and the drain terminal of the NMOS transistor M18 are all connected to the second bias voltage node nbias.

[0056] The source terminals of NMOS transistors M10, M16, M17, and M18 are grounded;

[0057] The gate terminals of NMOS transistor M16, PMOS transistor M12, PMOS transistor M15, and NMOS transistor M18 are all used to connect to the enable signal EN.

[0058] The gate terminals of NMOS transistors M10 and M11 are used to connect to the reference voltage Vref;

[0059] The threshold voltage VthM11 of the NMOS transistor M11 is 0 to 0.1V.

[0060] Preferably, the tail current generating circuit further includes a coupling capacitor C3;

[0061] The coupling capacitor C3 is connected between the first bias voltage node bgbiasn and the second bias voltage node nbias.

[0062] The clamping voltage generation circuit of the present invention uses the first output node Vout1 as the clamping voltage output terminal and includes three operational amplifiers. Operational amplifier A1 is the first stage, which is a common-source single-stage amplifier (high gain) with a constant current source Ir as the load. PMOS transistor M20 and NMOS transistor M23 constitute the second stage, which is a common-source single-stage amplifier (high output impedance) with a diode as the load. MOS resistors can be added on this basis to increase the output impedance and obtain greater gain. NMOS transistor M22 and PMOS transistor M21 constitute the third stage, which is a common-drain (source follower) single-stage amplifier (low output impedance, gain = 1). From the perspective of a single-stage amplifier, the third-stage source follower amplifier uses the negative input signal fdbk of operational amplifier A1 as its input and the first output node Vout1 of the second-stage amplifier as its output. Simultaneously, the voltage of the first output node Vout1 is used as a bias voltage to supply the diode loads (NMOS transistors M23 and M25) in the second-stage amplifier. The second-stage amplifier can also be considered a single-stage amplifier with a constant current source as its load. The NMOS transistor M22 of the third-stage amplifier uses the voltage of the first output node Vout1 as its bias voltage. Vout1 = Vref + VGSM22. Since Vref is a stable reference voltage unaffected by power supply and temperature, Vout1 is only affected by the gate-source voltage VGSM22 of NMOS transistor M22. Vout1 is relatively stable, thus enabling the output of a stable clamping voltage. Furthermore, in this clamping voltage generation circuit, the main load capacitance and parasitic capacitance of the operational amplifier are very small, resulting in rapid clamping voltage build-up. Attached Figure Description

[0063] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 This is a circuit diagram of a common sensitive amplifier;

[0065] Figure 2 This is a circuit diagram of an existing clamping voltage generation circuit;

[0066] Figure 3 This is a circuit diagram of an existing tail current generation circuit;

[0067] Figure 4 This is a circuit diagram of an embodiment of the clamping voltage generation circuit of the present invention;

[0068] Figure 5 This is a three-stage amplifier circuit diagram of an embodiment of the clamping voltage generation circuit of the present invention;

[0069] Figure 6 This is an external tail current generating circuit of one embodiment of the clamping voltage generating circuit of the present invention. Detailed Implementation

[0070] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0071] Example 1

[0072] like Figure 4 As shown, the clamping voltage generation circuit includes an operational amplifier A1, a PMOS transistor M20, a PMOS transistor M21, an NMOS transistor M22, an NMOS transistor M23, and a constant current source;

[0073] The source terminals of PMOS transistors M20 and M21 are connected to the operating voltage VDD.

[0074] The gate terminal of the PMOS transistor M20 is connected to the output terminal of the operational amplifier A1;

[0075] The drain terminal of the PMOS transistor M20 is connected to the first output node Vout1;

[0076] The gate terminal of NMOS transistor M22, the gate terminal and the drain terminal of NMOS transistor M23 are all shorted to the first output node Vout1;

[0077] The source terminal of the NMOS transistor M23 is grounded;

[0078] The gate and drain of the PMOS transistor M21 are connected to the drain of the NMOS transistor M22.

[0079] The source terminal of the NMOS transistor M22 is connected to the negative input terminal of the operational amplifier A1;

[0080] The positive input terminal of the operational amplifier A1 is used to connect to the reference voltage Vref;

[0081] The constant current source is connected between the source terminal of the NMOS transistor M22 and ground.

[0082] Preferably, the clamping voltage generating circuit serves as the bit line voltage clamping circuit of the sensitive amplifier, used to generate a clamping voltage output to the clamping voltage input terminal of the sensitive amplifier.

[0083] Preferably, the sensitive amplifier is a sensitive amplifier applied to Nor flash;

[0084] The sensitive amplifier has one input terminal for connecting to the clamping voltage, one input terminal for connecting to the read current Icell of the memory cell, and one input terminal for connecting to the reference current Iref. A common type of sensitive amplifier is... Figure 1 As shown.

[0085] The clamping voltage generation circuit in Embodiment 1, using the first output node Vout1 as the clamping voltage output terminal, includes a three-stage operational amplifier, such as... Figure 5 As shown, operational amplifier A1, as the first stage, is a common-source single-stage amplifier (high gain) with a constant current source Ir as the load. PMOS transistor M20 and NMOS transistor M23 constitute the second stage, which is a common-source single-stage amplifier (high output impedance) with diodes as loads. A MOS resistor can be added to this stage to increase the output impedance and obtain greater gain. NMOS transistor M22 and PMOS transistor M21 constitute the third stage, which is a common-drain (source follower) single-stage amplifier (low output impedance, gain = 1). Analyzing from the perspective of a single-stage amplifier, the third-stage source follower amplifier uses the negative input signal fdbk of operational amplifier A1 as input and the first output node Vout1 of the second-stage amplifier as output. Simultaneously, the voltage of the first output node Vout1 is used as a bias voltage to supply the diode loads (NMOS transistors M23 and M25) in the second-stage amplifier. The second-stage amplifier can also be considered as a single-stage amplifier with a constant current source as the load. The NMOS transistor M22 of the third-stage amplifier uses the voltage of the first output node Vout1 as its bias voltage. Vout1 = Vref + VGSM22. Since Vref is a stable reference voltage unaffected by power supply and temperature, Vout1 is only affected by the gate-source voltage VGSM22 of the NMOS transistor M22. Vout1 is relatively stable, thus enabling the output of a stable clamping voltage. Furthermore, this clamping voltage generation circuit has very small operational amplifier load capacitance and parasitic capacitance, resulting in fast clamping voltage build-up.

[0086] The clamping voltage generation circuit of this invention can output a stable clamping voltage that is unaffected by changes in power supply voltage and temperature. When applied to the sensitive amplifier of NOR flash, it can solve the problem that the slow clamping voltage build-up of the voltage clamping sensitive amplifier structure affects the read speed under wide voltage operation.

[0087] Example 2

[0088] Based on Embodiment 1, the clamping voltage generation circuit further includes an NMOS transistor M25;

[0089] The source terminal of the NMOS transistor M23 is connected to the drain terminal of the NMOS transistor M25;

[0090] The NMOS transistor M25 has its gate terminal connected to the first output node Vout1 and its source terminal grounded.

[0091] The clamping voltage generation circuit of Embodiment 2, wherein the source terminal of the NMOS transistor M23 is grounded through the NMOS transistor M25.

[0092] Embodiment 3

[0093] Based on Embodiment 1, the clamping voltage generation circuit further includes a resistor R1, a capacitor C1 and a capacitor C2;

[0094] The resistor R1 and the capacitor C1 are connected in series between the output terminal of the operational amplifier A1 and the ground;

[0095] The capacitor C2 is connected between the first output node Vout1 and the negative input terminal of the operational amplifier A1.

[0096] The clamping voltage generation circuit of Embodiment 3, two zero compensation poles are inserted in the three-stage amplification, namely the resistor R1, the capacitor C1 (the first stage to the ground) and the capacitor C2 (the third stage cross-connected), which respectively compensate the main pole and the high-frequency pole to ensure that the phase margin PM>70°; the resistor R1 and the capacitor C1 of the first zero are connected on the path from the output of the operational amplifier to the ground, the current deviation of the main branch of the operational amplifier is small, and the loop stability deviation is small; in addition to ensuring sufficient loop stability, from the perspective of transient establishment analysis, it can also reduce the jitter of the output of the first-stage amplification caused by the influence of the tail current establishment speed on the operational amplifier A1, further improving the speed of the overall three-stage amplification from establishment to stability and accelerating the establishment of the clamping voltage.

[0097] Embodiment 4

[0098] Based on Embodiment 1, the clamping voltage generation circuit further includes an NMOS transistor M24;

[0099] For the NMOS transistor M24, its drain terminal is short-circuited to the first output node Vout1, its source terminal is grounded, and its gate terminal is connected to the negative input terminal of the operational amplifier A1.

[0100] Preferably, the aspect ratio of the NMOS transistor M24 is less than 5. During the establishment of the operational amplifier, the feedback voltage fdbk at the negative input terminal of the operational amplifier A1 will have a certain degree of overshoot. Affected by source follower, Vout1 = fdbk + VthM22. When fdbk > VthM24, the NMOS transistor M24 conducts. VthM24 is the threshold voltage of the NMOS transistor M24. At this time, the NMOS transistor M24 will slowly discharge the overshoot charge of the first output node Vout1 until fdbk < VthM24. Here, the NMOS transistor M24 needs to be sized in an inverted ratio (width < 5 times the length, that is, the aspect ratio is less than 5) to avoid always maintaining VthM24 < fdbk and avoid making the NMOS transistor M24 always conduct, which has an adverse effect on the stability of the operational amplifier.

[0101] In the clamping voltage generation circuit of Embodiment 4, when the negative input voltage fdbk of the operational amplifier A1 overshoots, the NMOS transistor M24 conducts to discharge the charge of the first output node Vout1, accelerating the stable output clamping voltage. Under extreme conditions (such as high temperature and low power supply voltage), the clamping voltage settling time can be reduced to within 40ns, and the static power consumption problem of traditional clamping diodes can be avoided.

[0102] Example 5

[0103] Based on the clamping voltage generation circuit of Embodiment 4, the threshold voltage Vth of NMOS transistor M22 decreases with increasing temperature, and the constant current source current Ir decreases with increasing temperature.

[0104] The threshold voltage Vth of NMOS transistor M22 is affected by temperature; the higher the temperature, the lower Vth. The constant current source current Ir is a current that varies with temperature; the higher the temperature, the lower the current. This trend can be used to compensate for the deviation of the gate-source voltage VGSM22 of NMOS transistor M22 caused by the temperature effect on the threshold voltage Vth of NMOS transistor M22. According to the saturation current formula of MOS transistor, the gate-source voltage VGSM22 of NMOS transistor M22 is ensured to be unaffected by temperature.

[0105] The clamping voltage generation circuit in Example 5 employs a temperature-current collaborative compensation mechanism. It utilizes a temperature-sensitive constant current source current Ir (temperature ↑ → Ir ↓) to offset the temperature drift of the threshold voltage VthM22 of the NMOS transistor M22 (temperature ↑ → Vth ↓), thereby keeping the gate-source voltage VGSM22 of the NMOS transistor M22 constant. The temperature stability of Vout1 = Vref + VGSM22 is < ±1%.

[0106] Example 6

[0107] Based on Embodiment 1, the clamping voltage generation circuit further includes PMOS transistor M30, PMOS transistor M31, PMOS transistor M41, NMOS transistor M32, NMOS transistor M33, NMOS transistor M36, NMOS transistor M42, and NMOS transistor M43.

[0108] The source terminals of PMOS transistors M30, M31, and M41 are connected to the operating voltage VDD.

[0109] The gate of the PMOS transistor M31 is connected to the gate of the PMOS transistor M21, and its drain is connected to the drain of the NMOS transistor M32.

[0110] The gate of the NMOS transistor M32 is connected to the first output node Vout1, and its source is connected to the drain of the NMOS transistor M36.

[0111] The gate terminal of the PMOS transistor M30 is connected to the output terminal of the operational amplifier A1, and its drain terminal is connected to the second output node Vout2.

[0112] The gate and drain terminals of NMOS transistor M33 and the gate terminal of NMOS transistor M42 are all shorted to the second output node Vout2;

[0113] The gate and drain of the PMOS transistor M41 are connected to the drain of the NMOS transistor M42.

[0114] The source terminal of the NMOS transistor M42 is connected to the drain terminal of the NMOS transistor M43;

[0115] The gate terminal of the NMOS transistor M43 is connected to the gate terminal of the NMOS transistor M36 and the drain terminal of the NMOS transistor M32.

[0116] The source terminals of NMOS transistors M36, M33, and M43 are grounded.

[0117] Preferably, the clamping voltage generation circuit further includes an NMOS transistor M35;

[0118] The drain terminal of the NMOS transistor M35 is connected to the source terminal of the NMOS transistor M33, the gate terminal is connected to the second output node Vout2, and the source terminal is grounded.

[0119] Preferably, the clamping voltage generation circuit further includes an NMOS transistor M34;

[0120] The NMOS transistor M34 has its source terminal grounded, its drain terminal shorted to the second output node Vout2, and its gate terminal connected to the source terminal of the NMOS transistor M42.

[0121] The clamping voltage generation circuit in Example 6 uses a current mirror to transmit the clamping voltage to the load via an additional independent mirror branch (PMOS transistor M30, NMOS transistor M33, etc.). The second output node Vout2 serves as the clamping voltage output terminal of the clamping voltage generation circuit. There is no direct connection between the main operational amplifier and the second output node Vout2, isolating the load's influence on the main operational amplifier. Changes in load capacitance (e.g., 1pF-10pF) do not affect the main loop stability, avoiding the phase margin degradation introduced by the load in traditional solutions. The PMOS transistors M30, M33, M34, and M42 in the mirror branch are independent paths and can be considered as two additional unipolar amplifiers, but they are not in a closed-loop application, therefore loop stability does not need to be considered. The stable voltages of the second output node Vout2 and the first output node Vout1 differ only in their settling time; after reaching the quiescent operating point, the voltages of the second output node Vout2 and the first output node Vout1 are identical. By modifying the width-to-length ratio of PMOS transistors M20 and M30 (the two transistors have the same length, only their widths are modified proportionally, such as 1:2, 1:3, 1:4, etc.), the current mirror ratio can be adjusted to adapt to different load sizes, ensuring more flexible application of the clamping voltage generation circuit.

[0122] The clamping voltage generation circuit in Example 6 features a mirrored branch isolation design, allowing for independent optimization and flexible adaptation to various loads (different numbers of sensitive amplifiers SA), thus expanding application scenarios. Various loads can refer to different numbers of sensitive amplifiers SA. The more sensitive amplifiers SA there are, the more transistors are connected to the second output node Vout2, resulting in slower setup. Therefore, it is necessary to adjust the current mirror ratio between PMOS transistors M20 and M30 to increase the current, thereby improving setup speed and reducing setup time.

[0123] Example 7

[0124] Based on the clamping voltage generation circuit of Embodiment 1, the control terminal of the operational amplifier A1 is externally connected to a tail current generation circuit.

[0125] like Figure 6 As shown, the control terminal of the operational amplifier A1 is externally connected to a tail current generating circuit;

[0126] The tail current generating circuit includes PMOS transistors M12, M13, M14, M15, NMOS transistors M10, M11, M16, M17, and M18.

[0127] The source terminals of PMOS transistors M13 and M14 are connected to the operating voltage VDD.

[0128] The gate terminals of PMOS transistor M13, M14, M12, M11, and M16 are all connected to the first bias voltage node bgbiasn.

[0129] The drain terminal of the PMOS transistor M13 is connected to the source terminal of the PMOS transistor M12;

[0130] The source terminal of the NMOS transistor M11 is connected to the drain terminal of the NMOS transistor M10;

[0131] The drain terminal of the PMOS transistor M14 is connected to the source terminal of the PMOS transistor M15.

[0132] The source terminal of the PMOS transistor M15, the drain and gate terminals of the NMOS transistor M17, and the drain terminal of the NMOS transistor M18 are all connected to the second bias voltage node nbias.

[0133] The source terminals of NMOS transistors M10, M16, M17, and M18 are grounded;

[0134] The gate terminals of NMOS transistor M16, PMOS transistor M12, PMOS transistor M15, and NMOS transistor M18 are all used to connect to the enable signal EN.

[0135] The gate terminals of NMOS transistors M10 and M11 are used to connect to the reference voltage Vref;

[0136] The threshold voltage VthM11 of the NMOS transistor M11 is extremely small and close to 0 (0V~0.1V).

[0137] In the clamping voltage generation circuit of Embodiment 7, an NMOS transistor M11 (ZVT transistor) is added to the tail current generation circuit. When operating with a wide voltage range (e.g., 1.5V-3.8V), the NMOS transistor M11 acts as a switch controlled by the reference voltage Vref. The maximum voltage that can be transmitted is Vref - VthM11 (this is not a dynamic adjustment of the drain-source voltage VDSM10 of the NMOS transistor M10; the drain-source voltage VDSM10 of the NMOS transistor M10 is always equal to Vref - VthM11). The constant drain-source voltage VDSM10 of the NMOS transistor M10 can greatly reduce the difference in the drain-source voltage VDSM10 of the NMOS transistor M10 under wide voltage operation, eliminate the output current deviation of the tail current generation circuit caused by the channel length modulation effect (CLM), save area, and eliminate the need for complex feedback control.

[0138] Example 8

[0139] Based on the clamping voltage generating circuit of Embodiment 7, the tail current generating circuit further includes a coupling capacitor C3;

[0140] The coupling capacitor C3 is connected between the first bias voltage node bgbiasn and the second bias voltage node nbias.

[0141] In the clamping voltage generation circuit of Embodiment 8, the newly added coupling capacitor C3 is connected between the first bias voltage node bgbiasn and the second bias voltage node nbias of the tail current generation circuit. The voltages of both the first bias voltage node bgbiasn and the second bias voltage node nbias need to be established from 0 to stable. When the enable signal EN = 0, the tail current generation circuit does not work. When the NMOS transistor M11 is turned on as a switch, the instantaneous current in both branches is large, and the voltage of the second bias voltage node nbias will rise rapidly. The change in the voltage of the second bias voltage node nbias is quickly reflected to the first bias voltage node bgbiasn through the coupling capacitor C3, so that the voltage of the first bias voltage node bgbiasn rises rapidly, which accelerates the establishment of the voltage of the first bias voltage node bgbiasn. When the enable (EN) switches, the coupling capacitor C3 can suppress the tail current overshoot of the op-amp caused by the first bias voltage node bgbiasn voltage establishing from 0, and accelerate the establishment of the tail current of the op-amp to stable.

[0142] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A clamp voltage generation circuit characterized by comprising: It includes an operational amplifier (A1), PMOS transistors M20 and M21, NMOS transistors M22 and M23, and a constant current source; The source terminals of PMOS transistors M20 and M21 are connected to the operating voltage (VDD). The gate terminal of the PMOS transistor M20 is connected to the output terminal of the operational amplifier (A1); The drain of the PMOS transistor M20 is connected to the first output node (Vout1). The gate terminal of NMOS transistor M22, the gate terminal and the drain terminal of NMOS transistor M23 are all shorted to the first output node (Vout1). The source terminal of the NMOS transistor M23 is grounded; The gate and drain of the PMOS transistor M21 are connected to the drain of the NMOS transistor M22; The source terminal of the NMOS transistor M22 is connected to the negative input terminal of the operational amplifier (A1); The positive input terminal of the operational amplifier (A1) is used to connect to the reference voltage (Vref). The constant current source is connected between the source terminal of the NMOS transistor M22 and ground.

2. The clamping voltage generating circuit according to claim 1, characterized in that, The clamping voltage generation circuit serves as the bit line voltage clamping circuit for the sensitive amplifier, used to generate a clamping voltage output to the clamping voltage input terminal of the sensitive amplifier.

3. The clamping voltage generating circuit according to claim 2, characterized in that, The sensitive amplifier is a sensitive amplifier applied to Nor flash; The sensitive amplifier has one input terminal for connecting to the clamping voltage, one input terminal for connecting to the read current (Icell) of the memory cell, and one input terminal for connecting to the reference current (Iref).

4. The clamping voltage generating circuit according to claim 1, characterized in that, The clamping voltage generation circuit also includes an NMOS transistor M25; the NMOS transistor M25 is connected between the NMOS transistor M23 and ground; The source terminal of the NMOS transistor M23 is connected to the drain terminal of the NMOS transistor M25; The NMOS transistor M25 has its gate terminal connected to the first output node (Vout1) and its source terminal grounded.

5. The clamping voltage generating circuit according to claim 1, characterized in that, The clamping voltage generating circuit also includes a resistor R1, a capacitor C1, and a capacitor C2; The resistor R1 and capacitor C1 are connected in series between the output terminal of the operational amplifier (A1) and ground; The capacitor C2 is connected between the first output node (Vout1) and the negative input terminal of the operational amplifier (A1).

6. The clamping voltage generating circuit according to claim 1, characterized in that, The clamping voltage generation circuit also includes an NMOS transistor M24; The NMOS transistor M24 has its drain terminal shorted to the first output node (Vout1), its source terminal grounded, and its gate terminal connected to the negative input terminal of the operational amplifier (A1).

7. The clamping voltage generating circuit according to claim 6, characterized in that, The aspect ratio of the NMOS transistor M24 is less than 5.

8. The clamping voltage generating circuit according to claim 1, characterized in that, The threshold voltage Vth of the NMOS transistor M22 decreases with increasing temperature, and the constant current source current Ir also decreases with increasing temperature.

9. The clamping voltage generating circuit according to claim 1, characterized in that, The clamping voltage generation circuit also includes PMOS transistors M30, M31, M41, M32, M33, M36, M42, and M43. The source terminals of PMOS transistors M30, M31, and M41 are connected to the operating voltage (VDD). The gate of the PMOS transistor M31 is connected to the gate of the PMOS transistor M21, and its drain is connected to the drain of the NMOS transistor M32. The gate of the NMOS transistor M32 is connected to the first output node (Vout1), and its source is connected to the drain of the NMOS transistor M36. The PMOS transistor M30 has its gate terminal connected to the output terminal of the operational amplifier (A1) and its drain terminal connected to the second output node (Vout2). The gate and drain terminals of NMOS transistor M33 and the gate terminal of NMOS transistor M42 are all shorted to the second output node (Vout2). The gate and drain of the PMOS transistor M41 are connected to the drain of the NMOS transistor M42. The source terminal of the NMOS transistor M42 is connected to the drain terminal of the NMOS transistor M43; The gate terminal of the NMOS transistor M43 is connected to the gate terminal of the NMOS transistor M36 and the drain terminal of the NMOS transistor M32. The source terminals of NMOS transistors M36, M33, and M43 are grounded.

10. The clamping voltage generating circuit according to claim 9, characterized in that, The clamping voltage generation circuit also includes an NMOS transistor M35; the NMOS transistor M35 is connected between the NMOS transistor M33 and ground; The drain terminal of the NMOS transistor M35 is connected to the source terminal of the NMOS transistor M33, the gate terminal is connected to the second output node (Vout2), and the source terminal is grounded.

11. The clamping voltage generating circuit according to claim 9, characterized in that, The clamping voltage generation circuit also includes an NMOS transistor M34; The NMOS transistor M34 has its source terminal grounded, its drain terminal shorted to the second output node (Vout2), and its gate terminal connected to the source terminal of the NMOS transistor M42.

12. The clamping voltage generating circuit according to claim 1, characterized in that, The control terminal of the operational amplifier (A1) is connected to an external tail current generating circuit; The tail current generating circuit includes PMOS transistors M12, M13, M14, M15, NMOS transistors M10, M11, M16, M17, and M18. The source terminals of PMOS transistors M13 and M14 are connected to the operating voltage (VDD). The gate terminals of PMOS transistor M13, M14, M12, M11, and M16 are all connected to the first bias voltage node (bgbiasn). The drain terminal of the PMOS transistor M13 is connected to the source terminal of the PMOS transistor M12; The source terminal of the NMOS transistor M11 is connected to the drain terminal of the NMOS transistor M10; The drain terminal of the PMOS transistor M14 is connected to the source terminal of the PMOS transistor M15. The source terminal of the PMOS transistor M15, the drain and gate terminals of the NMOS transistor M17, and the drain terminal of the NMOS transistor M18 are all connected to the second bias voltage node (nbias). The source terminals of NMOS transistors M10, M16, M17, and M18 are grounded; The gate terminals of NMOS transistor M16, PMOS transistor M12, PMOS transistor M15 and NMOS transistor M18 are all used to connect to the enable signal (EN). The gate terminals of NMOS transistors M10 and M11 are used to connect to the reference voltage (Vref). The threshold voltage VthM11 of the NMOS transistor M11 is 0V to 0.1V.

13. The clamping voltage generating circuit according to claim 12, characterized in that, The tail current generating circuit also includes a coupling capacitor C3; The coupling capacitor C3 is connected between the first bias voltage node (bgbiasn) and the second bias voltage node (nbias).

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