Processing apparatus and method for a work queue element

Abstract

The application provides a processing device and method of work queue elements, the device comprising: a queue element obtaining unit, a multi-channel DMA engine unit, a queue element processing unit and a scheduling unit; the queue element obtaining unit is used for selecting a target queue pair, reading a target queue element in the selected target queue pair through the multi-channel DMA engine unit, and storing data of the target queue element to a shared storage space; the multi-channel DMA engine unit is used for reading target queue elements in multiple target queue pairs through multiple channels concurrently under the triggering of the queue element obtaining unit; the queue element processing unit is used for processing the target queue elements, and dynamically allocating storage space for storing control information of the target queue elements to the in-order cache space for the target queue elements; and the scheduling unit is used for scheduling and outputting data of the target queue elements according to the control information of the target queue elements stored in the in-order cache space.

Description

Technical Field

[0001] This application belongs to the field of storage technology, and specifically relates to a device and method for processing work queue elements. Background Technology

[0002] In RDMA (Remote Direct Memory Access) networks, the processing efficiency of Work Queue Elements (WQEs) is a key bottleneck affecting data transmission performance. Related technologies generally employ a single-channel blocking processing architecture for WQE transmission modules, which suffers from drawbacks such as serial processing blocking, low resource utilization, and insufficient bandwidth utilization. Summary of the Invention

[0003] The purpose of this application is to provide a device and method for processing work queue elements, which aims to solve the problems of low throughput and memory access latency in RDMA network cards for WQE (work queue elements) in related technologies.

[0004] According to a first aspect of this application, a work queue element processing apparatus is provided, comprising: a queue element acquisition unit, a multi-channel DMA engine unit, a queue element processing unit, and a scheduling unit;

[0005] The queue element acquisition unit is used to select a target queue pair, read the target queue element in the selected target queue pair through the multi-channel DMA engine unit, and store the target queue element data to the shared storage space.

[0006] The multi-channel DMA engine unit is used to concurrently read target queue elements from multiple target queue pairs through multiple channels under the triggering of the queue element acquisition unit.

[0007] The queue element processing unit is used to process the target queue element and dynamically allocate storage space for storing the control information of the target queue element in the order-preserving cache space.

[0008] The scheduling unit is used to schedule and output the data of the target queue element according to the control information of the target queue element stored in the order-preserving cache space.

[0009] This scheme uses a multi-channel DMA engine unit to concurrently read target queue elements from the target queue pair, which reduces memory latency. Furthermore, this scheme stores control information for each target queue element in a pre-order-keeping cache space, allowing the scheduling unit to output ready target queue elements based on this control information, thereby reducing unnecessary waiting time. In addition, storage space for control information is dynamically allocated in a shared pre-order-keeping cache space for the read target queue elements, achieving dynamic on-demand allocation of storage resources and eliminating the internal fragmentation and resource waste caused by fixed partition allocation in related technologies.

[0010] In an optional implementation, the queue element processing unit establishes a singly linked list node for each target queue element in the order-preserving cache space, and manages the singly linked list node according to the target queue pair; the singly linked list node is used to store the control information of the target queue element, and the control information includes the current processing status of the target queue element.

[0011] This embodiment achieves on-demand resource allocation for target queue pairs by dynamically allocating singly linked list nodes in the order-preserving cache space. This allows low-load queue pairs to occupy less storage space and high-load queue pairs to occupy more storage space when the load of queue pairs is uneven, thus avoiding resource waste.

[0012] In an optional implementation, the processing device for the work queue element further includes: an address translation unit, used to translate the virtual address to the physical address of the target queue element, and store the resulting translation information as part of the control information of the target queue element in the order-preserving cache space;

[0013] During the processing of the target queue element, the queue element processing unit determines whether the target queue element needs virtual address to physical address conversion;

[0014] If the target queue element requires a virtual address to physical address conversion, the queue element processing unit requests the address conversion unit to perform address conversion on the target queue element, and sets the current processing state of the target queue element to a waiting address conversion state in the control information corresponding to the order-preserving cache space.

[0015] In this scheme, for a target queue element that requires address translation, the scheduling unit can first pause the scheduling of that target queue element and instead schedule the target queue elements in other queue pairs that have already been processed. This way, the address translation or processing delay of the target queue element that requires address translation will not block the reading and processing of target queue elements in other queue pairs.

[0016] In an optional implementation, if the target queue element does not require virtual address to physical address translation, the current processing state of the target queue element is set to unconditional output state in the control information corresponding to the order-preserving cache space.

[0017] In this scheme, the scheduling unit can schedule and output target queue elements that do not require address translation in the first instance, thereby achieving low-latency output scheduling and minimizing waiting time while ensuring strict order.

[0018] In an optional implementation, after the address translation unit completes the address translation of the target queue element, it updates the current processing status in the control information of the target queue element to a conditional output status; after the scheduling unit outputs the data of the target queue element, it updates the current processing status in the control information of the target queue element to an idle status.

[0019] In this scheme, the order-preserving cache space adopts a shared cache pool, and a singly linked list is used to manage the control information of the target queue elements. This can ensure that the output order is consistent with the submission order. At the same time, combined with the different current processing states assigned to the target queue elements in the control information, efficient dynamic order preservation is achieved.

[0020] According to a second aspect of this application, a method for processing work queue elements is provided, comprising:

[0021] The queue element acquisition unit selects a target queue pair and reads the target queue element in the selected target queue pair through the multi-channel DMA engine unit;

[0022] The queue element acquisition unit stores the target queue element data in a shared storage space;

[0023] The queue element processing unit processes the target queue element and dynamically allocates storage space in the order-preserving cache space for storing the control information of the target queue element.

[0024] The scheduling unit schedules and outputs the data of the target queue element according to the control information of the target queue element stored in the order-preserving cache space.

[0025] In an optional implementation, the step of dynamically allocating storage space in the order-preserving cache space for storing the control information of the target queue element includes:

[0026] The queue element processing unit establishes a singly linked list node for each target queue element in the order-preserving cache space, and manages the singly linked list node according to the target queue pair; the singly linked list node stores the control information of the target queue element, and the control information includes the current processing status of the target queue element.

[0027] In an optional implementation, the method further includes:

[0028] The queue element processing unit determines whether the target queue element needs virtual address to physical address translation by parsing the type of the target queue element;

[0029] If the target queue element requires virtual address to physical address translation, the queue element processing unit submits a request to the address translation unit to perform address translation on the target queue element, and sets the current processing state of the target queue element to the waiting address translation state in the corresponding control information in the order-preserving cache space.

[0030] After receiving a request from the queue element processing unit, the address translation unit performs virtual address to physical address conversion on the target queue element, and stores the resulting conversion information as part of the control information of the target queue element in the order-preserving cache space.

[0031] In an optional implementation, the method further includes:

[0032] If the target queue element does not require virtual address to physical address translation, the queue element processing unit sets the current processing state of the target queue element to unconditional output state in the corresponding control information in the order-preserving cache space.

[0033] In an optional implementation, the method further includes:

[0034] After the address translation unit completes the address translation of the target queue element, it updates the current processing status in the control information of the target queue element to the conditional output status.

[0035] After the scheduling unit outputs the data of the target queue element, it updates the current processing status in the control information of the target queue element to the idle status.

[0036] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures and processes shown in the description and the accompanying drawings. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a structural block diagram of a work queue element processing apparatus according to an exemplary embodiment of this application.

[0039] Figure 2 This is a schematic diagram illustrating the processing flow of a work queue element according to an exemplary embodiment of this application.

[0040] Figure 3 This is a schematic diagram illustrating the state transition of the current processing state of a work queue element according to an exemplary embodiment of this application.

[0041] Figure 4 This is a flowchart illustrating a method for processing work queue elements according to an exemplary embodiment of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] As described in the background section, the relevant technology has the following drawbacks:

[0044] Serial processing blocking: After reading the WQE (Work Queue Element) of a QP (Queue Pair), it is necessary to wait for its VAPA (Virtual Address to Physical Address Translation) to complete before the WQE of the next QP can be processed, causing the DMA channel to be idle during the translation.

[0045] Low resource utilization: The order-preserving cache space caches WQE control information during processing to ensure that the output order is consistent with the commit order. It is usually allocated to different QPs using a fixed partitioning method. When the QP load is uneven, low-load QPs occupy redundant space, while high-load QPs may have insufficient resources, resulting in significant resource waste.

[0046] Insufficient bandwidth utilization: The aforementioned congestion and resource fragmentation issues result in DMA channel utilization typically being less than 40%, meaning memory bandwidth cannot be fully utilized, thus limiting system throughput.

[0047] In technologies employing single-channel sequential processing of QPs, VAPA conversion and WQE reading are executed serially (i.e., WQE is read first, then VAPA conversion is performed, and the next WQE is processed only after the conversion is complete). This technology has several drawbacks: First, the DMA channel is idle during VAPA conversion, failing to hide memory access latency and resulting in resource waste, potentially leading to severe channel congestion. Second, using a fixed-partition order-preserving cache module can easily lead to uneven resource allocation and internal fragmentation when QP loads vary or their sizes differ, reducing cache utilization. Third, output scheduling requires waiting for the entire processing chain (WQE reading, VAPA conversion, data processing) to be fully ready before outputting, limiting the output rate and causing a throughput decrease of approximately 30%, resulting in low order-preserving efficiency.

[0048] Based on the above analysis, see Figure 1 As shown, this application exemplarily proposes a work queue element processing apparatus, including: a queue element acquisition unit, a multi-channel DMA engine unit, a queue element processing unit, and a scheduling unit;

[0049] The system includes a queue element acquisition unit for selecting target queue pairs, reading target queue elements from the selected target queue pairs through a multi-channel DMA engine unit, and storing the target queue elements in a shared storage space. The multi-channel DMA engine unit, triggered by the queue element acquisition unit, concurrently reads target queue elements from multiple target queue pairs through multiple channels. The queue element processing unit processes the target queue elements and dynamically allocates storage space in the order-preserving cache space for storing the control information of the target queue elements. The scheduling unit schedules the output of the target queue element data based on the control information of the target queue elements stored in the order-preserving cache space.

[0050] For example, the processing device for this work queue element is located in the RDMA network interface card (NIC). The work queue element (WQE) is the basic unit of RDMA operation, containing control information such as data address and length. When a PCIe device needs to transmit new data, it places the data into a queue pair. A queue pair is the basic logical unit of communication in an RDMA network, consisting of a transmit queue (SQ) and a receive queue (RQ), used to isolate data streams from different applications. The target queue pair is selected by the queue element acquisition unit from all queue pairs with data to be transmitted, according to a time-sharing scheduling strategy or a priority selection strategy. See also... Figure 2As shown, the queue element acquisition unit can concurrently read target queue elements from selected target queue pairs through multiple parallel DMA channels. The data of the target queue elements in the target queue pairs read by the queue element acquisition unit is organized and stored in a shared cache space and managed using a singly linked list. That is, the data of the target queue elements read from each target queue pair is managed using the same singly linked list, while the data of the target queue elements read from different target queue pairs are managed using different singly linked lists.

[0051] For example, the multi-channel DMA engine unit can support 16 independent channels concurrently initiating memory read requests and support a maximum of 64 outstanding requests, deeply hiding memory access latency. This application employs a mechanism where multiple queues alternately use multiple DMA channels and a dynamic time-slice allocation strategy to achieve queue-level load balancing.

[0052] For example, after selecting a target queue pair, the queue element acquisition unit selects one of the DMA channels in the multi-channel DMA engine unit and reads the target queue element of the target queue pair from the selected channel through the DMA interface of the multi-channel DMA engine unit. The queue element processing unit processes the target queue element, dynamically allocates storage space for the target queue element in the order-preserving buffer space, and then stores the control information of the target queue element in the dynamically allocated storage space. The control information includes at least indication information as to whether the target queue element can be scheduled for output.

[0053] For example, the scheduling unit monitors the control information of each target queue element in the order-preserving buffer space in real time, and sends out the data of the target queue element when the control information indicates that the target queue element can be output. The scheduling unit can adopt different scheduling strategies, such as priority queues and weighted round-robin, to provide hierarchical scheduling capabilities for different queue pairs.

[0054] This scheme uses a multi-channel DMA engine unit to concurrently read target queue elements from the target queue pair, which reduces memory latency. Furthermore, this scheme stores control information for each target queue element in a pre-order-keeping cache space, allowing the scheduling unit to output ready target queue elements based on this control information, thereby reducing unnecessary waiting time. In addition, storage space for control information is dynamically allocated in a shared pre-order-keeping cache space for the read target queue elements, achieving dynamic on-demand allocation of storage resources and eliminating the internal fragmentation and resource waste caused by fixed partition allocation in related technologies.

[0055] In some optional implementations, the queue element processing unit establishes a singly linked list node for each target queue element in the order-preserving cache space and manages the singly linked list nodes according to the target queue. The singly linked list node is used to store the control information of the target queue element, including the current processing status of the target queue element.

[0056] For example, after reading the target queue element, the queue element processing unit dynamically allocates a singly linked list node for the target queue element in the order-preserving cache space to store the control information of the target queue element. The order-preserving cache space adopts a method where multiple queue pairs share a storage pool, and each queue pair uses a singly linked list to manage the control information of the work queue elements belonging to that queue pair. The control information is mainly used to indicate the current processing status of the work queue element. Through the current processing status, it can be determined whether the work queue element has been processed by the queue element processing unit, so that it can be scheduled for output by the scheduling unit. The processing of the target queue element by the queue element processing unit includes assembling the data of the target queue element into packets and waiting for the scheduling unit to schedule the output of the data packets. After the queue element processing unit completes all the data of the target queue element, it releases the DMA channel occupied by the target queue element. If the target queue pair still has data to be sent, the queue element processing unit also triggers a re-am doorbell mechanism to notify the upper-layer software or hardware.

[0057] This embodiment achieves on-demand resource allocation for target queue pairs by dynamically allocating singly linked list nodes in the order-preserving cache space. This allows low-load queue pairs to occupy less storage space and high-load queue pairs to occupy more storage space when the load of queue pairs is uneven, thus avoiding resource waste.

[0058] In some optional implementations, the processing device for work queue elements further includes: an address translation unit, used to translate the virtual address to the physical address of the target queue element, and store the resulting translation information as part of the control information of the target queue element in the order-keeping cache space;

[0059] During the processing of target queue elements, the queue element processing unit determines whether the target queue element requires virtual address to physical address translation.

[0060] If the target queue element requires a virtual address to physical address conversion, the queue element processing unit requests the address translation unit to perform address translation on the target queue element, and sets the current processing state of the target queue element to the waiting address translation state in the control information corresponding to the order-keeping cache space.

[0061] For example, target queue elements, due to their different types, include target queue elements that require virtual address to physical address translation (VAPA) and target queue elements that do not require VAPA translation. The target queue element processing device also includes an address translation unit for target queue elements that require VAPA translation. The address translation unit can be a parallel VAPA translation unit supporting 16 channels of concurrency and a maximum of 256 outstanding requests. When processing a target queue element, the queue element processing unit can first parse the type field of the target queue element and determine whether the target queue element requires VAPA translation based on the opcode or predefined flags in the type field. If so, the queue element processing unit requests the address translation unit to perform address translation for the target queue element. The address translation unit then converts the virtual address of the target queue element into a physical address and outputs the resulting conversion information, such as the physical address and length, to the order-keeping buffer space, thereby storing the control information of the target queue element. Since address translation of the target queue element requires a certain amount of time, the current processing status of the target queue element is set to "waiting for address translation to complete" in the order-preserving buffer. This allows the scheduling unit to pause scheduling of the target queue element and instead schedule target queue elements from other queue pairs that have already been processed. This ensures that the address translation or processing delay of the target queue element does not block the reading and processing of target queue elements from other queue pairs.

[0062] It should be noted that the control information stored in the singly linked list node corresponding to a work queue element in the order-preserving cache space includes at least the current processing state of the work queue element, the index of the work queue element's data (this index points to the position of the work queue element in the shared cache that stores the work queue element's data, and the shared cache also uses singly linked list nodes to manage the work queue element's data), and the index of the conversion result of the address translation unit (this index points to the conversion result storage area).

[0063] In some optional implementations, if the target queue element does not require virtual address to physical address translation, the current processing state of the target queue element is set to unconditional output state in the control information corresponding to the order-preserving cache space.

[0064] For example, for target queue elements that do not require virtual address to physical address translation, the queue element processing unit can skip the address translation process and directly set the current processing state in its control information to unconditional output state after processing the data of the target queue element. In this way, the scheduling unit can schedule the target queue element to output as soon as possible, thereby achieving low-latency output scheduling and minimizing the waiting time while ensuring strict order.

[0065] In some optional implementations, after the address translation unit completes the address translation of the target queue element, it updates the current processing status in the control information of the target queue element to the conditional output status; after the scheduling unit outputs the data of the target queue element, it updates the current processing status in the control information of the target queue element to the idle status.

[0066] For example, as shown in Table 1 below, the current processing state of a target queue element includes four states: idle, waiting for address translation, unconditional output, and conditional output. These four states are represented by 00, 01, 10, and 11 in a singly linked list node. When the queue element processing unit initially establishes a singly linked list node for a target queue element, the current processing state can be set to idle. If, during subsequent processing, the queue element processing unit determines that the target queue element requires virtual-to-physical address translation, it requests address translation from the address translation unit and sets the current processing state to waiting for address translation. If the target queue element does not require address translation, the current processing state is directly set to unconditional output. After completing the address translation, the address translation unit updates the current processing state of the target queue element from waiting for address translation to conditional output. The singly linked list node corresponding to the target queue element in both the unconditional and conditional output states can only be scheduled for output if it is located at the head of the singly linked list. After the scheduling unit completes the scheduling and output of the singly linked list node corresponding to the target queue element in the unconditional output state according to the scheduling strategy, it sets the current processing state of the target queue element to the idle state. See [link to relevant documentation] for the transition of the current processing state of the target queue element. Figure 3 As shown.

[0067] In this scheme, the order-preserving cache space adopts a shared cache pool, and a singly linked list is used to manage the control information of the target queue elements. This can ensure that the output order is consistent with the submission order. At the same time, combined with the different current processing states assigned to the target queue elements in the control information, efficient dynamic order preservation is achieved.

[0068] Table 1

[0069]

[0070] Accordingly, see Figure 4 As shown, this application also provides an exemplary method for processing work queue elements, including:

[0071] Step S401: The queue element acquisition unit selects the target queue pair and reads the target queue element in the selected target queue pair through the multi-channel DMA engine unit;

[0072] Step S402: The queue element acquisition unit stores the target queue element data in the shared storage space;

[0073] Step S403: The queue element processing unit processes the target queue element and dynamically allocates storage space in the order-preserving cache space for storing the control information of the target queue element;

[0074] Step S404: The scheduling unit schedules and outputs the data of the target queue element according to the control information of the target queue element stored in the order-preserving buffer space.

[0075] In an optional implementation, the aforementioned dynamic allocation of storage space in the order-preserving cache space for storing control information of the target queue elements includes:

[0076] The queue element processing unit establishes a singly linked list node for each target queue element in the order-preserving cache space and manages the singly linked list nodes according to the target queue. The singly linked list node stores the control information of the target queue element, including the current processing status of the target queue element.

[0077] In an optional implementation, the processing method further includes:

[0078] The queue element processing unit determines whether the target queue element needs virtual address to physical address translation by parsing the type of the target queue element;

[0079] If the target queue element requires virtual address to physical address translation, the queue element processing unit submits a request to the address translation unit to perform address translation on the target queue element, and sets the current processing state of the target queue element to the waiting address translation state in the corresponding control information in the order-keeping cache space.

[0080] After receiving a request from the queue element processing unit, the address translation unit performs virtual address to physical address translation on the target queue element and stores the resulting translation information as part of the control information of the target queue element in the order-keeping cache space.

[0081] In an optional implementation, the processing method further includes:

[0082] If the target queue element does not require virtual address to physical address translation, the queue element processing unit sets the current processing state of the target queue element to unconditional output state in the corresponding control information in the order-preserving cache space.

[0083] In an optional implementation, the processing method further includes:

[0084] After the address translation unit completes the address translation of the target queue element, it updates the current processing status in the control information of the target queue element to the conditional output status.

[0085] After the scheduling unit outputs the data of the target queue element, it updates the current processing status in the control information of the target queue element to the idle status.

[0086] The above processing method can be implemented by the processing device for work queue elements provided in the above embodiments. For specific implementation details, please refer to the description of the processing device for work queue elements in the above embodiments, which will not be repeated here.

[0087] It is understood that the circuit structures, names, and parameters described in the above embodiments are merely examples. Those skilled in the art can also make readily conceived combinations and adjustments to the structural features of the above embodiments according to their needs, and the concept of this application should not be limited to the specific details of the above examples.

[0088] Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A processing apparatus for work queue elements, characterized in that, include: The system includes a queue element acquisition unit, a multi-channel DMA engine unit, a queue element processing unit, and a scheduling unit. The queue element acquisition unit is used to select a target queue pair, read the target queue element in the selected target queue pair through the multi-channel DMA engine unit, and store the target queue element data to the shared storage space. The multi-channel DMA engine unit is used to concurrently read target queue elements from multiple target queue pairs through multiple channels under the triggering of the queue element acquisition unit. The queue element processing unit is used to process the target queue element and dynamically allocate storage space for storing the control information of the target queue element in the order-preserving cache space. The scheduling unit is used to schedule and output the data of the target queue element according to the control information of the target queue element stored in the order-preserving cache space; The processing device for the work queue element further includes: an address translation unit, used to translate the virtual address to the physical address of the target queue element, and store the resulting translation information as part of the control information of the target queue element in the order-preserving cache space; During the processing of the target queue element, the queue element processing unit determines whether the target queue element needs virtual address to physical address conversion; If the target queue element requires a virtual address to physical address conversion, the queue element processing unit requests the address conversion unit to perform address conversion on the target queue element, and sets the current processing state of the target queue element to a waiting address conversion state in the control information corresponding to the order-preserving cache space. When the current processing state of a target queue element is waiting for address translation, the scheduling unit first suspends scheduling the target queue element and then schedules target queue elements in other queue pairs that have already been processed.

2. The processing apparatus for work queue elements according to claim 1, characterized in that, The queue element processing unit establishes a singly linked list node for each target queue element in the order-preserving cache space, and manages the singly linked list node according to the target queue pair; the singly linked list node is used to store the control information of the target queue element, and the control information includes the current processing status of the target queue element.

3. The processing apparatus for work queue elements according to claim 1, characterized in that, If the target queue element does not require virtual address to physical address translation, then the current processing state of the target queue element is set to unconditional output state in the control information corresponding to the order-preserving cache space.

4. The processing apparatus for work queue elements according to claim 1, characterized in that, After the address translation unit completes the address translation of the target queue element, it updates the current processing status in the control information of the target queue element to the conditional output status. After the scheduling unit outputs the data of the target queue element, it updates the current processing status in the control information of the target queue element to the idle status.

5. A method for processing work queue elements, characterized in that, include: The queue element acquisition unit selects a target queue pair and reads the target queue element in the selected target queue pair through the multi-channel DMA engine unit; The queue element acquisition unit stores the target queue element data in a shared storage space; The queue element processing unit processes the target queue element and dynamically allocates storage space in the order-preserving cache space for storing the control information of the target queue element. The scheduling unit schedules and outputs the data of the target queue element according to the control information of the target queue element stored in the order-preserving cache space; The queue element processing unit determines whether the target queue element needs virtual address to physical address translation by parsing the type of the target queue element; If the target queue element requires virtual address to physical address translation, the queue element processing unit submits a request to the address translation unit to perform address translation on the target queue element, and sets the current processing state of the target queue element to the waiting address translation state in the corresponding control information in the order-preserving cache space. After receiving a request from the queue element processing unit, the address translation unit performs virtual address to physical address translation on the target queue element, and stores the resulting translation information as part of the control information of the target queue element in the order-preserving cache space. When the current processing state of a target queue element is set to the waiting address translation state, the scheduling unit first suspends the scheduling of that target queue element and schedules target queue elements in other queue pairs that have already been processed.

6. The method for processing work queue elements according to claim 5, characterized in that, The step of dynamically allocating storage space in the order-preserving cache space for storing the control information of the target queue element includes: The queue element processing unit establishes a singly linked list node for each target queue element in the order-preserving cache space, and manages the singly linked list node according to the target queue pair; the singly linked list node stores the control information of the target queue element, and the control information includes the current processing status of the target queue element.

7. The method for processing work queue elements according to claim 5, characterized in that, The method further includes: If the target queue element does not require virtual address to physical address translation, the queue element processing unit sets the current processing state of the target queue element to unconditional output state in the corresponding control information in the order-preserving cache space.

8. The method for processing work queue elements according to claim 7, characterized in that, The method further includes: After the address translation unit completes the address translation of the target queue element, it updates the current processing status in the control information of the target queue element to the conditional output status. After the scheduling unit outputs the data of the target queue element, it updates the current processing status in the control information of the target queue element to the idle status.

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