Semiconductor device, forming method thereof and memory
By retaining a mask layer to protect the gate after forming the gate and using the same etching process to remove the spacer layer and gate insulation layer, the process complexity and damage problems in the peripheral circuit of NAND-type three-dimensional memory are solved, achieving cost savings and performance improvements.
CN120825948APending Publication Date: 2025-10-21YANGTZE MEMORY TECH CO LTD
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Patent Information
- Application Number
- CN202410451687.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-15
- Publication Date
- 2025-10-21
AI Technical Summary
Technical Problem
When forming the peripheral circuits of a NAND-type three-dimensional memory, the prior art needs to take into account the difference in gate oxide thickness between the high-voltage and low-voltage regions, resulting in a complex process, high cost, and susceptibility to plasma-induced damage.
Method used
After forming the gate, the mask layer is retained to protect the gate, and the spacer layer and the gate insulating layer are removed through the same etching process, which reduces the process steps and improves the damage to the gate by high-energy plasma.
Benefits of technology
The process flow is simplified, the cost is reduced, the gate is effectively protected from plasma damage, and the device performance is improved.
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Smart Images
Figure CN120825948A_ABST
Abstract
The invention provides a semiconductor device and a forming method thereof, and a memory. The forming method of the semiconductor device comprises the following steps: providing a semiconductor structure; the semiconductor structure comprises a semiconductor layer with a first region and a first gate insulating layer located on the first region; forming a first columnar structure covering part of the first gate insulating layer on the first gate insulating layer; the first columnar structure comprises a grid electrode and a mask layer located on the grid electrode; forming a spacer layer covering the first columnar structure on the first region in a shape-preserving manner and the first gate insulating layer on the two sides of the first columnar structure; removing part of the spacing layer; the remaining spacer layer covers the side wall of the first columnar structure; and removing the exposed first gate insulating layer on the two sides of the first columnar structure.
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