Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to the technical field of semiconductor, and discloses a semiconductor structure and a forming method thereof. The forming method comprises: forming a pad layer on a substrate; forming a capacitor hole in the substrate, the capacitor hole being located at one side of the pad layer; forming a capacitor material layer on a structure formed by the substrate and the pad layer, the capacitor material layer comprising at least a first electrode layer, a second electrode layer and a first dielectric layer between the first electrode layer and the second electrode layer; and etching the capacitor material layer on the pad layer and at least part of the pad layer to cut off the capacitor material layer on the pad layer. The forming method can reduce structural defects and improve product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same. Background Technology

[0002] Deep trench capacitors (DTCs) are crucial components in integrated circuits, playing a vital role in improving the impedance and logic voltage of the power delivery network (PDN). However, structural defects are prone to occur during the DTC manufacturing process, resulting in low product yield.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can reduce structural defects and improve product yield.

[0005] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0006] A pad layer is formed on the substrate;

[0007] A capacitor hole is formed in the substrate, and the capacitor hole is located on one side of the pad layer;

[0008] A capacitor material layer is formed on the structure jointly formed by the substrate and the pad layer, wherein the capacitor material layer includes at least a first electrode layer, a second electrode layer and a first dielectric layer located between the first electrode layer and the second electrode layer;

[0009] The capacitor material layer located on the pad layer and at least a portion of the pad layer are etched to cut off the capacitor material layer located on the pad layer.

[0010] In one exemplary embodiment of this disclosure, the material of the padding layer is an insulating material; or, the material of the padding layer is the same as at least a portion of the material in the capacitor material layer.

[0011] In one exemplary embodiment of this disclosure, the thickness of the padding layer is greater than or equal to the thickness of the capacitor material layer.

[0012] In one exemplary embodiment of this disclosure, before forming the capacitive material layer that conformally covers the structure jointly formed by the substrate and the pad layer, the forming method further includes:

[0013] An insulating layer is formed on the structure formed by the substrate and the padding layer.

[0014] In one exemplary embodiment of this disclosure, the padding layer includes a first padding layer, a second padding layer, and a third padding layer sequentially stacked along a direction perpendicular to the substrate. The first padding layer is located on the surface of the substrate. The formation of a capacitive material layer conformally covering the structure jointly formed by the substrate and the padding layer includes:

[0015] A first electrode layer is formed that conformally covers the insulating layer;

[0016] A first dielectric layer is formed that conformally covers the surface of the first electrode layer;

[0017] A second electrode layer is formed that conformally covers the surface of the first dielectric layer;

[0018] The first pad layer is made of the same material as the insulating layer; the second pad layer is made of the same material as the first electrode layer and / or the second electrode layer; and the third pad layer is made of the same material as the first dielectric layer.

[0019] In one exemplary embodiment of this disclosure, after forming the capacitor material layer, the forming method further includes:

[0020] A conductive layer is formed on the surface of the capacitor material layer, and the conductive layer fills the capacitor hole; when etching the capacitor material layer located on the pad layer and at least a portion of the pad layer, the conductive layer located directly above the pad layer is also etched.

[0021] In one exemplary embodiment of this disclosure, the forming method further includes:

[0022] A portion of the film layer in the capacitor material layer located on the side of the capacitor hole away from the pad layer and the conductive layer located on the side of the capacitor hole away from the pad layer are etched to expose a portion of the surface of the first electrode layer.

[0023] An isolation layer is formed to cover the surface of the structure consisting of the substrate, the remaining conductive layer, the remaining padding layer, and the remaining capacitor material layer.

[0024] In one exemplary embodiment of this disclosure, the forming method further includes:

[0025] The isolation layer is etched to form a first contact hole that exposes a portion of the surface of the first electrode layer;

[0026] The remaining conductive layer and the isolation layer located on top of the conductive layer are etched to form a second contact hole;

[0027] A first lead for leading out the first electrode layer is formed in the first contact hole, and a second lead for leading out the second electrode layer is formed in the second contact hole.

[0028] In one exemplary embodiment of this disclosure, the formation of a capacitor material layer on the structure conformally covering the substrate and the pad layer further includes:

[0029] Before forming the first electrode layer, a third electrode layer is formed that conformally covers the surface of the insulating layer;

[0030] A second dielectric layer is formed to conformally cover the surface of the third electrode layer, wherein the first electrode layer conformally covers the surface of the second dielectric layer.

[0031] In one exemplary embodiment of this disclosure, the forming method further includes:

[0032] The remaining conductive layer, the remaining insulating layer, and a portion of the capacitor material layer are etched on the side of the first contact hole away from the second contact hole to form a third contact hole exposing the third electrode layer.

[0033] A third lead is formed within the third contact hole to bring out the third electrode layer.

[0034] In one exemplary embodiment of this disclosure, the forming method further includes:

[0035] When forming the capacitor hole, a recess is formed in the substrate; the capacitor material layer also conformally covers the recess; the conductive layer also fills the recess.

[0036] When etching the capacitor material layer and at least a portion of the padding layer located on the padding layer, the conductive layer located in the recess, the second electrode layer located at the bottom of the recess, and the first dielectric layer located at the bottom of the recess are also etched to form a via exposing the first electrode layer; the insulating layer also conformally covers the via, and the first lead is located inside the via.

[0037] In one exemplary embodiment of this disclosure, there are multiple capacitor holes, and the capacitor material layer conformally covers the multiple capacitor holes; the capacitor material layer in each capacitor hole constitutes a capacitor unit, and adjacent capacitor units are connected in series; multiple capacitor units form a capacitor group, and the padding layer is formed on the side of the outermost capacitor unit in the capacitor group away from the center of the capacitor group.

[0038] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0039] Substrate, the substrate having capacitor holes;

[0040] The padding layer is located on one side of the capacitor hole;

[0041] A capacitor material layer conformally covers the structure formed by the substrate, the padding layer, and the capacitor hole. The capacitor material layer includes at least a first electrode layer, a second electrode layer, and a first dielectric layer located between the first electrode layer and the second electrode layer.

[0042] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0043] An insulating layer conformally covers the structure formed by the substrate, the padding layer, and the capacitor aperture; the capacitor material layer is located on the insulating layer.

[0044] In one exemplary embodiment of this disclosure, the first electrode layer conformally covers the insulating layer; the first dielectric layer conformally covers the surface of the first electrode layer; and the second electrode layer conformally covers the surface of the first dielectric layer.

[0045] Alternatively, the capacitor material layer may further include a second dielectric layer and a third electrode layer, wherein the third electrode layer conformally covers the surface of the insulating layer; the second dielectric layer conformally covers the surface of the third electrode layer; the first electrode layer conformally covers the surface of the second dielectric layer; the first dielectric layer conformally covers the surface of the first electrode layer; and the second electrode layer conformally covers the surface of the first dielectric layer.

[0046] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0047] A conductive layer is located on the surface of the capacitor material layer, and the conductive layer fills the capacitor holes;

[0048] The first lead is located on the side of the capacitor hole away from the pad layer and is in contact with the first electrode layer to electrically lead out the first electrode layer;

[0049] The second lead is at least partially embedded in the conductive layer to electrically lead out the second electrode layer;

[0050] The third lead is located on the side of the first lead away from the second lead and is in contact with the third electrode layer to electrically lead out the third electrode layer.

[0051] In one exemplary embodiment of this disclosure, there are multiple capacitor holes, and the capacitor material layer conformally covers the multiple capacitor holes; the capacitor material layer in each capacitor hole constitutes a capacitor unit, and adjacent capacitor units are connected in series; the multiple capacitor holes form a capacitor group, and the padding layer is formed on the side of the capacitor unit located at the outermost edge of the capacitor group away from the center of the capacitor group.

[0052] The semiconductor structure and its formation method disclosed herein, by setting a pad layer below the capacitor material layer and etching the pad layer and the capacitor material layer located on the pad layer, can physically cut off the capacitor material layer located on the pad layer. This precisely disconnects the capacitor material layer that was originally connected across regions on the pad layer, thereby electrically isolating the capacitor structure within the capacitor hole on one side of the pad layer from the capacitor material layer covered by other regions, preventing short circuits. Furthermore, by simultaneously etching at least a portion of the pad layer during the etching of the capacitor material layer, the resulting corner extends deep into the pad layer or is formed by the pad layer and the substrate. In this case, the gap between the bottom surface of the corner and the remaining capacitor material layer after etching is larger. The conductive polymer generated during the etching process accumulates at the corner and is less likely to extend to the sidewalls of the remaining capacitor material layer. This reduces the probability of a short circuit between the first electrode layer and the second electrode layer in the remaining capacitor material layer due to the accumulation of conductive polymer generated during etching, helping to reduce structural defects and improve product yield.

[0053] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0055] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of this disclosure.

[0056] Figure 2 This is a schematic diagram of the substrate and pad layer in an embodiment of this disclosure.

[0057] Figure 3 This is a schematic diagram of the capacitor material layer in one embodiment of the present disclosure.

[0058] Figure 4 This is a schematic diagram of the capacitor material layer in one embodiment of the present disclosure.

[0059] Figure 5 This is a schematic diagram of the structure after etching away part of the padding layer when the capacitor material layer in this disclosure includes a first electrode layer, a first dielectric layer and a second electrode layer.

[0060] Figure 6 This is a schematic diagram of the structure after etching away a portion of the padding layer when the capacitor material layer in this disclosure includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, and a third electrode layer.

[0061] Figure 7 This is a schematic diagram of the structure after the padding layer is cut through when the capacitor material layer in this disclosure includes a first electrode layer, a first dielectric layer and a second electrode layer.

[0062] Figure 8 This is a schematic diagram of the structure after the padding layer is etched through when the capacitor material layer in this disclosure includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, and a third electrode layer.

[0063] Figure 9 This is a schematic diagram of a capacitor unit and a capacitor bank in one embodiment of the present disclosure.

[0064] Figure 10 This is a schematic diagram of a conductive layer in one embodiment of the present disclosure.

[0065] Figure 11 This is a schematic diagram of a conductive material layer in one embodiment of the present disclosure.

[0066] Figure 12 This is a schematic diagram of the structure after step S170 is completed in one embodiment of this disclosure.

[0067] Figure 13 This is a schematic diagram of the structure after step S170 is completed in another embodiment of this disclosure.

[0068] Figure 14 This is a schematic diagram of the structure after step S180 is completed in one embodiment of this disclosure.

[0069] Figure 15 This is a schematic diagram of the structure after step S180 is completed in another embodiment of this disclosure.

[0070] Figure 16 This is a schematic diagram of the first contact hole and the second contact hole in one embodiment of the present disclosure.

[0071] Figure 17 This is a schematic diagram of the first lead and the second lead in one embodiment of this disclosure.

[0072] Figure 18 This is a schematic diagram of the third contact hole in one embodiment of the present disclosure.

[0073] Figure 19This is a schematic diagram of the third lead in one embodiment of the present disclosure.

[0074] Figure 20 This is a schematic diagram of the capacitor hole and the recess in one embodiment of the present disclosure.

[0075] Figure 21 This is a schematic diagram of the capacitor material layer and the conductive layer in one embodiment of the present disclosure.

[0076] Figure 22 This is a schematic diagram of a through hole in one embodiment of the present disclosure.

[0077] Figure 23 This is a schematic diagram of the first contact hole and the second contact hole in one embodiment of the present disclosure.

[0078] Figure 24 This is a schematic diagram of the first lead and the second lead in one embodiment of the present disclosure.

[0079] Explanation of reference numerals in the attached figures:

[0080] 1. Substrate; 11. Capacitor via; 12. Recess; 2. Pad layer; 21. First pad layer; 22. Second pad layer; 23. Third pad layer; 3. Capacitor material layer; 31. First electrode layer; 32. First dielectric layer; 33. Second electrode layer; 34. Second dielectric layer; 35. Third electrode layer; 4. Insulating layer; 5. Conductive layer; 510. Conductive material layer; 6. Isolating layer; 71. First lead; 72. Second lead; 73. Third lead; 8. Dielectric layer; 10. First contact hole; 20. Second contact hole; 30. Third contact hole; 40. Through hole; 50. Capacitor unit; 100. Capacitor group. Detailed Implementation

[0081] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0082] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0083] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0084] In the DTC process, it is usually necessary to disconnect multiple adjacent capacitor cells. Therefore, the capacitor material layer between adjacent capacitor cells needs to be cut. However, during the process of cutting the capacitor material layer, the generated conductive polymer tends to accumulate at the corner formed between the remaining capacitor material layer and the substrate. As the etching process proceeds, the amount of accumulated conductive polymer increases and the accumulation height increases, which can easily conduct different electrodes in the capacitor material layer, resulting in a low product yield.

[0085] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, the forming method includes steps S110-S140, wherein:

[0086] Step S110: Form a pad layer on the substrate;

[0087] Step S120: A capacitor hole is formed in the substrate, and the capacitor hole is located on one side of the pad layer;

[0088] Step S130: Form a capacitor material layer that conformally covers the structure jointly formed by the substrate and the pad layer. The capacitor material layer includes at least a first electrode layer, a second electrode layer, and a first dielectric layer located between the first electrode layer and the second electrode layer.

[0089] Step S140: Etch the capacitor material layer and at least a portion of the padding layer located on the padding layer to cut off the capacitor material layer located on the padding layer.

[0090] The semiconductor structure formation method disclosed herein, by setting a pad layer below the capacitor material layer and etching the pad layer and the capacitor material layer located on the pad layer, can physically cut off the capacitor material layer located on the pad layer. This precisely disconnects the capacitor material layers that were originally connected across regions on the pad layer, thereby electrically isolating the capacitor structure within the capacitor hole on one side of the pad layer from the capacitor material layers covering other regions, preventing short circuits. Furthermore, by simultaneously etching at least a portion of the pad layer during the etching of the capacitor material layer, the resulting corner extends deep into the pad layer or is formed by the pad layer and the substrate. In this case, the gap between the bottom surface of the corner and the remaining capacitor material layer after etching is larger. The conductive polymer generated during the etching process accumulates at the corner and is less likely to extend to the sidewalls of the remaining capacitor material layer. This reduces the probability of a short circuit between the first electrode layer and the second electrode layer in the remaining capacitor material layer due to the accumulation of conductive polymer generated during etching, helping to reduce structural defects and improve product yield.

[0091] The steps and specific details of the semiconductor structure formation method disclosed herein are described in detail below:

[0092] like Figure 1 As shown, in step S110, a pad layer is formed on the substrate.

[0093] The substrate may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, such as silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate.

[0094] like Figure 2 As shown, the padding layer 2 can be a single-layer film structure or a composite film structure composed of multiple film layers, and no special limitation is made here. In an exemplary embodiment of this disclosure, the padding layer 2 may include a first padding layer 21, a second padding layer 22 and a third padding layer 23 sequentially stacked along a direction perpendicular to the substrate 1, wherein the first padding layer 21 is located on the surface of the substrate 1.

[0095] The material of the padding layer 2 can be an insulating material, such as silicon nitride or silicon carbide nitride. When the padding layer 2 is a composite film structure, some of the material in the padding layer 2 can also be a conductive material. The padding material layer can be formed on the substrate 1 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Subsequently, the padding material layer can be etched to remove the padding material layer covering a portion of the substrate 1, leaving the remaining padding material layer as the padding layer 2.

[0096] like Figure 1 As shown, in step S120, a capacitor hole 11 is formed in the substrate 1, and the capacitor hole 11 is located on one side of the pad layer 2.

[0097] Please continue reading Figure 2 As shown, capacitor holes 11 can be formed in substrate 1 through an etching process. In a direction parallel to the surface of substrate 1, the cross-sectional shape of the capacitor hole 11 can be circular, elliptical, rectangular, polygonal, or irregular; no special limitation is made to the shape of the capacitor hole 11 here. The number of capacitor holes 11 can be one or more; no special limitation is made here. It should be noted that when there are multiple capacitor holes 11, the multiple capacitor holes 11 can be distributed at intervals. Furthermore, when there are multiple capacitor holes 11, all capacitor holes 11 can be located on the same side of the padding layer 2.

[0098] like Figure 1 As shown, in step S130, a capacitor material layer 3 is formed on the structure jointly constituted by the conformal covering substrate 1 and the padding layer 2. The capacitor material layer 3 includes at least a first electrode layer 31, a second electrode layer 33, and a first dielectric layer 32 located between the first electrode layer 31 and the second electrode layer 33. For details, please refer to [link to relevant documentation]. Figure 3 As shown.

[0099] The materials of the first electrode layer 31 and the second electrode layer 33 can both be materials with strong conductivity. For example, the materials of the first electrode layer 31 and the second electrode layer 33 can both be titanium nitride. The material of the first dielectric layer 32 can be a material with a high dielectric constant. For example, its material can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide or a mixture thereof. Of course, it can also be other materials, which will not be listed here.

[0100] In one exemplary embodiment of this disclosure, the material of the padding layer 2 may be the same as at least a portion of the material in the capacitor material layer 3. For example, when the padding layer 2 is a composite film structure, the material of some film layers in the padding layer 2 is the same as the material of the first electrode layer 31 or the second electrode layer 33, and the material of some film layers in the padding layer 2 is the same as the material of the first dielectric layer 32.

[0101] In one exemplary embodiment of this disclosure, the thickness of the padding layer 2 may be greater than or equal to the thickness of the capacitor material layer 3. For example, the thickness of the capacitor material layer 3 may be 200 nm to 300 nm; for example, its thickness may be 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, or 300 nm. The thickness of the padding layer 2 may be 300 nm to 500 nm; for example, its thickness may be 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm. Of course, the thicknesses of the capacitor material layer 3 and the padding layer 2 may also be other values, which will not be listed here.

[0102] In one exemplary embodiment of this disclosure, before forming the capacitor material layer 3 on the structure jointly formed by the conformal covering substrate 1 and the pad layer 2, the method of forming the capacitor material layer 3 further includes:

[0103] Step S150: An insulating layer 4 is formed on the structure jointly formed by the substrate 1 and the pad layer 2. Please continue to the next step. Figure 3 As shown.

[0104] The insulating layer 4 isolates the substrate 1 and the capacitor material layer 3, preventing charge leakage from the subsequently formed capacitor cell 50 into the substrate 1, thus improving device reliability. Simultaneously, the insulating layer 4 also prevents metal ions or doped ions from the subsequently formed capacitor material layer 3 from diffusing into the substrate 1, further enhancing device reliability. Furthermore, the process of forming the insulating layer 4 (including high-temperature annealing) can repair damage caused during the etching process of the capacitor hole 11, eliminating charge traps, thereby reducing leakage current and improving interface integrity. The insulating layer 4 can be made of insulating materials, such as silicon oxide or silicon nitride. The insulating layer 4 can be formed on the structure jointly formed by the substrate 1 and the padding layer 2 using methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During this process, the insulating layer 4 can conformally cover the inner wall of the capacitor hole 11.

[0105] In one exemplary embodiment of this disclosure, forming the capacitor material layer 3 on the structure jointly constituted by the conformal covering substrate 1 and the pad layer 2 (i.e., step S130) may include steps S210 to S230, wherein:

[0106] Step S210: A first electrode layer 31 is formed that conformally covers the insulating layer 4.

[0107] Please continue reading Figure 3 As shown, a first electrode layer 31 can be formed on the insulating layer 4 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The first electrode layer 31 can conformally cover the insulating layer 4 located within the capacitor hole 11 and extend to the top of the substrate 1; that is, the first electrode layer 31 can cover the entire surface of the insulating layer 4.

[0108] Step S220: A first dielectric layer 32 is formed that conformally covers the surface of the first electrode layer 31.

[0109] Please continue reading Figure 3As shown, the first dielectric layer 32 can be formed on the first electrode layer 31 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the first dielectric layer 32, and no specific limitation is made here. For example, a suitable formation method can be selected according to the specific material of the first dielectric layer 32, as long as the dielectric properties of the first dielectric layer 32 are guaranteed and the first dielectric layer 32 can cover the entire surface of the first electrode layer 31.

[0110] Step S230: A second electrode layer 33 is formed that conformally covers the surface of the first dielectric layer 32.

[0111] Please continue reading Figure 3 As shown, a second electrode layer 33 can be formed on the first dielectric layer 32 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The second electrode layer 33 can cover the entire surface of the first dielectric layer 32.

[0112] In an exemplary embodiment of this disclosure, when the padding layer 2 is a composite film layer structure and the padding layer 2 includes a first padding layer 21, a second padding layer 22 and a third padding layer 23, the first padding layer 21 is made of the same material as the insulating layer 4; the second padding layer 22 is made of the same material as the first electrode layer 31 and / or the second electrode layer 33; and the third padding layer 23 is made of the same material as the first dielectric layer 32.

[0113] In an exemplary embodiment of this disclosure, forming the capacitor material layer 3 on the structure jointly constituted by the conformal covering substrate 1 and the padding layer 2 (i.e., step S130) may further include steps S310 and S320, wherein:

[0114] In step S310, before forming the first electrode layer 31, a third electrode layer 35 is formed that conformally covers the surface of the insulating layer 4. For details, please refer to [link to relevant documentation]. Figure 4 As shown.

[0115] The material of the third electrode layer 35 can be a material with strong conductivity. For example, the material of the third electrode layer 35 can be the same as that of the first electrode layer 31 and / or the second electrode layer 33. For instance, the material of the third electrode layer 35 can be titanium nitride. The third electrode layer 35 can be formed on the insulating layer 4 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The third electrode layer 35 can conformally cover the surface of the insulating layer 4 located within the capacitor hole 11 and extend to the top of the substrate 1; that is, the third electrode layer 35 can cover the entire surface of the insulating layer 4.

[0116] In step S320, a second dielectric layer 34 is formed that conformally covers the surface of the third electrode layer 35, and the first electrode layer 31 conformally covers the surface of the second dielectric layer 34. For details, please refer to [link to previous section]. Figure 4 As shown.

[0117] The material of the second dielectric layer 34 can be a material with a high dielectric constant. For example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof. Of course, it can also be other materials, which will not be listed here. It should be noted that the material of the second dielectric layer 34 can be the same as or different from the material of the first dielectric layer 32, and no special limitation is made here.

[0118] A second dielectric layer 34 can be formed on the third electrode layer 35 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The second dielectric layer 34 can conformally cover the surface of the third electrode layer 35 and extend to the top of the substrate 1. After the formation of the second dielectric layer 34, the first electrode layer 31, the first dielectric layer 32, and the second electrode layer 33 can be formed sequentially.

[0119] It should be noted that when there are multiple capacitor holes 11, the insulating layer 4 can cover multiple capacitor holes 11 in a conformal manner. At the same time, the capacitor material layer 3 located on the insulating layer 4 can also cover multiple capacitor holes 11 in a conformal manner.

[0120] like Figure 1 As shown, in step S140, the capacitor material layer 3 located on the pad layer 2 and at least a portion of the pad layer 2 are etched to cut off the capacitor material layer 3 located on the pad layer 2.

[0121] like Figure 5 and Figure 6 As shown, the capacitor material layer 3 on the pad 2 in the area far from the capacitor hole 11 can be etched, thereby cutting off the capacitor material layer 3 on the pad 2, so as to precisely disconnect the capacitor material layer 3 that was originally connected across regions on the pad 2, thereby electrically isolating the capacitor structure in the capacitor hole 11 on one side of the pad 2 from the capacitor material layer 3 covered by other areas to prevent short circuit; during the above etching process, the pad 2 exposed after etching the capacitor material layer 3 can also be subjected to anisotropic etching.

[0122] In one exemplary embodiment of this disclosure, please continue to refer to Figure 5 and Figure 6 As shown, in the above process, part of the film layer in the pad layer 2 is etched away (i.e., the thickness of the exposed pad layer 2 is reduced), thereby allowing the corner formed after etching to penetrate into the pad layer 2. The gap between the bottom surface of the corner and the remaining capacitor material layer 3 after etching is relatively large. The conductive polymer generated during the etching process accumulates at the corner and is not easy to extend to the sidewall of the remaining capacitor material layer 3. This can reduce the probability of short circuit between the first electrode layer 31 and the second electrode layer 33 in the remaining capacitor material layer 3 due to the accumulation of conductive polymer generated by etching, which helps to reduce structural defects and improve product yield.

[0123] In another exemplary embodiment of this disclosure, such as Figure 7 and Figure 8 As shown, during the above etching process, all the film layers in the exposed pad layer 2 are etched away, thus penetrating the pad layer 2. At this time, the gap between the bottom surface of the corner formed after etching and the remaining capacitor material layer 3 after etching is larger, and the probability of the conductive polymer accumulated at the corner accumulating between the electrode layers in the remaining capacitor material layer 3 after etching is smaller, resulting in a lower probability of short circuit.

[0124] It should be noted that when the thickness of the padding layer 2 is greater than or equal to the thickness of the capacitor material layer 3, after the padding layer 2 is cut through, the gap between the bottom surface of the corner and the remaining capacitor material layer 3 is larger. The conductive polymer accumulated at the corner will hardly accumulate on the sidewall of the capacitor material layer 3, and the probability of short circuit between the electrode layers in the capacitor material layer 3 is smaller.

[0125] like Figure 9 As shown, when there are multiple capacitor holes 11, after cutting the capacitor material layer 3 located on the padding layer 2, the capacitor material layer 3 in each capacitor hole 11 constitutes a capacitor unit 50, and adjacent capacitor units 50 are connected in series. Multiple capacitor units 50 can form a capacitor group 100, and the padding layer 2 is formed on the side of the capacitor unit 50 located at the outermost edge of the capacitor group 100 away from the center of the capacitor group 100. It should be noted that the number of capacitor units 50 in the capacitor group 100 can be 1 to 8, for example, it can be 1, 2, 4, 6 or 8. Of course, the number of capacitor units 50 in the capacitor group 100 can also be other, as long as it can increase the storage capacity.

[0126] In some embodiments of this disclosure, there may be multiple capacitor groups 100. Adjacent capacitor groups 100 are independent of each other and spaced apart. After the capacitor material layer 3 located on the pad layer 2 is cut, the adjacent capacitor groups 100 can be disconnected to prevent the adjacent capacitor groups 100 from failing due to short circuit.

[0127] In one exemplary embodiment of this disclosure, after forming the capacitor material layer 3, the forming method of this disclosure may further include:

[0128] In step S160, a conductive layer 5 is formed on the surface of the capacitor material layer 3, and the conductive layer 5 fills the capacitor hole 11; while etching the capacitor material layer 3 and at least part of the padding layer 2 located on the padding layer 2, the conductive layer 5 located directly above the padding layer 2 is also etched.

[0129] like Figure 10As shown, before etching the capacitor material layer 3 and at least a portion of the padding layer 2 located on the padding layer 2, a conductive layer 5 can be formed on the capacitor material layer 3. For example, the conductive layer 5 can be formed on the surface of the second electrode layer 33. The conductive layer 5 can cover the entire surface of the capacitor material layer 3 (e.g., the second electrode layer 33) and can fill the capacitor hole 11, through which the second electrode layer 33 can be electrically led out.

[0130] In one exemplary embodiment of this disclosure, the material of the conductive layer 5 may be doped polycrystalline silicon, such as... Figure 11 As shown, a conductive material layer 510 (the material of the conductive material layer 510 can be polycrystalline silicon) can be formed on the second electrode layer 33 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Subsequently, the conductive material layer 510 can be chemically mechanically polished to give the remaining conductive material layer 510 a flat surface, providing a flat process reference for subsequent processes and helping to reduce process difficulty. Furthermore, after chemical mechanical polishing, the remaining conductive material layer 510 can be doped to increase its conductivity, and the doped conductive material layer 510 can be used as the conductive layer 5.

[0131] After the conductive layer 5 is formed, the conductive layer 5 located on top of the pad layer 2, the capacitor material layer 3 located on the pad layer 2, and at least a portion of the pad layer 2 can be etched simultaneously using the same etching process.

[0132] In one exemplary embodiment of this disclosure, the method for forming this disclosure may further include steps S170 and S180, wherein:

[0133] In step S170, a portion of the film layer in the capacitor material layer 3 located on the side of the capacitor hole 11 away from the pad layer 2 and the conductive layer 5 located on the side of the capacitor hole 11 away from the pad layer 2 are etched to expose a portion of the surface of the first electrode layer 31.

[0134] In some embodiments of this disclosure, while etching the conductive layer 5 on top of the padding layer 2, the capacitor material layer 3 on the padding layer 2, and at least a portion of the padding layer 2 (i.e., during step S160), a portion of the film layer (e.g., the second electrode layer 33 and the first dielectric layer 32) in the capacitor material layer 3 located on the side of the capacitor hole 11 away from the padding layer 2, and the conductive layer 5 located on the side of the capacitor hole 11 away from the padding layer 2, are etched to expose a portion of the surface of the first electrode layer 31. It should be noted that in this process, the capacitor material layer 3 can be broken and the surface of the first electrode layer 31 exposed in a single photomask and etching process, resulting in lower production costs. In an exemplary embodiment of this disclosure, the structure after step S170 is as follows: Figure 12 As shown. In another embodiment of this disclosure, the structure after step S170 is as follows. Figure 13As shown.

[0135] In some other embodiments of this disclosure, after etching the capacitor material layer 3, the conductive layer 5, the second electrode layer 33 and the first dielectric layer 32 located on the side of the capacitor hole 11 away from the pad layer 2 can be etched to expose part of the surface of the first electrode layer 31.

[0136] In step S180, an isolation layer 6 is formed on the surface of the structure comprising the conformal covering substrate 1, the remaining conductive layer 5, the remaining padding layer 2, and the remaining capacitor material layer 3. In an exemplary embodiment of this disclosure, the structure after step S180 is as follows: Figure 14 As shown. In another embodiment of this disclosure, the structure after step S180 is as follows. Figure 15 As shown.

[0137] The material of the isolation layer 6 can be an insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide nitride, or silicon carbide. The isolation layer 6 can protect the sidewalls of the electrode material layer exposed after etching, thereby preventing short circuits between two adjacent electrode layers in the capacitor material layer 3.

[0138] In one exemplary embodiment of this disclosure, the method for forming this disclosure may further include steps S410-S430, wherein:

[0139] In step S410, the isolation layer 6 is etched to form a first contact hole 10 that exposes a portion of the surface of the first electrode layer 31.

[0140] like Figure 16 As shown, before etching the isolation layer 6, a dielectric layer 8 can be formed on the surface of the isolation layer 6. The dielectric layer 8 can cover the isolation layer 6 and fill the voids in the structure. The material of the dielectric layer 8 can be an insulating material, for example, silicon oxide or silicon nitride. The dielectric layer 8 and the isolation layer 6 covering the surface of the first electrode layer 31 can be etched on the side of the capacitor hole 11 away from the pad layer 2, thereby forming the first contact hole 10 exposing the first electrode layer 31.

[0141] In step S420, the remaining conductive layer 5 and the isolation layer 6 located on top of the conductive layer 5 are etched to form the second contact hole 20.

[0142] Please continue reading Figure 16As shown, in this disclosure, the second contact hole 20 can be a blind hole, and the bottom of the second contact hole 20 can be located within the conductive layer 5. In some embodiments of this disclosure, when forming the first contact hole 10 (i.e., performing step S410), the remaining conductive layer 5 and the isolation layer 6 located on the conductive layer 5 can be etched simultaneously to form the second contact hole 20. Thus, the first contact hole 10 and the second contact hole 20 can be formed simultaneously using the same photomask and etching process. In other embodiments of this disclosure, the second contact hole 20 can be formed after the first contact hole 10 is formed, so as to precisely control the opening depth of the first contact hole 10 and the second contact hole 20 respectively.

[0143] In step S430, a first lead 71 for leading out the first electrode layer 31 is formed in the first contact hole 10, and a second lead 72 for leading out the second electrode layer 33 is formed in the second contact hole 20.

[0144] like Figure 17 As shown, after forming the first contact hole 10 and the second contact hole 20, conductive materials can be filled into the first contact hole 10 and the second contact hole 20 respectively, thereby forming a first lead 71 in the first contact hole 10 and a second lead 72 in the second contact hole 20. It should be noted that when the capacitor material layer 3 only includes the first electrode layer 31, the first dielectric layer 32 and the second electrode layer 33, after performing step S140, the remaining capacitor material layer 3 can constitute a single-sided capacitor. The first electrode layer 31 can serve as the lower electrode layer of the single-sided capacitor, and the second electrode layer 33 can serve as the upper electrode layer of the single-sided capacitor. The lower electrode layer of the single-sided capacitor can be electrically led out through the first lead 71, and the upper electrode layer of the single-sided capacitor can be electrically led out through the second lead 72 and the conductive layer 5.

[0145] In an exemplary embodiment of this disclosure, when the capacitor material layer 3 further includes a second dielectric layer 34 and a third electrode layer 35, the formation method of this disclosure may further include steps S440 and S450, wherein:

[0146] In step S440, the remaining conductive layer 5, the remaining insulating layer 6, and part of the capacitor material layer 3 are etched on the side of the first contact hole 10 away from the second contact hole 20 to form a third contact hole 30 that exposes the third electrode layer 35.

[0147] like Figure 18As shown, when the capacitor material layer 3 includes a first electrode layer 31, a first dielectric layer 32, a second electrode layer 33, a second dielectric layer 34, and a third electrode layer 35, the remaining isolation layer 6, the remaining conductive layer 5, the remaining second electrode layer 33, the remaining first dielectric layer 32, the remaining first electrode layer 31, and the remaining second dielectric layer 34 can be etched on the side of the first contact hole 10 away from the second contact hole 20, thereby forming a third contact hole 30 that exposes the third electrode layer 35.

[0148] In some embodiments of this disclosure, the third contact hole 30 may be formed after the dielectric layer 8 is formed. For example, after the first contact hole 10 and the second contact hole 20 are formed, the remaining dielectric layer 8, the remaining insulating layer 6, the remaining conductive layer 5, the remaining second electrode layer 33, the remaining first dielectric layer 32, the remaining first electrode layer 31 and the remaining second dielectric layer 34 may be etched on the side of the first contact hole 10 away from the second contact hole 20, thereby forming the third contact hole 30 that exposes a portion of the surface of the third electrode layer 35.

[0149] It should be noted that when the capacitor material layer 3 includes the first electrode layer 31, the first dielectric layer 32, the second electrode layer 33, the second dielectric layer 34 and the third electrode layer 35, after step S140 is completed, the remaining capacitor material layer 3 can form a double-sided capacitor.

[0150] In step S450, a third lead 73 for leading out the third electrode layer 35 is formed in the third contact hole 30.

[0151] like Figure 19 As shown, conductive material can be filled into the third contact hole 30 to form a third lead 73, through which the third electrode layer 35 in the double-sided capacitor can be electrically led out.

[0152] In one exemplary embodiment of this disclosure, such as Figure 20 As shown, when the capacitor material layer 3 only includes the first electrode layer 31, the first dielectric layer 32, and the second electrode layer 33, the formation method of this disclosure further includes: forming a recess 12 in the substrate 1 when forming the capacitor hole 11 (i.e., after performing step S140); Figure 21 As shown, the capacitor material layer 3 formed subsequently can also cover the recessed portion 12 in a conformal manner; at the same time, the conductive layer 5 formed subsequently can also fill the recessed portion 12.

[0153] like Figure 22As shown, when etching the capacitor material layer 3 and at least part of the padding layer 2 located on the padding layer 2 (i.e., performing step S140), the conductive layer 5 located in the recess 12, the second electrode layer 33 located at the bottom of the recess 12 and the first dielectric layer 32 located at the bottom of the recess 12 are also etched to form a through hole 40 exposing the first electrode layer 31; the isolation layer 6 also conformally covers the through hole 40, and the first lead 71 is located in the through hole 40.

[0154] In one exemplary embodiment of this disclosure, such as Figure 23 As shown, the dielectric layer 8 subsequently formed on the isolation layer 6 can fill the via 40. The dielectric layer 8 and the isolation layer 6 on the bottom surface of the via 40 can be etched to form a first contact hole 10 exposing a portion of the surface of the first electrode layer 31. A first lead 71 is formed in the first contact hole 10, specifically as follows: Figure 24 As shown.

[0155] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0156] This disclosure also provides a semiconductor structure that can be formed by the semiconductor structure formation method of any of the above embodiments. The semiconductor structure includes a substrate 1, a pad layer 2, and a capacitor material layer 3, wherein:

[0157] Substrate 1 has a capacitor hole 11;

[0158] The padding layer 2 is located on one side of the capacitor hole 11;

[0159] The capacitor material layer 3 conformally covers the structure formed by the substrate 1, the padding layer 2 and the capacitor hole 11. The capacitor material layer 3 includes at least a first electrode layer 31, a second electrode layer 33 and a first dielectric layer 32 located between the first electrode layer 31 and the second electrode layer 33.

[0160] Compared with the prior art, the beneficial effects of the semiconductor structure provided in this disclosure are the same as the beneficial effects of the semiconductor structure formation method provided in the above example embodiments, and will not be repeated here.

[0161] The following provides a detailed description of the various parts of the semiconductor structure disclosed herein, along with their specific details:

[0162] Substrate 1 can be a silicon substrate. For example... Figure 2As shown, the substrate 1 has a capacitor hole 11. In a direction parallel to the surface of the substrate 1, the cross-sectional shape of the capacitor hole 11 can be circular, elliptical, rectangular, polygonal, or irregular. No particular limitation is made to the shape of the capacitor hole 11 here. The number of capacitor holes 11 can be one or more, without special limitation. It should be noted that when there are multiple capacitor holes 11, they can be spaced apart.

[0163] Please continue reading Figure 2 As shown, the padding layer 2 can be disposed on the substrate 1 and located on one side of the capacitor hole 11. The padding layer 2 can be a single-layer film structure or a composite film structure composed of multiple film layers, without special limitation. In an exemplary embodiment of this disclosure, the padding layer 2 may include a first padding layer 21, a second padding layer 22, and a third padding layer 23 sequentially stacked along a direction perpendicular to the substrate 1, wherein the first padding layer 21 is located on the surface of the substrate 1. The material of the padding layer 2 can be an insulating material, for example, silicon nitride or silicon carbide nitride. When the padding layer 2 is a composite film structure, some of the material in the padding layer 2 can also be a conductive material. When there are multiple capacitor holes 11, all capacitor holes 11 can be located on the same side of the padding layer 2.

[0164] like Figure 3 and Figure 4 As shown, the capacitor material layer 3 can conformally cover the structure formed by the substrate 1, the pad layer 2 and the capacitor hole 11. The capacitor material layer 3 may include at least a first electrode layer 31, a second electrode layer 33 and a first dielectric layer 32 located between the first electrode layer 31 and the second electrode layer 33.

[0165] In one exemplary embodiment of this disclosure, please continue to refer to Figure 3 and Figure 4 As shown, an insulating layer 4 may also be provided between the capacitor material layer 3 and the substrate 1. The insulating layer 4 can conformally cover the surface of the structure jointly formed by the substrate 1, the padding layer 2, and the capacitor via 11. The insulating layer 4 can isolate the substrate 1 and the capacitor material layer 3 to prevent the charge in the subsequently formed capacitor cell 50 from leaking into the substrate 1, thus helping to improve device reliability. The material of the insulating layer 4 can be an insulating material, such as silicon oxide or silicon nitride. The capacitor material layer 3 can be located on the insulating layer 4.

[0166] In one exemplary embodiment of this disclosure, please continue to refer to Figure 3As shown, the capacitor material layer 3 may consist only of a first electrode layer 31, a first dielectric layer 32, and a second electrode layer 33, wherein: the first electrode layer 31 conformally covers the insulating layer 4; the first dielectric layer 32 conformally covers the surface of the first electrode layer 31; and the second electrode layer 33 conformally covers the surface of the first dielectric layer 32. The materials of the first electrode layer 31 and the second electrode layer 33 can both be materials with high conductivity. For example, the materials of the first electrode layer 31 and the third electrode layer 35 can both be titanium nitride. The material of the first dielectric layer 32 can be a material with a high dielectric constant. For example, its material can be alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof. Of course, other materials can also be used, which will not be listed here.

[0167] In another exemplary embodiment of this disclosure, please continue to refer to Figure 4 As shown, the capacitor material layer 3 may include a first electrode layer 31, a first dielectric layer 32, a second electrode layer 33, a second dielectric layer 34, and a third electrode layer 35, wherein: the third electrode layer 35 conformally covers the surface of the insulating layer 4; the second dielectric layer 34 conformally covers the surface of the third electrode layer 35; the first electrode layer 31 conformally covers the surface of the second dielectric layer 34; the first dielectric layer 32 conformally covers the surface of the first electrode layer 31; and the second electrode layer 33 conformally covers the surface of the first dielectric layer 32. The materials of the first electrode layer 31, the second electrode layer 33, and the third electrode layer 35 may all be materials with strong conductivity. For example, the material of the third electrode layer 35 may be the same as the material of the first electrode layer 31 and / or the second electrode layer 33, for example, the material of the third electrode layer 35 may be titanium nitride.

[0168] In one exemplary embodiment of this disclosure, the material of the padding layer 2 may be the same as at least a portion of the material in the capacitor material layer 3. For example, when the padding layer 2 is a composite film structure, the material of some film layers in the padding layer 2 is the same as the material of the first electrode layer 31, the second electrode layer 33, or the third electrode layer 35, and the material of some film layers in the padding layer 2 is the same as the material of the first dielectric layer 32.

[0169] For example, when the padding layer 2 includes a first padding layer 21, a second padding layer 22 and a third padding layer 23, the first padding layer 21 is made of the same material as the insulating layer 4; the second padding layer 22 is made of the same material as the first electrode layer 31, the second electrode layer 33 or the third electrode layer 35; and the third padding layer 23 is made of the same material as the first dielectric layer 32 or the second dielectric layer 34.

[0170] In one exemplary embodiment of this disclosure, the thickness of the padding layer 2 may be greater than or equal to the thickness of the capacitor material layer 3. For example, the thickness of the capacitor material layer 3 may be 200 nm to 300 nm; for example, its thickness may be 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, or 300 nm. The thickness of the padding layer 2 may be 300 nm to 500 nm; for example, its thickness may be 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm. Of course, the thicknesses of the capacitor material layer 3 and the padding layer 2 may also be other values, which will not be listed here.

[0171] When there are multiple capacitor holes 11, the insulating layer 4 can conformally cover multiple capacitor holes 11. Simultaneously, the capacitor material layer 3 located on the insulating layer 4 can also conformally cover multiple capacitor holes 11. The capacitor material layer 3 within each capacitor hole 11 constitutes a capacitor unit 50, and adjacent capacitor units 50 are connected in series. Multiple capacitor units 50 can form a capacitor group 100, with the padding layer 2 formed on the side of the outermost capacitor unit 50 in the capacitor group 100 furthest from the center of the capacitor group 100. It should be noted that the number of capacitor units 50 in the capacitor group 100 can be from 1 to 8, for example, 1, 2, 4, 6, or 8. Of course, the number of capacitor units 50 in the capacitor group 100 can also be other than these, as long as it increases the storage capacity.

[0172] In some embodiments of this disclosure, there may be multiple capacitor groups 100, and adjacent capacitor groups 100 are independent of each other and spaced apart, so as to prevent adjacent capacitor groups 100 from failing due to short circuit.

[0173] It should be noted that when the capacitor material layer 3 only includes the first electrode layer 31, the first dielectric layer 32, and the second electrode layer 33, the capacitor formed by the capacitor material layer 3 is a single-sided capacitor, and the first electrode layer 31 can be used as the lower electrode layer of the single-sided capacitor, and the second electrode layer 33 can be used as the upper electrode layer of the single-sided capacitor. When the capacitor material layer 3 includes the first electrode layer 31, the first dielectric layer 32, the second electrode layer 33, the second dielectric layer 34, and the third electrode layer 35, the capacitor formed by the capacitor material layer 3 is a double-sided capacitor.

[0174] In one exemplary embodiment of this disclosure, such as Figure 17 As shown, when the capacitor material layer 3 only includes the first electrode layer 31, the first dielectric layer 32, and the second dielectric layer 34, the semiconductor structure of this disclosure may further include a conductive layer 5, a first lead 71, and a second lead 72, wherein:

[0175] A conductive layer 5 is located on the surface of the capacitor material layer 3, and fills the capacitor hole 11. That is, the conductive layer 5 can contact and connect with the second electrode layer 33 in the capacitor material layer 3. The material of the conductive layer 5 can be doped polycrystalline silicon, and the second electrode layer 33 can be electrically led out through the conductive layer 5. A first contact hole 10 is located on the side of the capacitor hole 11 away from the padding layer 2, exposing a portion of the surface of the first electrode layer 31. A first lead 71 can be located on the side of the capacitor hole 11 away from the padding layer 2 and contact and connect with the first electrode layer 31, allowing the first electrode layer 31 to be electrically led out through the first lead 71. For example, the first lead 71 can be located within the first contact hole 10. A second lead 72 can be at least partially embedded in the conductive layer 5 and contact and connect with the second conductive layer 5, allowing the second electrode layer 33 to be electrically led out through the second lead 72 and the conductive layer 5.

[0176] In one exemplary embodiment of this disclosure, such as Figure 19 As shown, when the capacitor material layer 3 includes a first electrode layer 31, a first dielectric layer 32, a second electrode layer 33, a second dielectric layer 34, and a third electrode layer 35, the semiconductor structure disclosed herein may include a conductive layer 5, a first lead 71, a second lead 72, and a third lead 73. The specific details and connection relationships of the conductive layer 5, the first lead 71, and the second lead 72 are the same as in the above embodiments, and will not be repeated here. The third lead 73 is located on the side of the first lead 71 away from the second lead 72 and is in contact with the third electrode layer 35, allowing the third electrode layer 35 to be electrically led out through the third lead 73.

[0177] In one exemplary embodiment of this disclosure, the semiconductor structure may further include an isolation layer 6. The isolation layer 6 can conformally cover the surface of the capacitor material layer 3, the pad layer 2, the conductive layer 5, and the first electrode layer 31 exposed on the side of the capacitor hole 11 away from the pad layer 2. The isolation layer 6 can protect the sidewalls of each exposed electrode layer in the capacitor material layer 3 to prevent short circuits between two adjacent electrode layers in the capacitor material layer 3. The first contact hole 10 for forming the first lead 71 can penetrate the isolation layer 6, thereby exposing a portion of the surface of the first electrode layer 31.

[0178] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A pad layer is formed on the substrate; A capacitor hole is formed in the substrate, and the capacitor hole is located on one side of the pad layer; A capacitor material layer is formed on the structure jointly formed by the substrate and the pad layer, wherein the capacitor material layer includes at least a first electrode layer, a second electrode layer and a first dielectric layer located between the first electrode layer and the second electrode layer; The capacitor material layer located on the pad layer and at least a portion of the pad layer are etched to cut off the capacitor material layer located on the pad layer; Before forming the capacitor material layer on the structure formed by the conformal covering of the substrate and the padding layer, the forming method further includes: An insulating layer is formed on the structure formed by the substrate and the padding layer.

2. The forming method according to claim 1, characterized in that, The material of the padding layer is an insulating material; or, the material of the padding layer is the same as at least a portion of the material in the capacitor material layer.

3. The forming method according to claim 1, characterized in that, The thickness of the padding layer is greater than or equal to the thickness of the capacitor material layer.

4. The forming method according to claim 1, characterized in that, The padding layer includes a first padding layer, a second padding layer, and a third padding layer stacked sequentially along a direction perpendicular to the substrate. The first padding layer is located on the surface of the substrate. The formation of a capacitor material layer that conformally covers the structure jointly formed by the substrate and the padding layer includes: A first electrode layer is formed that conformally covers the insulating layer; A first dielectric layer is formed that conformally covers the surface of the first electrode layer; A second electrode layer is formed that conformally covers the surface of the first dielectric layer; The first pad layer is made of the same material as the insulating layer; the second pad layer is made of the same material as the first electrode layer and / or the second electrode layer; and the third pad layer is made of the same material as the first dielectric layer.

5. The forming method according to claim 4, characterized in that, After forming the capacitor material layer, the forming method further includes: A conductive layer is formed on the surface of the capacitor material layer, and the conductive layer fills the capacitor hole; when etching the capacitor material layer located on the pad layer and at least a portion of the pad layer, the conductive layer located directly above the pad layer is also etched.

6. The forming method according to claim 5, characterized in that, The forming method further includes: A portion of the film layer in the capacitor material layer located on the side of the capacitor hole away from the pad layer and the conductive layer located on the side of the capacitor hole away from the pad layer are etched to expose a portion of the surface of the first electrode layer. An isolation layer is formed to cover the surface of the structure consisting of the substrate, the remaining conductive layer, the remaining padding layer, and the remaining capacitor material layer.

7. The forming method according to claim 6, characterized in that, The forming method further includes: The isolation layer is etched to form a first contact hole that exposes a portion of the surface of the first electrode layer; The remaining conductive layer and the isolation layer located on top of the conductive layer are etched to form a second contact hole; A first lead for leading out the first electrode layer is formed in the first contact hole, and a second lead for leading out the second electrode layer is formed in the second contact hole.

8. The forming method according to claim 7, characterized in that, The capacitor material layer formed on the structure that conformally covers the substrate and the padding layer also includes: Before forming the first electrode layer, a third electrode layer is formed that conformally covers the surface of the insulating layer; A second dielectric layer is formed to conformally cover the surface of the third electrode layer, wherein the first electrode layer conformally covers the surface of the second dielectric layer.

9. The forming method according to claim 8, characterized in that, The forming method further includes: The remaining conductive layer, the remaining insulating layer, and a portion of the capacitor material layer are etched on the side of the first contact hole away from the second contact hole to form a third contact hole exposing the third electrode layer. A third lead is formed within the third contact hole to bring out the third electrode layer.

10. The forming method according to claim 7, characterized in that, The forming method further includes: When forming the capacitor hole, a recess is formed in the substrate; the capacitor material layer also conformally covers the recess; the conductive layer also fills the recess. When etching the capacitor material layer and at least a portion of the padding layer located on the padding layer, the conductive layer located in the recess, the second electrode layer located at the bottom of the recess, and the first dielectric layer located at the bottom of the recess are also etched to form a via exposing the first electrode layer; the insulating layer also conformally covers the via, and the first lead is located inside the via.

11. The forming method according to any one of claims 1-10, characterized in that, The number of capacitor holes is multiple, and the capacitor material layer covers the multiple capacitor holes in a conformal manner; the capacitor material layer in each capacitor hole constitutes a capacitor unit, and adjacent capacitor units are connected in series; multiple capacitor units form a capacitor group, and the padding layer is formed on the side of the capacitor unit located at the outermost edge of the capacitor group away from the center of the capacitor group.

12. A semiconductor structure, characterized in that, include: Substrate, the substrate having capacitor holes; The padding layer is located on one side of the capacitor hole; A capacitor material layer conformally covers the structure formed by the substrate, the padding layer and the capacitor hole, and the capacitor material layer includes at least a first electrode layer, a second electrode layer and a first dielectric layer located between the first electrode layer and the second electrode layer. An insulating layer conformally covers the structure formed by the substrate, the padding layer, and the capacitor aperture; the capacitor material layer is located on the insulating layer.

13. The semiconductor structure according to claim 12, characterized in that, The first electrode layer conformally covers the insulating layer; the first dielectric layer conformally covers the surface of the first electrode layer; the second electrode layer conformally covers the surface of the first dielectric layer. Alternatively, the capacitor material layer may further include a second dielectric layer and a third electrode layer, wherein the third electrode layer conformally covers the surface of the insulating layer; The second dielectric layer conformally covers the surface of the third electrode layer; the first electrode layer conformally covers the surface of the second dielectric layer; the first dielectric layer conformally covers the surface of the first electrode layer; the second electrode layer conformally covers the surface of the first dielectric layer.

14. The semiconductor structure according to claim 13, characterized in that, The semiconductor structure also includes: A conductive layer is located on the surface of the capacitor material layer, and the conductive layer fills the capacitor holes; The first lead is located on the side of the capacitor hole away from the pad layer and is in contact with the first electrode layer to electrically lead out the first electrode layer; The second lead is at least partially embedded in the conductive layer to electrically lead out the second electrode layer; The third lead is located on the side of the first lead away from the second lead and is in contact with the third electrode layer to electrically lead out the third electrode layer.

15. The semiconductor structure according to any one of claims 12-14, characterized in that, The number of capacitor holes is multiple, and the capacitor material layer covers the multiple capacitor holes in a conformal manner; the capacitor material layer in each capacitor hole constitutes a capacitor unit, and adjacent capacitor units are connected in series; multiple capacitor holes form a capacitor group, and the padding layer is formed on the side of the capacitor unit located at the outermost edge of the capacitor group away from the center of the capacitor group.

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