A bonding apparatus and a bonding method for a semiconductor wafer

Abstract

The present application improves the bonding strength between wafers in a semiconductor manufacturing process by a simple structure. The present application provides a vacuum cavity 14 for bonding semiconductor wafers W1, W2 to each other. Before bonding the wafers W1, W2 opposite to each other, one uses a silicon electrode G1 and the other uses a semiconductor wafer W2. After a first treatment of the silicon electrode G1 and the semiconductor wafer W2, the silicon electrode G1 is replaced by a bonding wafer G2, and a second treatment of the bonding wafer G2 and the semiconductor wafer W2 is performed. Subsequently, the pair of wafers W1, W2 opposite to each other are bonded together by electrostatic force in a vacuum environment.

Description

Technical Field

[0001] This invention relates to a bonding process for semiconductor wafers, such as a bonding apparatus and method for bonding semiconductor wafers to each other by high-frequency ion-activated bonding (RFIon Flow Bonding, (RFIFB)). Background Technology

[0002] Hybrid bonding is part of a traditional semiconductor manufacturing process, which may include plasma processing, cleaning, drying and bonding processes.

[0003] In plasma processing, for example, atmospheric pressure plasma or vacuum plasma is applied to the semiconductor wafer to activate its surface. In the cleaning process, for example, the semiconductor wafer is rotated around a central axis while a cleaning solution (pure water or chemical solution) is dripped onto its surface to clean it. In the drying process, for example, the semiconductor wafer is rotated at high speed around a central axis while water droplets on its surface are dispersed. In the bonding process, for example, two semiconductor wafers that have undergone the plasma processing and drying processes are bonded together face-to-face using a bonding device.

[0004] Here, in conventional bonding apparatus, semiconductor wafers are mounted on a planar stage arranged opposite each other, and a pair of opposite semiconductor wafers are bonded together using a room temperature surface-activated bonding (SAB) method.

[0005] Surface activated bonding refers to the ionization of inert gases such as argon to form an ion beam. By irradiating the surface of the materials to be bonded with the ion beam and plasma, the oxide film and contaminant layer on the surface of the bonding materials are removed, thereby activating the surface and enabling bonding at low temperature or room temperature.

[0006] However, in the SAB method, the surface of the wafer material is roughened due to the high-energy ion beam bombardment to facilitate oxide film removal, which reduces the bonding strength between semiconductor wafers. Point irradiation by the Ar ion beam can generate particles on the surface as the wafer or beam moves, leading to voids and other problems, and causing voids and bubbles in the bonding interlayer.

[0007] Citing patent literature

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2018-201022 Invention Summary

[0009] The problem the invention aims to solve

[0010] Therefore, in view of the above-mentioned problems, the present invention aims to provide a bonding apparatus and bonding method for semiconductor wafers that can improve the bonding strength between wafers in the semiconductor manufacturing process through a simple configuration.

[0011] Problem-solving methods

[0012] This invention relates to a bonding apparatus and method for bonding semiconductor wafers. The semiconductor wafers are subjected to plasma treatment to activate their surface, followed by a period of time under high vacuum. Ion polarization is applied to the surface of the semiconductor wafers, and by applying a high-frequency power supply, the ions move on the surface of the semiconductor wafers, thereby increasing the bonding strength between the semiconductor wafers.

[0013] The predetermined time is preferably 1 to 30 seconds.

[0014] The predetermined time is further preferably 1 to 10 seconds.

[0015] Invention Effects

[0016] According to the present invention, the bonding strength between semiconductor wafers in the semiconductor manufacturing process can be improved through a simple configuration. Attached Figure Description

[0017] Figure 1 This is a structural diagram of a semiconductor wafer bonding apparatus according to one embodiment of the present invention.

[0018] Figure 2 This is a structural diagram of the plasma processing and bonding process of a semiconductor wafer in a semiconductor wafer bonding apparatus according to an embodiment of the present invention.

[0019] Figure 3 This is a process diagram of a semiconductor wafer bonding apparatus according to an embodiment of the present invention performing plasma processing and bonding processing on a semiconductor wafer.

[0020] Figure 4 This is a flowchart of an example of high-frequency ion flow bonding treatment.

[0021] Figure 5 This is a plan view of a semiconductor manufacturing system equipped with a semiconductor wafer bonding apparatus according to an embodiment of the present invention.

[0022] Figure 6 This is a side view of a semiconductor manufacturing system equipped with a semiconductor wafer bonding apparatus according to an embodiment of the present invention.

[0023] Figure 7 This is a structural diagram showing the structure of a unipolar electrostatic chuck.

[0024] Figure 8 This is a structural diagram showing the structure of a bipolar electrostatic chuck.

[0025] Figure 9 This is a structural diagram showing the state of a semiconductor wafer being bonded by a bipolar electrostatic chuck disposed on a stage constituting a semiconductor wafer bonding apparatus. Detailed Implementation

[0026] First, a bonding apparatus and bonding method for a semiconductor wafer according to one embodiment of the present invention will be described.

[0027] One embodiment of the semiconductor wafer bonding apparatus and bonding method of the present invention uses a plasma chamber or a vacuum chamber to perform bonding between semiconductor wafers. In other words, the plasma chamber or vacuum chamber may be referred to as a bonding chamber, bonding apparatus, bonding device, etc.

[0028] [Technical Concept of the Invention]

[0029] The technical concept of this invention is to perform plasma treatment on wafers inside a vacuum chamber, and in a vacuum environment, Coulomb force (also known as "electrostatic force") is used to improve the bonding strength between a pair of opposing wafers in a semiconductor wafer bonding device.

[0030] The vacuum chamber has a pair of wafer holding mechanisms positioned opposite each other on a stage. By moving at least one of the wafer holding mechanisms while the wafer is being held in place, the wafer holding mechanisms are positioned opposite each other and bonded together.

[0031] Here, before bonding the wafers that are opposite each other, it is known that one of the wafers uses a silicon electrode and the other uses a semiconductor wafer. After performing a first plasma treatment on the silicon electrode and the other semiconductor wafer, the silicon electrode is changed to a bonding wafer. Preferably, a second plasma treatment is performed on the bonding wafer and the semiconductor wafer.

[0032] Between the first plasma treatment and the second plasma treatment, an etching gas can be provided to remove the oxide film formed on the opposing semiconductor wafer surfaces.

[0033] The technical concept of the present invention is not limited to bonding apparatus for semiconductor wafers, but also applicable to bonding methods for semiconductor wafers having the same features as described above.

[0034] [Structure of a semiconductor wafer bonding device]

[0035] like Figure 1As shown, the semiconductor wafer bonding apparatus 34 of this embodiment bonds various wafers. Furthermore, the semiconductor wafer and the bonding wafer can be, for example, silicon wafers, but are not limited to silicon wafers. Semiconductor wafers of different materials used conventionally can be used, and semiconductor wafers of different materials can be bonded.

[0036] like Figure 1 As shown, the semiconductor wafer bonding apparatus 34 has a chamber 14 serving as a housing, a first stage 36 located on the upper side inside the chamber, and a second stage 38 located on the lower side inside the chamber. The first stage 36 is provided with a first wafer holding mechanism 102, which is capable of holding a semiconductor wafer or an electrode (e.g., a silicon electrode). The second stage 38 is provided with a second wafer holding mechanism 104, which is also capable of holding a semiconductor wafer or an electrode (e.g., a silicon electrode).

[0037] Alternatively, the chamber 14 or bonding device 34, which serves as the housing, can also be referred to as a "vacuum chamber".

[0038] Here, the first stage 36 and the second stage 38, or the first wafer holding mechanism 102 and the second wafer holding mechanism 104, are, for example, electrostatic chucks or mechanical clamps. It should be noted that electrostatic chucks, for example, can be used... Figures 7 to 9 The electrostatic chucks 78 and 80 are shown. Figures 7-9 The structure of the electrostatic chucks 78 and 80 will be described later.

[0039] In addition, such as Figure 2 As shown, a first replacement device 106 is provided on or near the first stage 36 on the upstream side of the direction of gravity to replace the first wafer fixing mechanism 102 and the semiconductor wafer W1 or silicon electrode G1 held by the first wafer fixing mechanism 102 with semiconductor wafers or silicon electrodes held by other wafer fixing mechanisms. It should be noted that although it is ideal to replace the silicon electrode G1 and the semiconductor wafer W1 in groups, with the silicon electrode G1 and the first wafer fixing mechanism 102 holding the silicon electrode G1 as one group and the semiconductor wafer W1 and the first wafer fixing mechanism 102 holding the semiconductor wafer W1 as another group, this method is not limited to this approach.

[0040] Silicon electrode G1 is known, and is also referred to as virtual wafer or carrier wafer, for example.

[0041] The semiconductor wafer W1 held by the first wafer fixing mechanism 102 includes, for example, a silicon wafer electrode G1 and a bonding wafer G2.

[0042] The first replacement device 106 is not limited to the configuration provided on the side of the first stage 36, but may also be provided as other configurations of the bonding device 34 or provided outside the bonding device 34.

[0043] Additionally, a second replacement device 108 may be configured at or near the second stage 38 on the downstream side of the direction of gravity to replace the second wafer fixing mechanism 38 and the semiconductor wafer W2 or silicon electrode held by the second wafer fixing mechanism 38 with semiconductor wafer W2 or silicon electrodes held by other wafer fixing mechanisms. Furthermore, the exchange process of silicon electrodes (not shown) and semiconductor wafer W2 retains silicon electrodes (not shown). Preferably, the exchange is performed group by group, with the second wafer fixing mechanism 104 configured as a group and the semiconductor wafer W2 and the second wafer fixing mechanism 104 holding the semiconductor wafer W2 configured as a group, but this is not a limitation.

[0044] The second replacement device 108 is not limited to a configuration located on the side of the second stage 38, but can also be used as other configurations of the bonding device 34 or located outside the bonding device 34.

[0045] In addition, the first replacement device 106 or the second replacement device 108 is preferably configured with at least one of the following structures.

[0046] Here, the first replacement device 106 and the second replacement device 108 may be replaced by, for example, a robotic arm, but are not limited thereto.

[0047] Semiconductor wafers W1 held by the first wafer fixing mechanism 102 and semiconductor wafers W2 held by the second wafer fixing mechanism 104 can be, for example, Si wafers or SiC wafers, but are not limited thereto.

[0048] like Figure 1 As shown, the high-frequency power supply 110 is connected to the first stage 36 and the second stage 38, respectively. The high-frequency power supply 110 has the capability to generate a high-frequency electric field (13.56 MHz, 200 W). By applying the high-frequency power supply 110, the electric field promotes the flow and diffusion of atoms, thereby improving the bonding tightness of the bonding surfaces of the semiconductor wafers W1 and W2.

[0049] The semiconductor wafer bonding apparatus 34 includes an automatic pressure controller 112 (APC) capable of controlling the pressure inside the housing. The automatic pressure controller 112 controls the pressure inside the housing.

[0050] The semiconductor wafer bonding device 34 is equipped with a turbomolecular pump 114 (TMP). The turbomolecular pump 114, for example, consists of a rotor (moving blades) and a stator (stationary blades) with turbine-type blades.

[0051] The turbomolecular pump 114 is a 1×10 -6 High-performance pump with fast exhaust speed in high vacuum environments.

[0052] [Effect of semiconductor wafer bonding devices]

[0053] The bonding between the individual wafers has become stronger.

[0054] When bonding semiconductor wafers requiring different plasma processing times, the semiconductor wafer requiring a short plasma processing time can be used as the bonding wafer and replaced with the silicon electrode, thus shortening the plasma processing time. This allows for short-time plasma processing of the bonding wafers. As a result, the surface of the bonding wafers does not deteriorate due to prolonged plasma processing, preventing quality degradation of the semiconductor products (semiconductor devices, etc.) formed by bonding individual wafers.

[0055] [Execution of the first plasma treatment]

[0056] like Figure 1 and Figure 2 As shown, the semiconductor wafer bonding apparatus 34 has a parallel planar electrode structure. The interior of the housing is in a vacuum. A silicon electrode G1 (e.g., also called a "silicon wafer electrode") is sputtered using a first wafer holding mechanism 102, and a first plasma treatment based on argon plasma is performed while the semiconductor wafer W2 (e.g., a silicon wafer) is held in a second wafer holding mechanism 104. Thus, argon plasma is used inside the vacuum chamber 14 to sputter silicon to create the silicon electrode G1, and the surface of the semiconductor wafer W2 held by the second wafer holding mechanism 104 is activated by the plasma, forming a silicon-based vapor-deposited film X on the surface of the semiconductor wafer W2. Furthermore, when activating the surface of the semiconductor wafer W2 with plasma, gases such as argon (Ar) or nitrogen (N2) are used to remove oxide films and contaminants from the surface of the semiconductor wafer W2, respectively. The same effect is achieved when activating the surface of the semiconductor wafer W2 in the second plasma treatment.

[0057] Here, because a high-frequency power supply 110 is used, the energy is low, which can reduce plasma damage to the surface of the semiconductor wafer W2. In addition, a thin vapor-deposited film X is formed on the semiconductor wafer W2 by sputtering the plasma electrode G1, which serves as the silicon wafer electrode.

[0058] Isotropic etching

[0059] Additionally, between the first plasma treatment and the second plasma treatment described below, an isotropic etching process can be performed to remove the oxide film formed on the surface of the semiconductor wafer W2 by supplying an etching gas such as SF6. After the isotropic etching process, the plasma gas is switched to argon (gas replacement), and the wafer surface is activated in the second plasma treatment.

[0060] [Execution of the second plasma treatment]

[0061] Next, the silicon electrode G1 is replaced with a bonding wafer G2, i.e., a semiconductor wafer W1. For example, a silicon wafer or other semiconductor wafer, but not limited to silicon. The replacement process of the silicon electrode G1 and the bonding wafer W1 can be performed, for example, by replacing the silicon electrode G1 and the first wafer holding mechanism 102 holding the silicon electrode G1 as one set of components with another set of components consisting of the bonding wafer G2 and the first wafer holding mechanism 102 holding the bonding wafer G2. Alternatively, the first wafer holding mechanism 102 can remain unchanged and be used together, separating the silicon electrode G1 from the first wafer holding mechanism 102 while holding the bonding wafer G2. During and after the replacement process, plasma treatment is performed using gases such as argon (Ar) or nitrogen (N2) to activate the surfaces of the bonding wafer G2 held by the first wafer holding mechanism 102 and the semiconductor wafer W2 held by the second wafer holding mechanism 104. The oxide films and contaminants on the surfaces of the bonding wafer G2 held by the first wafer holding mechanism 102 and the semiconductor wafer W2 held by the second wafer holding mechanism 104 are removed respectively. Then, under the continuous application of the high-frequency power supply 110, the supply of gases such as argon (Ar) or nitrogen (N2) is stopped, and the automatic pressure control device 112 is driven at high output to bring the vacuum level inside the chamber 14 to the target vacuum level (e.g., 1×10⁻⁶) within approximately 10 seconds. -6 At this time, the plasma disappears, but the surfaces of the bonding wafer G2 held by the first wafer fixing mechanism 102 and the semiconductor wafer W2 held by the second wafer fixing mechanism 104 are respectively in an ion-polarized state.

[0062] The time required to reach the vacuum level inside chamber 14 is not limited to approximately 10 seconds; for example, it can be set to a range of 1 to 30 seconds, more preferably to a range of 1 to 15 seconds, and even more preferably to a range of 1 to 10 seconds. The faster the vacuum level required to be reached inside chamber 14, the better.

[0063] [Execution of wafer bonding process]

[0064] In this state, for example, Figure 3As shown, by moving the first stage 36 and / or the second stage 38 closer together, the distance between the mating wafer G2 held in the first wafer fixing mechanism 102 and the semiconductor wafer W2 held in the second wafer fixing mechanism 104 is reduced, and a Coulomb force (electrostatic force) is generated on the surfaces of both, bringing the interatomic distance between the wafers closer and eventually leading to contact. At this time, the first stage 36 can be fixed to move the second stage 38 closer to the side of the first stage 36. Alternatively, the second stage 38 can be fixed to move in a manner that brings the first stage 36 closer to the side of the second stage 38. The initial bonding force between the bonding wafer G2 held in the first wafer fixing mechanism 102 and the semiconductor wafer W2 held in the second wafer fixing mechanism 104 is enhanced. However, after the wafers G2 and W2, which are opposite each other, come into contact with each other, a high-frequency power supply 110 continues to be applied, so that the RF high frequency flows between the surfaces of wafers G2 and W2 respectively, and ion flow (atomic diffusion) is generated under the action of electric field, making the bonding between the two more solid.

[0065] The semiconductor wafer manufacturing method of this embodiment is an industry-first manufacturing method, called high-frequency ion flow activated bonding (RF Ion Flow Bonding, RFIFB).

[0066] In addition, for the bonding wafer G2 held by the first wafer fixing mechanism 102, the plasma processing is performed only once, while for the semiconductor wafer W2 held by the second wafer fixing mechanism 104, the plasma processing is performed twice.

[0067] Furthermore, instead of the first wafer fixing mechanism 102 and the silicon electrode G1 held by the first wafer fixing mechanism 102, a bonding wafer G2 held by the second wafer fixing mechanism 104 is preferred after being replaced by another first wafer fixing mechanism 102 and a bonding wafer G2 held by the second wafer fixing mechanism 104. However, this is not a limitation. Additionally, it is preferable that the first wafer fixing mechanism 102 is located upstream (upper) in the direction of gravity, and the second wafer fixing mechanism 104 is located downstream (lower) in the direction of gravity.

[0068] On the other hand, existing technologies include atomic diffusion bonding (ADB). ADB is a technique known as room-temperature active bonding, which activates the surface of semiconductor wafers by using an Ar beam or by Si sputtering. However, regardless of the method, bonding the activated semiconductor wafers together takes several minutes.

[0069] Generally, the active state of a semiconductor wafer surface deteriorates in a short period of time, so it is necessary to quickly evacuate the vacuum and perform bonding.

[0070] Therefore, according to this embodiment, after the wafer surface is activated by plasma treatment, a vacuum is applied by a turbomolecular pump 114 for approximately 10 seconds until pressure is reached, and the individual wafers are bonded together. Atom diffusion bonding, where the surface activity degradation after wafer surface activation is reduced to a limit, becomes possible.

[0071] In other words, this embodiment provides a parallel planar plasma electrode in the vertical direction, utilizing a structure that can hold the wafer on the upper and lower electrodes (e.g., an electrostatic chuck, a mechanical clamp, etc.), wherein one electrode is designed to be replaceable with the bonded wafer.

[0072] According to this embodiment, sputtering of the silicon target G1 causes surface roughness of the electrode, resulting in the formation of microparticles within the parallel planar wafer plasma, thus creating voids. Furthermore, the silicon grown from secondary sputtering detaches from the surface of the silicon target G1. These detached silicon particles continue to undergo Brownian motion and remain suspended, contributing to the formation of wafer void defects. However, in this embodiment, since the silicon target G1 (e.g., a bare silicon wafer) is used instead of the bonding wafer G2 in the initial stage, the damage to the bonding wafer G2 caused by voids can be reduced. Therefore, this method avoids quality degradation and deterioration of the semiconductor product obtained through bonding the bonding wafer G2 to the semiconductor wafer W2. Additionally, the silicon target G1 is preferably replaced periodically, once or multiple times.

[0073] As described above, by surface activation of the wafers used on one or both sides of the parallel plate and by soft sputtering by applying a high-frequency power supply 110 to the silicon target G1, an extremely thin vapor-deposited film X of high purity Si is generated on the processed surface of the semiconductor wafer W2 opposite to the silicon target G1.

[0074] In a plasma environment, the surface of the semiconductor wafer W2 is bombarded by ions, thus exposing a clean surface. After the surface of the semiconductor wafer W2 is cleaned, a high-frequency power supply 110 of different frequencies is applied to the silicon target G1 (e.g., a silicon wafer) located at the upper part (upper side). As a result, tiny Si particles fly out from the silicon target G1 and accumulate on the surface of the semiconductor wafer W2 located at the lower part (lower side), forming a thin film, namely the vapor-deposited film X, which is formed by vapor deposition.

[0075] Alternatively, this step can be omitted if a thin film evaporation is not required.

[0076] Next, in the bonding of the bonding wafer G2 and the semiconductor wafer W2, with G2 positioned as, for example, the upper electrode, the surface of the bonding wafer G2 is activated using a gas such as argon (Ar) or nitrogen (N2). At this time, the surface of the semiconductor wafer W2, which is disposed at the lower position, is also activated. Therefore, the surface activation of the bonding wafer G2 is performed only once, and the surface activation of the semiconductor wafer W2 is performed only twice.

[0077] Inside chamber 14, which serves as a shell, pressure is applied between opposing electrodes to generate plasma, and pressure is maintained at the highest possible vacuum level, thereby producing two wafers. The surfaces of each wafer (bonding wafer G2 and semiconductor wafer W2) are activated. As an electrode structure, magnetrons, ICP coils, etc., can also be added to maintain the plasma in a high vacuum.

[0078] Furthermore, after plasma surface activation, the spacing between the bonding wafer G2 disposed on the upper side and the semiconductor wafer W2 disposed on the lower side should be as narrow as possible. Similarly, the spacing between the silicon target G1 disposed on the upper side and the semiconductor wafer W2 disposed on the lower side should also be as narrow as possible. For example, during plasma processing, this spacing should be the smallest possible between electrodes capable of uniformly applying plasma, and after processing, when changing the pressure to a high vacuum, it can be in the range of 10 μm to 50 μm. This is because by reducing the spacing, external particles are less likely to intrude between the electrodes, preventing particle contamination during the wafer bonding process, and shortening the time from reaching a vacuum state to bonding.

[0079] After activating each surface of the bonded wafer G2 and the semiconductor wafer W2 through plasma treatment, the supply of gas such as argon (Ar) or nitrogen (N2) is stopped, and the automatic pressure controller 112 is driven to control the vacuum pressure reached by the turbomolecular pump 114 (or cryogenic pump), for example, within approximately 100 seconds. At this time, a high-frequency power supply 110 continues to be applied, but is not limited thereto.

[0080] Thus, polarized ions (electrons) remain on the surfaces of the bonding wafer G2 and the semiconductor wafer W2, respectively. During the bonding of the bonding wafer G2 and the semiconductor wafer W2 in a high vacuum, the increased atomic motion due to the charged ion potentials on the surfaces of the bonding wafer G2 and the semiconductor wafer W2 makes it easier for atoms to temporarily move on their respective surfaces. Furthermore, applying a high-frequency power supply 110 after bonding the bonding wafer G2 and the semiconductor wafer W2 further increases atomic motion, making it easier for atoms to temporarily move on their respective surfaces. Through these synergistic effects, atoms are reconfigured to a more stable energy state. Especially when the surfaces of the bonding wafer G2 and the semiconductor wafer W2 are activated, atoms are more easily reconfigured to more ideal positions. As a result, the energy on the surfaces of the bonding wafer G2 and the semiconductor wafer W2 is minimized, and the bonding strength between the bonding wafer G2 and the semiconductor wafer W2 is improved.

[0081] Here, generally speaking, the time from the plasma treatment of the semiconductor wafer to the bonding between the semiconductor wafers is the time it takes for the semiconductor wafer to move from the plasma treatment chamber to the bonding chamber. This transition time, added to the plasma treatment time and transport time for the second semiconductor wafer, results in a waiting period of several minutes. During this period, the surface activity of the semiconductor wafer deteriorates by approximately 10% to 50% immediately after the plasma treatment (attenuation rate 10% to 50%).

[0082] In contrast, in this embodiment, since instantaneous bonding is performed immediately after plasma treatment of the bonding wafer G2 and the semiconductor wafer W2, the bonding wafer G2 and the semiconductor wafer W2 are bonded while the activation state on the respective surfaces of the bonding wafer G2 and the semiconductor wafer W2 maintains a decay rate of less than 1%. As a result, the bonding between the bonding wafer G2 and the semiconductor wafer W2 becomes strong.

[0083] [No void bonding]

[0084] Most voids are caused by silicon sputtering debris and particles within the cavity. Frequent replacement of the silicon target G1 eliminates sputtering debris and particles, thereby reducing voids. Furthermore, in vacuum plasma, organic matter that serves as a seed for intrusive voids between the bonding wafer G2 and the semiconductor wafer W2 is removed. Moreover, the plasma prevents organic matter from intruding between the wafers from the outside. Through these measures, void-free bonding is achieved.

[0085] [Characteristics of high-frequency ion flow-activated bonding]

[0086] High-frequency ion flow activated bonding has the following characteristics.

[0087] (1) The surface activation and cleaning of wafers can be achieved through plasma treatment and instantaneous vacuum management and control.

[0088] (2) Coulomb force (electrostatic force) can be used to strengthen the initial bonding force between wafers.

[0089] (3) Promote the flow and diffusion of atoms through high-frequency power supply (RF high frequency) to improve the bonding strength between wafers.

[0090] [Flowchart of High-Frequency Ion Flow Activation Bonding Treatment]

[0091] An example of a process for high-frequency ion flow activation bonding treatment is described.

[0092] like Figure 4 As shown, for example, a wafer is removed from the wafer cassette (S100) and wafer alignment is performed (S200). A wafer cleaning process is performed (S300), and the wafer is transported to a load-locking chamber (S400). The wafer undergoes plasma treatment (S500) and is then bonded (S600). Finally, the semiconductor product formed between the bonded wafers is removed from the load-locking chamber (S700), and the semiconductor product is inspected (S800).

[0093] Here, the time required from the end of the plasma processing step (S500) of the wafer to the end of the bonding step (S600) is preferably 10 seconds or less.

[0094] As described above, for example, by using the Coulomb force control of the ESC chuck to assist bonding, deviations can be prevented when opposite wafers are in contact, and high frequencies can be generated. High-strength bonding can be achieved through high-frequency ion flow activated bonding technology.

[0095] (Example)

[0096] Next, examples of high-frequency ion flow-activated bonding will be described.

[0097] [Overview]

[0098] (1) A parallel plate electrode structure is adopted, and two silicon wafers are arranged in a vacuum.

[0099] (2) Use a replaceable silicon wafer electrode on one side and activate the surface of the silicon wafer electrode with argon plasma.

[0100] (3) Silicon sputtered from the silicon wafer electrode surface is deposited onto the semiconductor wafer surface opposite the silicon wafer electrode by sputtering vapor deposition.

[0101] [project]

[0102] (1) Surface activation of silicon wafer electrodes

[0103] Silicon is sputtered from the silicon wafer electrode by activating the surfaces of the silicon wafer electrode and the semiconductor wafer opposite the silicon wafer electrode through plasma treatment (first time) using argon plasma.

[0104] The silicon wafer is a bonding wafer where the electrodes are replaced with bonding targets.

[0105] Argon plasma treatment (second time) is performed on the bonded wafers and semiconductor wafers. After the gas supply is stopped, a vacuum level is achieved, for example, within about 10 seconds, using a turbomolecular pump or the like.

[0106] Although the plasma disappears due to vacuum stretching, the ions remain in a polarized state on each surface of the bonded wafers and semiconductor wafers that are facing each other.

[0107] (2) Bonding between wafers

[0108] Ions trapped on the surfaces of bonding wafers and semiconductor wafers due to polarization generate Coulomb forces (electrostatic forces), reducing the interatomic spacing between wafers and bringing them into contact. RF high-frequency current flows across the surface of each wafer, and the electric field induces ion flow (atomic diffusion), resulting in strong bonding between the wafers.

[0109] [Specific Structure]

[0110] (1) Parallel plate plasma electrode structure

[0111] (1-1) Wafer holding mechanism

[0112] Electrostatic chucks or mechanical clamps are used as their respective wafer holding mechanisms, and a structure is adopted that can hold the wafers on the upper and lower electrodes.

[0113] At least one of the upper or lower electrodes should be designed with a replaceable bonding wafer structure. Replacement is best performed by a robotic arm or similar device. Furthermore, it is preferable to replace the bonding wafer of the upper electrode. This helps suppress particles generated due to electrode surface roughness.

[0114] (1-2) Electrode sputtering

[0115] As electrodes, silicon electrodes composed of silicon carrier wafers are used to control particles during the plasma process. This reduces the voids during bonding between the bonding wafer and the semiconductor wafer.

[0116] (1-3) Activation of wafer surfaces with one or both sides facing each other

[0117] By applying a high-frequency power supply to each electrode for soft sputtering, silicon sputtered from the electrodes accumulates on the opposing wafer surfaces, forming a high-purity thin silicon film. Alternatively, the step of forming the high-purity silicon film (silicon thin film) can be omitted if necessary.

[0118] High-frequency power supplies of different frequencies can also be applied to the upper electrode to sputter silicon (Si).

[0119] (2) Setting up the bonding wafer

[0120] (2-1) Surface activation of wafers using gas

[0121] Ar (argon) or N2 (nitrogen) gas is used to activate the wafer surface.

[0122] Plasma processing is performed simultaneously on two wafers positioned on the upper and lower sides within a single chamber.

[0123] (2-2) Plasma treatment

[0124] Plasma processing is performed in a high vacuum. Magnetrons or ICP coils can be used.

[0125] The space between electrodes is a structure where plasma is uniform and unaffected by external influences such as dust intrusion.

[0126] (2-3) Vacuuming after plasma treatment

[0127] Stop supplying argon and nitrogen to the chamber, activate the automatic pressure controller (APC), and use a turbomolecular pump to control the chamber to reach a vacuum pressure, for example, in about 10 seconds.

[0128] Depending on the product, high-frequency power can be applied to the upper and lower electrodes, or the application of high-frequency power can be stopped.

[0129] (2-4) Vacuum bonding (vacuum bonding)

[0130] The charged wafers are brought close together and brought into contact using Coulomb force (electrostatic force). This Coulomb force enhances the initial bonding strength between the wafers. Furthermore, the increased atomic movement due to the Coulomb force makes it easier for atoms residing on each wafer surface to move.

[0131] By applying a high-frequency power supply to each electrode, atoms rearrange to a stable energy state, thereby forming a strong bond between wafers.

[0132] (3) Instantaneous bonding between wafers after plasma treatment (instantaneous bonding)

[0133] After the surface activation of each wafer, bonding occurs, for example, in about 10 seconds, thereby minimizing the degradation of the active state (activity) of the wafer surface.

[0134] In contrast, in typical room-temperature activated bonding or atomic diffusion bonding, bonding between wafers requires time. Specifically, if a waiting time of several minutes occurs, the active state will decrease by approximately 20%. This leads to a problem of product quality degradation in semiconductor wafers, but this problem is solved by the high-frequency ion flow bonding of this embodiment.

[0135] [In high vacuum (1×10)] -6 [Pa) Attenuation rate after surface activation]

[0136] The decay rate after 10 seconds in a vacuum is: A(10 seconds) ≈ 99.83%, A(10 seconds) = 99.83%, which means the decay rate is 0.17%.

[0137] The decay rate after 2 minutes in a vacuum is: A(2 minutes) ≈ 81.87%, A(2 minutes) = 81.87%, which means the decay rate is 18.13%.

[0138] In summary, rapid vacuuming and wafer bonding are crucial for maintaining the surface activation state, and the results demonstrate that a strong bond between wafers can be achieved.

[0139] Then, the silicon wafers were plasma-treated in a vacuum to activate their surfaces. The ion diffusion in the bonding process of wafers bonding with high-frequency ion flow activation by applying a high-frequency power supply was analyzed under the condition of maintaining the surface active state in a closed gas and high-speed vacuum.

[0140] [High-frequency ion flow activated bonding process]

[0141] (1) Plasma surface activation

[0142] Organic contaminants and oxides on the wafer surface are chemically removed by plasma etching using fluorine-based gases. Argon sputtering removes any remaining minute contaminants and uneven chemical residues. While the wafer surface is cleaned through activation and plasma etching, argon sputtering physically impacts the surface, further activating the atoms and improving bonding efficiency between wafers.

[0143] Due to the dual effects of wafer surface cleaning and activation, atoms can diffuse, resulting in higher bonding strength between wafers.

[0144] (2) Gas stoppage and high-speed vacuum pumping

[0145] After plasma treatment of the wafer, the supply of argon and nitrogen is stopped, and a turbomolecular pump is used for control to achieve a high vacuum (1×10⁻⁶) at high speed. -6 Pa).

[0146] By reaching the ultimate vacuum level within approximately 10 seconds, the activated state of the wafer surface is maintained.

[0147] (3) Wafer bonding

[0148] The wafers are bonded together while polarized ions remain on the surface of each wafer.

[0149] Due to Coulomb force (electrostatic force), the interatomic spacing between closely spaced wafer surfaces decreases, thus strengthening the contact between wafers.

[0150] (4) Apply high-frequency power supply

[0151] After the wafers are bonded together, a high-frequency power supply is applied to generate an electric field on the surface of each wafer.

[0152] This electric field causes ions to flow on the wafer surface, strengthening the bonds between atoms.

[0153] [A Discussion on Ion Diffusion]

[0154] (1) State of ions on the wafer surface

[0155] Due to the activation effect of plasma treatment, the ions remaining on the wafer surface are in a polarized state.

[0156] Ions in a polarized state are strongly adsorbed onto the wafer surface, making their movement easier.

[0157] In a high vacuum environment, the electrodes are in an insulating state, and ions will not ionize (discharge), but will remain on the wafer surface.

[0158] (2) High vacuum state

[0159] In a high vacuum, the active state of the wafer surface is maintained, and recontamination of the wafer surface is suppressed.

[0160] (3) Effects of high-frequency power supply

[0161] The high-frequency electric field (13.56MHz, 200W) has the following effects on the wafer surface and interface.

[0162] (3-1) Surface potential variation

[0163] A high-frequency electric field generates an alternating electric field on the wafer surface. This causes potential fluctuations on the wafer surface, resulting in the following effects:

[0164] Surface potential variation: A potential of ±200V varies at 13.56mch z, causing the movement of electrons and ions on the wafer surface.

[0165] High-frequency electric field effect: A high-frequency electric field (alternating electric field) causes atoms and ions on the wafer surface to rearrange.

[0166] (3-2) Promote atomic diffusion at the interface

[0167] High-frequency electric fields have the following effects on the wafer surface:

[0168] Ion movement: Alternating electric fields make it easier for ions to move on the wafer surface.

[0169] Changes between atoms: Due to the alternating electric field, the atomic forces between wafers change, forming stronger coupling.

[0170] Lowering the active energy: The alternating electric field reduces the energy required for atomic diffusion, promoting the bonding between atoms.

[0171] [Mechanism of ion diffusion]

[0172] By applying a high-frequency power source, ions diffuse through the following mechanism.

[0173] (1) Ion movement induced by electric field

[0174] Due to the high-frequency electric field (the effect generated by the high-frequency electric field), ions on the wafer surface are attracted or squeezed out. As a result, ions move uniformly across the entire wafer surface.

[0175] (2) Surface diffusion

[0176] Ions move on the wafer surface, causing atoms to rearrange.

[0177] A more stable energy state is formed by rearranging the atoms on the wafer surface.

[0178] (3) Strengthening of interatomic bonds

[0179] By rearranging the atoms on the wafer surface, the bonds between atoms are strengthened. As a result, the bonding between wafers becomes stronger.

[0180] According to the high-frequency ion flow bonding process, specifically by chemically reacting a silicon wafer in a vacuum to isotropically etch the oxide film on the wafer surface, followed by activation of the wafer surface through soft argon sputtering. Then, for example, the wafers are bonded together in a high-vacuum environment at a high speed of about 10 seconds, while maintaining the activated state of the wafer surface. Furthermore, by continuing to apply a high-frequency power supply between the wafers, the diffusion and movement of ions on the wafer surface strengthens the interatomic bonding. This results in a more robust bond between the wafers. Therefore, high-frequency ion flow bonding technology is highly effective in wafer bonding, simultaneously improving both the bonding strength and quality between the wafer and the substrate.

[0181] Furthermore, frequent automatic electrode replacement and the use of carrier wafers help reduce flakes and particles formed by Si sputtering, achieving void-free bonding. This significantly reduces the frequency of cleaning within the chamber, decreases maintenance-related time, and improves equipment uptime.

[0182] [An example of a semiconductor manufacturing system]

[0183] An example of assembling a semiconductor wafer bonding apparatus into a semiconductor manufacturing system according to this embodiment and example will be described.

[0184] like Figure 5 and Figure 6 As shown, the bonding device 34 for semiconductor wafers can also be assembled into the semiconductor manufacturing system 200 to replace the plasma chamber 10 of the conventional system. Figure 5 and Figure 6 The semiconductor manufacturing system 200 shown has a central chamber 202 housing a robotic arm, and around it are a semiconductor wafer bonding device 34 for plasma processing and inter-wafer bonding, a vacuum bonding chamber 204, an atomic bonding chamber 206, a rotary cleaning chamber 208, a standby chamber 210, and a load locking chamber 212. Near the load locking chamber 212 are a wafer transport mechanism 214 and multiple wafer cassettes 216.

[0185] [An example of a wafer holding mechanism]

[0186] Next, an example of a wafer holding mechanism used to hold each wafer will be described.

[0187] Regarding the semiconductor wafer bonding apparatus and bonding method of this embodiment, an electrostatic chuck 80 (see reference) is provided as a wafer holding mechanism on the first stage 36 and the second stage 38 used to hold the semiconductor wafers W1 and W2. Figures 7 to 9 Alternatively, an electrostatic chuck 80 can be used as an alternative (see reference). Figures 7 to 9 The structure is configured with the first wafer fixing mechanism 102 and the second wafer fixing mechanism 104.

[0188] Figure 7 and Figure 8 The structures of a unipolar electrostatic chuck 78 and a bipolar electrostatic chuck 80 are shown. The electrostatic chucks 78 and 80 are made of insulating materials such as alumina (Al2O3) and aluminum nitride (ALN). Their structure consists of an electrode built into the insulator, which is applied to the electrode to attract semiconductor wafers W1, W2, and other objects 86 and 92.

[0189] Figure 7The unipolar electrostatic chuck 78 shown is unipolar and includes a base substrate 82 and an internal electrode (also called an electrode sheet or polyimide film electrode layer) 84 disposed on the base substrate 82. The base substrate 82 applies a positive (+) or negative (-) voltage to the internal electrode 84. For example, when a positive (+) voltage is applied to the internal electrode 84, negative (-) charges move on the surface of the object to be attracted 86, and the object to be attracted 86 is attracted by the unipolar electrostatic chuck 78. Conversely, when a negative (-) voltage is applied to the internal electrode 84, positive (+) charges move on the surface of the object to be attracted 86, and the object to be attracted 86 is attracted by the unipolar electrostatic chuck 78.

[0190] Figure 8 The electrostatic chuck 80 shown is bipolar, having a base substrate 88 and internal electrodes (also called electrode sheets or polyimide film electrode layers) 90 disposed on the base substrate 88. The base substrate 88 applies both positive (+) and negative (-) voltages to the internal electrodes 90. For example, on the surface of the object 92 opposite to the internal electrode 90 to which a positive (+) voltage is applied, negative (-) charges move, and on the surface of the object 92 opposite to the internal electrode 90 to which a negative (-) voltage is applied, positive (+) charges move, thereby causing the object 92 to be adsorbed onto the bipolar electrostatic chuck 80.

[0191] This section illustrates an example of using a bipolar electrostatic chuck in a semiconductor wafer bonding apparatus. For example... Figure 9 As shown, the electrostatic chucks 80 are preferably built into the first stage 36 and the second stage 38, respectively. For ease of explanation, the electrostatic chuck 80 built into the first stage 36 is referred to as the first electrostatic chuck 80A, and the electrostatic chuck 80 built into the second stage 38 is referred to as the second electrostatic chuck 80B. Each electrostatic chuck 80A and 80B is, for example, bipolar. Since the first stage 36 and the second stage 38 are arranged opposite each other, the electrostatic chucks 80A and 80B are arranged in opposite positions, thus forming a pair of electrostatic chucks.

[0192] The first electrostatic chuck 80A has a first base substrate 88A and a first internal electrode 90A disposed on the first base substrate 88A. The first internal electrode 90A is grounded. The first base substrate 88A controls the voltage applied to the first internal electrode 90A. The first internal electrode 90A is composed of two or more adjacent first unit electrodes 91A, and positive and negative voltages are applied between adjacent first unit electrodes 91A respectively.

[0193] The second electrostatic chuck 80B is positioned opposite the first electrostatic chuck 80A. The second electrostatic chuck 80B has the same structure as the first electrostatic chuck 80A, including a second base substrate 88B and a second internal electrode 90B disposed on the second base substrate 88B. The second internal electrode 90B is grounded. The second base substrate 88B controls the voltage applied to the second internal electrode 90B. The second internal electrode 90B is composed of two or more adjacent second unit electrodes 91B, with opposite voltages applied between adjacent second unit electrodes 91B.

[0194] Here, the first unit electrode 91A on the side of the first electrostatic chuck 80A and the second unit electrode 91B on the side of the second electrostatic chuck 80B, which are opposite to the first unit electrode 91A, are controlled by the first base substrate 88A and the second base substrate 88B, respectively, to apply voltages of opposite polarities (positive and negative). Therefore, the first unit electrode 91A in the first internal electrode 90A of the first electrostatic chuck 80A, which is subjected to a negative (-) voltage, is positioned opposite to the second unit electrode 91B in the second internal electrode 90B of the second electrostatic chuck 80B, which is subjected to a positive (+) voltage. Similarly, the first unit electrode 91A in the first internal electrode 90A of the first electrostatic chuck 80A, which is subjected to a positive (+) voltage, is positioned opposite to the first unit electrode 91B in the second internal electrode 90B of the second electrostatic chuck 80B, which is subjected to a negative (-) voltage.

[0195] As per the general principle of the bipolar electrostatic chuck 80, with a semiconductor wafer W1 placed on the first electrostatic chuck 80A and a semiconductor wafer W2 placed on the second electrostatic chuck 80B, a positive voltage and a negative voltage are applied to the first internal electrode 90A and the second internal electrode 90B, respectively. As a result, the positive and negative charges on the semiconductor wafers W1 and W2 move in the direction of attraction to their respective internal electrodes 90A and 90B (dielectric polarization). Consequently, adsorption forces are generated between the first internal electrode 90A and the semiconductor wafer W1, and between the second internal electrode 90B and the semiconductor wafer W2, thereby fixing the semiconductor wafers W1 and W2 in place.

[0196] like Figure 7 As shown, generally speaking, in a unipolar electrostatic chuck 78, by applying a voltage between the object being attracted (such as a semiconductor wafer) 86 and the internal electrode 84 (also called a chuck or holding device), a charge is generated on the surface of the object being attracted (such as a semiconductor wafer) 86. Specifically, if the internal electrode 84 is positively (+), then the surface of the object being attracted (such as a semiconductor wafer) 86 opposite to it is negatively (-); and if the internal electrode 84 is negatively (-), then the surface of the object being attracted (such as a semiconductor wafer) 86 opposite to it is positively (+). This principle is... Figure 8The same applies to the bipolar electrostatic chuck 80 shown.

[0197] Typically, the surfaces of semiconductor wafers W1 and W2, after plasma treatment and activation, will be negatively charged (or possibly positively charged). Therefore, when attempting to bond semiconductor wafers W1 and W2, both with negatively charged (or both with positively charged) surfaces, they will generate electrical repulsion. In this state, if semiconductor wafers W1 and W2 are forcibly bonded together, they will repel each other, causing positional shifts and resulting in a decrease in the bonding accuracy of semiconductor wafers W1 and W2.

[0198] like Figure 9 As shown, by making the surface of one semiconductor wafer W1, which is facing each other, positively (negatively) charged, and the surface of the other semiconductor wafer W2, negatively (positively) charged, a state with opposite polarity charges is intentionally formed between the semiconductor wafers to be bonded. Thus, for example, the van der Waals forces (intermolecular forces) and Coulomb forces (electrostatic forces) generated between them are used to enhance the adsorption force, thereby assisting the bonding between semiconductor wafers W1 and W2.

[0199] Generally speaking, objects with negative static electricity will repel each other when they approach each other (or objects with positive static electricity will repel each other when they approach each other). This is one of the fundamental properties of static electricity: charges of the same sign (e.g., both are negative) will repel each other, while charges of opposite polarities (e.g., one is positive and the other is negative) will attract each other.

[0200] By making semiconductor wafers W1 and W2 have opposite polarities (reverse polarities) and controlling the voltage between their surfaces to prevent discharge, when the positively (+) charged semiconductor wafer W1 (or W2) comes into contact with the negatively (-) charged semiconductor wafer W2 (or W1), electrons move from the positively (+) charged object to the negatively (-) charged object, thus neutralizing the charge. This reduces the effect of electrostatics and increases the bonding and adsorption forces during bonding.

[0201] In a typical bipolar electrostatic chuck (ESC), the electrical balance of the semiconductor wafer surface is maintained by applying the same voltage (absolute value) to both the positive (+) and negative (-) sides.

[0202] In contrast, instead of applying voltages of equal magnitude (absolute value) for positive and negative (negative) signals, different magnitudes of voltage are deliberately applied to intentionally disrupt the balance between positive and negative (negative) signals. In other words, an imbalance is created between positive and negative voltages by adjusting the magnitude of the applied voltage.

[0203] like Figure 9As shown, for example, a voltage of -400 volts is applied to the first unit electrode 91A on one side of the first internal electrode 90A constituting the first electrostatic chuck 80A, and a voltage of +500 volts is applied to the first unit electrode 91A on the other side. Simultaneously, a voltage of +400 volts is applied to the second unit electrode 91B on one side of the second internal electrode 90B constituting the second electrostatic chuck 80B, and a voltage of -500 volts is applied to the second unit electrode 91B on the other side.

[0204] Here, in the first internal electrode 90A of the first electrostatic chuck 80A, the first unit electrode 91A on the side where a -400 volt voltage is applied is positioned opposite to the second unit electrode 91B on the side where a +400 volt voltage is applied in the second internal electrode 90B of the second electrostatic chuck 80B. Although their polarities are different, their absolute values ​​are the same.

[0205] Furthermore, the first unit electrode 91A on the side of the first internal electrode 90A of the first electrostatic chuck 80A, to which a +500 volt voltage is applied, and the second unit electrode 91B on the side of the second internal electrode 90B of the second electrostatic chuck 80B, to which a -500 volt voltage is applied, are positioned opposite each other. Although their polarities are different, their absolute values ​​are the same.

[0206] Through these processes, the surface of the semiconductor wafer W1, opposite to the first electrostatic chuck 80A, is charged by the difference of +500 volts and -400 volts, i.e., +100 volts, from the first electrostatic chuck 80A. Similarly, the surface of the semiconductor wafer W2, opposite to the second electrostatic chuck 80B, is charged by the difference of +400 volts and -500 volts, i.e., -100 volts, from the second electrostatic chuck 80B.

[0207] At this point, floating charges will be generated on the surfaces of semiconductor wafers W1 and W2. Consequently, by applying a reverse voltage between the opposing internal electrodes 90A and 90B (or between unit electrodes), semiconductor wafers W1 and W2 will attract and adhere to each other due to a strong Coulomb force. As a result, bubbles generated during the adhesion of semiconductor wafers W1 and W2 can be suppressed.

[0208] Here, semiconductor wafers W1 and W2 are held by a pair of electrostatic chucks 80A and 80B, with the spacing between them preferably set in a micro-space (minimum space) environment of 10μm or more and 50μm or less. Within the micro-space, semiconductor wafers W1 and W2 maintain a planar orientation while being bonded.

[0209] Furthermore, this embodiment and example only demonstrate one aspect of the invention, and the invention is not limited thereto. Differences in design modifications and other aspects of this embodiment and example are, of course, also included within the scope of the technical concept of the invention.

[0210] Explanation of symbols

[0211] 14 chambers

[0212] 16 platforms

[0213] 34 Semiconductor wafer bonding device

[0214] 36. Platform 1

[0215] 38. Second platform

[0216] 78 Unipolar electrostatic chuck

[0217] 80 Bipolar Electrostatic Chuck

[0218] 80A First Electrostatic Chuck

[0219] 80B Second Electrostatic Chuck

[0220] 82 Base substrate

[0221] 84 Internal Electrodes

[0222] 86 Adsorbed body

[0223] 88 base substrate

[0224] 88A First Baseboard

[0225] 88B Second Baseboard

[0226] 90 Internal Electrode

[0227] 90A First Internal Electrode

[0228] 90B Second Internal Electrode

[0229] 91A First Unit Electrode

[0230] 91B Second Unit Electrode

[0231] 92 Adsorbed body

[0232] 102 First Wafer Fixing Mechanism

[0233] 104 Second Wafer Fixing Mechanism

[0234] 106 First Replacement Device

[0235] 108 Second Replacement Device

[0236] 110 High-Frequency Power Supply

[0237] 112 Automatic pressure control device

[0238] 114 Turbomolecular Pump

[0239] 200 Semiconductor Manufacturing Systems

[0240] 202 Central Chamber

[0241] 204 Vacuum Bonding Chamber

[0242] 206 Atomic Bonding Chamber

[0243] 208 Rotary Cleaning Chamber

[0244] 210 Standby Chamber

[0245] 212 Load-locking chamber

[0246] 214 Wafer Handling Mechanism

[0247] 216 wafer box

[0248] G1 silicon wafer

[0249] G2 bonded wafer

[0250] W1 Semiconductor Wafer

[0251] W2 Semiconductor wafer.

Claims

1. A semiconductor wafer bonding apparatus, characterized in that, The semiconductor wafer bonding apparatus includes a chamber serving as a housing, a first stage located on the upper side inside the chamber, and a second stage located on the lower side inside the chamber. A first wafer fixing mechanism is arranged on the first stage, and a second wafer fixing mechanism is arranged on the second stage. By moving at least one of the first and second wafer fixing mechanisms while the wafer is fixed by the first and second wafer fixing mechanisms, the first and second wafer fixing mechanisms are positioned opposite each other to perform bonding. A silicon electrode and a first semiconductor wafer are fixed by a first wafer fixing mechanism and a second wafer fixing mechanism. After performing a first plasma treatment on the silicon electrode and the first semiconductor wafer, the silicon electrode is replaced with a second semiconductor wafer. Plasma treatment is then performed on both the first and second semiconductor wafers to activate their surfaces. A high vacuum state is then generated within a predetermined time to polarize the ions on the surfaces of the first and second semiconductor wafers. A high-frequency power supply is applied to the semiconductor wafers to cause ions to move on the surfaces of the first and second semiconductor wafers, thereby improving the bonding strength. The predetermined time is 1 to 30 seconds.

2. The semiconductor wafer bonding apparatus as described in claim 1, characterized in that, The predetermined time is 1 to 10 seconds.

3. A semiconductor wafer bonding method, characterized in that, After performing a first plasma treatment on the silicon electrode and the first semiconductor wafer, the silicon electrode is replaced with a second semiconductor wafer. Plasma treatment is then applied to both the first and second semiconductor wafers to activate their surfaces. A high vacuum state is then created within a predetermined time to polarize the ions on the surfaces of both semiconductor wafers. A high-frequency power supply is applied to both semiconductor wafers, causing ions to move across the semiconductor wafer surfaces, thereby improving the bonding strength. The predetermined time is 1 to 30 seconds.

4. The bonding method for semiconductor wafers as described in claim 3, wherein the predetermined time is 1 to 10 seconds.

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