A modeling optimization method and system for performance of a GPU heterogeneous acceleration card based on sparse matrix vector multiplication
By constructing a hierarchical decision tree model for kernel selection and parameter configuration, the problems of low memory bandwidth utilization and unbalanced load in sparse matrix-vector multiplication on heterogeneous GPU accelerator cards are solved, resulting in a significant performance improvement that is applicable to various GPU platforms.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- COMP NETWORK INFORMATION CENT CHINESE ACADEMY OF SCI
- Filing Date
- 2025-09-22
- Publication Date
- 2026-07-14
AI Technical Summary
In existing technologies, sparse matrix-vector multiplication achieves optimal computational performance on GPU heterogeneous accelerator cards, but suffers from problems such as low memory bandwidth utilization, irregular memory access patterns leading to low cache efficiency, and unbalanced load among parallel processing units.
By analyzing the structural features of sparse matrices, the candidate kernel features of prior knowledge, and the hardware configuration features of accelerator cards, a hierarchical decision tree model is constructed to perform kernel selection and parameter configuration, optimize the sparse matrix vector multiplication algorithm, and improve the performance of GPU heterogeneous accelerator cards.
It achieves significant performance improvements and is suitable for domestic C86 and NVIDIA V100 GPU accelerator card platforms, improving memory access efficiency and load balancing in parallel processing, thereby enhancing computing performance.
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Figure CN120849129B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of high-performance numerical computing technology, and more specifically to a modeling and optimization method and system for the performance of heterogeneous GPU accelerator cards based on sparse matrix-vector multiplication. Background Technology
[0002] Currently, GPU heterogeneous accelerator cards are core hardware components supporting high-performance computing, artificial intelligence, big data processing and other fields. With the rapid upgrade and iteration of accelerator cards, more and more complex computing tasks are being transferred to accelerator cards for computation.
[0003] Sparse matrix-vector multiplication (SpMV), a fundamental algorithm implementation on accelerator cards, is widely used in various scientific computing software and applications, including neural networks, finite element analysis, large language models, and linear system solvers. However, despite the widespread use of SpMV computation, achieving optimal computational performance on accelerator cards remains challenging due to several factors, such as limited memory bandwidth utilization, inefficient caching caused by irregular memory access patterns, and unbalanced load among parallel processing units.
[0004] Therefore, how to provide a GPU heterogeneous accelerator card performance optimization method based on sparse matrix-vector multiplication that can optimize the computing performance of accelerator cards is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] In view of this, the present invention provides a modeling and optimization method and system for the performance of heterogeneous GPU accelerator cards based on sparse matrix-vector multiplication. By analyzing the row-oriented sparse matrix structure features, candidate kernel features from prior knowledge, and accelerator card hardware configuration features to form feature parameters, effective kernel selection and parameter configuration accuracy are achieved, resulting in a significant performance improvement. This method demonstrates good adaptability on both domestic C86 GPU accelerator cards and NVIDIA V100 GPU accelerator card platforms.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] A method for modeling and optimizing the performance of heterogeneous GPU accelerator cards based on sparse matrix-vector multiplication includes the following steps:
[0008] Determine the data features of the effective sparse matrix and obtain the hardware parameters of the GPU heterogeneous accelerator card;
[0009] The data features and hardware parameters are associated and used as a dataset, and the dataset is divided into a training set and a test set according to a certain ratio;
[0010] A performance evaluation model based on a hierarchical decision tree is constructed, and the performance evaluation model is trained and tested using the training set and the test set to obtain the optimal performance evaluation model.
[0011] The SpMV algorithm of the accelerator card under test is optimized using the optimal performance evaluation model to achieve performance optimization of the accelerator card under test.
[0012] Preferably, the performance evaluation model is a hierarchical decision tree model, which includes a kernel selection layer and a parameter configuration layer. The first layer of the decision tree is used for coarse-grained kernel type classification; the second layer consists of multiple independently trained parameter configuration decision trees, which perform fine-grained parameter selection modeling for each kernel type. The loss of the hierarchical decision tree consists of two parts: one part is the kernel selection loss based on the candidate kernel tower, and the other part is the parameter selection loss based on the upper-level candidate parameter tower. That is, for a sample, it will only enter a certain candidate parameter tower.
[0013] Preferably, the specific processing steps to obtain the optimal performance evaluation model include:
[0014] During the training phase, each matrix iterates through all candidate kernels and their candidate parameter spaces, calculating the actual execution time for each configuration. After obtaining the execution times for all configurations, the optimal kernel and optimal configuration parameters for each matrix can be determined. Hardware-related information is also considered when selecting the candidate parameter space, thereby improving the algorithm's robustness and transferability.
[0015] A hierarchical decision tree model is constructed to solve the problems of kernel prediction and parameter prediction respectively. The specific process includes: the first layer of decision tree is used for coarse-grained kernel type classification; the second layer is a parameter configuration decision tree for multiple independently trained kernel types, which performs fine-grained parameter selection modeling for each kernel type. This structure can fully capture the heterogeneity of parameter distribution under different kernels and effectively improve the overall prediction accuracy.
[0016] The training set is input into the performance evaluation model for training to obtain the corresponding candidate kernel parameters and configurations. The optimal kernel parameters and parameter configurations are determined through the test set, and the model at this time is saved as the optimal performance evaluation model.
[0017] Preferably, the hardware parameters include the number of streaming multiprocessors or computing units.
[0018] Preferably, the data features of the sparse matrix include the matrix's basic dimensions, row distribution features, column distribution features, and overall pattern.
[0019] This invention provides a GPU heterogeneous accelerator card performance optimization system based on sparse matrix-vector multiplication, comprising:
[0020] The acquisition module is used to acquire the hardware parameters of the GPU heterogeneous accelerator card and determine the data characteristics of the sparse matrix.
[0021] The processing module is used to associate the data features and the hardware parameters as a dataset, and to divide the dataset into a training set and a test set according to a certain ratio;
[0022] The model analysis module is used to construct a performance evaluation model, and to train and test the performance evaluation model using the training set and the test set to obtain the optimal performance evaluation model.
[0023] The optimization module is used to optimize the SpMV algorithm of the accelerator card under test using the optimal performance evaluation model, thereby achieving performance optimization of the accelerator card under test.
[0024] As can be seen from the above technical solutions, compared with the prior art, the present invention discloses a modeling and optimization method and system for GPU heterogeneous accelerator card performance based on sparse matrix vector multiplication. Through the proposed comprehensive optimization model based on matrix features, algorithm characteristics and hardware architecture, an interpretable optimization decision process is provided. While maintaining simplicity of implementation, it achieves significant performance improvement and shows good adaptability on accelerator cards in the domestic C86 environment and NVIDIA V100 accelerator card platforms. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0026] Figure 1 The overall flowchart of a modeling and optimization method for the performance of heterogeneous GPU accelerator cards based on sparse matrix-vector multiplication provided by the present invention;
[0027] Figure 2 This is a flowchart of the decision tree model training process provided in an embodiment of the present invention;
[0028] Figure 3 A schematic diagram showing the performance comparison between the computation time of the four candidate kernel optimal parameters provided in the embodiments of the present invention and the computation time of fixing a certain parameter;
[0029] Figure 4A schematic diagram showing the time speedup of the adaptive framework selection with fixed parameters on a domestic C86 GPU accelerator card platform provided in this embodiment of the invention, and the time speedup of the adaptive framework selection after parameter optimization and optimal kernel selection.
[0030] Figure 5 A schematic diagram showing the time speedup of the optimal computation time of adaptive framework selection with fixed parameters on an NVIDIA accelerator card, compared with the time speedup of adaptive framework selection after parameter optimization and optimal kernel selection, provided in an embodiment of the present invention.
[0031] Figure 6 A diagram showing the comparison between the optimized kernel implementation strategy provided in this embodiment of the invention and the computation time of the hipsparsecsrmv function in hipSPARSE;
[0032] Figure 7 The present invention provides a structural principle block diagram of a GPU heterogeneous accelerator card performance modeling and optimization system based on sparse matrix-vector multiplication. Detailed Implementation
[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] See Figure 1 As shown, this embodiment of the invention provides a method for modeling and optimizing the performance of heterogeneous GPU accelerator cards based on sparse matrix-vector multiplication, including the following steps:
[0035] Determine the data features of the effective sparse matrix and obtain the hardware parameters of the GPU heterogeneous accelerator card;
[0036] The data features and hardware parameters are associated and used as a dataset, and the dataset is divided into a training set and a test set according to a certain ratio;
[0037] A performance evaluation model based on a hierarchical decision tree is constructed, and the performance evaluation model is trained and tested using the training set and the test set to obtain the optimal performance evaluation model.
[0038] The SpMV algorithm of the accelerator card under test is optimized using the optimal performance evaluation model to achieve performance optimization of the accelerator card under test.
[0039] In one specific embodiment, the hardware parameters include the number of streaming multiprocessors or computing units. Furthermore, the GPU's memory capacity and memory bandwidth are also important factors affecting SpMV performance, as SpMV is a typical memory-bandwidth-constrained computation. Secondly, the size of thread blocks and thread bundles are also key parameters, affecting the kernel's parallel granularity and scheduling efficiency. Simultaneously, the GPU's multi-level cache structure (such as the capacity and hierarchy of L1 and L2 caches), the number of registers, and the capacity of shared memory are also important hardware features affecting memory access efficiency and data reuse capabilities.
[0040] In one specific embodiment, the data characteristics of the sparse matrix include the matrix's basic dimensions, row distribution characteristics, column distribution characteristics, and overall pattern, which directly determine the parallel computing capability.
[0041] In a specific embodiment, sparse matrix-vector multiplication can be described in the following form:
[0042]
[0043] In the formula, Represents a sparse matrix. x Represents the input vector. y Indicates the output vector.
[0044] The data characteristics of a sparse matrix include the matrix's basic dimensions, row distribution characteristics, column distribution characteristics, and overall pattern. The specific parameters are shown in Table 1. These characteristics are mainly described from multiple dimensions such as the matrix's basic dimensions, row distribution characteristics, column distribution characteristics, and overall pattern.
[0045] First, the basic dimensions of the matrix are characterized by the number of rows, columns, and the number of non-zero elements. Regarding row distribution characteristics, the maximum, minimum, and average values of non-zero elements in each row are considered, and the variance of the number of non-zero elements in a row is introduced to quantify the uniformity of the distribution of non-zero elements between rows. For column distribution characteristics, a feature is designed to characterize the variance of the column index difference between adjacent non-zero elements. This feature effectively reflects the locality of memory access along the column direction; a smaller variance value generally indicates better locality of memory access. Simultaneously, this application introduces a bandwidth feature to measure the average span between the first and last non-zero elements in each row. This feature is significant for evaluating the banding characteristics of the matrix.
[0046] Table 1. Characteristics of Sparse Matrices
[0047]
[0048] This invention extracts structural features of sparse matrices through a matrix feature extraction pipeline, namely, the number of rows, the number of columns, the number of non-zero elements, the variance of non-zero elements, the variance of the distribution of non-zero elements in each row, and the proportion of non-zero elements in sparse and dense regions. Based on the above analysis, the invention provides judgment labels for matrix row features, such as "long and short rows", "banded rows", and "irregular rows".
[0049] In a specific embodiment, the performance evaluation model is a hierarchical decision tree model, which includes a kernel selection layer and a parameter configuration layer. For each training sample, representative features of the sparse matrix and computation time are first extracted. Then, iterative optimization is performed using the hierarchical decision tree. The first layer of the decision tree is used for coarse-grained kernel type classification; the second layer consists of multiple independently trained parameter configuration decision trees, which perform fine-grained parameter selection modeling for each kernel type. The loss of the hierarchical decision tree consists of two parts: one is the kernel selection loss based on the candidate kernel tower, and the other is the parameter selection loss based on the upper-level candidate parameter tower. That is, for a sample, it will only enter a certain candidate parameter tower. Both parts of the loss are subject to the cross-entropy loss function. The hierarchical structure allows each kernel type to have its own dedicated parameter decision tree and encoding method, and each decision tree independently minimizes its own information entropy (loss), avoiding interference from noise from other classes and preventing interference from class imbalance and irrelevant features on parameter prediction, thus improving the accuracy and generalization ability of parameter prediction. It also balances the differences in parameter space and optimal parameter distribution between kernel types.
[0050] See Figure 2 As shown, in a specific embodiment, the specific processing steps for obtaining the optimal performance evaluation model include:
[0051] Based on the data characteristics, candidate kernels for sparse matrix-vector multiplication are determined, and key feature parameters affecting the performance of sparse matrix-vector multiplication are determined based on the candidate kernels.
[0052] A hierarchical decision tree model is constructed to solve the problems of kernel prediction and parameter prediction respectively. The specific process includes: the first layer of decision tree is used for coarse-grained kernel type classification; the second layer is a parameter configuration decision tree for multiple independently trained kernel types, which performs fine-grained parameter selection modeling for each kernel type. This structure can fully capture the heterogeneity of parameter distribution under different kernels and effectively improve the overall prediction accuracy.
[0053] The training set is input into the performance evaluation model for training to obtain the corresponding candidate kernel parameters and configurations. The optimal kernel parameters and parameter configurations are determined through the test set, and the model at this time is saved as the optimal performance evaluation model.
[0054] Specifically, this invention designs and integrates several representative SpMV computing kernels tailored to the structural characteristics of different sparse matrices. Each candidate kernel is optimized for a specific matrix distribution pattern, and various implementation methods are designed for different scenarios such as banded distribution, sparse and uniform row distribution, dense row distribution, or uneven load distribution, including register cache optimization, warp grouping, warp collaborative processing, and dynamic row block partitioning. These kernels each have their own characteristics in terms of parallel granularity, memory access patterns, and load balancing strategies, and can cover mainstream sparse matrix distribution types, including:
[0055] Candidate kernels (i.e.) Figure 2 The candidate functions involved include four GPU-accelerated SpMV computation kernels for model selection and parameter optimization. These four candidate kernels utilize different parallel optimization methods and techniques, and their algorithm design characteristics are as follows:
[0056] Candidate kernel 1 utilizes thread-level parallel SpMV computation optimization. It uses a register cache to store a segment of the input vector x, and the kernel employs vectorization processing and loop unrolling for memory access. For each row, it prefetches the x values within the bandwidth into a register, and then performs vectorization computation through conditional access cache or global memory values. Candidate kernel 2 divides the twist into multiple sub-twists, utilizes loop unrolling and __ldg memory for memory access, and uses __shfl_down_sync to reduce the twist level for parallel computation. Candidate kernel 3 implements thread-level parallel SpMV computation, where each thread processes one matrix row. It uses loop unrolling for efficient memory access and employs dynamic row block partitioning to balance the workload across threads. Candidate kernel 4 uses twist-level parallel SpMV computation, where each twist processes one matrix row.
[0057] For each candidate kernel, key variable parameters are extracted from four kernels, including the optimal configuration parameters to be tested (including thread allocation parameters and algorithm-related parameters). Specifically, the variable parameters for candidate kernel 1 are the kernel function's kernel call configuration, bandwidth, and register memory space; for candidate kernel 2, they are the kernel function's kernel call configuration and the number of threads in the sub-twisting; for candidate kernel 3, they are the kernel function's kernel call configuration and the number of lines processed per thread; and for candidate kernel 4, they are the kernel function's kernel call configuration. The candidate kernels and their parameters also serve as labels for network training, guiding the model's training process.
[0058] The key feature parameter extraction process can automatically analyze and extract core parameters affecting performance, such as thread block size, warp size, bandwidth buffer size, subwarp size, and line block granularity. These parameters will also participate in model training and construction as key parameters affecting SpMV performance. Based on different accelerator card hardware information and thread parallel scheduling, multiple candidate values are given for each parameter. Candidate values for the thread block size used in kernel calls include 32, 64, 128, 256, and 512. Candidate values for bandwidth include 32, 64, 128, and 256. Subwarp sizes are set to 4, 8, 16, and 32, and line block sizes include 16, 32, 64, and 128. The determination of these candidate values is related to the accelerator card's hardware design.
[0059] Specifically, in this embodiment of the invention, a decision tree model is selected as the interpretable classifier model to train all extracted parameters. The decision tree model consists of two layers: the first layer is kernel selection (coarse-grained decision), and the second layer is parameter configuration (fine-grained decision), constructed based on descriptions of matrix features and hardware features. The model evaluation mechanism provided in this embodiment of the invention also consists of two parts, evaluating the kernel selection and parameter configuration respectively. This embodiment of the invention uses stratified random sampling to divide the dataset into training and test sets to ensure a balanced distribution of feature patterns.
[0060] A large amount of sparse matrix data was acquired, and the sparse matrix feature extraction module and the GPU platform hardware parameter extraction module were invoked to extract sparse matrices and hardware parameters. Basic dimensional features (m, n, nnz), row distribution features (max_nnz, min_nnz, avg_nnz, nnz_variance), column distribution features (col_variance, bandwidth), and recognition features (sparsity_imbalance, row_pattern) were collected. The parameters extracted by the sparse matrix feature extraction module and the GPU platform hardware parameter extraction module were used as input data to test different parameter configurations, execute SpMV candidate kernels, and record performance data. By testing the sparse matrix SpMV computation time of different kernels and kernel parameters, the fastest kernel and kernel parameters were obtained as feature labels. The extracted matrix features were correlated with the performance data, and a decision tree model was used to analyze the impact of features on performance. The data was then used for training and validation. During the training and validation of the model, 80% of the data is used as the training set and 20% of the data is used as the test set. Entropy is used as the classification standard, and the maximum tree depth and the minimum number of samples per leaf node are set (the maximum tree depth can be set to 5 and the minimum number of samples per leaf node can be set to 2). The model is evaluated to assess the accuracy of kernel selection and parameter selection, and the overall prediction performance is analyzed.
[0061] This invention is compatible with two types of GPU computing platforms, and tests were conducted on NVIDIA (Tesla V100-PCIE) accelerator card computing platforms and accelerator card computing platforms under the domestic C86 environment. The effectiveness of the invention is verified as follows:
[0062] Sixty-one large matrices (row numbers Nr > 50000, non-zero elements nnz > 100000) were selected from the general-purpose sparse matrix library SuiteSpearse to test the performance of the adaptive sparse matrix-vector multiplication model optimized for SpMV. Double-precision data was used in the tests, and each kernel function was run 50 times to measure the average performance. In this embodiment of the invention, stratified random sampling was used to divide the dataset into training and test sets.
[0063] Compared to kernel implementations using fixed default parameters, the adaptive framework's optimized parameter configuration improves performance to some extent. For example... Figure 3 As shown, parameter configuration can significantly impact the performance of certain SpMV kernels. The recommended order of optimal SpMV kernel sorting can also be altered by using different parameters. These experimental results further demonstrate that achieving optimal performance is difficult without a comprehensive optimization of kernel selection and parameter optimization.
[0064] To demonstrate the effectiveness of the hierarchical classifier, the classification accuracy was evaluated, as shown in Table 2. The method described in this application achieves a kernel prediction accuracy of approximately 0.8.
[0065] Secondly, in terms of the prediction accuracy of candidate parameters, different SpMV kernels also achieved very high accuracy, with the prediction accuracy of many parameters exceeding 0.8, and the accuracy of bandwidth buffer parameters exceeding 90%. This proves the effectiveness of the adaptive framework feature extraction, as well as the effectiveness of the hierarchical structure in predicting kernels and parameters respectively.
[0066] Table 2 Performance metrics of hierarchical decision trees
[0067]
[0068] Figure 4 and Figure 5 The optimal computation time of adaptive framework selection with fixed parameters was compared with that of adaptive framework selection after parameter optimization and optimal kernel selection on both domestic and NVIDIA accelerator card platforms. The results show that in over 97% of the matrices, the computational performance after parameter optimization and kernel selection is better than or approximates the scheme with fixed parameters and kernel selection. This result verifies the effectiveness of the adaptive framework in combining parameter optimization and algorithm selection.
[0069] This invention compares and analyzes the computational efficiency of the adaptive sparse matrix-vector multiplication model with that of the sparse matrix computation library hipSPARSE. Figure 6 The prediction kernel implementation strategy of the performance prediction framework is compared with the computation time of hipSPARSE's hipsparsecsrmv. Experimental results show that the method provided in this embodiment of the invention is on average more than 1.22 times faster than the hipSPARSE implementation.
[0070] Within the preset error tolerance range, after repeated testing, the decision tree model achieved a prediction accuracy of over 95% for the optimal computational kernel and over 75% for the combined prediction accuracy of the optimal kernel and parameters.
[0071] See Figure 7 As shown, this embodiment of the invention also provides a system for modeling and optimizing the performance of GPU heterogeneous accelerator cards based on sparse matrix-vector multiplication as described in any of the above embodiments, comprising:
[0072] The acquisition module is used to acquire the hardware parameters of the GPU heterogeneous accelerator card and determine the data characteristics of the sparse matrix.
[0073] The processing module is used to associate the data features and the hardware parameters as a dataset, and to divide the dataset into a training set and a test set according to a certain ratio;
[0074] The model analysis module is used to construct a performance evaluation model, and to train and test the performance evaluation model using the training set and the test set to obtain the optimal performance evaluation model.
[0075] The optimization module is used to optimize the SpMV algorithm of the accelerator card under test using the optimal performance evaluation model, thereby achieving performance optimization of the accelerator card under test.
[0076] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.
[0077] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for modeling and optimizing the performance of heterogeneous GPU accelerator cards based on sparse matrix-vector multiplication, characterized in that, Includes the following steps: Determine the data features of the effective sparse matrix and obtain the hardware parameters of the GPU heterogeneous accelerator card; The data features and hardware parameters are associated and used as a dataset, and the dataset is divided into a training set and a test set according to a certain ratio; A performance evaluation model based on a hierarchical decision tree is constructed. The performance evaluation model is trained and tested using the training set and the test set to obtain the optimal performance evaluation model. The performance evaluation model is a hierarchical decision tree model, which includes a kernel selection layer and a parameter configuration layer. The hierarchical decision tree model makes decisions on two aspects respectively. The first level determines the best kernel selection, while the second level optimizes the parameters of the selected kernel. The specific processing steps to obtain the optimal performance evaluation model include: Based on the data characteristics, candidate kernels for sparse matrix-vector multiplication are determined, and key feature parameters affecting the performance of sparse matrix-vector multiplication are determined based on the candidate kernels. A hierarchical decision tree model is constructed to solve the problems of kernel prediction and parameter prediction respectively. The specific process includes: the first layer of decision tree is used for coarse-grained kernel type classification; the second layer is a parameter configuration decision tree for multiple independently trained kernel types, which performs fine-grained parameter selection modeling for each kernel type. This structure can fully capture the heterogeneity of parameter distribution under different kernels and effectively improve the overall prediction accuracy. The training set is input into the performance evaluation model for training to obtain the corresponding candidate kernel parameters and configurations. The optimal kernel parameters and parameter configurations are determined through the test set, and the model at this time is saved as the optimal performance evaluation model. The loss of the hierarchical decision tree consists of two parts: one part is the kernel selection loss based on the candidate kernel tower, and the other part is the parameter selection loss based on the upper-level candidate parameter tower. Both parts of the loss are subject to the cross-entropy loss function. The hierarchical structure allows each kernel type to have its own exclusive parameter decision tree and encoding method, and each decision tree independently minimizes its own information entropy. The candidate kernels include four GPU-accelerated SpMV computation kernels. Candidate kernel 1 utilizes thread-level parallel SpMV computation optimization, using a register cache to store a segment of the input vector x. The kernel employs vectorization processing and loop unrolling for memory access. For each row, it prefetches the x values within the bandwidth into a register, and then performs vectorization computation through conditional access cache or global memory values. Candidate kernel 2 divides the twist into multiple sub-twists, utilizes loop unrolling and __ldg memory for memory access, and uses __shfl_down_sync to reduce the twist level for parallel computation. Candidate kernel 3 employs thread-level parallel SpMV computation, where each thread processes one matrix row, uses loop unrolling for memory access, and employs dynamic row block partitioning to balance the workload across threads. Candidate kernel 4 employs twist-level parallel SpMV computation, where each twist processes one matrix row. For each candidate kernel, key variable parameters are extracted from four kernels, including the optimal configuration parameters to be tested simultaneously. The variable parameters for candidate kernel 1 are the kernel call configuration of the kernel function, bandwidth, and register memory space; the variable parameters for candidate kernel 2 are the kernel call configuration of the kernel function and the number of threads for sub-twisting; the variable parameters for candidate kernel 3 are the kernel call configuration of the kernel function and the number of lines processed per thread; and the variable parameters for candidate kernel 4 are the kernel call configuration of the kernel function. The candidate kernels and their parameters also serve as labels for network training to guide the model training process. The SpMV algorithm of the accelerator card under test is optimized using the optimal performance evaluation model to achieve performance optimization of the accelerator card under test.
2. The method for modeling and optimizing the performance of heterogeneous GPU accelerator cards based on sparse matrix-vector multiplication according to claim 1, characterized in that, The hardware parameters include the number of streaming multiprocessors or computing units.
3. The method for modeling and optimizing the performance of heterogeneous GPU accelerator cards based on sparse matrix-vector multiplication according to claim 1, characterized in that, The data features of the sparse matrix include the matrix's basic dimensions, row distribution features, column distribution features, and overall pattern.
4. A system for modeling and optimizing the performance of heterogeneous GPU accelerator cards based on sparse matrix-vector multiplication as described in any one of claims 1-3, characterized in that, include: The acquisition module is used to acquire the hardware parameters of the GPU heterogeneous accelerator card and determine the data characteristics of the sparse matrix. The processing module is used to associate the data features and the hardware parameters as a dataset, and to divide the dataset into a training set and a test set according to a certain ratio; The model analysis module is used to construct a performance evaluation model, and to train and test the performance evaluation model using the training set and the test set to obtain the optimal performance evaluation model. The optimization module is used to optimize the SpMV algorithm of the accelerator card under test using the optimal performance evaluation model, thereby achieving performance optimization of the accelerator card under test.