Display panel, display driving method and display device

Abstract

This application belongs to the field of display technology, specifically relating to a display panel, a display driving method, and a display device. The display panel includes a pixel driving circuit, which includes a first transistor, a second transistor, a third transistor, and a first capacitor. The control terminal of the first transistor is connected to the scan line of the nth row, its first terminal is connected to the data line of the mth column, and its second terminal is connected to the sub-pixel of the nth row and 2m-1th column. The first terminal of the second transistor is connected to the data line of the mth column, its second terminal is connected to the sub-pixel of the nth row and 2m-1th column, and its control terminal is connected to a first reset signal line. The first terminal of the third transistor is connected to the scan line of the n+1th row, and its second terminal is connected to the control terminal of the second transistor. The first terminal of the third transistor is unidirectionally conductive to the second terminal. The pixel driving circuit disclosed in this embodiment only requires N+1 scan lines to drive N rows of sub-pixels, significantly reducing the number of scan lines and lowering the manufacturing cost of the display panel and the scan driving circuit.

Description

Technical Field

[0001] This application belongs to the field of display technology, and specifically relates to a display panel, a display driving method, and a display device. Background Technology

[0002] Display devices may include liquid crystal displays (LCDs), electronic paper displays (e-paper), and organic light-emitting diode (OLED) displays. A display device includes a display panel, a scan driving circuit, and a data driving circuit. The scan driving circuit is connected to the scan lines of the display panel, and the data driving circuit is connected to the data lines of the display panel. Display panels typically employ a single-gate design, meaning each sub-pixel corresponds one-to-one with the intersection of the scan line and the data line.

[0003] To reduce the number of data lines and lower the manufacturing cost of the data driver circuit, some display panels employ a dual-gate design. In this design, two adjacent odd-numbered and even-numbered sub-pixels in each row share a single data line, which outputs the data signal (Vdata) to the two adjacent sub-pixels in a time-division multiplexing manner. With this dual-gate design, only M data lines are needed for 2M columns of sub-pixels, halving the number of data output channels in the data driver chip, thus reducing the manufacturing cost of the data driver circuit.

[0004] However, the shared data line outputs data signals to two adjacent sub-pixels in a time-division manner. The sub-pixels in adjacent odd-numbered columns and even-numbered columns in each row need to be connected to different scan lines, which doubles the number of scan lines and increases the manufacturing cost of the display panel and scan drive circuit. Summary of the Invention

[0005] The purpose of this application is to provide a display panel, a display driving method, and a display device to reduce the number of scan lines and lower the manufacturing cost of the display panel and the scan driving circuit.

[0006] To achieve the above objectives, this application provides a display panel including a plurality of pixel driving circuits arranged in an array, wherein the pixel driving circuits include:

[0007] The first transistor has a control terminal connected to the scan line in the nth row, a first terminal connected to the data line in the mth column, and a second terminal connected to the sub-pixel in the nth row and 2m-1th column.

[0008] The second transistor has a first terminal connected to the data line in the m-th column, a second terminal connected to the sub-pixel in the n-th row and 2m-th column, and a control terminal connected to a first reset signal line. The first reset signal line is used to turn on the second transistor in the n-th row before scanning the n-th row. The first transistor and the second transistor have different channel types.

[0009] The third transistor has a first terminal connected to the scan line of the (n+1)th row, and a second terminal connected to the control terminal of the second transistor. The third transistor is unidirectionally conductive from its first terminal to its second terminal.

[0010] The first capacitor is connected to the control terminal of the second transistor and the constant voltage power supply.

[0011] Optionally, the pixel driving circuit further includes a fourth transistor and a second capacitor. The control terminal of the fourth transistor is connected to the scan line in the nth row. The first terminal of the fourth transistor is connected to the second terminal of the second transistor. The second terminal of the fourth transistor is connected to the sub-pixel in the nth row and 2m column. The second capacitor is connected to the control terminal of the fourth transistor and the constant voltage power supply. The first transistor and the fourth transistor have the same channel type.

[0012] Optionally, the control terminal of the fourth transistor is connected to a second reset signal line, which is used to turn off the fourth transistor in the nth row before scanning the nth row.

[0013] Optionally, the pixel driving circuit further includes a fifth transistor, the first end of which is connected to the scan line of the nth row, the second end of which is connected to the control terminal of the fourth transistor, and the first end of the fifth transistor is unidirectionally conductive to the second end.

[0014] Optionally, the fifth transistor is a diode; or

[0015] The fifth transistor is a field-effect transistor, and the control terminal of the fifth transistor is connected to the scan line in the nth row. The first transistor and the fifth transistor have the same channel type.

[0016] Optionally, the third transistor is a diode; or

[0017] The third transistor is a field-effect transistor, and the control terminal of the third transistor is connected to the scan line in the (n+1)th row. The first transistor and the third transistor have the same channel type.

[0018] Optionally, the sub-pixel includes a liquid crystal capacitor, and the second terminals of the first transistor and the second transistor are connected to the pixel electrode of the liquid crystal capacitor; or

[0019] The sub-pixel includes a light-emitting diode, and the second terminal of the first transistor and the second terminal of the second transistor are connected to the anode of the light-emitting diode.

[0020] This application also provides a display driving method for driving the above-described display panel, the display driving method comprising:

[0021] Scan line by line and write the data signal into N rows of sub-pixels;

[0022] During the frame blanking phase after the last line scan is completed, the second transistors of all the pixel driving circuits are turned on via the first reset signal line.

[0023] Optionally, the pixel driving circuit further includes a fourth transistor and a second capacitor. The control terminal of the fourth transistor is connected to the scan line of the nth row. The first terminal of the fourth transistor is connected to the second terminal of the second transistor. The second terminal of the fourth transistor is connected to the sub-pixel in the nth row and 2m column. The second capacitor is connected to the control terminal of the fourth transistor and a constant voltage power supply. The control terminal of the fourth transistor is connected to a second reset signal line. The display driving method includes:

[0024] During the frame blanking phase after the last line scan is completed, the fourth transistor of all the pixel driving circuits is turned off via the second reset signal line.

[0025] This application also provides a display device, including:

[0026] The display panel;

[0027] A scan drive circuit is connected to the scan lines of the display panel;

[0028] The data driving circuit is connected to the data line of the display panel.

[0029] The display panel, display driving method, and display device disclosed in this application have the following beneficial effects:

[0030] In this application, the display panel includes multiple pixel driving circuits arranged in an array. Each pixel driving circuit includes a first transistor, a second transistor, a third transistor, and a first capacitor. The control terminal of the first transistor is connected to the scan line of the nth row, the first terminal of the first transistor is connected to the data line of the mth column, and the second terminal of the first transistor is connected to the sub-pixel of the nth row and 2m-1th column. The first terminal of the second transistor is connected to the data line of the mth column, and the second terminal of the second transistor is connected to the sub-pixel of the nth row and 2m-1th column. The control terminal of the second transistor is connected to a first reset signal line. The first terminal of the third transistor is connected to the scan line of the n+1th row, and the second terminal of the third transistor is connected to the control terminal of the second transistor. The first and second terminals of the third transistor are unidirectionally conductive. Using the pixel driving circuit disclosed in this embodiment, driving N rows of sub-pixels requires only N+1 scan lines. Compared with a single-gate-line design display panel, only one more scan line is added, significantly reducing the number of scan lines and lowering the manufacturing cost of the display panel and the scan driving circuit.

[0031] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0034] Figure 1 This is a schematic diagram of the pixel driving circuit in Embodiment 1 of this application.

[0035] Figure 2 This is a schematic diagram of the display panel structure in Embodiment 1 of this application.

[0036] Figure 3 This is a schematic diagram of a field-effect transistor in Embodiment 1 of this application.

[0037] Figure 4 This is a signal timing diagram of the pixel driving circuit in Embodiment 1 of this application.

[0038] Figure 5 This is a schematic diagram of the pixel driving circuit reset in Embodiment 1 of this application.

[0039] Figure 6This is a schematic diagram of the first data signal being written in Embodiment 1 of this application.

[0040] Figure 7 This is a schematic diagram of the second data signal writing in Embodiment 1 of this application.

[0041] Figure 8 This is a schematic diagram of the second data signal locking in Embodiment 1 of this application.

[0042] Figure 9 This is a schematic diagram of the display driving method in Embodiment 2 of this application.

[0043] Figure 10 This is a schematic diagram of the display device in Embodiment 3 of this application.

[0044] Explanation of reference numerals in the attached figures:

[0045] 100. Display panel; 110. Sub-pixel; 111. Pixel electrode; 112. Common electrode; 121. Scan line; 122. Data line; 123. First reset signal line; 124. Second reset signal line; 130. Pixel driving circuit; 131. First transistor; 132. Second transistor; 133. Third transistor; 134. Fourth transistor; 135. Fifth transistor; 136. First capacitor; 137. Second capacitor; 140. Constant voltage power supply;

[0046] 200. Scan drive circuit; 300. Data drive circuit. Detailed Implementation

[0047] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0048] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0049] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0050] Example 1

[0051] See Figure 1 and Figure 2 As shown, the display panel 100 includes multiple arrayed sub-pixels 110, with the sub-pixel array consisting of N rows and 2M columns, where N and M are both positive integers. The display panel 100 includes M data lines 122. In each row of sub-pixels 110, adjacent odd-numbered columns of sub-pixels 110 and even-numbered columns of sub-pixels 110 share one data line 122. The shared data line 122 outputs data signals to adjacent two sub-pixels 110 in a time-division manner.

[0052] In other words, in this embodiment, the display panel 100 adopts a dual-gate design, and only M data lines 122 are needed for the 2M columns of sub-pixels 110. Compared with the display panel 100 with a single-gate design, the dual-gate design of the display panel 100 reduces the number of data output channels of the data driver chip 300 by half, thereby reducing the manufacturing cost of the data driver circuit.

[0053] The display panel 100 also includes a plurality of pixel driving circuits 130 arranged in an array. In each row of sub-pixels 110, adjacent odd-numbered columns of sub-pixels 110 and even-numbered columns of sub-pixels 110 share a pixel driving circuit 130. The pixel driving circuit 130 array has a total of N rows and M columns.

[0054] The pixel driving circuit 130 includes a first transistor 131, a second transistor 132, a third transistor 133, and a first capacitor 136. The control terminal of the first transistor 131 is connected to the scan line 121 in the nth row, the first terminal of the first transistor 131 is connected to the data line 122 in the mth column, and the second terminal of the first transistor 131 is connected to the sub-pixel 110 in the nth row and 2m-1th column. n and m are both positive integers, where n is less than or equal to N and m is less than or equal to M.

[0055] The first terminal of the second transistor 132 is connected to the data line 122 of the m-th column, and the second terminal of the second transistor 132 is connected to the sub-pixel 110 of the n-th row and 2m-th column. The control terminal of the second transistor 132 is connected to the first reset signal line 123, which is used to turn on the second transistor 132 of the n-th row before scanning the n-th row. The first transistor 131 and the second transistor 132 have different channel types, that is, one of the first transistor 131 and the second transistor 132 is an N-type field-effect transistor and the other is a P-type field-effect transistor. This embodiment uses the example of the first transistor 131 being an N-type field-effect transistor for explanation. The principle is the same when the first transistor 131 is a P-type field-effect transistor, so it will not be described again.

[0056] The first terminal of the third transistor 133 is connected to the scan line 121 of the (n+1)th row, and the second terminal of the third transistor 133 is connected to the control terminal of the second transistor 132. The third transistor 133 is unidirectionally conductive from the first terminal to the second terminal. The first capacitor 136 is connected to the control terminal of the second transistor 132 and the constant voltage power supply 140, and the voltage of the constant voltage power supply 140 is Vss.

[0057] See Figures 4 to 8 As shown, when the pixel driving circuit 130 is working:

[0058] During the reset phase, the reset signal Vint1 output by the first reset signal line 123 is at a low level, the scan signal Scan(n+1) output by the scan line 121 of the n+1th row is at a low level, the first capacitor 136 discharges and its voltage drops, keeping the second transistor 132 on, the scan signal Scan(n) output by the scan line 121 of the nth row is at a low level, and the first transistor 131 is off.

[0059] In the first writing stage, the scan signal output by the scan line 121 of the nth row is high, the first transistor 131 is turned on, and the data line 122 of the mth column writes the first data signal (data1) into the sub-pixel 110 of the odd-numbered column.

[0060] In the second writing stage, the scan signal output by the scan line 121 of the nth row is low, the first transistor 131 is turned off to lock the first data signal, and the data line 122 of the mth column writes the second data signal (data2) into the sub-pixel 110 of the even-numbered column.

[0061] During the locking phase, the scan signal output by the scan line 121 of the (n+1)th row is at a high level, the first capacitor 136 is charged and its voltage increases, and the second transistor 132 is turned off to lock the second data signal.

[0062] In some technical solutions, the display panel 100 adopts a dual-line design, where the sub-pixels 110 of adjacent odd-numbered columns and the sub-pixels 110 of even-numbered columns in each row need to be connected to different scan lines 121, which doubles the number of scan lines 121 and increases the manufacturing cost of the scan driving circuit 200.

[0063] In this embodiment, the display panel 100 includes multiple pixel driving circuits 130 arranged in an array. Each pixel driving circuit 130 includes a first transistor 131, a second transistor 132, a third transistor 133, and a first capacitor 136. The control terminal of the first transistor 131 is connected to the scan line 121 of the nth row, the first end of the first transistor 131 is connected to the data line 122 of the mth column, and the second end of the first transistor 131 is connected to the sub-pixel 110 of the nth row and 2m-1th column. The first end of the second transistor 132 is connected to the data line 122 of the mth column, and the second end of the second transistor 132 is connected to the sub-pixel 110 of the nth row and 2mth column. The control terminal of the second transistor 132 is connected to the first reset signal line 123. The first end of the third transistor 133 is connected to the scan line 121 of the n+1th row, and the second end of the third transistor 133 is connected to the control terminal of the second transistor 132. The first end of the third transistor 133 is unidirectionally conductive from the second end to the first end. Using the pixel driving circuit 130 disclosed in this embodiment, driving N rows of sub-pixels 110 only requires N+1 rows of scan lines 121. Compared with the display panel 100 with a single gate line design, only one scan line 121 is added, which greatly reduces the number of scan lines 121 and reduces the manufacturing cost of the display panel 100 and the scan driving circuit 200.

[0064] See Figure 1 As shown, the third transistor 133 is a diode, with its first terminal being the anode and its second terminal being the cathode.

[0065] The third transistor 133 is a diode. The diode conducts in one direction, which can prevent the first capacitor 136 from discharging and causing the voltage at the control terminal of the second transistor 132 to drop when the scan signal of the scan line 121 of the (n+1)th row is low. This would cause the second transistor 132 to turn on, and the data signals of other rows to be written to the sub-pixel 110 controlled by the second transistor 132.

[0066] It should be noted that the third transistor 133 can be a diode, but is not limited to this; the third transistor 133 can also be a field-effect transistor. The control terminal of the third transistor 133 is connected to the scan line 121 of the (n+1)th row, as shown below. Figure 3 As shown. The first transistor 131 and the third transistor 133 have the same channel type.

[0067] The third transistor 133 is a field-effect transistor. When the scan signal output from the scan line 121 in the (n+1)th row is high, the third transistor 133 is turned on, the first capacitor 136 is charged and its voltage increases, and the second transistor 132 is turned off to lock the second data signal. When the scan signal output from the scan line 121 in the (n+1)th row is low, the third transistor 133 is turned off to prevent the charge stored in the first capacitor 136 from being released to the scan line 121 in the (n+1)th row through the third transistor 133.

[0068] In some embodiments, the pixel driving circuit 130 further includes a fourth transistor 134 and a second capacitor 137. The control terminal of the fourth transistor 134 is connected to the scan line 121 of the nth row, the first terminal of the fourth transistor 134 is connected to the second terminal of the second transistor 132, and the second terminal of the fourth transistor 134 is connected to the sub-pixel 110 of the nth row and 2m column. The second capacitor 137 is connected to the control terminal of the fourth transistor 134 and the constant voltage power supply 140. The first transistor 131 and the fourth transistor 134 have the same channel type.

[0069] During the first writing stage, the scan signal output by the scan line 121 in the nth row is high, the first transistor 131 is turned on, and the data line 122 in the mth column writes the first data signal into the odd-numbered sub-pixels 110. Simultaneously, the scan signal output by the scan line 121 in the nth row also charges the second capacitor 137, causing the voltage at the control terminal of the fourth transistor 134 to rise. By controlling the charging time of the second capacitor 137 to be equal to the high-level time, the fourth transistor 134 can be turned on only after the first data signal has been written into the odd-numbered sub-pixels 110. This design avoids writing the first data signal into the even-numbered sub-pixels 110, reducing the power consumption of the display panel 100.

[0070] It should be noted that the charging time of the second capacitor 137 can also be controlled to enable the fourth transistor 134 before the first data signal is written. This design allows the first data signal to pre-charge the even-numbered sub-pixels 110, preventing insufficient charging of these sub-pixels. Simultaneously, the charging time of the even-numbered sub-pixels 110 can be appropriately shortened; that is, the interval between the high level of the scan signal in the nth row and the high level of the scan signal in the (n+1)th row can be appropriately shortened. In other words, the high level time of the scan signal and the interval between the high levels of adjacent rows can be different.

[0071] In some embodiments, the control terminal of the fourth transistor 134 is connected to the second reset signal line 124, which is used to turn off the fourth transistor 134 of the nth row before scanning the nth row.

[0072] Discharging the second capacitor 137 via the second reset signal line 124 allows for more precise control of the turn-off time of the fourth transistor 134 compared to discharging the second capacitor 137 via the leakage current of the fourth transistor 134.

[0073] It should be noted that the fourth transistor 134 can be turned off immediately after the second data signal is written, or it can be turned off after a delay. The delay in turning off the fourth transistor 134 after the second data signal is written allows for a shorter charging time for the first capacitor 136. Simultaneously, the writing of the third data signal (data3) from the m-th column data line 122 to the (n+1)-th row can be delayed compared to the high level of the (n+1)-th row scan signal, preventing the third data signal from being written to the sub-pixel 110 of the n-th row.

[0074] In some embodiments, the pixel driving circuit 130 further includes a fifth transistor 135, the first end of which is connected to the scan line 121 of the nth row, the second end of which is connected to the control terminal of the fourth transistor 134, and the first end of the fifth transistor 135 is unidirectionally conductive to the second end.

[0075] The fifth transistor 135 is unidirectionally conductive from the first terminal to the second terminal, which prevents the charge stored in the second capacitor 137 from being released through the scan line 121 of the nth row, causing the fourth transistor 134 to turn off before the second data signal is written.

[0076] In some embodiments, the fifth transistor 135 is a diode, with its first terminal being the anode and its second terminal being the cathode.

[0077] The fifth transistor 135 is a diode. The diode conducts in one direction, which can prevent the second capacitor 137 from discharging when the scan signal of the scan line 121 of the nth row is at a low level, causing the control terminal voltage of the fourth transistor 134 to drop, which in turn causes the fourth transistor 134 to turn off prematurely and affect the writing of the second data signal to the sub-pixel 110 controlled by the fourth transistor 134.

[0078] It should be noted that the fifth transistor 135 can be a diode, but is not limited to this; the fifth transistor 135 can also be a field-effect transistor. The control terminal of the fifth transistor 135 is connected to the scan line 121 of the nth row, as shown below. Figure 3 As shown. The first transistor 131 and the fifth transistor 135 have the same channel type.

[0079] In some embodiments, the sub-pixel 110 includes a liquid crystal capacitor, which includes a pixel electrode 111 and a common electrode 112. The second terminal of the first transistor 131 and the second terminal of the second transistor 132 are connected to the pixel electrode 111 of the liquid crystal capacitor. When the pixel driving circuit 130 includes a fourth transistor 134, the second transistor 132 is connected to the pixel electrode 111 through the fourth transistor 134.

[0080] The sub-pixel 110 may also include a light-emitting diode (LED), with the second terminal of the first transistor 131 and the second terminal of the second transistor 132 connected to the anode of the LED.

[0081] Sub-pixels 110 include liquid crystal capacitors, meaning the display panel 100 can be a liquid crystal display panel; sub-pixels 110 also include light-emitting diodes, meaning the display panel 100 can be an LED display panel. In other words, the pixel driving circuit 130 can be used with different types of display panels 100.

[0082] In summary, when the pixel driving circuit 130 is working:

[0083] During the reset phase, the reset signal Vint1 output by the first reset signal line 123 is at a low level, the scan signal output by the scan line 121 of the (n+1)th row is at a low level, the first capacitor 136 discharges and its voltage drops, keeping the second transistor 132 on, the reset signal Vint2 output by the second reset signal line 124 is at a low level, the fourth transistor 134 is off, the scan signal output by the scan line 121 of the nth row is at a low level, and the first transistor 131 is off.

[0084] In the first writing stage, the scan signal output by the scan line 121 of the nth row is high, the first transistor 131 is turned on, the data line 122 of the mth column writes the first data signal into the sub-pixel 110 of the odd-numbered column, and at the same time the scan signal charges the second capacitor 137, and the voltage at the control terminal of the fourth transistor 134 increases.

[0085] In the second writing stage, the scan signal output by the scan line 121 of the nth row is low, the first transistor 131 is turned off to lock the first data signal, the second capacitor 137 turns on the fourth transistor 134, and the data line 122 of the mth column writes the second data signal into the sub-pixel 110 of the even-numbered column.

[0086] During the locking phase, the scan signal output by the scan line 121 of the (n+1)th row is at a high level, the first capacitor 136 is charged and its voltage increases, and the second transistor 132 is turned off to lock the second data signal.

[0087] Similarly, the scan signal Scan(n+1) of the scan line 121 in the (n+1)th row and the scan signal Scan(n+2) of the scan line 121 in the (n+2)th row can control the pixel driving circuit 130 in the (n+1)th row to write the third data signal and the fourth data signal (data4). In other words, only N+1 scan lines 121 are needed to drive N rows of sub-pixels 110.

[0088] Example 2

[0089] In this embodiment, the display driving method is used to drive the display panel 100 disclosed in Embodiment 1. See also... Figure 9 As shown, the display driving method includes:

[0090] S100: Scan line by line and write the data signal to N rows of sub-pixels 110;

[0091] S200: During the frame blanking (VBK) stage after the last line of scanning is completed, the second transistor 132 of the entire pixel driving circuit 130 is turned on by the first reset signal line 123.

[0092] During the frame blanking phase, the second transistor 132 controlling all pixel driving circuits 130 is turned on, resetting all pixel driving circuits 130. When displaying the next frame, line-by-line scanning writes data voltage to N rows of sub-pixels 110, thus displaying one frame. Since the second transistors 132 of all pixel driving circuits 130 are turned on during the frame blanking phase, it is unnecessary to set a separate first reset signal line 123 for each row of pixel driving circuits 130, reducing the manufacturing cost of the display panel 100 and the scanning driving circuit 200.

[0093] In some embodiments, the pixel driving circuit 130 further includes a fourth transistor 134 and a second capacitor 137. The control terminal of the fourth transistor 134 is connected to the scan line 121 of the nth row, the first terminal of the fourth transistor 134 is connected to the second terminal of the second transistor 132, and the second terminal of the fourth transistor 134 is connected to the sub-pixel 110 of the nth row and 2m column. The second capacitor 137 is connected to the control terminal of the fourth transistor 134 and the constant voltage power supply 140. The first transistor 131 and the fourth transistor 134 have the same channel type. The control terminal of the fourth transistor 134 is connected to the second reset signal line 124.

[0094] The display driving method includes, in step S200: during the frame blanking stage after the last line scan is completed, the fourth transistor 134 of the entire pixel driving circuit 130 is turned off by the second reset signal line 124.

[0095] The scan signal output from scan line 121 in the nth row charges the second capacitor 137, causing the voltage at the control terminal of the fourth transistor 134 to rise. By controlling the charging time of the second capacitor 137 to be equal to the high-level time, the fourth transistor 134 can be turned on only after the first data signal is written to the odd-numbered sub-pixels 110. This design avoids the first data signal being written to the even-numbered sub-pixels 110, thus reducing the power consumption of the display panel 100.

[0096] During the frame blanking stage, the fourth transistor 134 of all pixel driving circuits 130 is turned off, which prevents the data voltage of the previous row from being written to the sub-pixels 110 of the following row, thereby reducing the power consumption of the display panel 100. Since the fourth transistor 134 of all pixel driving circuits 130 is turned off by the reset signal Vint2 during the frame blanking stage, it is not necessary to set up a separate second reset signal line 124 for each row of pixel driving circuits 130, thus reducing the manufacturing cost of the display panel 100 and the scan driving circuit 200.

[0097] Example 3

[0098] See Figure 10 As shown, the display device in this embodiment includes the display panel 100, the scanning drive circuit 200 and the data drive circuit 300 disclosed in Embodiment 1. The scanning drive circuit 200 is connected to the scan line 121 of the display panel 100, and the data drive circuit 300 is connected to the data line 122 of the display panel 100.

[0099] The display device includes a display panel 100, which includes multiple pixel driving circuits 130 arranged in an array. Each pixel driving circuit 130 includes a first transistor 131, a second transistor 132, a third transistor 133, and a first capacitor 136. The control terminal of the first transistor 131 is connected to the scan line 121 in the nth row, the first end of the first transistor 131 is connected to the data line 122 in the mth column, and the second end of the first transistor 131 is connected to the sub-pixel 110 in the nth row and 2m-1th column. The first end of the second transistor 132 is connected to the data line 122 in the mth column, and the second end of the second transistor 132 is connected to the sub-pixel 110 in the nth row and 2m-1th column. The control terminal of the second transistor 132 is connected to a first reset signal line 123. The first end of the third transistor 133 is connected to the scan line 121 in the n+1th row, and the second end of the third transistor 133 is connected to the control terminal of the second transistor 132. The first end of the third transistor 133 is unidirectionally conductive from the second end to the first end. Using the pixel driving circuit 130 disclosed in this embodiment, driving N rows of sub-pixels 110 only requires N+1 rows of scan lines 121. Compared with the display panel 100 with a single gate line design, only one scan line 121 is added, which greatly reduces the number of scan lines 121 and reduces the manufacturing cost of the display panel 100, the scan driving circuit 200 and the display device.

[0100] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0101] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0102] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0103] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A display panel comprising a plurality of pixel driving circuits arranged in an array, characterized in that, The pixel driving circuit includes: The first transistor has a control terminal connected to the scan line in the nth row, a first terminal connected to the data line in the mth column, and a second terminal connected to the sub-pixel in the nth row and 2m-1th column. The second transistor has a first terminal connected to the data line in the m-th column, a second terminal connected to the sub-pixel in the n-th row and 2m-th column, and a control terminal connected to a first reset signal line. The first reset signal line is used to turn on the second transistor in the n-th row before scanning the n-th row. The first transistor and the second transistor have different channel types. The third transistor has a first terminal connected to the scan line of the (n+1)th row, and a second terminal connected to the control terminal of the second transistor. The third transistor is unidirectionally conductive from its first terminal to its second terminal. The first capacitor is connected to the control terminal of the second transistor and the constant voltage power supply. When the pixel driving circuit operates: during the reset phase, the first reset signal line signal and the scan line signal in the (n+1)th row turn on the second transistor; during the first write phase, the scan line signal in the nth row turns on the first transistor, and the data line in the mth column writes the first data signal to the sub-pixels in the odd-numbered columns; during the second write phase, the scan line signal in the nth row turns off the first transistor, and the data line in the mth column writes the second data signal to the sub-pixels in the even-numbered columns; during the locking phase, the scan line signal in the (n+1)th row turns off the second transistor to lock the second data signal.

2. The display panel according to claim 1, characterized in that, The pixel driving circuit further includes a fourth transistor and a second capacitor. The control terminal of the fourth transistor is connected to the scan line in the nth row. The first terminal of the fourth transistor is connected to the second terminal of the second transistor. The second terminal of the fourth transistor is connected to the sub-pixel in the nth row and 2m column. The second capacitor is connected to the control terminal of the fourth transistor and the constant voltage power supply. The first transistor and the fourth transistor have the same channel type.

3. The display panel according to claim 2, characterized in that, The control terminal of the fourth transistor is connected to the second reset signal line, which is used to turn off the fourth transistor in the nth row before scanning the nth row.

4. The display panel according to claim 2, characterized in that, The pixel driving circuit further includes a fifth transistor, the first end of which is connected to the scan line of the nth row, the second end of which is connected to the control terminal of the fourth transistor, and the fifth transistor is unidirectionally conductive from the first end to the second end.

5. The display panel according to claim 4, characterized in that, The fifth transistor is a diode; or The fifth transistor is a field-effect transistor, and the control terminal of the fifth transistor is connected to the scan line in the nth row. The first transistor and the fifth transistor have the same channel type.

6. The display panel according to claim 1, characterized in that, The third transistor is a diode; or The third transistor is a field-effect transistor, and the control terminal of the third transistor is connected to the scan line in the (n+1)th row. The first transistor and the third transistor have the same channel type.

7. The display panel according to claim 1, characterized in that, The sub-pixel includes a liquid crystal capacitor, and the second terminals of the first transistor and the second transistor are connected to the pixel electrode of the liquid crystal capacitor; or The sub-pixel includes a light-emitting diode, and the second terminal of the first transistor and the second terminal of the second transistor are connected to the anode of the light-emitting diode.

8. A display driving method for driving a display panel as described in any one of claims 1 to 7, characterized in that, The display driving method includes: Scan line by line and write the data signal into N rows of sub-pixels; During the frame blanking phase after the last line scan is completed, the second transistors of all the pixel driving circuits are turned on via the first reset signal line.

9. The display driving method according to claim 8, characterized in that, The pixel driving circuit further includes a fourth transistor and a second capacitor. The control terminal of the fourth transistor is connected to the scan line of the nth row. The first terminal of the fourth transistor is connected to the second terminal of the second transistor. The second terminal of the fourth transistor is connected to the sub-pixel in the nth row and 2m column. The second capacitor is connected to the control terminal of the fourth transistor and a constant voltage power supply. The control terminal of the fourth transistor is connected to a second reset signal line. The display driving method includes: During the frame blanking phase after the last line scan is completed, the fourth transistor of all the pixel driving circuits is turned off via the second reset signal line.

10. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 7; A scan drive circuit is connected to the scan lines of the display panel; The data driving circuit is connected to the data line of the display panel.

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