Display panel and display device

Abstract

The application provides a display panel and a display device; by making the mobility of the first voltage stabilizing transistor less than the mobility of the first pull-down control transistor, i.e., the mobility of the first voltage stabilizing transistor is small, the on-state current of the first voltage stabilizing transistor is reduced, the potential of the first type of level source transmitted to the pull-up node through the first voltage stabilizing transistor is reduced, and the technical problem that the potential of the pull-up node cannot be pulled down to a preset low potential is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) display panels include gate driving circuits and pixel driving circuits. The gate driving circuit is used to output control signals to the transistors in the pixel driving circuit.

[0003] Current gate drive circuits include multiple transistors connected to pull-up nodes to raise or lower the potential of the pull-up nodes. However, because some transistors are more capable of receiving high-level source signals than others, the pull-up nodes cannot be pulled down to the target low potential, resulting in abnormal control signals output by the gate drive circuit. Summary of the Invention

[0004] This application provides a display panel and display device to solve the technical problem of abnormal control signals output by existing gate drive circuits.

[0005] This application provides a display panel, which includes a gate driving circuit, the gate driving circuit comprising:

[0006] The pull-up control module is electrically connected to the pull-up node;

[0007] A pull-up module, wherein the control terminal of the pull-up module is electrically connected to the pull-up node, and the output terminal of the pull-up module is electrically connected to the output terminal of the gate drive circuit;

[0008] A pull-down module, wherein the control terminal of the pull-down module is electrically connected to the pull-down node, and the output terminal of the pull-down module is electrically connected to the output terminal of the gate drive circuit;

[0009] A pull-down control module includes a first pull-down control transistor, the input terminal of which is electrically connected to a first type of level source, and the output terminal of which is electrically connected to the pull-down node.

[0010] A voltage stabilization module includes a first Zener transistor, the gate of which is electrically connected to the pull-down node, the input of which is electrically connected to the first type of voltage source, and the output of which is electrically connected to the pull-up node.

[0011] The mobility of the first Zener transistor is less than that of the first pull-down control transistor.

[0012] This application provides a display device, which includes the display panel described above.

[0013] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0016] Figure 1 This is a first structural diagram of the display panel of this application.

[0017] Figure 2 This is a structural diagram of the pixel driving circuit in the display panel of this application.

[0018] Figure 3 This is a second structural diagram of the display panel in this application.

[0019] Figure 4 This is a first structural diagram of the gate driving circuit in the display panel of this application.

[0020] Figure 5 This is a diagram of the film structure in the display panel of this application.

[0021] Figure 6 This is a diagram showing the film stacking of the first gate circuit in the first gate circuit of this application.

[0022] Figure 7 This is a film diagram of the first active layer in the first gate circuit of this application.

[0023] Figure 8 This is a film diagram of the second active layer in the first gate circuit of this application.

[0024] Figure 9 This is a stacked diagram of the first active layer, the second active layer, and the first gate layer in the first gate circuit of this application.

[0025] Figure 10 This is a film diagram of the third gate layer in the first gate circuit of this application.

[0026] Figure 11 This is a film layer diagram of the fourth gate layer in the first gate circuit of this application.

[0027] Figure 12 This is a stacked diagram of the first active layer, second active layer, first gate layer, third gate layer and fourth gate layer in the first gate circuit of this application.

[0028] Figure 13 This is a film diagram of the first source-drain layer in the first gate circuit of this application.

[0029] Figure 14 This is a stacked diagram of the first active layer, second active layer, first gate layer, third gate layer, fourth gate layer and first source / drain layer in the first gate circuit of this application.

[0030] Figure 15 This is a first type of film layer diagram of the second source / drain layer in the first gate circuit of this application.

[0031] Figure 16 This is a first type of film layer stack diagram of the first active layer, second active layer, first gate layer, third gate layer, fourth gate layer, first source-drain layer and second source-drain layer in the first gate circuit of this application.

[0032] Figure 17 This is a second structural diagram of the gate driving circuit in the display panel of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0034] Please see Figures 1 to 17 This application proposes a display panel 100, which includes a gate driving circuit 300, the gate driving circuit 300 including a pull-up control module 311, a pull-up module 312, a pull-down module 313, a pull-down control module 314 and a voltage stabilization module 315.

[0035] In this embodiment, the pull-up control module 311 is electrically connected to the pull-up node Q; the control terminal of the pull-up module 312 is electrically connected to the pull-up node Q, and the output terminal of the pull-up module 312 is electrically connected to the output terminal of the gate drive circuit 300; the control terminal of the pull-down module 313 is electrically connected to the pull-down node P, and the output terminal of the pull-down module 313 is electrically connected to the output terminal of the gate drive circuit 300.

[0036] In this embodiment, the pull-down control module 314 includes a first pull-down control transistor T2, the input terminal of the first pull-down control transistor T2 is electrically connected to a first type of level source, and the output terminal of the first pull-down control transistor T2 is electrically connected to the pull-down node P;

[0037] In this embodiment, the voltage stabilization module 315 includes a first Zener transistor T4, the gate of the first Zener transistor T4 is electrically connected to the pull-down node P, the input terminal of the first Zener transistor T4 is electrically connected to the first level source, and the output terminal of the first Zener transistor T4 is electrically connected to the pull-up node Q.

[0038] In this embodiment, the mobility of the first Zener transistor T4 is less than the mobility of the first pull-down control transistor T2.

[0039] This application improves the technical problem that the potential of the pull-up node Q cannot be pulled down to a preset low potential by making the mobility of the first Zener transistor T4 less than that of the first pull-down control transistor T2, i.e., making the mobility of the first Zener transistor T4 smaller. This reduces the on-state current of the first Zener transistor T4, thereby reducing the potential of the first type of level source transmitted to the pull-up node Q through the first Zener transistor T4.

[0040] It should be noted that the first type of level source is either a high-level source or a low-level source. The following embodiment will be described using the first type of level source as a high-level source as an example.

[0041] The technical solution of this application will now be described in conjunction with specific embodiments.

[0042] Please see Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA has multiple rows of sub-pixels PL. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that implement its display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in displaying information.

[0043] Please see Figure 1 A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data trace, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0044] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits (PCs) for driving the LEDs can be arrayed within the display area AA. The pixel driving circuit PC can be aTbC, where a is greater than or equal to 2 and b is greater than or equal to 1. The following description uses a 6T1C pixel driving circuit PC as an example.

[0045] Please see Figure 2 The pixel driving circuit PC may include a switching transistor T2A, a driving transistor T1A, a compensation transistor T3A, a reset transistor T4A, a first light-emitting transistor T5A, a second light-emitting transistor T6A, and a storage capacitor Cst.

[0046] Please see Figure 2 The first electrode of switching transistor T2A is connected to the data signal line Data, and the second electrode of switching transistor T2A is connected to the control node Ba. The gate of switching transistor T2A receives the switching control signal Nscan1. The first electrode of driving transistor T1A is connected to the control node Aa, the second electrode of driving transistor T1A is connected to the control node Ba, and the gate of driving transistor T1A is connected to the control node Qa. The first electrode of compensation transistor T3A is connected to the control node Aa, the second electrode of compensation transistor T3A is connected to the control node Qa, and the gate of compensation transistor T3A receives the compensation control signal Nscan2. The first electrode of reset transistor T4A receives the reset signal Vi, and the second electrode of reset transistor T4A is connected to the control node Ca. The gate of reset transistor T4A receives the second light-emitting control signal EM2; the first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to the control node Aa, and the gate of the first light-emitting transistor T5A receives the first light-emitting control signal EM1; the first electrode of the second light-emitting transistor T6A is connected to the control node Ba, the second electrode of the second light-emitting transistor T6A is connected to the control node Ca, and the gate of the second light-emitting transistor T6A receives the second light-emitting control signal EM2; one end of the storage capacitor Cst is connected to the control node Qa, and the other end of the storage capacitor Cst is connected to the control node Ca; the anode of the light-emitting device LED is connected to the control node Ca, and the cathode of the light-emitting device LED is connected to the low-level source VSS.

[0047] In this embodiment, the high-level source VDD is used to provide a constant high voltage to the pixel driving circuit PC, and the low-level source VSS is used to provide a constant low voltage to the pixel driving circuit PC.

[0048] In this embodiment, the switching transistor T2A, driving transistor T1A, compensation transistor T3A, and reset transistor T4A can be either P-type or N-type transistors, and the first light-emitting transistor T5A and the second light-emitting transistor T6A can be either P-type or N-type transistors. For example, in this application, the switching transistor T2A, driving transistor T1A, compensation transistor T3A, and reset transistor T4A are N-type transistors, and the first light-emitting transistor T5A and the second light-emitting transistor T6A are P-type transistors. That is, the effective level of the switching transistor T2A, driving transistor T1A, compensation transistor T3A, and reset transistor T4A is high, and the effective level of the first light-emitting transistor T5A and the second light-emitting transistor T6A is low.

[0049] In this embodiment, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain.

[0050] In this embodiment, the first light-emitting transistor T5A and the second light-emitting transistor T6A can be composed of at least two transistors connected in series to reduce the leakage current of the first light-emitting transistor T5A and the second light-emitting transistor T6A.

[0051] In this embodiment, the second direction Y is parallel to the scan line of the display panel 100, and the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°.

[0052] Please see Figure 3 The gate driving circuit 300 is disposed within the non-display area NA, and the gate driving circuit 300 can also be disposed on both sides of the display area AA; the gate driving circuit 300 may include N cascaded gate driving units 300a, and the multiple gate driving units 300a can be arranged along the first direction X. The structure of the gate driving unit 300a can be various, for example in... Figure 3 In the structure, the gate driving unit 300a may include a plurality of first gate circuits 310 arranged and cascaded along the first direction X, a plurality of second gate circuits 320 arranged and cascaded along the first direction X, and a plurality of third gate circuits 330 arranged and cascaded along the first direction X.

[0053] Please see Figure 3 The first gate circuit 310 is located on one side of the display area AA. The first gate circuit 310 is used to output a switch control signal Nscan1 to a row of sub-pixels PL, that is, the row of pixel driving circuit PC needs a first gate circuit 310.

[0054] Please see Figure 3The second gate circuit 320 is located on the side of the first gate circuit 310 away from the display area AA. The second gate circuit 320 is used to output the compensation control signal Nscan2 to the two rows of sub-pixels PL, that is, the two rows of pixel driving circuits PC need one stage of the second gate circuit 320.

[0055] Please see Figure 3 The third gate circuit 330 is located on the side of the second gate circuit 320 away from the display area AA. The third gate circuit 330 is used to output the first light emission control signal EM1 or the second light emission control signal EM2 to the two rows of sub-pixels PL. That is, the two rows of pixel driving circuits PC require one stage of the third gate circuit 330. For example, the third gate circuit 330 located on one side of the display area AA is used to output the first light emission control signal EM1, and the third gate circuit 330 located on the other side of the display area AA is used to output the second light emission control signal EM2.

[0056] It should be noted that the reset signal Vi is a constant voltage, which does not require the corresponding gate drive circuit 300 to control it, and can be directly connected to the corresponding constant voltage source.

[0057] It should be noted that the positions of the first gate circuit 310, the second gate circuit 320, and the third gate circuit 330 in this application can be changed. For example, the second gate circuit 320, the third gate circuit 330, and the first gate circuit 310 can be arranged along the second direction Y, the third gate circuit 330, the second gate circuit 320, and the first gate circuit 310 can be arranged along the second direction Y, and the third gate circuit 330, the first gate circuit 310, and the second gate circuit 320 can be arranged along the second direction Y.

[0058] In this embodiment, the first gate circuit 310, the second gate circuit 320, and the third gate circuit 330 of this application can be mTnC gate circuits. In the following embodiment, the structure of the gate driving unit 300a of this application will be described using an 8T1C first gate circuit as an example.

[0059] Please see Figure 4 The first gate circuit 310 includes a signal generation module 310a and an output module 310b. The signal generation module 310a may include a pull-up control module 311, a pull-down control module 313 and a voltage stabilization module 315. The output module 310b may include a pull-up module 312 and a pull-down module 314. The clock signal line is connected to the pull-up module 312 and the constant voltage signal line is connected to the pull-down module 314.

[0060] Please see Figure 4The control terminal of the pull-up control module 311 is electrically connected to the corresponding first-type clock line XCK for transmitting pull-up control signals, and the output terminal of the pull-up control module 311 is electrically connected to the corresponding pull-up node Q.

[0061] Please see Figure 4 The input terminal of the pull-up module 312 is electrically connected to the corresponding clock signal line (hereinafter referred to as the second type clock line CK) for transmitting the pull-up signal. The control terminal of the pull-up module 312 is electrically connected to the corresponding pull-up node Q. The output terminal of the pull-up module 312 is electrically connected to the output terminal OUT of the first gate circuit 310, and the output terminal OUT of the first gate circuit 310 is connected to the gate of the switching transistor T2A, which is equivalent to the output module 310b and the gate of the switching transistor T2A being connected.

[0062] Please see Figure 4 The control terminal of the pull-down control module 313 is electrically connected to the output terminal of the pull-up control module 311 (i.e., the pre-pull-up node K), and the output terminal of the pull-down control module 313 is electrically connected to the corresponding pull-down node P.

[0063] Please see Figure 4 The input terminal of the pull-down module 314 is electrically connected to the corresponding second-type level source for transmitting pull-down signals. The control terminal of the pull-down module 314 is electrically connected to the corresponding pull-down node P. The output terminal of the pull-down module 314 is electrically connected to the output terminal OUT of the first gate circuit 310.

[0064] Please see Figure 4 The control terminal of the voltage stabilization module 315 is electrically connected to the corresponding pull-down node P, and the output terminal of the voltage stabilization module 315 is electrically connected to the corresponding pull-up node Q.

[0065] It should be noted that the second type of level source is either a high-level source or a low-level source. This application will use the example of the second type of level source being a low-level source for illustration.

[0066] Please see Figure 4 The pull-up control module 311 includes a pull-up control transistor T1. The input terminal of the pull-up control transistor T1 is connected to the initial signal line or the output terminal OUT of the previous stage first gate circuit 310, and the output terminal of the pull-up control transistor T1 is connected to the pre-pull-up node K. The pull-up control transistor T1 can be a single-control terminal or dual-control terminal structure, for example... Figure 4 The control terminals of the pull-up control transistor T1 include the first gate and the second gate of the pull-up control transistor T1. Both control terminals of the pull-up control transistor T1 are connected to the first type clock line XCK.

[0067] Please see Figure 4 The pull-up module 312 includes a pull-up transistor T5 and a first capacitor C1. The input terminal of the pull-up transistor T5 is connected to a second type of signal line, and the input terminal of the pull-up transistor T5 is connected to the output terminal OUT of the first gate circuit 310. The pull-up transistor T5 can be a single-control terminal or a dual-control terminal structure, for example... Figure 4 The control terminals of the pull-up transistor T5 include the first gate of the pull-up transistor T5 and the second gate of the pull-up control transistor T1. Both control terminals of the pull-up transistor T5 are connected to the pull-up node Q. The first plate C1a of the first capacitor C1 is connected to the pull-up node Q, and the second plate C1b of the first capacitor C1 is connected to the output terminal OUT of the first gate circuit 310.

[0068] Please see Figure 4 The pull-down control module 313 includes a first pull-down control transistor T2 and a second pull-down control transistor T3. The control terminal of the first pull-down control transistor T2 is connected to the pre-pull-up node K, the input terminal of the first pull-down control transistor T2 is connected to a first-type level source, and the output terminal of the first pull-down control transistor T2 is connected to the pull-down node P. The input terminal of the second pull-down control transistor T3 is connected to a second-type level source, and the output terminal of the second pull-down control transistor T3 is connected to the pull-down node P. The second pull-down control transistor T3 can be a single-control-terminal or dual-control-terminal structure, for example... Figure 4 The control terminals of the second pull-down control transistor T3 include the first gate of the second pull-down control transistor T3 and the second gate of the second pull-down control transistor T3. Both control terminals of the second pull-down control transistor T3 can be connected to the pre-pull-up node K.

[0069] Please see Figure 4 The pull-down module 314 includes a pull-down transistor T6. The input terminal of the pull-down transistor T6 is connected to a second type of level source, and the output terminal of the pull-down transistor T6 is connected to the output terminal OUT of the first gate circuit 310. The pull-down transistor T6 can be a single-control terminal or a dual-control terminal structure, for example... Figure 4 The control terminal of the pull-down transistor T6 includes the first gate and the second gate of the pull-down transistor T6. The first gate of the pull-down transistor T6 is connected to the pull-down node P, and the second gate of the pull-down transistor T6 is connected to the second type of level source.

[0070] Please see Figure 4The voltage stabilization module 315 includes a first Zener transistor T4, a second Zener transistor T7, and a third Zener transistor T8. The input terminal of the first Zener transistor T4 is connected to a first-class voltage source, the output terminal of the first Zener transistor T4 is connected to a pre-pull-up node K, and the control terminal of the first Zener transistor T4 is connected to a pull-down node P. The control terminal of the second Zener transistor T7 is connected to a first-class voltage source, the input terminal of the second Zener transistor T7 is connected to the pre-pull-up node K, and the output terminal of the second Zener transistor T7 is connected to a pull-up node Q. The input terminal of the third Zener transistor T8 is connected to a second-class voltage source, and the output terminal of the third Zener transistor T8 is connected to the pull-up node Q. The third Zener transistor T8 can be a single-control terminal or a dual-control terminal structure, for example... Figure 4 The control terminal of the third Zener transistor T8 includes the first gate and the second gate of the third Zener transistor T8. Both the first gate and the second gate of the third Zener transistor T8 are connected to the pull-down node P.

[0071] Specifically, the transistor types of pull-up control transistor T1, first pull-down control transistor T2, second pull-down control transistor T3, first Zener transistor T4, pull-up transistor T5, pull-down transistor T6, second Zener transistor T7, and third Zener transistor T8 can be either silicon semiconductor transistors or oxide semiconductor transistors. For example, the first pull-down control transistor T2 and the first Zener transistor T4 can be silicon semiconductor transistors, while the pull-up control transistors T1, second pull-down control transistor T3, pull-up transistor T5, pull-down transistor T6, second Zener transistor T7, and third Zener transistor T8 can be oxide semiconductor transistors. The pull-up transistors T5 and pull-down transistor T6 can be type 1 oxide transistors, while the pull-up control transistors T1, second pull-down control transistor T3, second Zener transistor T7, and third Zener transistor T8 can be type 2 oxide transistors.

[0072] Specifically, oxide semiconductor transistors can be metal oxide transistors, and silicon semiconductor transistors can be low-temperature polycrystalline silicon transistors.

[0073] In this embodiment, the first type of clock line XCK and the second type of clock line CK can be one of the following: the first control clock line NCK1, the second control clock line NCK2, the third control clock line NCK3, and the fourth control clock line NCK4.

[0074] For example, in the (n-3)th stage first gate circuit 310, the first type of clock line XCK is the fourth control clock line NCK4, and the second type of clock line CK is the first control clock line NCK1; in the (n-2)th stage first gate circuit 310, the first type of clock line XCK is the first control clock line NCK1, and the second type of clock line CK is the second control clock line NCK2; in the (n-1)th stage first gate circuit 310, the first type of clock line XCK is the second control clock line NCK2, and the second type of clock line CK is the third control clock line NCK3; in the nth stage first gate circuit 310, the first type of clock line XCK is the third control clock line NCK3, and the second type of clock line CK is the fourth control clock line NCK4.

[0075] It should be noted that some transistors in this application adopt a single-gate design, while some transistors adopt a dual-gate design. For transistors with a single-gate design, the gate is its only gate. For transistors with a dual-gate design, the gate refers to the bottom gate and the top gate. For example, the pull-up control transistor T1 is a dual-gate design. The gate of the pull-up control transistor T1 refers to the first gate and the second gate of the pull-up control transistor T1. Similarly, the description of the gate of other transistors can be found in the description of the transistors above, and will not be repeated in the following embodiments.

[0076] It should be noted that the control terminal of this application can be the gate of a transistor, the input terminal can be the drain of a transistor, and the output terminal can be the source of a transistor.

[0077] It should be noted that since the second Zener transistor T7 is an N-type transistor and its gate is connected to a high-level source, the second Zener transistor T7 is always in the on state in this application, that is, the pre-pull-up node K and the pull-up node Q are on.

[0078] The following is about Figure 4 The structure of the film layer of the display panel 100 of this application is described.

[0079] Please see Figure 5 The display panel 100 may have a substrate 110 and an array driving layer 120 disposed on the substrate 110 in the display area AA and the non-display area NA. In the display area AA, the display panel 100 may also have a pixel definition layer disposed on the array driving layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer, and an encapsulation layer disposed on the pixel definition layer. The following mainly describes the film layer structure in the non-display area NA.

[0080] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate 110 is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate 110 and a transparent substrate 110 can be used.

[0081] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110. The substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0082] In this embodiment, the substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 stacked together. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0083] In this embodiment, the first flexible substrate 111 is formed by coating a polymeric material onto a support substrate (not shown) and then curing the polymeric material. The second flexible substrate 113 is formed by coating the first flexible substrate 111 with the same material and then curing the material. The second flexible substrate 113 is formed by the same method as that used to form the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 may be formed to have a thickness of about 8 μm to about 12 μm. Furthermore, when the substrate 110 is formed from the first flexible substrate 111 and the second flexible substrate 113, pinholes, cracks, etc., formed during the manufacturing of the first flexible substrate 111 are covered by the second flexible substrate 113, thereby removing the aforementioned defects.

[0084] Please see Figure 5 The array driving layer 120 may include multiple thin-film transistors (TFTs). These TFTs may be etch-block type, back-channel etch type, or classified according to the position of the gate and active layer as bottom-gate TFTs, top-gate TFTs, etc., or according to their performance as N-type TFTs, P-type TFTs; among them, Figure 5 The thin-film transistor in the text does not represent Figure 2 The structural diagram of any transistor is merely a schematic diagram of each film layer of the display panel 100 of this application.

[0085] Please see Figure 5The array driving layer 120 may include a light-shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light-shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a first inter-insulator 128 disposed on the second gate layer 127, a second active layer 129 disposed on the first inter-insulator 128, a third gate insulating layer 130 disposed on the second active layer 129, and a third gate insulating layer 130 disposed on the second active layer 129. The third gate layer 131 on the third gate insulating layer 130, the fourth gate insulating layer 132 on the third gate insulating layer 131, the fourth gate layer 133 on the fourth gate insulating layer 132, the second inter-insulating layer 134 on the fourth gate layer 133, the first source-drain layer 135 on the second inter-insulating layer 134, the first planarization layer 136 on the first source-drain layer 135, the second source-drain layer 137 on the first planarization layer 136, the second planarization layer 138 on the second source-drain layer 137, the third source-drain layer 139 on the second planarization layer 138, and the third planarization layer 140 on the third source-drain layer 139.

[0086] Please see Figure 5 The light-shielding layer 121 is disposed on or inside the second barrier layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be a black light-shielding material, such as black light-shielding metal or black organic material.

[0087] Please see Figure 5 The buffer layer 122 is disposed on the light-shielding layer 121. The material of the buffer layer 122 may be a compound composed of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0088] Please see Figure 5 The first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the first insulating layer 128. The materials of the first active layer 123 and the second active layer 129 can be one of silicon semiconductor transistors or oxide semiconductor transistors, such as metal oxide semiconductor, amorphous silicon or low temperature polycrystalline silicon. In this application, the material of the first active layer 123 can be low temperature polycrystalline silicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0089] Please see Figure 5The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 130, the fourth gate insulating layer 132, the first interlayer insulating layer 128, and the second interlayer insulating layer 134 are respectively disposed on the corresponding metal layer or semiconductor layer, so that the metal layer or semiconductor layer of different layers is disposed separately; the materials of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 128, the third gate insulating layer 130, the fourth gate insulating layer 132, and the second interlayer insulating layer 134 can be inorganic materials composed of silicon oxynitride or organic materials with planarity, or stacked structures such as silicon oxide, silicon nitride, and aluminum oxide.

[0090] Please see Figure 5 The first gate layer 125, the second gate layer 127, the third gate layer 131 and the fourth gate layer 133 are respectively disposed on the corresponding insulating layer. The materials of the first gate layer 125, the second gate layer 127, the third gate layer 131 and the fourth gate layer 133 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu or single-layer or multi-layer metal structures composed of at least two of the above metals. For example, the materials may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0091] Please see Figure 5 The materials of the first source-drain layer 135, the second source-drain layer 137, and the third source-drain layer 139 may include metals such as Cr, W, Ti, Ta, Mo, Al, and Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals. For example, the materials may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0092] Please see Figure 5 The first planarization layer 136, the second planarization layer 138, and the third planarization layer 140 can be laid as a whole or only in the display area AA and part of the non-display area NA to ensure the flatness of the film layer of the array driving layer 120. The materials of the first planarization layer 136, the second planarization layer 138, and the third planarization layer 140 can be inorganic materials composed of silicon oxynitride or organic materials with flatness, such as flexible materials such as polytetrafluoroethylene.

[0093] It should be noted that, Figure 5 The document lists the structures of two oxide transistors and one silicon semiconductor transistor. Figure 5The three types of transistors shown are only schematic diagrams of the film layers of different types of transistors in the non-display area NA, and do not represent the specific structure of the transistors in the non-display area NA.

[0094] It should be noted that, since the material of the second gate layer 127 in this application is typically made of titanium to shield the influence of the bottom charge in the display area AA, and the spacing between the second gate layer 127 and the second active layer 129 is small, in order to improve the bias temperature stress (BTS) characteristics of the oxide transistor, this application uses the first gate layer 125 as the bottom gate of the oxide transistor. Figure 5 The second gate layer 127 is not shown in the structure.

[0095] The following is about Figure 4 The specific structure of the circuit in the description describes the technical solution of this application.

[0096] Please see Figure 6 The first gate layer 125 includes the gate T1G of the pull-up control transistor T1, the gate T2G of the first pull-down control transistor T2, the gate T3G of the second pull-down control transistor T3, the gate T4G of the first Zener transistor T4, the gate T5G of the pull-up transistor T5, the gate T6G of the pull-down transistor T6, the gate T7G of the second Zener transistor T7, and the gate T8G of the third Zener transistor T8.

[0097] Please see Figure 6 Since the pull-up control transistor T1, the second pull-down control transistor T3, the pull-up transistor T5, the pull-down transistor T6, the second Zener transistor T7, and the third Zener transistor T8 are all oxide transistors, in order to improve the mobility of the above transistors, this application sets the above transistors as dual-gate transistors, and the first gate layer 125 includes the bottom gate of the above transistors; for example, the first gate layer 125 includes the first gate T1Ga of the pull-up control transistor T1, the first gate T3Ga of the second pull-down control transistor T3, the first gate T5Ga of the pull-up transistor T5, the first gate T6Ga of the pull-down transistor T6, the first gate T7Ga of the second Zener transistor T7, and the first gate T8Ga of the third Zener transistor T8.

[0098] Please see Figure 6The first gate T3Ga of the second pull-down control transistor T3 and the first gate T1Ga of the pull-up control transistor T1 are arranged along the first direction X. The first gate T6Ga of the pull-down transistor T6 and the first gate T5Ga of the pull-up transistor T5 are arranged along the first direction X. The gate T4G of the first Zener transistor T4 and the first gate T7Ga of the second Zener transistor T7 are arranged along the first direction X. The first gate T3Ga of the second pull-down control transistor T3, the gate T2G of the first pull-down control transistor T2, the gate T4G of the first Zener transistor T4, and the first gate T8Ga of the third Zener transistor T8 are arranged along the second direction Y. The first gate T8Ga of the third Zener transistor T8 is arranged adjacent to the first gate T6Ga of the pull-down transistor T6 and the first gate T5Ga of the pull-up transistor T5.

[0099] Please see Figure 6 Both the first gate T6Ga of the pull-down transistor T6 and the first gate T5Ga of the pull-up transistor T5 include branch gates extending along the second direction Y; for example, the first gate T6Ga of the pull-down transistor T6 includes one branch gate, and the first gate T5Ga of the pull-up transistor T5 includes a main gate and three branch gates connected to the main gate and arranged and spaced apart along the first direction X.

[0100] Please see Figure 6 The spacing between the first gate T6Ga of pull-down transistor T6 and the first gate T5Ga of pull-up transistor T5 can be equal to the spacing between two adjacent branch gates in the first gate T5Ga of pull-up transistor T5.

[0101] Please see Figure 6 The first gate layer 125 also includes a conduction segment ET0, a first transmission segment ET1, a second transmission segment ET2, a third transmission segment ET3, a fourth transmission segment ET4 and a fifth transmission segment ET5. The first transmission segment ET1, the second transmission segment ET2, the third transmission segment ET3 and the fourth transmission segment ET4 all extend along the second direction Y, and the fifth transmission segment ET5 is a broken line segment.

[0102] Please see Figure 6The first transmission segment ET1 is connected to the first gate T5Ga of the pull-up transistor T5 at one end and the first gate T1Ga of the pull-up control transistor T1 at the other end. The middle position of the second transmission segment ET2 is connected to the gate T4G of the first Zener transistor T4 at one end away from the first gate T7Ga of the second Zener transistor T7. The second transmission segment ET2 is also connected to the first gate T8Ga of the third Zener transistor T8. The third transmission segment ET3 is connected to the main gate of the first gate T5Ga of the pull-up transistor T5. The two ends of the fourth transmission segment ET4 are connected to the gate T2G of the first pull-down control transistor T2 and the first gate T3Ga of the second pull-down control transistor T3. The fifth transmission segment ET5 is located between the first gate T3Ga of the second pull-down control transistor T3 and the first gate T1Ga of the pull-up control transistor T1. The end of the fifth transmission segment ET5 away from the first gate T1Ga of the pull-up control transistor T1 and the fourth transmission segment ET4 are connected to the first gate T3Ga of the second pull-down control transistor T3 at the same position.

[0103] Please see Figure 6 Since the pull-up transistor T5 is used to output the compensation control signal Nscan2, the load of the pull-up transistor T5 is greater than that of other non-output transistors. In order to ensure the output load of the pull-up transistor T5, this application allows the area of ​​the pull-up transistor T5 to be larger than the area of ​​other transistors not used for output load. At the same time, since the pull-down transistor T6 is used to pull down the potential of the output point of the pull-up transistor T5, the area of ​​the pull-down transistor T6 can be smaller than the area of ​​the pull-up transistor T5, but the area of ​​the pull-down transistor T6 must be larger than the area of ​​other transistors not used for output load.

[0104] In this embodiment, the area of ​​the first gate T5Ga of the pull-up transistor T5 is larger than the area of ​​the first gate T6Ga of the pull-down transistor T6, and the area of ​​the first gate T6Ga of the pull-down transistor T6 is larger than the area of ​​the gates of other transistors not used for the output load.

[0105] Please see Figure 7 The first active layer 123 includes an active pattern T2A of a first pull-down control transistor T2 and an active pattern T4A of a first Zener transistor T4. Both the active pattern T2A of the first pull-down control transistor T2 and the active pattern T4A of the first Zener transistor T4 extend along the second direction Y, and the active pattern T2A of the first pull-down control transistor T2 and the active pattern T4A of the first Zener transistor T4 are connected along the second direction Y.

[0106] Please see Figure 9The active pattern T2A of the first pull-down control transistor T2 and the gate T2G of the first pull-down control transistor T2 have an overlapping portion, and the overlapping portion is the channel of the first pull-down control transistor T2; the active pattern T4A of the first Zener transistor T4 and the gate T4G of the first Zener transistor T4 have an overlapping portion, and the overlapping portion is the channel of the first Zener transistor T4.

[0107] Please see Figure 8 The second active layer 129 includes an active pattern T1A of a pull-up control transistor T1, an active pattern T3A of a second pull-down control transistor T3, an active pattern T5A of a pull-up transistor T5, an active pattern T6A of a pull-down transistor T6, an active pattern T7A of a second Zener transistor T7, and an active pattern T8A of a third Zener transistor T8.

[0108] Please see Figure 8 The active pattern T6A of the pull-down transistor T6 and the active pattern T5A of the pull-up transistor T5 are connected. The active pattern T6A of the pull-down transistor T6 and the active pattern T5A of the pull-up transistor T5 both include at least two active sub-parts arranged at intervals along the second direction Y. The active sub-parts of the pull-down transistor T6 and the pull-up transistor T5 are connected in the first direction X.

[0109] Please see Figure 9 The active pattern T1A of the pull-up control transistor T1 and the first gate T1Ga of the pull-up control transistor T1 have overlapping portions; the active pattern T3A of the second pull-down control transistor T3 and the first gate T3Ga of the second pull-down control transistor T3 have overlapping portions; the active pattern T6A of the pull-down transistor T6 and the first gate T6Ga of the pull-down transistor T6 have overlapping portions; the active pattern T7A of the second Zener transistor T7 and the first gate T7Ga of the second Zener transistor T7 have overlapping portions; the active pattern T8A of the third Zener transistor T8 and the first gate T8Ga of the third Zener transistor T8 have overlapping portions; and the active pattern T5A of the pull-up transistor T5 and the first gate T5Ga of the pull-up transistor T5 have overlapping portions.

[0110] Please see Figure 9The gate T6G of pull-down transistor T6 and the gate T5G of pull-up transistor T5 have relatively long lengths along the second direction Y. Since pull-down transistor T6 and pull-up transistor T5 are oxide transistors, they have the advantage of low leakage current, but the characteristic of low mobility. In order to improve the mobility of pull-down transistor T6 and pull-up transistor T5, this application can increase the channel width in the transistor. Therefore, in order to further increase the channel width of the transistor, the dimensions of the active pattern T6A of pull-down transistor T6 and the active pattern T5A of pull-up transistor T5 along the second direction Y can be increased as much as possible. However, since the active part will have the problem of electrostatic concentration when the semiconductor structure is too large in the second direction Y, causing the active part to be damaged by electrostatic discharge, this application can set the structure of the active pattern T6A of pull-down transistor T6 and the active pattern T5A of pull-up transistor T5 as multiple sub-active parts arranged at intervals.

[0111] In this embodiment, the widths of the active pattern T6A of the pull-down transistor T6 and the active pattern T5A of the pull-up transistor T5 can be the same; or, please refer to... Figure 8 and Figure 9 The width of the active pattern T6A of the pull-down transistor T6 can be smaller than the width of the active pattern T5A of the pull-up transistor T5.

[0112] Please see Figure 8 and Figure 9 The channel width of the active pattern T1A of the pull-up control transistor T1 is greater than the channel width of the transistors not used for the output load (i.e., except for the pull-down transistor T6, the second Zener transistor T7, the tenth transistor T10, and the ninth transistor T9). Since the pull-up control transistor T1 is used to pull up the potential of node K, in order to ensure the accuracy of the potential of the pull-up node K, this application improves the mobility of the pull-up control transistor T1 by increasing the width of the active pattern T1A of the pull-up control transistor T1.

[0113] Please see Figure 10 The third gate layer 131 includes the second gate T1Gb of the pull-up control transistor T1, the second gate T3Gb of the second pull-down control transistor T3, the second gate T5Gb of the pull-up transistor T5, the second gate T6Gb of the pull-down transistor T6, the second gate T7Gb of the second Zener transistor T7, and the second gate T8Gb of the third Zener transistor T8. The above gates can be used as the top gates of the corresponding transistors.

[0114] Please see Figure 10The second gate T6Gb of pull-down transistor T6 and the second gate T5Gb of pull-up transistor T5 both include branch gates extending along the second direction Y; for example, the second gate T6Gb of pull-down transistor T6 includes one branch gate, and the second gate T5Gb of pull-up transistor T5 includes a main gate and three branch gates connected to the main gate and arranged and spaced apart along the first direction X.

[0115] Please see Figure 10 and Figure 12 The spacing between the second gate T6Gb of pull-down transistor T6 and the second gate T5Gb of pull-up transistor T5 can be equal to the spacing between two adjacent branch gates in the second gate T5Gb of pull-up transistor T5; at the same time, the spacing between two adjacent branch gates in the second gate T5Gb of pull-up transistor T5 can be greater than the spacing between two adjacent branch gates in the first gate T5Ga of pull-up transistor T5.

[0116] Please see Figure 12 The second gate T1Gb and the first gate T1Ga of the pull-up control transistor T1 overlap; the second gate T3Gb and the first gate T3Ga of the second pull-down control transistor T3 overlap; the second gate T5Gb and the first gate T5Ga of the pull-up transistor T5 overlap; the second gate T6Gb and the first gate T6Ga of the pull-down transistor T6 overlap; the second gate T7Gb and the first gate T7Ga of the second Zener transistor T7 overlap; and the second gate T8Gb and the first gate T8Ga of the third Zener transistor T8 overlap. Furthermore, the width of the second gate of each of the aforementioned transistors is smaller than the width of the first gate.

[0117] Please see Figure 12 The active pattern T1A of the pull-up control transistor T1 and the second gate T1Gb of the first pull-down control transistor T2T1 have an overlapping portion; the active pattern T3A of the second pull-down control transistor T3 and the second gate T3Gb of the second pull-down control transistor T3 have an overlapping portion; the active pattern T6A of the pull-down transistor T6 and the second gate T6Gb of the pull-down transistor T6 have an overlapping portion; the active pattern T7A of the second Zener transistor T7 and the second gate T7Gb of the second Zener transistor T7 have an overlapping portion; the active pattern T8A of the third Zener transistor T8 and the second gate T8Gb of the third Zener transistor T8 have an overlapping portion; the active pattern T5A of the pull-up transistor T5 and the second gate T5Gb of the pull-up transistor T5 have an overlapping portion, and the aforementioned overlapping portion is the channel of the corresponding transistor, and the channel of the aforementioned transistor completely falls into the first gate of the corresponding transistor.

[0118] Please see Figure 10The third gate layer 131 further includes a first plate C1a of a first capacitor C1, a sixth transmission segment ET6, a seventh transmission segment ET7, an eighth transmission segment ET8, and a ninth transmission segment ET9. The sixth transmission segment ET6 is connected to the main gate of the first plate C1a and the second gate T5Gb of the pull-up transistor T5. The seventh transmission segment ET7 is connected to the main gate of the second gate T5Gb of the pull-up transistor T5. The eighth transmission segment ET8, the seventh transmission segment ET7, and the sixth transmission segment ET6 are arranged along the first direction X. The two ends of the eighth transmission segment ET8 are connected to the second gate T6Gb of the pull-down transistor T6 and the second gate T8Gb of the third Zener transistor T8. The ninth transmission segment ET9 is connected to the second gate T7Gb of the second Zener transistor T7.

[0119] Please see Figure 11 and Figure 12 The fourth gate layer 133 includes the second plate C1b of the first capacitor C1 and the transmission segment ET10, which is used to transmit control signals from other gate circuits to the display area.

[0120] In this embodiment, the second electrode plate C1b is disposed correspondingly to the first electrode plate C1a, and the orthogonal projection of the first electrode plate C1a on the fourth gate layer 133 is located within the second electrode plate C1b, that is, the area of ​​the first electrode plate C1a can be smaller than the area of ​​the second electrode plate C1b.

[0121] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes the source T6S of pull-down transistor T6, the drain T6D of pull-down transistor T6, the source T5S of pull-up transistor T5, and the drain T5D of pull-up transistor T5.

[0122] Please see Figure 13 and Figure 14 The source T6S and drain T6D of pull-down transistor T6, the source T5S and drain T5D of pull-up transistor T5 all include branch electrodes extending along the second direction Y and spaced apart along the first direction X. For example, the source T5S and drain T5D of pull-up transistor T5 each include two branch electrodes extending along the second direction Y and arranged along the first direction X, and the source T5S and drain T5D of pull-up transistor T5 are alternately arranged along the first direction X.

[0123] Please see Figure 13 and Figure 14The branch electrode of the source T6S of the pull-down transistor T6, which is close to the drain T5D of the pull-up transistor T5, is shared by the source T6S of the pull-down transistor T6 and the source T5S of the pull-up transistor T5. The end of the shared branch electrode that is close to the display area AA is the output terminal OUT of the first gate circuit 310.

[0124] Please see Figure 13 and Figure 14 The two gate branch electrodes of the pull-down transistor T6 can be disposed between the branch electrodes of the source T6S and the drain T6D of the pull-down transistor T6, which are arranged at intervals. The two gate branch electrodes of the pull-up transistor T5 are disposed between the branch electrodes of the source T5S and the drain T5D of the pull-up transistor T5, which are arranged at intervals.

[0125] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a first connection segment CT1. One end of the first connection segment CT1 is connected to the drain T5S of the pull-up transistor T5, and the other end of the first connection segment CT1 is connected to the second type clock line CK through a via.

[0126] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a second connection segment CT2. One end of the second connection segment CT2 passes through a via and is connected to a first type clock line XCK. The other end of the second connection segment CT2 passes through a via and is connected to one end of the first transmission segment ET1.

[0127] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a third connection segment CT3. One end of the third connection segment CT3 passes through a via and is connected to the other end of the first transmission segment ET1. The other end of the third connection segment CT3 passes through a via and is connected to the first gate T1Ga and the second gate T1Gb of the pull-up control transistor T1.

[0128] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a fourth connection segment CT4, which includes a lateral segment CT4a and a vertical segment CT4b connected to the middle of the lateral segment CT4a. One end of the lateral segment CT4a is connected to one end of the active pattern T7A of the second Zener transistor T7, and the other end of the lateral segment CT4a is connected to the seventh transmission segment ET7. The end of the vertical segment CT4b away from the lateral segment CT4a is connected to one end of the active pattern T8A of the third Zener transistor T8.

[0129] Please see Figure 13 and Figure 14The first source-drain layer 135 includes a fifth connection segment CT5, which includes four connection points arranged along the second direction Y. The first connection point of the fifth connection segment CT5 is connected to the end of the fifth transmission segment ET5 away from the second pull-down control transistor T3. The second connection point of the fifth connection segment CT5 is connected to the end of the active pattern T1A of the pull-up control transistor T1 away from the first transmission segment ET1. The third connection point of the fifth connection segment CT5 is connected to the end of the active pattern T7A of the second Zener transistor T7 away from the fourth connection segment CT4. The fourth connection point of the fifth connection segment CT5 is connected to the end of the active pattern T4A of the first Zener transistor T4 away from the first pull-down control transistor T2.

[0130] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a sixth connection segment CT6. One end of the sixth connection segment CT6 is connected to the high potential line Nvgh of the second source-drain layer 137. The other end of the sixth connection segment CT6 is connected to the other end of the active pattern T4A of the first Zener transistor T4. The middle section of the sixth connection segment CT6 is connected to the ninth transmission segment ET9.

[0131] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a seventh connection segment CT7. One end of the seventh connection segment CT7 is connected to the end of the active pattern T3A of the second pull-down control transistor T3 away from the fifth transmission segment ET5. The other end of the seventh connection segment CT7 is connected to the end of the active pattern T2A of the first pull-down control transistor T2 away from the first Zener transistor T4. The middle segment of the seventh connection segment CT7 is connected to the end of the second transmission segment ET2 away from the eighth transmission segment ET8.

[0132] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes an eighth connection segment CT8. One end of the eighth connection segment CT8 passes through a via and is connected to the second gate T3Gb of the second pull-down control transistor T3. The other end of the eighth connection segment CT8 passes through a via and is connected to the connection point of the fifth transmission segment ET5 and the fourth transmission segment ET4.

[0133] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a ninth connection segment CT9. One end of the ninth connection segment CT9 passes through a via and is connected away from the active pattern T3A of the second pull-down control transistor T3. The other end of the ninth connection segment CT9 passes through a via and is connected to the first low potential line Nvgh1 of the second source-drain layer 137.

[0134] Please see Figure 13 and Figure 14The first source-drain layer 135 includes a tenth connection segment CT10. One end of the tenth connection segment CT10 passes through a via and connects to one end of the second transmission segment ET2 away from the second pull-down control transistor T3. The other end of the tenth connection segment CT10 passes through a via and connects to the connection point of the eighth transmission segment ET8 and the second gate T8Gb of the third Zener transistor T8.

[0135] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes an eleventh connection segment CT11. One end of the eleventh connection segment CT11 passes through a via and is connected to the second low potential line Nvgh2 of the second source-drain layer 137. The other end of the eleventh connection segment CT11 passes through a via and is connected to the active pattern T8A of the third Zener transistor T8 near the end of the pull-down transistor T6. The middle section of the eleventh connection segment CT11 is connected to the conduction section ET0 adjacent to the first gate T8Ga of the third Zener transistor T8.

[0136] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a twelfth connection segment CT12. One end of the twelfth connection segment CT12 passes through a via and is connected to the source T5S of the pull-up transistor T5 and the source T6S of the pull-down transistor T6 of this stage. The other end of the twelfth connection segment CT12 passes through a via and is connected to the end of the active pattern T1A of the pull-up control transistor T1 of the next stage first gate circuit 310 away from the fifth connection segment CT5.

[0137] Please see Figure 15 and Figure 16 The second source-drain layer 137 includes a first low potential line Nvgh1, a high potential line Nvgh, a first control clock line NCK1, a second control clock line NCK2, a third control clock line NCK3, a fourth control clock line NCK4, a first low potential line Nvgh1, a second low potential line Nvgh2, a third low potential line Nvgh3, and a start signal line STV, all extending along the first direction X and arranged along the second direction Y.

[0138] In this embodiment, the first low-potential line Nvgh1 is connected to the active pattern T3A of the second pull-down control transistor T3 through the ninth connection segment CT9, the high-potential line Nvgh is connected to the sixth connection segment CT6 through a via, the second low-potential line Nvgh2 is connected to the active pattern T8A of the third Zener transistor T8 and the second gate T8Gb of the third Zener transistor T8 through the eleventh connection segment CT11, and the third low-potential line Nvgh3 is connected to the source T6S of the pull-down transistor T6.

[0139] In this embodiment, since the third low-potential line Nvgh3 and the pull-down transistor T6 overlap and are connected, the first low-potential line Nvgh1 and the second pull-down control transistor T3 are connected, the second low-potential line Nvgh2 and the third Zener transistor T8 are connected, the second pull-down control transistor T3 and the third Zener transistor T8 are used for signal switching control, and the pull-down transistor T6 is used to pull down the potential of the output terminal OUT of the first gate circuit 310. Therefore, the output load of the pull-down transistor T6 is greater than the output load of the second pull-down control transistor T3 and the third Zener transistor T8.

[0140] Please see Figure 15 and Figure 16 The width of the third low potential line Nvgh3 is greater than the width of the first low potential line Nvgh1 and the second low potential line Nvgh2, which improves the output load capacity of the third low potential line Nvgh3.

[0141] In the embodiments of this application, in order to ensure that the output signals of different output clock lines are the same, this application can make the line widths of the four output clock lines equal.

[0142] In this embodiment, the start signal line STV and the pull-up control transistor T1 in the signal generation module 310a are electrically connected, and the start signal line STV and the output module 310b have an overlapping portion.

[0143] The following embodiment uses the following example: the gate of the second Zener transistor T7 is connected to the first high-level source VGH1, the drain of the first Zener transistor T4 is connected to the second high-level source VGH2, the drain of the first pull-down control transistor T2 is connected to the third high-level source VGH3, and the drains of the second pull-down control transistor T3, the pull-down transistor T6, and the third Zener transistor T8 are connected to the low-level source VGL.

[0144] Since the first Zener transistor T4 is used to pull up the potential of the pull-up node Q to a high potential, and the third Zener transistor T8 and the pull-up control transistor T1 are used to pull down the potential of the pull-up node Q to a target low potential, when the ability of the first Zener transistor T4 to transmit a high level is greater than the ability of the pull-up control transistor T1 and the third Zener transistor T8 to transmit a low level, the node of the pull-up node Q will not be able to be pulled down to the target low potential, which will cause the output of the first gate circuit 310 to be abnormal.

[0145] In this embodiment, the channel width and channel length of the first Zener transistor T4 are in a first ratio, and the channel width and channel length of the first pull-down control transistor T2 are in a second ratio, wherein the first ratio is less than the second ratio; that is, this application can adjust the channel width and channel length of the first Zener transistor T4 to adjust the mobility of the first Zener transistor T4.

[0146] In this embodiment, the channel width of the first pull-down control transistor T2 and the channel width of the first Zener transistor T4 can be equal, and the channel length of the first pull-down control transistor T2 is less than the channel length of the first Zener transistor T4.

[0147] For example, in Figures 6 to 9 In the structure, the active pattern T2A of the first pull-down control transistor T2 and the active pattern T4A of the first Zener transistor T4 can have equal widths in the first direction X. The width of the gate of the first pull-down control transistor T2 in the second direction Y is smaller than the width of the gate of the first Zener transistor T4 in the second direction Y, and the width of the gate is the channel length of the corresponding transistor. Therefore, this application reduces the mobility of the first Zener transistor T4 by adjusting the width of the gate of the first Zener transistor T4 in the second direction Y, thereby reducing the on-state current of the first Zener transistor T4. This reduces the potential of the high-level source transmitted to the pull-up node Q through the first Zener transistor T4, thus improving the technical problem that the potential of the pull-up node Q cannot be pulled down to a preset low potential.

[0148] For example, the channel width of the first pull-down control transistor T2 is greater than the channel width of the first Zener transistor T4, and the channel length of the first pull-down control transistor T2 is equal to the channel length of the first Zener transistor T4; that is, this application can make the width of the active pattern T2A of the first pull-down control transistor T2 in the first direction X greater than the width of the active pattern T4A of the first Zener transistor T4 in the first direction X, and the width of the gate of the first pull-down control transistor T2 is equal to the width of the gate of the first Zener transistor T4, thereby reducing the mobility of the first Zener transistor T4 and improving the technical problem that the potential of the pull-up node Q cannot be pulled down to a preset low potential.

[0149] In this embodiment, the potential of the input terminal of the first Zener transistor T4 connected to the first type of voltage source can be made lower than the potential of the gate of the second Zener transistor T7 connected to the first type of voltage source; that is, it is equivalent to reducing the voltage of the second high-level source VGH2 connected to the first Zener transistor T4, thereby reducing the potential transmitted to the pull-up node Q through the first Zener transistor T4, and improving the technical problem that the potential of the pull-up node Q cannot be pulled down to a preset low potential.

[0150] Please see Figure 4 The third Zener transistor T8 includes a first gate and a second gate, and both the first gate and the second gate of the third Zener transistor T8 are electrically connected to the pull-down node P.

[0151] In other words, this application can set the third Zener transistor T8 as a dual-gate structure, and both gates of the third Zener transistor T8 are connected to the pull-down node P. This means that the conduction of the third Zener transistor T8 is driven by the two gates, which increases the mobility of the third Zener transistor T8, improves the ability of the third Zener transistor T8 to transmit a low-level source to the pull-up node Q, and improves the technical problem that the potential of the pull-up node Q cannot be pulled down to the preset low potential.

[0152] It should be noted that, since the third Zener transistor T8 and the pull-up control transistor T1 are used to pull the potential of the pull-up node Q down to the target low potential, this application can also improve the mobility of the pull-up control transistor T1 and / or the first pull-down control transistor T2, for example, by reducing the channel length of the pull-up control transistor T1 and the third Zener transistor T8, or / and increasing the channel width of the pull-up control transistor T1 and the third Zener transistor T8.

[0153] In this embodiment, the ratio of the channel width to the channel length of the pull-up control transistor T1 and the ratio of the channel width to the channel length of the third Zener transistor T8 are greater than the ratio of the channel width to the channel length of the first Zener transistor T4. For example, this application can keep the channel width and length of the pull-up control transistor T1 unchanged, reduce the channel length of the third Zener transistor T8 to 0.5 times the original length, and increase the channel length of the first Zener transistor T4 to 1.5 times the original length.

[0154] Please see Figure 17 The first Zener transistor T4 includes a first gate and a second gate. The first gate of the first Zener transistor T4 is connected to the pull-down node P, and the second gate of the first Zener transistor T4 is connected to the first type of level source. The conduction level of the first Zener transistor T4 is the second type of level source.

[0155] In this embodiment, the first Zener transistor T4 can be configured as a dual-gate structure, but the voltage types transmitted by the first gate and the second gate of the first Zener transistor T4 are different; for example, since the first Zener transistor T4 is a P-type transistor, the voltage transmitted by the second gate of the first Zener transistor T4 in this application can be a fourth high-level source VGH4.

[0156] It should be noted that this application also proposes a display device, which includes the aforementioned display panel, and the display device of this application can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0157] This application provides a display panel and a display device. The gate driving circuit of the display panel includes a pull-up control module, a pull-up module, a pull-down module, a pull-down control module, and a voltage stabilization module. The input terminal of the first pull-down control transistor of the pull-down control module is electrically connected to a first type of level source, and the output terminal of the first pull-down control transistor is electrically connected to a pull-down node. The gate of the first Zener transistor of the voltage stabilization module is electrically connected to the pull-down node, the input terminal of the first Zener transistor is electrically connected to the first type of level source, and the output terminal of the first Zener transistor is electrically connected to the pull-up node. The mobility of the first Zener transistor is less than the mobility of the first pull-down control transistor. This application reduces the on-state current of the first Zener transistor by making the mobility of the first Zener transistor less than the mobility of the first pull-down control transistor, i.e., reducing the mobility of the first Zener transistor, thereby reducing the potential of the first type of level source transmitted to the pull-up node through the first Zener transistor and improving the technical problem that the potential of the pull-up node cannot be pulled down to a preset low potential.

[0158] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0159] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0160] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0161] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, Includes a gate driving circuit, the gate driving circuit comprising: The pull-up control module is electrically connected to the pull-up node; A pull-up module, wherein the control terminal of the pull-up module is electrically connected to the pull-up node, and the output terminal of the pull-up module is electrically connected to the output terminal of the gate drive circuit; A pull-down module, wherein the control terminal of the pull-down module is electrically connected to the pull-down node, and the output terminal of the pull-down module is electrically connected to the output terminal of the gate drive circuit; A pull-down control module includes a first pull-down control transistor, the input terminal of the first pull-down control transistor is electrically connected to a first type of level source, the output terminal of the first pull-down control transistor is electrically connected to the pull-down node, and the control terminal of the first pull-down control transistor is electrically connected to the pull-up node. A voltage stabilization module includes a first Zener transistor, the gate of which is electrically connected to the pull-down node, the input of which is electrically connected to a first type of voltage level source, and the output of which is electrically connected to the pull-up node. The first type of voltage level source is a high-level source. The mobility of the first Zener transistor is less than that of the first pull-down control transistor, and both the first Zener transistor and the first pull-down control transistor are P-type transistors.

2. The display panel as described in claim 1, characterized in that, The channel width and channel length of the first Zener transistor are in a first ratio, and the channel width and channel length of the first pull-down control transistor are in a second ratio, wherein the first ratio is less than the second ratio.

3. The display panel as described in claim 2, characterized in that, The channel width of the first pull-down control transistor is equal to the channel width of the first Zener transistor, and the channel length of the first pull-down control transistor is less than the channel length of the first Zener transistor; or The channel width of the first pull-down control transistor is greater than the channel width of the first Zener transistor, and the channel length of the first pull-down control transistor is equal to the channel length of the first Zener transistor.

4. The display panel as described in claim 1, characterized in that, The first Zener transistor includes a first gate and a second gate, the first gate of the first Zener transistor is connected to the pull-down node, and the second gate of the first Zener transistor is connected to the first type of level source; The conduction level of the first Zener transistor is a second type of level source.

5. The display panel as described in claim 4, characterized in that, The second type of level source is a low-level source.

6. The display panel as described in any one of claims 1 to 5, characterized in that, The voltage stabilization module further includes a second Zener transistor, the gate of which is connected to the first type of level source that turns the second Zener transistor on, the input of which is electrically connected to a pre-pull-up node, and the output of which is electrically connected to the pull-up node. The output terminal of the first Zener transistor is electrically connected to the pre-pull-up node, and the potential of the first Zener transistor's input terminal connected to the first type of voltage source is less than the potential of the second Zener transistor's gate connected to the first type of voltage source.

7. The display panel as described in claim 6, characterized in that, The voltage stabilization module further includes a third Zener transistor, the input terminal of which is electrically connected to a second type of level source, and the input terminal of which is electrically connected to the pull-up node; The third Zener transistor includes a first gate and a second gate, and both the first gate and the second gate of the third Zener transistor are electrically connected to the pull-down node.

8. The display panel as described in claim 6, characterized in that, The voltage stabilization module further includes a third Zener transistor, the input terminal of which is electrically connected to a second type of level source, the input terminal of which is electrically connected to the pull-up node, and the gate of which is electrically connected to the pull-down node. The pull-up control module includes a pull-up control transistor, the output of which is electrically connected to the pre-pull-up node. The ratio of the channel width to the channel length of the pull-up control transistor and the ratio of the channel width to the channel length of the third Zener transistor are greater than the ratio of the channel width to the channel length of the first Zener transistor.

9. The display panel as described in any one of claims 1 to 5, characterized in that, The first pull-down control transistor and the first Zener transistor are both one of oxide semiconductor transistors or silicon semiconductor transistors, and the other transistors in the gate drive circuit are the other of oxide semiconductor transistors or silicon semiconductor transistors.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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