A Low-Disturbance Self-Recovery Operation Method for Cross-Lattice Ferroelectric Memory

Abstract

This invention discloses a low-disturbance self-recovery operation method for cross-matrix ferroelectric memory. This method operates on a cross-matrix ferroelectric memory array, comprising four consecutive pulse cycles, sequentially performing selected memory cell activation, data reading, data recovery, and reset operations. Using the low-disturbance self-recovery operation method provided by this invention, voltage pulse disturbances experienced by unselected cells during cross-matrix ferroelectric memory operation can be reduced, while simultaneously achieving automatic data recovery for the ferroelectric capacitive memory. This invention achieves lower read / write disturbances, a lower bit error rate, and faster access speeds.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memories, and in particular to a low-disturbance self-recovery operation method for cross-matrix ferroelectric memories. Background Technology

[0002] For decades, Dynamic Random Access Memory (DRAM) has been the mainstream memory architecture in storage systems due to its high-speed read / write speeds and low cost. Improving DRAM storage density has also been a research hotspot in recent years. Conventional DRAM primarily achieves size reduction by shrinking the cell area of ​​transistors and capacitors. However, with the advancement of process nodes and the continuous shrinking of transistor feature sizes, the large capacitor area requirements in DRAM and considerations for transistor reliability pose significant challenges to further miniaturization. In recent years, novel two-terminal non-volatile memories have been widely studied, which can form the smallest in-plane 4F... 2 Cell-area cross-matrix memory arrays, with the ability to be stacked in three dimensions, can significantly improve storage density. Common double-ended non-volatile devices include resistive devices (RRAM, MRAM, PCRAM, etc.) and capacitive devices (FeRAM). Among them, cross-matrix memory based on ferroelectric capacitance has the characteristics of ultra-low power access and fast readout due to its field-induced switching and polarization readout features. Moreover, due to its good reliability and fluctuation characteristics, it is one of the popular technologies for next-generation memory.

[0003] Among different types of ferroelectric capacitor memories, hafnium oxide (HfO2)-based ferroelectric materials exhibit excellent CMOS process compatibility and size miniaturization potential, making them more suitable for high-density memory fabrication and integration compared to traditional ferroelectric materials. However, due to the polycrystalline and multi-domain characteristics of HfO2-based ferroelectric materials and the wide coercive field distribution of their ferroelectric domains, unselected cells are subject to voltage pulse perturbations when writing information to cells in a cross-array without gated transistors. Furthermore, since ferroelectric memories read stored data through a destructive charge-sharing mechanism, the polarization charge of the original storage needs to be restored after the read operation, leading to a decrease in the overall access speed of the ferroelectric memory. Therefore, achieving a low-perturbation self-recovery operation method has become an urgent problem to be solved in cross-array ferroelectric memories. Summary of the Invention

[0004] This invention aims to propose a low-disturbance self-recovery operation method for cross-matrix ferroelectric memories. Operating a cross-matrix memory array using this invention enables the memory to exhibit smaller cell perturbations, lower bit error rates, and faster access speeds.

[0005] The specific technical solution of this invention is as follows:

[0006] A low-disturbance self-recovery operation method for cross-matrix ferroelectric memory (CMM) is disclosed. This method operates on a CMM array. The CMM array has multiple orthogonal word lines and bit lines. The intersection of each word line and bit line constitutes a memory cell. Each memory cell is composed of a ferroelectric capacitor, which stores two data states through its spontaneous polarization direction: downward polarization corresponds to data "1", and upward polarization corresponds to data "0". The operation method involves simultaneously applying voltage pulses to one word line and one bit line of the CMM array to select a memory cell in the array. This selected memory cell is called the selected memory cell, and all other memory cells are unselected memory cells. The word line and bit line containing the selected memory cell are the selected word line and selected bit line, respectively, while all other word lines and bit lines are the unselected word line and unselected bit line, respectively.

[0007] The specific low-disturbance self-recovery operation method of this invention requires four consecutive pulse cycles to achieve. During the operation, only the selected word / bit line needs to be energized with voltage, while the unselected word / bit line always maintains the GND voltage.

[0008] (1) In the first cycle, apply amplitudes of GND and -V to the selected word line and selected bit line respectively. dd A voltage pulse of / 2 is applied to activate the selected word line and the selected bit line, and then proceed to the next step.

[0009] (2) In the second cycle, apply an amplitude of V to the selected character line. dd A voltage pulse of / 2 is applied, keeping the selected bit line floating to enable data reading operations on the selected memory cell. The data read is the ferroelectric dielectric of the ferroelectric capacitor in the selected memory cell at V... dd The amount of polarization charge generated by polarization reversal under high voltage access causes a change in the selected bit line voltage signal.

[0010] (3) In the third cycle, the voltage of the selected bit line is amplified to V by the external circuit connected to it. dd / 2 or -V dd / 2, the voltage of the selected bit line corresponds to the state voltage value stored in the selected memory cell, that is, if "1" is stored, it corresponds to V dd / 2, stores "0" corresponding to -V dd / 2, then set the selected word line voltage to -V dd / 2, to precharge the selected word line and simultaneously restore the data of the selected memory cell;

[0011] (4) In the fourth cycle, the voltage of the selected word line and the selected bit line is set to GND to reset the selected memory cell and its word line and bit line.

[0012] Using the operating method of this invention, V can be utilizeddd The / 2 voltage operation mode enables the writing, reading, and automatic data recovery processes of the capacitive cross-matrix ferroelectric memory. In the first and second cycles, the selected bit line is pre-charged to -V. dd / 2 potential and keep floating, then apply V to the selected word line. dd / 2 voltage, the selected memory cell will be subject to V dd The voltage is accessed, and data is read onto the selected bit line to read the stored state data. Because the charge-sharing readout method of ferroelectric capacitors is destructive, the amount of polarization charge stored in the selected memory cell changes after it is accessed. Specifically, if the selected cell originally stored "1", the polarization reversal is significant during the read operation, resulting in a large loss of polarization charge and severe state corruption; if the selected cell originally stored "0", the polarization reversal is weak, resulting in minimal loss of polarization charge and almost no change in state. Therefore, data recovery of the selected memory cell is necessary. In the third cycle, the selected bit line voltage is amplified to V. dd / 2 or -V dd / 2, the selected original "1" memory location is affected by -V dd Voltage access causes a polarity flip, restoring the previously stored data "1". The selected previously stored "0" cell is accessed with GND voltage, but its storage state remains unchanged. In the fourth cycle, the selected word line and selected bit line are reset, completing one read cycle and allowing data to be read from the next group of memory cells. Compared to other write methods, this operation method is based on V... dd The / 2 voltage pulse can reduce cell write crosstalk to a certain extent while completing the reading of memory array data and automatic recovery operation.

[0013] The beneficial effects and corresponding principles of the low-disturbance self-recovery operation method for cross-matrix ferroelectric memories of the present invention are as follows:

[0014] The low-disturbance self-recovery operation method of this invention is compatible with the standard "activation, read operation, write operation, precharge reset" memory operation logic, wherein the write operation and precharge are combined to realize the data self-recovery operation. When a memory cell of a cross-matrix ferroelectric memory is accessed according to the low-disturbance self-recovery operation method of this invention, the memory cells on the non-selected word line and bit line are not disturbed by voltage pulses. In the first and second cycles, the data in the selected memory cell is successfully read, and the state of the original "1" cell is destroyed. In the third cycle, by combining the precharge of the selected word line, -V is applied to the original "1" cell. ddVoltage operation restores data "1" without affecting the storage state of "0" cells. Since the restoration operation is performed during word line pre-charging, no additional operands or access time are required, making it an automatic restoration method. Compared to traditional cross-matrix ferroelectric memory operation modes, this invention's low-disturbance self-recovery method achieves smaller read / write disturbances, lower bit error rates, and faster access speeds, further improving the reliability of high-density cross-matrix ferroelectric memories. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the electrical circuitry of the cross-point ferroelectric storage array for the low-disturbance self-recovery operation method of the present invention.

[0016] In the picture:

[0017] 1 - Bit Line

[0018] 2 - Word Line

[0019] 3 — Individual storage cell (ferroelectric capacitor)

[0020] Figure 2 This is a schematic diagram of the pulse waveform of the low-disturbance self-recovery operation method of the present invention. Detailed Implementation

[0021] The invention will be further described below with reference to the accompanying drawings and through implementation.

[0022] This invention provides an operation method for a cross-matrix ferroelectric memory. For example... Figure 1 As shown, the cross-matrix ferroelectric memory array has multiple orthogonal word lines and bit lines. The intersection of each word line and bit line constitutes a memory cell. That is, the two sides of the memory cell array are connected by orthogonal word lines and bit lines. The memory cell is composed of ferroelectric capacitors. During access to a memory cell, if a voltage pulse is simultaneously applied to one word line and one bit line of the cross-matrix array to select a memory cell, this cell is called the selected memory cell. The word line and bit line containing the selected memory cell are the selected word line and selected bit line, respectively. All other memory cells are unselected memory cells. The word line and bit line of the unselected memory cells are the unselected word line and unselected bit line, respectively. This operation requires four consecutive pulse cycles. During the operation, only the selected word / bit line needs to be energized; the unselected word / bit line remains at GND voltage.

[0023] Perform an access operation on the selected memory cell, such as Figure 2 As shown, a complete access operation consists of four cycles. In the first cycle, amplitudes of GND and -V are applied to the selected word line and bit line, respectively. ddA voltage pulse of / 2 is applied, while the unselected word line and bit line maintain GND voltage; in the second cycle, the selected word line voltage is set to V. dd / 2, the selected bit line voltage remains floating, and the selected memory cell shares charge with the parasitic capacitance on the selected bit line. The bit line voltage will rise significantly when the data "1" is read (corresponding to the solid line in the diagram), and will rise slightly when the data "0" is read (corresponding to the dashed line in the diagram). In the third cycle, the selected bit line voltage is amplified to V by the external read / write circuit. dd / 2 or -V dd / 2, then set the selected word line voltage to -V dd / 2, the selected memory cell that originally contained "1" is affected by -V dd The voltage access is used to restore and write the data "1"; in the fourth cycle, the voltage of the selected word line and the selected bit line are both set to GND to realize the reset of the selected memory cell and its word line and bit line.

[0024] This operation method avoids voltage pulse disturbances to non-word / bit line memory cells during access, resulting in smaller read / write disturbances and a lower bit error rate. It also allows for automatic recovery of the corrupted memory state after the selected memory cell read operation is completed, reducing the overall cycle time and enabling faster access speeds.

[0025] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A low-disturbance self-recovery operation method for cross-matrix ferroelectric memories, characterized in that, The cross-matrix ferroelectric memory array has multiple orthogonal word lines and bit lines. The intersection of each word line and bit line is a memory cell. Each memory cell is composed of a ferroelectric capacitor. The ferroelectric capacitor stores two data states through its spontaneous polarization direction: downward polarization corresponds to data "1", and upward polarization corresponds to data "0". If a voltage pulse is simultaneously applied to a word line and a bit line of the cross-matrix array to select a memory cell, that cell is called the selected memory cell. The word line and bit line containing the selected memory cell are the selected word line and selected bit line, respectively. All other memory cells are unselected memory cells. The word line and bit line of the unselected memory cells are the unselected word line and unselected bit line, respectively. The operation requires four consecutive pulse cycles. During the operation, only the selected word line and bit line need to be energized; the unselected word line and bit line always maintain a GND voltage. The specific steps are as follows: 1) In the first cycle, apply amplitudes of GND and -V to the selected word line and selected bit line respectively. dd A voltage pulse of / 2 is applied to activate the selected word line and the selected bit line, and then proceed to the next step. 2) In the second cycle, apply an amplitude of V to the selected character line. dd A voltage pulse of / 2 is applied, keeping the selected bit line floating to enable data reading operations on the selected memory cell. The data read is the ferroelectric dielectric of the ferroelectric capacitor in the selected memory cell at V... dd The amount of polarization charge generated by polarization reversal under high voltage access causes a change in the selected bit line voltage signal. 3) In the third cycle, the voltage of the selected bit line is amplified to V by the external circuit connected to it. dd / 2 or -V dd / 2, the voltage of the selected bit line corresponds to the state voltage value stored in the selected memory cell, that is, if "1" is stored, it corresponds to V dd / 2, if storing "0" corresponds to -V dd / 2, then set the selected word line voltage to -V dd / 2, to precharge the selected word line and simultaneously restore the data of the selected memory cell; 4) In the fourth cycle, the voltage of the selected word line and the selected bit line is set to GND to reset the selected memory cell and its corresponding word line and bit line.

2. The low-disturbance self-recovery operation method for cross-matrix ferroelectric memory as described in claim 1, characterized in that, The ferroelectric capacitor device is made of hafnium oxide-based ferroelectric material.

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