Power module based on ed3 package form

Abstract

The application provides a power module based on an ED3 packaging form, comprising a substrate unit, a first chip unit and a second chip unit. The substrate unit comprises a first metal layer and a second metal layer arranged separately. The first chip unit is arranged on the first metal layer and comprises a first chip group and a second chip group arranged separately. The second chip unit is arranged on the second metal layer and comprises a third chip group and a fourth chip group arranged separately. The current paths of the first chip group and the second chip group are symmetrical. And / or, the current paths of the third chip group and the fourth chip group are symmetrical. The current sharing characteristics and the internal stray inductance characteristics of the power module are effectively improved, and the comprehensive working performance of the power module is optimized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power module technology, and relates to a power module based on ED3 package. Background Technology

[0002] In the field of power semiconductor devices, high-power IGBT (Insulated Gate Bipolar Transistor) modules are widely used in key areas such as new energy power generation, industrial frequency conversion, and electric vehicle drives due to their high voltage and high current handling capabilities. The module's packaging structure design plays a decisive role in device performance, especially switching characteristics and reliability.

[0003] However, current standard power module packaging structures generally suffer from the following significant drawbacks, limiting further performance improvements and making it particularly difficult to meet the higher packaging requirements of next-generation wide-bandgap semiconductor materials (such as silicon carbide, SiC). For example, the internal stray inductance (Ls) of existing packaging structures is generally high (e.g., approximately 20 nH). High Ls severely restricts the module's maximum allowable rate of change of current (dI / dt), resulting in limited switching speed and significantly increased switching losses (especially turn-off losses). In high-frequency switching applications, the overvoltage stress and electromagnetic interference (EMI) problems caused by high Ls are even more prominent, even threatening device safety. Furthermore, the rated current capability of a power module is highly dependent on the number of chips connected in parallel within the package and the uniformity of their current distribution (including static and dynamic). Maintaining a uniform distribution of drain current among the chips is crucial during both static and dynamic operation. In related technologies, due to constraints in package layout design (e.g., chips arranged in a specific direction), multiple power chips (such as IGBTs or diodes) connected in parallel within a module struggle to achieve ideal current balance during dynamic switching. This dynamic current imbalance leads to some chips experiencing excessively high instantaneous current stress and switching losses, accelerating chip aging and reducing the overall reliability and lifespan of the module. For SiC-based chips that prioritize switching speed and higher power density, the negative impacts of high internal inductance and dynamic current imbalance are even more severe, becoming a significant obstacle to the direct application of SiC-based chips.

[0004] Therefore, how to improve or enhance the performance of power modules (e.g., current sharing characteristics, spurious inductance) has become an important technical problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power module based on ED3 packaging to solve the problem that the performance of power modules in the prior art needs to be improved.

[0007] This invention provides a power module based on ED3 package, comprising: A substrate unit includes a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are disposed separately. A first chip unit is disposed on the first metal layer. The first chip unit includes a first chip group and a second chip group, which are arranged separately and connected in parallel. A second chip unit is disposed on the second metal layer. The second chip unit includes a third chip group and a fourth chip group, wherein the third chip group and the fourth chip group are arranged separately and connected in parallel. The current path of the first chipset is symmetrical to the current path of the second chipset; and / or, the current path of the third chipset is symmetrical to the current path of the fourth chipset.

[0008] In some embodiments, the power module further includes a first electrode, a second electrode, and a third electrode, which are separately disposed, and the first chip unit and the second chip unit are connected in series; wherein... The first chip unit is electrically connected between the first terminal and the third terminal; and the second chip unit is electrically connected between the third terminal and the second terminal.

[0009] In some embodiments, the substrate unit includes a first substrate, a second substrate, and a third substrate; wherein... In a first direction, the first substrate and the second substrate are arranged side by side, and the first metal layer is located in the first substrate and the second metal layer is located in the second substrate; In the second direction, the third substrate is stacked on the second substrate. The third substrate includes a third metal layer, a third insulating layer and a fourth metal layer stacked sequentially along the second direction. The third metal layer is connected to the second metal layer. The second direction is perpendicular to the first direction.

[0010] In some embodiments, the first metal layer includes a first metal and a second metal disposed separately, the first chip unit is disposed on the first metal, and the first chip unit is electrically connected to the second metal; The first electrode, the fourth metal layer, and the first metal layer are electrically connected in sequence, and the second metal layer is also electrically connected to the third electrode.

[0011] In some embodiments, the first metal includes a first connection region, the fourth metal layer is connected to the first connection region, and the first connection region has a first central axis extending along the first direction; The second metal includes a second connection region, the third electrode is connected to the second connection region, and the second connection region has a second central axis extending along the first direction; The first central axis coincides with the second central axis, and the first chip group and the second chip group are symmetrically distributed about the first central axis and the second central axis.

[0012] In some embodiments, the second metal layer includes a third metal, a fourth metal, and a fifth metal disposed separately, wherein at least a portion of the fifth metal is disposed between the third metal and the fourth metal; The third chipset is disposed on the third metal, the fourth chipset is disposed on the fourth metal, and the third chipset and the fourth chipset are electrically connected to the fifth metal respectively; the second electrode is electrically connected to the fifth metal.

[0013] In some embodiments, the third substrate includes a first extension and a second extension, the first extension being stacked on the fifth metal, the second extension extending from the fifth metal to the third metal, the first extension being electrically connected to the second metal, and the second extension being connected to the first electrode.

[0014] In some embodiments, the fifth metal includes a fifth connection region and a sixth connection region, the third chipset is electrically connected to the fifth connection region, and the fourth chipset is connected to the battery cell of the sixth connection region; wherein... The first extension has a third central axis extending along the first direction, the fifth connection region and the sixth connection region are symmetrically distributed about the third central axis, and the third chipset and the fourth chipset are also symmetrically distributed about the third central axis.

[0015] In some embodiments, the first substrate includes either a DBC substrate or an AMB substrate; the second substrate includes either a DBC substrate or an AMB substrate; and the third substrate includes either a DBC substrate or an AMB substrate.

[0016] In some embodiments, both the first chip unit and the second chip unit include a plurality of power chips; wherein the power chips include at least one of Si-based IGBT chips, SiC-based IGBT chips, and SiC-based MOSFET chips.

[0017] As described above, the power module based on the ED3 package of the present invention achieves current sharing among the chips in the power module by configuring the current paths of the first chipset symmetrically with those of the second chipset (and / or, the current paths of the third chipset symmetrically with those of the fourth chipset), thereby improving the waveform overlap of the circuit. Furthermore, the spatial layout of the current paths within the power module based on the third substrate (layered and reversed current paths) significantly reduces parasitic inductance within the power module. This structural design of the power module synergistically and positively optimizes the current sharing characteristics and low parasitic inductance characteristics within the power module, effectively improving the operating performance of the power module. It also enables the large-scale application of SiC-based power chips in this packaged power module, fully leveraging the performance advantages of SiC-based chips and contributing to a significant improvement in the overall performance of the power module. Attached Figure Description

[0018] Figure 1 This is a top view of a power module based on the ED3 package in related technologies. Figure 2 for Figure 1 The diagram shows a comparison of the circuit waveforms of current path A and current path B in the power module. Figure 3 This is a top view of the power module based on the ED3 package according to an embodiment of the present invention; Figure 4 This is a top view of the substrate unit in a power module based on ED3 packaging according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the substrate unit in a power module based on ED3 packaging according to an embodiment of the present invention; Figure 6 For along Figure 1 Cross-sectional view at point B-B'; Figure 7 This is a top view of a power module based on ED3 packaging according to an embodiment of the present invention, in which the first chip unit and the second chip unit are disposed behind the substrate unit. Figure 8 for Figure 3 A simplified structural diagram; Figure 9 for Figure 8 The diagram shows a comparison of the current waveforms of current path C and current path D.

[0019] Explanation of reference numerals in the attached figures: 101-Upper bridge arm unit, 101a First upper bridge arm chipset, 101b-Second upper bridge arm chipset, 102-Lower bridge arm unit, 102a First lower bridge arm chipset, 102b-Second lower bridge arm chipset; 10-First substrate, 11-First metal layer, 111-First metal, 111a-First connection region, I-First central axis, 111b-Third connection region, 111c-Fourth connection region, 111d-Seventh connection region, 111e-Eighth connection region, 112-Second metal, 112a-Second connection region, II-Second central axis, 12-First insulating layer, 13-Fifth metal layer; 20-Second substrate, 21-Second metal layer, 211-Third metal, 212-Fourth metal, 213-Fifth metal, 213a-Fifth connection region, 231b-Sixth connection region, 22-Second insulating layer, 23-Sixth metal layer; 30-Third substrate, 31-Third metal layer, 32-Third insulating layer, 33-Fourth metal layer, 30a-First extension, III-Third central axis, 30b-Second extension; 40 - First chip unit, 41 - First chipset, 42 - Second chipset; 50 - Second chip unit, 51 - Third chipset, 52 - Fourth chipset; 60-Supporting substrate; 70-Housing; 81-First electrode; 82-Second electrode; 83-Third electrode. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0021] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] Please see Figure 1 , Figure 1This diagram shows a top view of a power module based on an ED3 package in the related technology. The power module includes an upper bridge arm unit 101 and a lower bridge arm unit 102. The upper bridge arm unit 101 is electrically connected between the P+ electrode and the AC electrode, and the lower bridge arm unit 102 is electrically connected between the AC electrode and the N- electrode. The upper bridge arm unit 101 and the lower bridge arm unit 102 are symmetrically distributed about the long axis of the package module. Each upper bridge arm unit 101 and the lower bridge arm unit 102 includes multiple chips, and these chips are arranged along the long axis of the power module. For the same bridge arm unit, due to the arrangement of multiple chip units along the long axis of the power module, dynamic current sharing and loop inductance between the chips still need improvement.

[0023] Please see Figure 2 , Figure 2 It shows Figure 1 The diagram shows a comparison of the circuit waveforms of current path A and current path B in the power module. Current path A is the current path of the first upper bridge arm chip group 101a in the upper bridge arm unit 101, and current path B is the current path of the second upper bridge arm chip group 101b in the upper bridge arm unit 101. Figure 2 It can be seen that, Figure 1 In the power module shown, the uneven current distribution between the two chipsets in the upper bridge arm unit 101 is evident. This is easily understood, although not illustrated. Figure 1 In the power module shown, the loop currents of the first lower bridge arm chipset 102a and the second lower bridge arm chipset 102b in the lower bridge arm unit 102 are also uneven. This uneven current distribution can seriously affect the performance, reliability, and lifespan of the power module.

[0024] For Si-based chips, the switching speed is relatively slow (microseconds), and the sensitivity to differences in loop inductance during switching is relatively low. The impact of dynamic current imbalance on their performance is likely within an acceptable range. However, for SiC-based chips, the switching speed is extremely fast (nanoseconds), and their di / dt (rate of change of current) and dv / dt (rate of change of voltage) are much higher than those of silicon-based chips (taking IGBT chips as an example). The extremely high di / dt means that even small differences in loop inductance (L difference) can generate significant instantaneous voltage differences. This causes the chip with the smallest loop inductance (the middle chip) to experience a larger current surge at the moment of switching due to its lower impedance along its path. In other words, during the switching transient, the current distribution across different chips becomes severely unbalanced. Dynamic current imbalance causes some chips to experience current stress far exceeding the average value at the moment of switching, generating localized hot spots, accelerating device aging, and reducing reliability.

[0025] Based on the above analysis, this embodiment of the invention provides a power module based on an ED3 package, including a first chip unit and a second chip unit. By configuring the current paths of different chip groups in the first chip unit (and / or the second chip unit) to be symmetrical, dynamic current imbalance is improved. Furthermore, structural adjustments are made to the substrate in the power module to effectively reduce parasitic inductance and improve its performance. Here, "ED3 package" is short for EconoDUAL™ 3 package. It should be noted that this embodiment uses an IGBT chip as an example for power chip illustration, and the electrical connection relationship is described based on the IGBT device. In actual applications, the power chip can also be other suitable chip types (e.g., MOSFETs), and the electrical connection relationship can be adaptively adjusted based on the type of power chip; no strict limitation is imposed here. Specific solutions are described below.

[0026] This invention provides a power module (hereinafter referred to as "power module") based on the ED3 package. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 A schematic diagram of the overall structure of the power module is shown. The power module includes a substrate unit, a first chip unit 40, and a second chip unit 50. For ease of explanation of the structure of the power module, in this paper, the first direction X is the major axis (or length direction) of the power module, the second direction Z is the thickness direction (or height direction) of the power module, and the third direction Y is the minor axis direction (or width direction) of the power module.

[0027] Specifically, the substrate unit includes a first metal layer 11 and a second metal layer 21 (please refer to the relevant documentation). Figure 4 The first metal layer 11 and the second metal layer 21 are separately disposed. A first chip unit 40 is disposed on the first metal layer 11, and the first chip unit 40 includes a first chip group 41 and a second chip group 42, which are arranged separately and connected in parallel. A second chip unit 50 is disposed on the second metal layer 21, and the second chip unit 50 includes a third chip group 51 and a fourth chip group 52, which are arranged separately and connected in parallel. The current path of the first chip group 41 is symmetrical to the current path of the second chip group 42. And / or, the current path of the third chip group 51 is symmetrical to the current path of the fourth chip group 52.

[0028] To avoid ambiguity, "current path symmetry" includes at least one of the following: layout symmetry and electrical parameter symmetry (e.g., loop inductance, loop distance, dynamic current sharing, and waveform overlap). It should be noted that slight offsets due to manufacturing process precision limitations that prevent ideal symmetry are included within the scope of symmetry in this document. For example, a tolerance between the loop distances of the two components being less than or equal to ±5%, or a dynamic current sharing of the two components being ≥85%, can be considered as symmetrical current paths.

[0029] In some embodiments, such as Figure 3 As shown, the power module also includes a first electrode 81, a second electrode 82, and a third electrode 83, which are separately disposed. The first chip unit 40 and the second chip unit 50 are connected in series. Specifically, the first chip unit 40 is electrically connected between the first electrode 81 and the third electrode 83, and the second chip unit 50 is electrically connected between the third electrode 83 and the second electrode 82. That is, the third electrode 83 serves as the series connection point between the first chip unit 40 and the second chip unit 50.

[0030] For a specific example, please refer to [reference needed]. Figure 1 and Figure 3 The first electrode 81 is the P+ electrode of the power module, the second electrode 82 is the N- electrode of the power module, and the third electrode 83 is the AC electrode of the power module. The first chip unit 40 is the upper bridge arm unit of the power module, and the second chip unit 50 is the lower bridge arm unit of the power module. When the chips included in the first chip unit 40 and the second chip unit 50 are IGBT chips, the electrical connection of the first chip unit 40 between the first electrode 81 and the third electrode 83 means that the collector of each IGBT device in the first chip unit 40 is electrically connected to the first electrode 81, and the emitter of each IGBT device in the first chip unit 40 is electrically connected to the third electrode 83. The electrical connection of the second chip unit 50 between the third electrode 83 and the second electrode 82 means that the collector of each IGBT device in the second chip unit 50 is electrically connected to the third electrode 83, and the emitter of each IGBT device in the second chip unit 50 is electrically connected to the second electrode 82.

[0031] In some embodiments, please refer to Figure 4 and Figure 5 ,in, Figure 4 A top view of the substrate unit in this power module is shown. Figure 5 A schematic diagram of the split structure of the substrate unit in the power module is shown. The substrate unit includes a first substrate 10, a second substrate 20, and a third substrate 30. Wherein, in the first direction ( Figure 1In the X direction shown, the first substrate 10 and the second substrate 20 are arranged side by side, with the first metal layer 11 located in the first substrate 10 and the second metal layer 21 located in the second substrate 20. Please refer to [link / reference]. Figure 6 , Figure 6 It shows along Figure 1 The cross-sectional view at point B-B' shows that, in the second direction Z, a third substrate 30 is stacked on top of a second substrate 20. The third substrate 30 includes a third metal layer 31, a third insulating layer 32, and a fourth metal layer 33 stacked sequentially along the second direction Z. The third metal layer 31 is connected to the second metal layer 21. The second direction Z is perpendicular to the first direction X.

[0032] In some embodiments, please refer to Figure 7 , Figure 7 This diagram shows a top view of the power module, where the first chip unit 40 and the second chip unit 50 are disposed behind the substrate unit. The first metal layer 11 includes a first metal 111 and a second metal 112 separately disposed therefrom. The first chip unit 40 is disposed on the first metal 111, and the first chip unit 40 is electrically connected to the second metal 112. Please refer to the accompanying documentation. Figure 3 The first electrode 81, the fourth metal layer 33 and the first metal layer 11 are electrically connected in sequence, and the second metal 112 is also electrically connected to the third electrode 83. The first electrode 81 and the fourth metal layer 33, the fourth metal 212 and the first metal layer 11, and the second metal 112 and the third electrode 83 are all electrically connected through bonding wire groups.

[0033] In this embodiment of the invention, the third substrate 30 is provided, and the third metal layer 31 in the third substrate 30 is connected to the second metal layer 21 in the second substrate 20. This ensures that the P+ current path formed by the fourth metal layer 33 (a portion of the current path from the first electrode 81 through the first chip unit 40 to the third electrode 83) and the N- current path formed by the second metal layer 21 and the third metal layer 31 (a portion of the current path from the third electrode 83 through the second chip unit 50 to the second electrode 82) have equal currents but opposite current directions. This causes the electromagnetic fields generated by the current paths in both paths to cancel each other out, thereby reducing the parasitic stray inductance within the power module and effectively improving the problem of excessive stray inductance in power modules based on ED3 packaging in related technologies. Actual verification shows that the internal parasitic inductance in the power module of this embodiment is less than or equal to 10nH, a 50% reduction compared to the internal parasitic inductance (20nH) in related technologies. In addition, it should be noted that the electrical connection methods between the various structures shown in the accompanying drawings provided in the embodiments of the present invention are only illustrative examples. In actual applications, they can be adjusted according to actual needs, and no specific limitations are made here.

[0034] In some embodiments, please refer to Figure 3 and Figure 8 In order to facilitate the demonstration of the electrical connection locations between the various structures, Figure 8 It shows Figure 3 A simplified structural diagram (mainly omitting bonding wires) shows that the first metal 111 includes a first connection region 111a, and a fourth metal layer 33 is connected to the first connection region 111a. The first connection region 111a has a first central axis I extending along a first direction X. The second metal 112 includes a second connection region 112a, and a third electrode 83 is connected to the second connection region 112a. The second connection region 112a has a second central axis II extending along the first direction X. The first central axis I and the second central axis II coincide, and the first chipset 41 and the second chipset 42 are symmetrically distributed about the first central axis I and the second central axis II.

[0035] Furthermore, the second metal 112 includes a third connection region 111b and a fourth connection region 111c. The first chipset 41 is electrically connected to the third connection region 111b, and the second chipset 42 is connected to the fourth connection region 111c. The third connection region 111b and the fourth connection region 111c are symmetrically distributed about a first central axis I and a second central axis II. In a specific embodiment, the second metal 112 exhibits an axisymmetric morphology about the first central axis I and the second central axis II.

[0036] In this embodiment of the invention, for the first chip unit 40, the current input from the first electrode 81 flows through the fourth metal layer 33 and, based on the electrical connection between the fourth metal layer 33 and the first connection region 111a, flows into the first metal 111. Further, due to the different locations of the first chip group 41 and the second chip group 42 on the first metal 111, the current is split into a first part and a second part. The first part of the current flows from the collector of the first chip group 41 into each chip within the first chip group 41, and then flows out from the emitter of each chip, entering the third connection region 111b. Similarly, the second part of the current flows from the collector of each chip in the second chip group 42 into each chip within the second chip group 42, and then flows out from the emitter of each chip, entering the fourth connection region 111c. Then, these two parts of the current converge into the second connection region 112a and flow into the third electrode 83. Therefore, through the symmetrical arrangement of the various connection regions in the fourth metal layer 33 and the first metal layer 11, the current path of the first chipset 41 and the current path of the second chipset 42 in the first chip unit 40 are symmetrically distributed. Of course, in practical applications, other structural designs can also achieve a symmetrical distribution of current paths, without being strictly required to be identical to the above structure. Please refer to... Figure 9 , Figure 9 It shows Figure 8 The diagram shows a comparison of the current waveforms along current path C and current path D. Figure 3 and Figure 9 As can be seen, in the power module of this embodiment, the waveforms of the current paths of the two chipsets in the first chip unit 40 are basically overlapping, which effectively improves the current sharing characteristics.

[0037] In some embodiments, such as Figure 3 As shown (can be consulted in conjunction with other resources) Figure 4 , Figure 5 , Figure 7 and Figure 8 The second metal layer 21 includes a third metal 211, a fourth metal 212, and a fifth metal 213, which are separately disposed. At least a portion of the fifth metal 213 is spaced between the third metal 211 and the fourth metal 212. A third chipset 51 is disposed on the third metal 211, and a fourth chipset 52 is disposed on the fourth metal 212. The third chipset 51 and the fourth chipset 52 are electrically connected to the fifth metal 213. The second electrode terminal 82 is electrically connected to the fifth metal 213.

[0038] In some embodiments, such as Figure 3 As shown, the third substrate 30 includes a first extension 30a and a second extension 30b. The first extension 30a is stacked on the fifth metal 213, and the second extension 30b extends from the fifth metal 213 to the third metal 211. The first extension 30a is electrically connected to the second metal 112 (including direct or indirect connection), and the second extension 30b is connected to the first electrode 81. Specifically, the second extension 30b is used for electrical connection to the first electrode 81, and the first extension 30a is used for connection to the second metal 112, to transmit the current input to the first electrode 81 to the first chip unit 40. In a specific example, such as... Figure 3 As shown, the first extension 30a extends along the first direction X, and the second extension 30b extends along the third direction Y. The third direction Y is perpendicular to the first direction X and the second direction Z. At this time, the third substrate 30 is generally L-shaped. This shape of the third substrate 30 can reduce the electrical transmission distance between different structures, thereby reducing transmission loss and interference.

[0039] In some embodiments, the fifth metal 213 includes a fifth connection region 213a and a sixth connection region 213b. The third chipset 51 is electrically connected to the fifth connection region 213a, and the fourth chipset 52 is battery-connected to the sixth connection region 213b. The first extension 30a has a third central axis III extending along a first direction X. The fifth connection region 213a and the sixth connection region 213b are symmetrically distributed about the third central axis III, and the third chipset 51 and the fourth chipset 52 are also symmetrically distributed about the third central axis III.

[0040] Furthermore, the first metal 111 also includes a seventh connection region 111d and an eighth connection region 111e. The third metal 211 is connected to the seventh connection region 111d, and the fourth metal 212 is connected to the eighth connection region 111e, so that the current flowing in through the third electrode 83 flows through the first metal 111 to the second chip cell 50. The seventh connection region 111d and the eighth connection region 111e are also symmetrically distributed about the third central axis III.

[0041] In this embodiment of the invention, based on the third substrate 30, a portion of the connection areas of the third chipset 51, the fourth chipset 52, the third metal 211 and the fourth metal 212, and the first metal 111 are arranged in a symmetrical layout about the third central axis III, thus achieving a symmetrical distribution of the current paths of the third chipset 51 and the fourth chipset 52 in the second chip unit 50. Of course, in practical applications, other structural designs can also achieve a symmetrical distribution of the current paths, without being strictly required to be completely consistent with the above structure.

[0042] In the power module of this embodiment, firstly, by configuring the current path of the first chipset 41 to be symmetrical with the current path of the second chipset 42 (and / or, the current paths of the third chipset 51 and the fourth chipset 52 to be symmetrical), current sharing among the chips in the power module is achieved, thereby improving the overlap of circuit waveforms. Secondly, based on the arrangement of the third substrate 30, the current paths inside the power module are spatially arranged (the current paths are layered and arranged in reverse), which significantly reduces parasitic inductance within the power module (by more than 50%). Furthermore, the improved current sharing characteristics increase the overlap (or symmetry) of the current waveforms, allowing the electromagnetic fields generated by the current in the current path formed by the fourth metal layer 33 and the current path formed by the third metal layer 31 and the second metal layer 21 to be phase-matched and more effectively canceled, thus synergistically reducing stray inductance. The reduced loop inductance due to the spatial arrangement of the current paths further improves dynamic current sharing. In other words, through the improvements in the above two aspects, the current sharing characteristics and low stray inductance characteristics inside the power module are synergistically and positively optimized, effectively improving the operating performance of the power module.

[0043] It is easy to understand that, although not identified or described in detail, the first metal layer 11 and the second metal layer 21, in addition to the first metal 111 to the fifth metal 213 described above, also include other metals used to implement the power module function, such as multiple metal traces located between the first metal 111 and the second metal 112, multiple metal traces located between the third metal 211 and the fifth metal 213 and between the fourth metal and the fifth metal 213, and the aforementioned traces include source traces and gate traces, etc.

[0044] In some embodiments, both the first chip unit 40 and the second chip unit 50 include multiple power chips. For example, as... Figure 3 As shown, in each of the first chipset 41 to the fourth chipset 52, there are four power chips arranged at intervals along the first direction x. It should be noted that the accompanying drawings provided in this embodiment are for illustrative purposes only. In practical applications, the number of power chips included in each chipset (each chip unit) is not limited to those shown in the figures. For example, each chipset may contain fewer or more than four power chips, and the arrangement, position, or direction of the chips in the same chipset can be flexibly adjusted provided that the current paths of the two chipsets in the same chip unit are symmetrical.

[0045] Furthermore, the power chip includes at least one of Si-based IGBT chips, SiC-based IGBT chips, and SiC-based MOSFET chips. Due to the material characteristics of SiC-based chips (such as high switching speed), they are extremely sensitive to stray inductance and dynamic current imbalance. In related technologies, the EconoDUAL™ 3 package has a large internal stray inductance and poor dynamic current sharing, making it difficult to fully utilize the performance advantages of SiC-based chips. In the embodiments of the present invention, the stray inductance and dynamic current sharing characteristics of the power module are effectively improved, enabling SiC-based chips to be applied on a large scale to the EconoDUAL™ 3 package, significantly improving the overall performance of the power module (such as reducing switching losses and increasing power density). For Si-based chips, although their sensitivity is lower than that of SiC-based chips, stray inductance and current imbalance can still lead to increased switching oscillations and heat loss. After applying the power module provided in the embodiments of the present invention, the operating performance of Si-based chips under the same package is also effectively improved.

[0046] Furthermore, the power chip also includes a diode chip, which is connected to the IGBT chip via an adapter. For example, the diode chip may be a freewheeling diode, providing a low-impedance discharge path for the reverse current generated when the IGBT chip is turned off, preventing the IGBT chip from being damaged by reverse voltage breakdown. Furthermore, the diode chip can be integrated with the IGBT chip, that is, integrating the IGBT device and the diode device within the same chip. This increases chip integration density, reduces parasitic parameters, simplifies the structure and packaging process of the packaging module, and reduces costs.

[0047] In some embodiments, the power module further includes a housing 70, and a substrate unit on which the first chip unit 40 and the second chip unit 50 are disposed in the internal space of the housing 70 for encapsulation.

[0048] In some embodiments, the first substrate 10 further includes a first insulating layer 12 and a fifth metal layer 13, wherein the fifth metal layer 13, the first insulating layer 12, and the first metal layer 11 are stacked sequentially in the second direction Z. The second substrate 20 further includes a second insulating layer 22 and a sixth metal layer 23, wherein the sixth metal layer 23, the second insulating layer 22, and the second metal layer 21 are stacked sequentially in the second direction Z. Further, the fifth metal layer 13 and the sixth metal layer 23 are integrally formed, and the first insulating layer 12 and the second insulating layer 22 are integrally formed, to improve the overall mechanical structural stability and electrical reliability of the substrate unit.

[0049] Further, the first substrate 10 includes either a direct-bonded copper (DBC) substrate or an active metal brazing (AMB) substrate. The second substrate 20 includes either a DBC substrate or an AMB substrate. The third substrate 30 includes either a DBC substrate or an AMB substrate. The types of the first substrate 10, the second substrate 20, and the third substrate 30 can be the same or different. The third substrate 30 is soldered to the second substrate 20.

[0050] In some embodiments, the power module further includes a support substrate 60, which is located on the side of the substrate unit where the first chip unit 40 and the second chip unit 50 are not disposed, to provide mechanical support and heat dissipation for the substrate unit. For example, the support substrate 60 is a copper substrate.

[0051] In summary, the power module based on the ED3 package of the present invention achieves current sharing among the chips in the power module by configuring the current paths of the first chipset symmetrically with those of the second chipset (and / or, the current paths of the third chipset symmetrically with those of the fourth chipset), thereby improving the waveform overlap of the circuit. Furthermore, the spatial layout of the current paths within the power module based on the third substrate (layered and reversed current paths) significantly reduces parasitic inductance within the power module. This structural design of the power module synergistically and positively optimizes the current sharing characteristics and low parasitic inductance characteristics within the power module, effectively improving its operating performance. It also enables the large-scale application of SiC-based power chips in this packaged power module, fully leveraging the performance advantages of SiC-based chips and contributing to a significant improvement in the overall performance of the power module. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0052] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A power module based on ED3 package, characterized in that, include: A substrate unit includes a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are disposed separately. A first chip unit is disposed on the first metal layer. The first chip unit includes a first chip group and a second chip group, which are arranged separately and connected in parallel. A second chip unit is disposed on the second metal layer. The second chip unit includes a third chip group and a fourth chip group, wherein the third chip group and the fourth chip group are arranged separately and connected in parallel. The current path of the first chipset is symmetrical to the current path of the second chipset; and / or, the current path of the third chipset is symmetrical to the current path of the fourth chipset. The power module further includes separately disposed first, second, and third terminals, with the first chip unit and the second chip unit connected in series; wherein... The first chip unit is electrically connected between the first terminal and the third terminal; and the second chip unit is electrically connected between the third terminal and the second terminal. The second metal layer includes a third metal, a fourth metal, and a fifth metal disposed separately, with at least a portion of the fifth metal disposed between the third metal and the fourth metal; The third chipset is disposed on the third metal, the fourth chipset is disposed on the fourth metal, and the third chipset and the fourth chipset are electrically connected to the fifth metal respectively; the second electrode is electrically connected to the fifth metal.

2. The power module based on the ED3 package according to claim 1, characterized in that: The substrate unit includes a first substrate, a second substrate, and a third substrate; wherein... In a first direction, the first substrate and the second substrate are arranged side by side, and the first metal layer is located in the first substrate and the second metal layer is located in the second substrate; In the second direction, the third substrate is stacked on the second substrate. The third substrate includes a third metal layer, a third insulating layer and a fourth metal layer stacked sequentially along the second direction. The third metal layer is connected to the second metal layer. The second direction is perpendicular to the first direction.

3. The power module based on the ED3 package according to claim 2, characterized in that: The first metal layer includes a first metal and a second metal disposed separately, the first chip unit is disposed on the first metal, and the first chip unit is electrically connected to the second metal; The first electrode, the fourth metal layer, and the first metal layer are electrically connected in sequence, and the second metal layer is also electrically connected to the third electrode.

4. The power module based on the ED3 package according to claim 3, characterized in that: The first metal includes a first connection region, the fourth metal layer is connected to the first connection region, and the first connection region has a first central axis extending along the first direction; The second metal includes a second connection region, the third electrode is connected to the second connection region, and the second connection region has a second central axis extending along the first direction; The first central axis coincides with the second central axis, and the first chip group and the second chip group are symmetrically distributed about the first central axis and the second central axis.

5. The power module based on the ED3 package according to claim 2, characterized in that: The third substrate includes a first extension and a second extension. The first extension is stacked on the fifth metal, and the second extension extends from the fifth metal to the third metal. The first extension is electrically connected to the second metal, and the second extension is connected to the first electrode.

6. The power module based on the ED3 package according to claim 5, characterized in that: The fifth metal includes a fifth connection region and a sixth connection region. The third chipset is electrically connected to the fifth connection region, and the fourth chipset is electrically connected to the sixth connection region. The first extension has a third central axis extending along the first direction, the fifth connection region and the sixth connection region are symmetrically distributed about the third central axis, and the third chipset and the fourth chipset are also symmetrically distributed about the third central axis.

7. The power module based on the ED3 package according to claim 2, characterized in that: The first substrate includes either a DBC substrate or an AMB substrate; the second substrate includes either a DBC substrate or an AMB substrate; and the third substrate includes either a DBC substrate or an AMB substrate.

8. The power module based on the ED3 package according to claim 1, characterized in that: Both the first chip unit and the second chip unit include multiple power chips; wherein, the power chips include at least one of Si-based IGBT chips, SiC-based IGBT chips, and SiC-based MOSFET chips.

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