An external synchronization method for an infrared detector driven by an FPGA

Abstract

The application relates to an external synchronization method of an infrared detector driven by an FPGA, which comprises the following steps: an FPGA receives an external frame synchronization signal, resets the value of a frame counter, and records the current value T of an infrared detector clock frequency counter shift ; when a falling edge of an integral signal output by the FPGA is generated, the length of time between the falling edge of the integral signal and the time point at which the FPGA starts reading data of the infrared detector is calculated as an initial expected length of time based on the current value T intneg and T shift ; the expected length of time and the target length of time are adjusted multiple times based on the initial expected length of time and the initial target length of time until the expected length of time of the current time is zero, and the FPGA starts reading the data input by the infrared detector; and when the frame counter reaches the value corresponding to the preset integral start time point, the FPGA outputs the rising edge of the integral signal, and the driving of the infrared detector interface signal in one frame period is completed.

Description

Technical Field

[0001] This invention relates to the field of infrared thermal imaging technology, and in particular to an external synchronization method for an infrared detector driven by an FPGA. Background Technology

[0002] As existing cooled infrared detectors evolve towards higher resolution and higher frame rates, infrared detector modules increasingly operate in IWR (Integral Readout) mode to meet the requirements of short frame periods and long data validity times. In current cooled infrared detector devices, the clock, data readout signal, and integration signal output to the detector are all generated by the FPGA according to a specific timing sequence based on the device's local clock. When operating in IWR mode, the detector requires the time interval between the edge of the integration signal change and the start of the data readout signal to remain constant. When frame synchronization is provided by an external synchronization source, the unavoidable non-homogeneity between the external clock and the device's local clock will cause the device's frame period to deviate from the ideal value (the frame period generated by the device's local clock), thus affecting the timing relationship between the various signals output to the detector. In this case, the detector's output sampling data will become abnormal, resulting in stripes and jitter on the device's output screen.

[0003] Existing technologies employ a method that determines the duration of external synchronization cycles and then automatically switches to internal / external synchronization based on the duration range. However, since the determination and switching of external synchronization cycles does not address the issue at its root cause—the detector's driving timing—it cannot fundamentally compensate for time variations caused by differences between external and internal synchronization sources, or the instability of the external synchronization source. Therefore, the determination and switching of external synchronization cycles can only ensure that the deviation between the external synchronization cycle and the ideal internal synchronization cycle is within a certain threshold; it does not fundamentally eliminate timing errors in the signal supplied to the detector. This still manifests as some degree of stripes or jitter on the screen (related to the magnitude of the deviation). Furthermore, when this deviation is large, the device automatically switches to internal synchronization, effectively operating in internal synchronization mode rather than external synchronization. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide an external synchronization method for infrared detectors driven by FPGA, in order to solve the problem that existing external synchronization schemes do not fundamentally eliminate the timing relationship error of the signal to the detector, and that the image still shows a certain degree of stripes or jitter.

[0005] The objective of this invention is mainly achieved through the following technical solutions:

[0006] This invention provides an external synchronization method for an infrared detector driven by an FPGA, the method comprising the following steps:

[0007] The FPGA receives an external frame synchronization signal and resets the frame counter C. frame The value of the infrared detector clock divider counter C is recorded. mc The current value T shift ;

[0008] When the falling edge of the FPGA output integration signal occurs, based on the frame counter C frame The current value T intneg and T shift The duration between the falling edge of the FPGA output integral signal and the time point at which the FPGA begins reading data from the infrared detector is calculated as the initial estimated duration.

[0009] Based on the initial estimated duration and the initial target duration, the estimated duration and the target duration are adjusted iteratively multiple times until the current estimated duration is zero, at which point the FPGA begins to read the data input from the infrared detector;

[0010] When the frame counter C frame When the preset integration start time point is reached, the FPGA outputs the rising edge of the integration signal to complete the driving of the infrared detector interface signal within one frame period.

[0011] Furthermore, in an iteration of adjusting the expected duration and target duration, the following are included:

[0012] Obtain the estimated duration and target duration of this iteration;

[0013] When the estimated duration is equal to the target duration, the estimated duration is subtracted by one normal detector clock cycle to obtain the adjusted estimated duration; when the estimated duration is greater than the target duration, the estimated duration is subtracted by one long detector clock cycle to obtain the adjusted estimated duration; when the estimated duration is less than the target duration, the estimated duration is subtracted by one short detector clock cycle to obtain the adjusted estimated duration; the adjusted estimated duration is used as the estimated duration for the next iteration.

[0014] Subtract one normal detector clock cycle from the target duration to obtain the target duration for the next iteration.

[0015] Furthermore, the frame counter C is calculated using the following formula, from the falling edge of the FPGA output integral signal to the time point when the FPGA begins reading data from the infrared detector. frame The difference is used as the initial estimated duration:

[0016] T real =FREQ_CLK*100+(Div / 2-T shift )%Div+N wait*Div-T intneg

[0017] Among them, T real The initial estimated duration; FREQ_CLK is the local clock frequency of the FPGA; N wait The number of infrared detector clock cycles between the falling edge of the integral and the start of valid data output as required by the infrared detector timing; Div is the division ratio of the FPGA's internal clock and the infrared detector's clock; T intneg The frame counter C is the one that outputs the integral signal to the FPGA when the signal falls. frame The value is ; % is the modulo operation.

[0018] Furthermore, the initial target duration is the number of infrared detector clock cycles N between the falling edge of the integral required by the infrared detector timing and the start of valid data output. wait The product of the division ratio Div of the internal clock of the FPGA and the clock of the infrared detector.

[0019] Furthermore, a normal detector clock cycle is Div times the internal clock cycle of the FPGA; where Div is the frequency division ratio of the internal clock of the FPGA and the clock of the infrared detector;

[0020] The long detector clock cycle is Div+1 times the internal clock cycle of the FPGA;

[0021] The short detector clock cycle is Div-1 of the FPGA's internal clock cycles.

[0022] Furthermore, the frame counter C frame This frame counter C is used to accumulate the number of internal clock cycles that have elapsed within the current frame. When the external frame reset signal arrives, this frame counter C... frame After resetting to zero, the accumulation will start again.

[0023] Furthermore, the infrared detector clock divider counter C mc The system cyclically generates a count from 1 to Div, which is used to record the number of clock beats generated by dividing the internal clock of the FPGA to produce the clock of the infrared detector; where Div is the division ratio between the internal clock of the FPGA and the clock of the infrared detector.

[0024] Furthermore, the frame counter C corresponding to the preset rising edge time point of the integral signal frame The value is (T) frame -T int +1)*FREQ_CLK*100+(DIV / 2-T shift )%Div; where, Tframe For the ideal frame period; T int The preset integration time for the infrared detector; FREQ_CLK is the local clock frequency of the FPGA; N wait is the number of infrared detector clock cycles between the integrated falling edge of the infrared detector timing requirement and the start of valid data output; Div is the frequency division ratio of the FPGA's internal clock and the infrared detector's clock; % is the modulus take-off operation.

[0025] Furthermore, the FPGA uses an integration time counter C int Reaching T int When *FREQ_CLK*100, the falling edge of the output integral signal is simultaneously reached, and the integral time counter C... int The value of T is cleared to zero; where, T int The preset integration time for the infrared detector; FREQ_CLK is the local clock frequency of the FPGA.

[0026] Furthermore, the integration time counter C int It is used to control the integration time to reach the preset integration duration, and the accumulation begins when the FPGA outputs the integration signal at the rising edge.

[0027] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0028] 1. This invention dynamically adjusts the detector clock cycle output by the FPGA within the time interval T1 between the falling edge of the integral signal and the start of reading infrared detector data, so as to ensure that the number of detector clock cycles output by the FPGA between the falling edge of the integral signal and the start of reading infrared detector data is constant, thereby keeping the changing edges of the interface signals between the FPGA and the infrared detector and the data window at a fixed number of infrared detector clock beats under different external synchronization frame cycles.

[0029] 2. In this invention, there is no valid integral signal output from the FPGA to the infrared detector or valid data signal output from the infrared detector to the FPGA during the time interval T1 between the falling edge of the adjusted integral signal and the start of reading infrared detector data, thereby avoiding the influence of the changing infrared detector clock cycle on the output data of the infrared detector.

[0030] 3. This invention employs real-time time capture and dynamic adjustment, ensuring that the deviation between the external synchronization period and the ideal frame synchronization period does not exceed the processing limit (equal to N). wait It can compensate for different external synchronization frame period deviations, and has high applicability.

[0031] 4. This invention does not involve an internal or external synchronization switching mechanism, which can ensure that the equipment continues to work in the required state, thereby ensuring the stability of the equipment.

[0032] 5. This invention uses a small number of counters, caches the count values, and employs a simple state machine algorithm, introducing only a small amount of FPGA resources and having minimal impact on the device's resources and power consumption.

[0033] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0034] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0035] Figure 1 This is a timing diagram of the interface of the infrared detector in an embodiment of the present invention;

[0036] Figure 2 This is a flowchart illustrating an external synchronization method for an infrared detector driven by an FPGA, as described in an embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of FPGA frequency division generating the infrared detector clock in an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram illustrating the calculation of the time point when the FPGA starts reading data from the infrared detector and the rising edge time point of the FPGA output integral signal in an embodiment of the present invention. Detailed Implementation

[0039] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0040] This invention provides an external synchronization method for an infrared detector driven by an FPGA. When the infrared detector in a cooled infrared detector device is operating in IWR (Integral Readout) mode, and an external frame synchronization signal is used as the synchronization source, dynamic time adjustment of the driving signal output to the infrared detector is achieved based on the measurement and calculation of the period of the external synchronization signal. This ensures that the final output image of the infrared detector device is stable and is not affected by the non-homogeneity and instability of the clock generated by the external synchronization signal.

[0041] Specifically, such as Figure 1 The timing diagram of the infrared detector interface is shown below. T1 is the time interval between the falling edge of the integration signal output by the FPGA to the infrared detector and the time point when the FPGA starts reading data from the infrared detector. T2 is the time interval between the time point when the FPGA starts reading data from the infrared detector and the rising edge of the integration signal output by the FPGA to the infrared detector. T3 is the integration time of the infrared detector.

[0042] For infrared detectors operating in IWR (Integrating Readout) mode, once the integration time is determined, T1, T2, and T3 must all be fixed values ​​to ensure that the detector's effective output data does not produce abnormalities. Furthermore, according to the time relationship in the diagram, T1 + T2 + T3 equals the frame synchronization period. When the infrared detector is in external synchronization mode, the frame synchronization period is determined by an external clock source. The non-homogeneity and instability of the external clock source will cause changes in the frame synchronization period. Conventional solutions cannot meet the requirement of keeping T1, T2, and T3 constant.

[0043] Therefore, in a specific embodiment of the present invention, an external synchronization method for an infrared detector driven by an FPGA is disclosed, such as... Figure 2 As shown, it includes the following steps S1-S4:

[0044] Step S1: The FPGA receives an external frame synchronization signal and resets the frame counter C. frame The value of the infrared detector clock divider counter C is recorded. mc The current value T shift ;

[0045] Specifically, the external frame synchronization signal refers to a frame synchronization signal input from the device's external interface. This signal generates a pulse or level change edge at regular intervals. When the FPGA detects the arrival of this pulse signal or level change edge, it serves as the frame reset time point. The infrared detector device starts acquiring, processing, and outputting a new frame of image by responding to the frame synchronization signal. Therefore, the frequency of the frame synchronization signal is equal to the frame frequency of the output image. For example, for a 50Hz infrared detector device, the frame reset frequency is 50Hz, and the frame period is 1s / 50 = 20ms. The frame synchronization signal can be divided into internal synchronization and external synchronization methods depending on the source of its generation. In the internal synchronization method, the frame reset is generated by the infrared detector device based on the internal clock count of the infrared detector, producing a trigger signal with a fixed period. In the external synchronization method, the frame synchronization signal is input from an external device.

[0046] Furthermore, the FPGA is equipped with the following three counters:

[0047] The first one: Frame counter C frameThe frame counter C is used to accumulate the number of clock cycles that have elapsed within the current frame. When the external frame synchronization signal arrives, the frame counter C... frame After resetting to zero, the accumulation will start again.

[0048] The second one: Infrared detector clock divider counter C mc The counter cyclically generates counts from 1 to Div with a period of Div. It is used to count the internal clock of the FPGA to generate the clock for the infrared detector, which is divided by Div. This counter does not respond to frame synchronization signals. When the count reaches Div / 2, the FPGA outputs the rising edge of the infrared detector clock to pull the clock signal high; when the count reaches Div, the FPGA outputs the falling edge of the detector clock to pull the clock signal low. Here, Div is the division ratio between the FPGA's local internal clock and the clock output to the infrared detector; that is, the duration of one frame of the infrared detector clock is equal to the duration of Div frames of the FPGA's internal clock.

[0049] Specifically, the infrared detector requires an input clock frequency within a specified range, typically around 10MHz. The FPGA's local operating clock frequency is higher than the infrared detector's required clock frequency. Therefore, the FPGA's local operating clock frequency is divided, and the lower frequency clock output is given to the infrared detector as its required clock. For example, if the infrared detector's clock frequency is 10MHz and the FPGA's local operating clock frequency is 80MHz, then Div = 80MHz / 10MHz = 8, meaning 8 clock cycles from the FPGA's internal clock correspond to 1 clock cycle from the infrared detector.

[0050] For example, such as Figure 3 As shown, taking Div=8 as an example, when the frame reset arrives, the infrared detector clock divider counter C... mc The count value is T shift At this time, the corresponding frame counter C frame The value is 0, after (Div / 2-T) shift )%Div time, at this time, frame counter C frame The value is (Div / 2-T) shift )%Div, Infrared detector clock divider counter C mc The value is Div / 2, corresponding to the rising edge of the infrared detector clock. After another Div*N time intervals (N = 0, 1, 2, 3, 4...), the detector clock will experience its Nth rising edge. At this time, C... frame =(Div / 2-T) shift )%Div+Div*N. Therefore, for any frame counter C frame For time points where the value is an integer multiple of Div, increase by (Div / 2-T)shift )%Div's frame counter C frame The delay aligns the timing points to the rising edge of the infrared detector clock. The start and end times of the integral signal output from the FPGA to the infrared detector, as well as the start time of the FPGA reading data from the infrared detector, all need to be aligned to the rising edge of the infrared detector clock to meet the timing requirements of the infrared detector.

[0051] The third one: Integral time counter C int When the frame counter C frame When the count reaches the set rising edge time of the integration signal, the FPGA outputs the rising edge of the integration signal to pull up the integration signal of the infrared detector. At this time, the integration time counter C... int Start accumulating from zero, and continue accumulating until the count reaches the value corresponding to the set integration time (T). int When *FREQ_CLK*100 is reached, the counter is cleared and accumulation stops. Simultaneously, the falling edge of the FPGA outputs the integration signal to pull down the integration signal of the infrared detector. This counter does not respond to frame reset. Where T... int The preset integration time for the infrared detector is 0.1ms; FREQ_CLK is the local clock frequency of the FPGA, in MHz.

[0052] It should be noted that the preset integration time T of the infrared detector int It is an adjustable value. Depending on the scene and temperature of the target being detected by the infrared detector, it needs to be set to different values, with a range of 0.1ms to (ideal frame period - 0.1ms).

[0053] Step S2: When the FPGA outputs the falling edge of the integral signal, based on the frame counter C... frame The current value T intneg and T shift The duration between the falling edge of the FPGA output integral signal and the time point at which the FPGA begins reading data from the infrared detector is calculated as the initial estimated duration.

[0054] Specifically, as described above, when the integration time counter C int Accumulated to T int When *FREQ_CLK*100, the FPGA outputs a falling edge of the integration signal to the infrared detector and pulls down the integration signal of the infrared detector.

[0055] It should be noted that when the frame counter C frame Reaching (T) frame -T int +1)*FREQ_CLK*100+(Div / 2-T shiftWhen %Div occurs, the rising edge of the FPGA outputs the integral signal and pulls up the integral signal of the infrared detector, where T frame The ideal frame synchronization period is 0.1ms, which is determined by the frame rate of the infrared detector.

[0056] Specifically, such as Figure 4 As shown, under ideal conditions (the frame synchronization period is stable and equal to the ideal frame synchronization period), the falling edge of the preset integral signal is located 0.1ms after the frame reset. Therefore, under this idealized assumption, the frame counter C... frame The time point when the count reaches 0.1ms corresponds to the falling edge of the integral signal. When the frame counter C... frame Counting to the ideal frame period T frame At time point +0.1ms (assuming that C in this frame arrives after the frame synchronization signal), frame (Instead of resetting to 0, it continues counting), which will generate the next falling edge of the integration signal. At this time, the corresponding frame counter C... frame The count value is: (T) frame +1)*0.1*10 -3 *FREQ_CLK*10 6 That is: (T) frame +1)*100*FREQ_CLK.

[0057] Based on the above, the preset integration time T of the infrared detector int The falling edge of the above integral signal is pushed forward by T. int The frame counter C corresponding to the rising edge time point of the ideal integral signal is obtained at the given time. frame Count value: (T) frame -T int +1)*FREQ_CLK*100, align this time point to the rising edge of the infrared detector clock, and obtain: F intpos =(T frame -T int +1)*FREQ_CLK*100+(Div / 2-T shift The time point of %Div is taken as the time point corresponding to the rising edge of the FPGA output integral signal. frame Count value.

[0058] Based on the ideal time of 0.1ms between the falling edge of the integrated signal and the frame reset, and the time interval N between the falling edge of the integrated signal and the rising edge of the data readout signal required by the infrared detector timing,... wait The frame counter C is set to the ideal time point when the FPGA starts reading data from the infrared detector, based on the clock cycle of the infrared detector. frameThe value is 1*FREQ_CLK*100+N wait *Div, then align this time point to the rising edge of the detector clock to obtain the frame counter C corresponding to the ideal time point when the FPGA starts reading infrared detector data. frame Count value F data :

[0059] F data =FREQ_CLK*100+(Div / 2-T shift )%Div+N wait *Div

[0060] Therefore, the time interval between the FPGA starting to read infrared detector data and the rising edge of the output integral signal (the frame counter C) frame The difference in count values ​​is: T2 = F intpos -F data =(T frame -T int )*FREQ_CLK*100-N wait *Div, due to the ideal frame period T frame Detector integration time T int The FPGA local clock frequency FREQ_CLK, and the number of detector clock cycles N between the falling edge of the detector timing requirement and the start of valid data output. wait Since the division ratio Div of the internal clock of the FPGA and the clock output to the infrared detector are both fixed values, T2 can be obtained as a fixed value. And since the integral time counter C... int The value of is fixed, therefore, the integration time T3 of the infrared detector is also a fixed value.

[0061] Since the external synchronization period is determined by an external source in external synchronization mode, and the arrival time of the external frame synchronization signal is uncertain, the end point of T3 is the frame counter C in the next frame. frame The value is uncertain. Assume that the frame counter C arrives when an external frame reset occurs. frame If it is not cleared to zero, then when the falling edge of the FPGA output integral signal occurs, the frame counter C... frame The count value should be F. intpos +T int *100*FREQ_CLK. However, due to the frame counter C arriving at the next frame reset... frame The frame counter C needs to be reset and restarted. Assume that when the next frame reset arrives, the frame counter C... frame The count value is T' frame Then at this time, the frame counter C frame The count value will be from T' frameIt becomes 0 and starts accumulating again, accumulating up to F. intpos +T int *100*FREQ_CLK-T' frame At the falling edge of the FPGA output integral signal, the frame counter C is recorded. frame Let the value be T. intneg Then T intneg =F intpos +T int *100*FREQ_CLK-T' frame Because of T' frame The uncertainty of T leads to intneg There is an uncertainty, specifically the time interval between the arrival of the frame synchronization signal and the falling edge of the FPGA output integration signal. The time interval T1 between the falling edge of the integration signal and the start of reading infrared detector data is FREQ_CLK*100+(Div / 2-T). shift )%Div+N wait *Div-T intneg By dynamically adjusting the clock period output by the FPGA to the infrared detector within time T1, the FPGA generates N. wait One infrared detector clock cycle is used to ensure that the interface signals and data between the FPGA and the infrared detector still meet the timing requirements under the infrared detector clock.

[0062] It should be noted that, since there is no valid integral signal and valid data output from the FPGA to the infrared detector during the time interval T1 between the falling edge of the integral signal and the start of reading the infrared detector data, dynamically adjusting the clock cycle of the infrared detector during the time interval T1 can avoid affecting the output data of the infrared detector.

[0063] Furthermore, the estimated duration from the falling edge of the FPGA output integral signal to the point when the FPGA begins reading data from the infrared detector is calculated using the following formula, and this duration is used as the initial estimated duration for the iteration:

[0064] T real =FREQ_CLK*100+(Div / 2-T shift )%Div+N wait *Div-T intneg

[0065] Among them, T real The initial estimated duration; FREQ_CLK is the internal clock frequency of the FPGA, in MHz; N waitThe number of infrared detector clock cycles from the falling edge of the integral to the start of valid data output is the timing requirement of the infrared detector; Div is the division ratio of the FPGA's internal clock and the infrared detector's clock; T intneg The frame counter C is the one that outputs the integral signal to the FPGA when the signal falls. frame The value is ; % is the modulo operation.

[0066] Step S3: Based on the initial estimated duration and the initial target duration, the estimated duration and the target duration are adjusted iteratively multiple times until the current estimated duration is zero, at which point the FPGA begins to read the infrared detector data;

[0067] Furthermore, the initial target duration is defined as the number of infrared detector clock cycles N between the falling edge of the integral of the infrared detector timing requirement and the start of valid data output. wait The product of the division ratio Div of the internal clock of the FPGA and the clock of the infrared detector is denoted as T. target That is, T target =N wait* Div.

[0068] It should be noted that, as mentioned above, the time interval between the falling edge of the integral and the start of outputting valid data required by the infrared detector timing is N. wait One beat of the infrared detector clock, and the duration of one beat of the infrared detector clock is equal to that of one Div beat of the FPGA's internal clock, therefore, the target duration is T. target The internal clock cycle of the FPGA is captured.

[0069] Furthermore, in an iteration of adjusting the expected duration and target duration, the following are included:

[0070] Obtain the estimated duration and target duration of this iteration; where the estimated duration of the first iteration is the initial estimated duration, and the target duration of the first iteration is the initial target duration;

[0071] When the expected duration is equal to the target duration, the FPGA outputs a normal detector clock cycle, and at the same time, the expected duration is subtracted by a normal detector clock cycle to obtain the adjusted expected duration.

[0072] When the expected duration is greater than the target duration, the FPGA outputs a long detector clock cycle, and at the same time, the expected duration is subtracted by a long detector clock cycle to obtain the adjusted expected duration.

[0073] When the expected duration is less than the target duration, the FPGA outputs a short detector clock cycle, and the expected duration is subtracted by the short detector clock cycle to obtain the adjusted expected duration.

[0074] The adjusted estimated duration will be used as the estimated duration for the next iteration.

[0075] Subtract one normal detector clock cycle from the target duration to obtain the target duration for the next iteration.

[0076] It should be noted that the estimated duration T real With the target duration T target The number of clock cycles of the FPGA's internal clock between the falling edge of the integral signal and the start of reading infrared detector data can be determined by the frame counter C. frame The change in the count value is used to determine this.

[0077] Specifically, the target duration T target Iterative calculations are performed according to the normal detector clock cycle, that is, T is calculated in each iteration. target -Div serves as the target duration for the next iteration.

[0078] When the estimated duration T real =The target duration T target When the time is equal to the time required to output the remaining infrared detector clock cycles, it means that the time required is equal to the ideal time. Therefore, the FPGA needs to output one detector clock cycle in the form of the ideal detector clock cycle. Correspondingly, the expected time T is... real Iterative calculations are performed according to the normal detector clock cycle, i.e., T... real -Div sets the expected duration T for the next iteration. real .

[0079] When the estimated duration T real >The target duration T target When the time required to output the remaining infrared detector clock cycles is greater than the ideal time, the FPGA needs to output a detector clock cycle in a manner longer than the ideal detector clock cycle. Correspondingly, the expected time T... real Iterative calculations are required over a long detector clock cycle. After Div / 2+1 cycles, the FPGA outputs the falling edge of the infrared detector clock, and after another Div / 2 cycles, the FPGA outputs the falling edge of the infrared detector clock again. This sets T... real -(Div / 2+1+Div / 2)=T real -(Div+1) sets the expected duration T for the next iteration.real Through this iteration, the estimated duration T... real With the target duration T target The positive difference between them will decrease by 1.

[0080] Furthermore, the long detector clock cycle is one normal detector clock cycle (in units of FPGA internal clock cycles) + 1, i.e., Div+1; for example, when Div = 8, a long detector clock cycle = 9.

[0081] When the estimated duration T real <The target duration T target When the time required to output the remaining infrared detector clock cycles is less than the ideal time, the FPGA needs to output one detector clock cycle in a manner shorter than the ideal detector clock cycle. Correspondingly, the expected time T... real Iterative calculations are required based on a segment of the detector clock cycle. After Div / 2-1 cycles, the FPGA outputs the rising edge of the infrared detector clock, and after Div / 2 cycles, the FPGA outputs the falling edge of the infrared detector clock, setting T... real -(Div / 2-1+Div / 2)=T real -(Div-1) sets the expected duration T for the next iteration. real Through this iteration, the estimated duration T... real With the target duration T target The negative difference between them will increase by 1.

[0082] Furthermore, the short detector clock cycle is one normal detector clock cycle (in units of FPGA internal clock cycles) - 1, i.e., Div-1; for example, when Div = 8, a short detector clock cycle = 7.

[0083] Repeat the above iterations until the expected duration T is reached. real When the value is 0, the FPGA begins reading data from the infrared detector.

[0084] Step S4, in the frame counter C frame When the preset rising edge time of the integral signal is reached, the FPGA outputs the rising edge of the integral signal to pull up the integral signal of the infrared detector, thus completing the driving of the infrared detector interface signal within one frame synchronization cycle.

[0085] Furthermore, as mentioned above, the frame count value C corresponding to the rising edge time point of the preset integral signal frame The value is (T) frame -T int+1)*FREQ_CLK*100+(DIV / 2-T shift )%Div; where, T frame The ideal frame period is 0.1ms; T int The preset integration time for the infrared detector is 0.1ms; FREQ_CLK is the local clock frequency of the FPGA, in MHz; N wait is the number of infrared detector clock cycles between the integrated falling edge and the start time of valid data, as required by the timing of the infrared detector; Div is the frequency division ratio between the internal clock of the FPGA and the clock of the infrared detector; % is the modulus take-off operation.

[0086] The above process completes the synchronization of interface signals and data between the FPGA and the infrared detector when an external frame synchronization signal is used as the synchronization source.

[0087] In summary, the FPGA-driven external synchronization method for infrared detectors of this invention has the following beneficial effects:

[0088] 1. This invention dynamically adjusts the infrared detector clock cycle output by the FPGA within the time interval T1 between the falling edge of the integral signal output by the FPGA and the start of reading infrared detector data. This ensures that the FPGA outputs a fixed number of detector clock cycles within this time interval, thereby fixing the number of clock cycles received by the detector between the falling edge of the integral signal and the start of reading infrared detector data. This ensures that the interface signals and data between the FPGA and the infrared detector always meet the timing requirements under the infrared detector clock.

[0089] 2. In this invention, there is no valid integral signal output from the FPGA to the infrared detector and valid data output from the infrared detector to the FPGA during the time interval T1 between the falling edge of the adjusted integral signal and the start of reading infrared detector data. This avoids the influence of the dynamically changing infrared detector clock cycle on the output data of the infrared detector.

[0090] 3. This invention employs real-time time capture and dynamic adjustment, ensuring that the deviation between the external synchronization period and the ideal frame synchronization period does not exceed the processing limit (equal to N). wait It can compensate for different external synchronization frame period deviations, and has high applicability.

[0091] 4. This invention does not involve an internal or external synchronization switching mechanism, which can ensure that the equipment works in the required state, thereby ensuring the stability of the equipment.

[0092] 5. This invention uses a small number of counters, caches the count values, and employs a simple state machine algorithm, introducing only a small amount of FPGA resources and having minimal impact on the device's resources and power consumption.

[0093] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An external synchronization method for an infrared detector driven by an FPGA, characterized in that, The method includes the following steps: The FPGA receives an external frame synchronization signal and resets the frame counter C. frame The value of the infrared detector clock divider counter C is recorded. mc The current value T shift ; When the falling edge of the FPGA output integration signal occurs, based on the frame counter C frame The current value T intneg and T shift The duration between the falling edge of the FPGA output integral signal and the time point at which the FPGA begins reading data from the infrared detector is calculated as the initial estimated duration. Based on the initial estimated duration and the initial target duration, the estimated duration and the target duration are adjusted iteratively multiple times until the current estimated duration is zero, at which point the FPGA begins to read the data input from the infrared detector; When the frame counter C frame When the value corresponding to the preset integration start time point is reached, the FPGA outputs the rising edge of the integration signal to complete the driving of the infrared detector interface signal within one frame period. An iteration of adjusting the estimated duration and target duration includes: Obtain the estimated duration and target duration of this iteration; When the estimated duration is equal to the target duration, the estimated duration is subtracted by one normal detector clock cycle to obtain the adjusted estimated duration; when the estimated duration is greater than the target duration, the estimated duration is subtracted by one long detector clock cycle to obtain the adjusted estimated duration; when the estimated duration is less than the target duration, the estimated duration is subtracted by one short detector clock cycle to obtain the adjusted estimated duration; the adjusted estimated duration is used as the estimated duration for the next iteration. Subtract one normal detector clock cycle from the target duration to obtain the target duration for the next iteration.

2. The method according to claim 1, characterized in that, The frame counter C, calculated using the following formula, is the time between the falling edge of the FPGA output integral signal and the point at which the FPGA begins reading data from the infrared detector. frame The difference is used as the initial estimated duration: T real =FREQ_CLK 100+(Div / 2-T shift )%Div+N wait Div-T intneg Among them, T real The initial estimated duration; FREQ_CLK is the local clock frequency of the FPGA; N wait The number of infrared detector clock cycles between the integrated falling edge of the infrared detector's timing requirement and the start of valid data output; Div is the division ratio of the FPGA's internal clock and the infrared detector's clock; T intneg The frame counter C is the one that outputs the integral signal to the FPGA when the signal falls. frame The value is ; % is the modulo operation.

3. The method according to claim 2, characterized in that, The initial target duration is the number of infrared detector clock cycles N between the integral falling edge of the infrared detector timing requirement and the start of valid data output. wait The product of the division ratio Div of the internal clock of the FPGA and the clock of the infrared detector.

4. The method according to any one of claims 1-3, characterized in that, A normal detector clock cycle is Div times the internal clock cycle of the FPGA; where Div is the frequency division ratio of the internal clock of the FPGA and the clock of the infrared detector; The long detector clock cycle is Div+1 times the internal clock cycle of the FPGA; The short detector clock cycle is Div-1 of the FPGA's internal clock cycles.

5. The method according to claim 1, characterized in that, The frame counter C frame This frame counter C is used to accumulate the number of internal clock cycles that have elapsed within the current frame. When the external frame reset signal arrives, this frame counter C... frame After resetting to zero, the accumulation will start again.

6. The method according to claim 5, characterized in that, The infrared detector clock divider counter C mc The system cyclically generates a count from 1 to Div, which is used to record the number of clock beats generated by dividing the internal clock of the FPGA to produce the clock of the infrared detector; where Div is the division ratio between the internal clock of the FPGA and the clock of the infrared detector.

7. The method according to claim 1, characterized in that, The frame counter C corresponding to the preset integration start time point frame The value is (T) frame -T int +1) FREQ_CLK 100+ (Div / 2-T) shift )%Div; where T frame For the ideal frame period; T int The preset integration time for the infrared detector; FREQ_CLK is the local clock frequency of the FPGA; Div is the division ratio between the internal clock of the FPGA and the clock of the infrared detector; % is the modulus operation.

8. The method according to claim 1, characterized in that, The FPGA uses an integration time counter C int Reaching T int FREQ_CLK At 100, the falling edge of the output integration signal is activated, and simultaneously the integration time counter C... int The value of T is cleared to zero; where, T int The preset integration time for the infrared detector; FREQ_CLK is the local clock frequency of the FPGA.

9. The method according to claim 8, characterized in that, The integral time counter C int It is used to control the integration time to reach the preset integration duration, and the accumulation begins when the FPGA outputs the integration signal at the rising edge.

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