Photoelectric conversion device and equipment

Abstract

The invention relates to a photoelectric conversion device and equipment. A photoelectric conversion device is provided. The apparatus includes a pixel array, an A / D conversion circuit that converts a pixel signal output from the pixel array into a digital signal, and a signal line to which a reference signal having a different changed gradient is supplied. Each of the A / D conversion circuits includes a comparator that compares the pixel signal with the reference signal, a selector that selects one of the signal lines to which the reference signal for A / D conversion is supplied, and a connector that connects the signal lines to the comparator. The connector connects a signal line selected by the selector among the signal lines to the comparator via a buffer and connects a signal line not selected by the selector among the signal lines to a load capacitive element via another buffer different from the buffer.

Description

Technical Field

[0001] This disclosure relates to photoelectric conversion devices and equipment. Background Technology

[0002] It is known that photoelectric conversion devices perform A / D conversion by comparing pixel signals output from pixels with time-varying reference signals using a comparator. Japanese Patent Application Publication No. 2013-179577 discloses a solid-state imaging device to which multiple types of reference signals of different gradients are supplied. For each column of readout signals, the reference signal used for A / D conversion is selected based on the signal level of the pixel signal. When selecting a reference signal for each column, the number of loads to be connected to each reference signal line changes for each A / D conversion, and this change in load can alter the signal level of the reference signal and reduce the accuracy of the A / D conversion. Figure 16 of Japanese Patent Application Publication No. 2013-179577 shows an arrangement in which a buffer is connected between each reference signal line and the comparator to suppress changes in the load connected to each reference signal line regardless of which reference signal line is used. Summary of the Invention

[0003] Some embodiments of this disclosure provide techniques that are advantageous in further improving the accuracy of A / D conversion.

[0004] According to some embodiments, a photoelectric conversion device is provided, the photoelectric conversion device including a pixel array, a plurality of A / D conversion circuits, and a plurality of reference signal lines. The pixel array is provided with a plurality of pixels. The plurality of A / D conversion circuits are configured to convert pixel signals output from the pixel array into digital signals. Reference signals with different gradients are supplied to the plurality of reference signal lines. Each of the plurality of A / D conversion circuits includes a comparator circuit, a selector, and a connector. The comparator circuit is configured to compare the pixel signals with the reference signals. The selector is configured to select the reference signal line from the plurality of reference signal lines to which the reference signal for A / D conversion is supplied. The connector is configured to connect the reference signal line selected by the selector to the comparator circuit via a buffer and to connect the reference signal line not selected by the selector to a load capacitor element via a buffer different from the buffer.

[0005] Further features of the invention will become clear from the following description of exemplary embodiments (with reference to the accompanying drawings). Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating an example arrangement of the photoelectric conversion device according to this embodiment;

[0007] Figure 2 It is shown Figure 1 A circuit diagram illustrating an example of the arrangement of pixels in a photoelectric conversion device;

[0008] Figure 3 It is shown Figure 1 A circuit diagram illustrating an example of the arrangement of the A / D conversion circuit in a photoelectric conversion device;

[0009] Figure 4 It is shown Figure 1 A timing diagram illustrating the operation of a photoelectric conversion device;

[0010] Figure 5 It is shown Figure 1 A circuit diagram illustrating an example of the arrangement of the A / D conversion circuit in a photoelectric conversion device;

[0011] Figure 6 It is shown Figure 1 A circuit diagram illustrating an example of the arrangement of the A / D conversion circuit in a photoelectric conversion device; and

[0012] Figure 7 It shows the incorporation Figure 1 A view showing an example of the arrangement of photoelectric conversion devices. Detailed Implementation

[0013] In the following, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention. Several features are described in the embodiments, but it is not a limitation requiring all such features, and multiple such features can be suitably combined. Furthermore, in the drawings, the same reference numerals are given to the same or similar configurations, and redundant descriptions thereof are omitted.

[0014] Reference Figures 1 to 6 A photoelectric conversion device according to an embodiment of the present disclosure is described. Figure 1 This is a block diagram illustrating an example arrangement of a photoelectric conversion device 100. The photoelectric conversion device 100 includes a pixel array 101, a vertical readout circuit 102, an analog-to-digital (A / D) conversion circuit 104, a column memory 106, a horizontal scanning circuit 107, a signal processing circuit 115, a signal output circuit 112, a vertical scanning circuit 110, and a timing generator 111. The photoelectric conversion device 100 also includes a reference bias circuit 103, a reference bias circuit 105, a ramp signal generation circuit 108, a phase-locked loop (PLL) circuit 113, and a counter 109.

[0015] Pixel array 101 has multiple pixels 121 arranged in a two-dimensional array pattern to form multiple rows and multiple columns. Vertical readout circuit 102 is provided to read pixel signals from pixel array 101. Reference bias circuit 103 can generate a reference bias for vertical readout circuit 102 and can also generate pulse signals for controlling vertical readout circuit 102. A / D conversion circuit 104 converts the pixel signals, which are analog signals, output from pixel array 101 into digital signals. Figure 1 The A / D conversion circuit 104 is shown as a block diagram. The photoelectric conversion device 100 is provided with multiple A / D conversion circuits 104 to correspond respectively to multiple vertical output lines 114 provided according to, for example, pixel rows of pixel array 101. The A / D conversion circuit 104 will be described in detail later. The reference bias circuit 105 can generate a reference bias for the A / D conversion circuit 104 and can also generate pulse signals for controlling the A / D conversion circuit 104. The ramp signal generation circuit 108 generates a reference signal (ramp signal) for comparison with the pixel signals in the A / D conversion circuit 104. The ramp signal generation circuit 108 supplies multiple types of reference signals with different gradients over time via multiple reference signal lines. The column memory 106 holds the value of the counter 109 according to the conversion result obtained by the A / D conversion circuit 104. The PLL circuit 113 generates a reference clock used in the counter 109. The horizontal scan circuit 107 transmits the digital value held in the column memory 106 to the signal processing circuit 115. Signal output circuit 112 is a circuit for outputting the signal processed by signal processing circuit 115 from photoelectric conversion device 100 to the outside. Vertical scanning circuit 110 scans pixel array 101 in the vertical direction. Vertical scanning circuit 110 scans pixel array to output pixel signal from pixel 121. Timing generator 111 supplies control signals to reference bias circuits 103 and 105, ramp signal generation circuit 108, counter 109, vertical scanning circuit 110, and PLL circuit 113 to control the operation of various components provided in photoelectric conversion device 100. In this case, vertical readout circuit 102 includes a current source load for reading pixel signal from pixel 121 or a column amplifier for current source load and signal amplification. In this embodiment, vertical readout circuit 102 is exemplified as a current source load.

[0016] Figure 2 This is a circuit diagram showing an example of the arrangement of pixel 121. Figure 2The connection between pixel 121, vertical readout circuit 102, and A / D conversion circuit 104 is also shown. Pixel 121 includes a photodiode 201, a transfer transistor 202, a reset transistor 203, an amplification transistor 205, and a selection transistor 206. The photodiode 201 generates a charge corresponding to the incident light. The transfer transistor 202 transfers the charge converted by the photodiode 201 to the floating diffuser 204. The reset transistor 203 resets the floating diffuser 204 to the potential of the power line VDD. The amplification transistor 205 is an amplifying transistor that converts the signal from the floating diffuser 204 into a voltage signal. The selection transistor 206 is arranged between the amplification transistor 205 and the vertical output line 114. When the selection transistor 206 is set to the ON (conducting) state, the pixel signal is output from pixel 121 to the vertical scan line 141.

[0017] A control signal pTX is supplied to the gate of the transfer transistor 202. If the control signal pTX is high (Hi), the transfer transistor 202 is turned on to transfer the charge converted by the photodiode 201 to the floating diffuser 204. A control signal pFDRES is supplied to the gate of the reset transistor 203. If the control signal pFDRES is high, the reset transistor 203 is turned on to establish continuity between the floating diffuser 204 and the power line VDD and reset the floating diffuser 204 to the potential of the power line VDD. A control signal pSEL is supplied to the gate of the select transistor 206. If the control signal pSEL is high, the select transistor is turned on to electrically connect the source of the amplifying transistor 205 to the vertical output line 114.

[0018] The vertical readout circuit 102 and the A / D conversion circuit 104 are connected to the vertical output line 114. In this embodiment, as described above, the vertical readout circuit 102 is a current source load.

[0019] Figure 3 This is a circuit diagram illustrating an example arrangement of the A / D conversion circuit 104 according to this embodiment. As described above, although the photoelectric conversion device 100 is provided with multiple A / D conversion circuits 104, Figure 3A circuit arrangement for an A / D conversion circuit 104 is shown. The A / D conversion circuit 104 may include a comparator circuit 304, a selector 303, buffers 301 and 302, and a connector. The comparator circuit 304 compares a pixel signal supplied from a pixel array 101 with a reference signal supplied from a ramp signal generation circuit 108. The selector 303 selects the reference signal line supplied for A / D conversion from a plurality of reference signal lines 321 and 322 connected to the ramp signal generation circuit 108. The connector connects the reference signal line selected by the selector 303 from reference signal lines 321 and 322 to the comparator circuit 304 via one of buffers 301 and 302. The connector connects the reference signal line not selected by the selector 303 from reference signal lines 321 and 322 as a reference signal line for A / D conversion to a load capacitor element 310 via another of buffers 301 and 302. Figure 3 The arrangement shown provides two reference signal lines 321 and 322, to which two different types of reference signals with varying gradients over time are supplied. Furthermore, this arrangement provides two buffers 301 and 302. However, it is not limited to this. The arrangement may provide three or more reference signal lines, to which three or more different types of reference signals with varying gradients over time are supplied, and three or more buffers are provided depending on the number of reference signal lines in the arrangement. The number of reference signal lines supplied with reference signals may be equal to the number of buffers provided in an A / D conversion circuit 104.

[0020] exist Figure 3 In the arrangement shown, multiple reference signal lines 321 and 322 are respectively connected to the input nodes of multiple buffers 301 and 302, such that one reference signal line corresponds to one buffer. More specifically, the input node of buffer 301 is connected to reference signal line 321, and the input node of buffer 302 is connected to reference signal line 322. The ramp signal generation circuit 108 supplies reference signals 1 and 2, which are different at varying gradients, to reference signal lines 321 and 322, respectively.

[0021] The output node of buffer 301 is connected to one of the two terminals of each of switches 311 and 314. The output node of buffer 302 is connected to one of the two terminals of each of switches 312 and 313. One terminal of switch 311 that is not connected to a terminal of buffer 301 and one terminal of switch 312 that is not connected to a terminal of buffer 302 are connected to the load capacitor element 310. Figure 3As shown, load capacitor element 310 may be a grounded capacitor element with one terminal connected to ground level. One of the two terminals of switch 314 that is not connected to one terminal of buffer 301 and one of the two terminals of switch 313 that is not connected to one terminal of buffer 302 are connected to clamping capacitor element 307, which is connected to the positive input terminal, which is one of the input nodes of comparator circuit 304.

[0022] Switch 305 is provided between the positive input terminal and the negative output terminal of comparator circuit 304. Vertical output line 114 is connected to the negative input terminal of comparator circuit 304 via clamping capacitor element 308. Switch 306 is provided between the negative input terminal and the positive output terminal of comparator circuit 304. The negative output terminal of comparator circuit 304 is connected to selector 303 and column memory 106.

[0023] Selector 303 also functions as a circuit for determining the signal level of the supplied pixel signal, and selects one of the multiple reference signal lines 321 and 322 to which the reference signal for A / D conversion is supplied, based on the determination result. If the output from selector 303 is low (Lo), then switches 311 and 313 are set to the OFF (non-conducting) state. Furthermore, if the output from inverter 309 is high, then switches 312 and 314 are set to the ON state. That is, as described above, selector 303 functions as a circuit for selecting one of the reference signal lines 321 and 322 to which the reference signal for A / D conversion is supplied. Furthermore, switches 311 to 314 serve as connectors for connecting reference signal lines 321 and 322 via buffers 301 and 302 to the comparator circuit 304 or the load capacitor element 310. Switches 311 to 314 are configured to switch the connection between the output nodes of buffers 301 and 302 and the input nodes of the comparator circuit 304 and the load capacitor element 310.

[0024] Control signals 1 to 3 are supplied to selector 303. Control signals 1 to 3 can be supplied from timing generator 111 or from a selector control circuit that operates according to control signals supplied from timing generator 111. Control signal 1 is the reset signal for selector 303. For example, if a high-level signal is supplied, selector 303 is reset. Control signal 2 is the input enable signal for selector 303. If the input enable signal is high, selector 303 accepts the input signal. Control signal 3 is the output enable signal for selector 303. If the output enable signal is high, the determined result obtained by selector 303 is output.

[0025] Next, we will refer to Figure 4 The operation of pixel 121 and A / D conversion circuit 104 is described. At time t1, control signal pSEL is set to high, and selection transistor 206 switches to the ON state. As a result, the source of amplification transistor 205 is connected to vertical output line 114. During the interval from time t0 to time t3, control signal pFDRES is set to high, reset transistor 203 is set to the ON state, and floating diffuser 204 is reset to the potential of power line VDD.

[0026] Assume that the potential PIXSIG of the vertical output line 114 is potential Vn when the floating diffuser 204 is reset. For example, when the reset transistor 203 changes to the OFF state, the potential of the floating diffuser 204 changes. This change also occurs as a potential change at potential PIXSIG. However, for simplicity, this specification does not mention the potential change caused when the reset transistor 203 changes between the ON and OFF states.

[0027] During the interval from time t0 to time t2, control signal 1 supplied to selector 303 is set to a high level to reset the state of selector 303. The output from the reset selector 303 is set to a low level. Since control signal 3 remains low until time t13, selector 303 maintains a low output level until time t13. Accordingly, during the interval from time t0 to time t13, switches 311 and 313 are set to the OFF (non-conducting) state, and switches 312 and 314 are set to the ON state. For this reason, buffer 301 connected to reference signal line 321 is connected to comparator circuit 304 via clamping capacitor element 307, and buffer 302 connected to reference signal line 322 is connected to load capacitor element 310. That is, the potential of node C between buffers 301 and 302 and clamping capacitor element 307 (comparator circuit 304) is the potential of reference signal line 321 until time t13.

[0028] The potential Vrampres, which is the initial potential of the ramp signal generation circuit 108 in the period from time t0 to time t4, is supplied to the reference signal line 321. Further, the potential Vrampres is supplied from the ramp signal generation circuit 108 to the reference signal line 322 in the period from time t0 to time t14.

[0029] In the period from time t4 to time t5, the control signal pAZ is set to the high level. The control signal pAZ is a signal for controlling the switches 305 and 306. In the period when the control signal pAZ is at the high level, the switches 305 and 306 are in the ON state. In the period from time t4 to time t6, a potential that has decreased by ΔVoffset from the potential Vrampres is supplied to the reference signal line 321.

[0030] In the period when the control signal pAZ is at the high level, the reference signal line 321 is connected to the clamping capacitor element 307 via the buffer 301, and the vertical output line 114 is connected to the clamping capacitor element 308. The potentials at this time are written into the clamping capacitor element 307 and the clamping capacitor element 308, respectively. At time t5, the control signal pAZ is set to the low level, and the switches 305 and 306 change to the OFF state, thereby terminating the clamping operation.

[0031] By means of this clamping operation, the potentials of the positive input terminal and the negative input terminal of the comparison circuit 304 become the same, and the output comp_o of the comparison circuit 304 is equal to the output of each input terminal. The potential at this time changes depending on the circuit arrangement. In the following description, it is assumed that this potential is the potential Vcres.

[0032] At time t6, the potential of the reference signal line 321 returns to the potential Vrampres. At this time, the potential Vinp of the positive input terminal and the potential Vinn of the negative input terminal of the comparison circuit 304 have a relationship defined by Vinp > Vinn, so the output comp_o of the comparison circuit 304 is set to the low level. At time t7, the reference signal 1 is supplied to the reference signal line 321, and the potential of the reference signal line 321 decreases from the potential Vrampres at a gradient A.

[0033] If the potential of the node C combined with the change in the potential of the reference signal line 321 decreases by approximately ΔVoffset from the potential Vrampres, then the potential Vinp of the positive input terminal and the potential Vinn of the negative input terminal of the comparison circuit 304 have a relationship defined by Vinp < Vinn. As a result, the output comp_o of the comparison circuit 304 changes to the high level. This change occurs near the time tn1 shown in Figure 4 and the potential Vn of the vertical output line 114 at time tn1 undergoes A / D conversion.

[0034] At time t8, the potential of the reference signal line 321 returns to the potential Vrampres. With this operation, since the potential Vinp of the positive input terminal and the potential Vinn of the negative input terminal of the comparison circuit 304 have a relationship defined by Vinp > Vinn, the output comp_o of the comparison circuit 304 is set to a low level.

[0035] At time t9, the control signal pTX is set to a high level, and the charge photoelectrically converted by the photodiode 201 is transferred to the floating diffusion section 204. If no light enters the photodiode 201 and no charge is stored in the photodiode 201 (during the dark time), then no charge is transferred to the floating diffusion section 204, and the potential PIXSIG is maintained at the potential Vn as indicated by the solid line. In practice, there are dark current components and potential changes in the floating diffusion section 204 when the transfer transistor 202 operates. However, such changes are not considered in this case. In contrast, if charge is stored in the photodiode 201 and transferred to the floating diffusion section 204, then the potential PIXSIG changes as indicated by the broken line. Assume that the voltage change on the vertical output line 114 due to this stored charge is represented by ΔVsigs.

[0036] At time t10, the control signal pTX is set to a low level to set the transfer transistor 202 to an OFF state. This completes the transfer of charge from the photodiode 201 to the floating diffusion section 204.

[0037] In the period from time t9 to time t12, the potential of the reference signal line 321 decreases by ΔVjdg from the potential Vrampres. The voltage ΔVjdg is a comparison voltage for determining the signal level of the potential PIXSIG. The selector 303 determines whether ΔVsig is greater than or less than (ΔVjdg - ΔVoffset). The determination operation will be described next.

[0038] During the dark time, at time t9, at the end of the clamping operation, the change amount of the potential Vinn of the negative input terminal of the comparison circuit 304 is 0V, and the change amount of the potential Vinp of the positive input terminal is -(ΔVjdg - ΔVoffset). Accordingly, Vinp < Vinn, and the output comp_o from the comparison circuit 304 transitions to a high level and is input to the selector 303.

[0039] In contrast, if the potential PIXSIG changes by ΔVsigs when irradiated with light, the photodiode operates as follows. Compared with the state at the end of the clamping operation, the change in the potential Vinn of the negative input terminal of the comparator circuit 304 is -ΔVsigs, and the change in the potential Vinp of the positive input terminal is -(ΔVjdg - ΔVoffset). When ΔVsigs < (ΔVjdg - ΔVoffset), as in the case of the dark time, since Vinp < Vinn, the output comp_o from the comparator circuit 304 is set to the high level and input to the selector 303. When ΔVsigs > (ΔVjdg - ΔVoffset), since Vinp > Vinn, the output comp_o from the comparator circuit 304 is set to the low level and input to the selector 303.

[0040] In the period from time t10 to time t11, the control signal 2 for controlling the selector 303 is set to the high level. The selector 303 holds the determination result according to the level of the output comp_o from the comparator circuit 304 input to the selector 303 during the period when the control signal 2 is at the high level. The following is the determination result. If the output comp_o from the comparator circuit 304 is at the high level (the pixel signal is less than the determination signal), the selector 303 outputs the low level. If the output comp_o from the comparator circuit 304 is at the low level (the pixel signal is greater than the determination signal), the selector 303 outputs the high level.

[0041] At time t12, the potential of the reference signal line 321 returns to the potential Vrampres. This also sets the output comp_o from the comparator circuit 304 to the low level.

[0042] At time t13, the control signal 3 for controlling the selector 303 is set to a high level so that the selector 303 can output the held determination result. As described above, when ΔVsigs < (ΔVjdg - ΔVoffset), the selector 303 outputs a low level. With this operation, the switches 312 and 314 are set to the ON state, and the switches 311 and 313 are set to the OFF state to connect the output node of the buffer 301 connected to the reference signal line 321 to the node C. In addition, the output node of the buffer 302 connected to the reference signal line 322 is connected to the load capacitance element 310. In contrast, when ΔVsigs > (ΔVjdg - ΔVoffset), the selector 303 outputs a high level. With this operation, the switches 312 and 314 are set to the OFF state, and the switches 311 and 313 are set to the ON state to connect the output node of the buffer 302 connected to the reference signal line 322 to the node C. In addition, the output node of the buffer 301 connected to the reference signal line 321 is connected to the load capacitance element 310. The period from time t9 to time t13 is sometimes referred to as the signal level determination period.

[0043] At time t14, the reference signal 1 is supplied to the reference signal line 321, and the potential of the reference signal line 321 decreases from the potential Vrampres at a gradient A. In addition, the reference signal 2 is supplied to the reference signal line 322, and the potential of the reference signal line 322 decreases from the potential Vrampres at a gradient B. In this case, since gradient A < gradient B, the reference signal 1 has a higher gain than the reference signal 2. If it is determined that the signal level of the potential PIXSIG is less than (ΔVjdg - ΔVoffset), then A / D conversion is performed by using the reference signal 1 with a high gain and gradient A. If it is determined that the signal level of the potential PIXSIG is greater than (ΔVjdg - ΔVoffset), then A / D conversion is performed by using the reference signal 2 with a low gain and gradient B.

[0044] Since A / D conversion is performed by using the reference signal 1 during the dark time, the potential of the node C changes at a gradient A as indicated by the solid line. At time ts1, the potential Vinp of the positive input terminal and the potential Vinn of the negative input terminal of the comparison circuit 304 have the relationship Vinp < Vinn, and the output comp_o from the comparison circuit 304 changes to a high level. This completes the A / D conversion of the pixel signal output from the photodiode 201 during the dark time.

[0045] In contrast, if the potential PIXSIG changes by ΔVsigs during photoelectric conversion such that ΔVsigs > (ΔVjdg - ΔVoffset), then A / D conversion is performed using the reference signal 2. Accordingly, the potential of node C changes with a gradient B as indicated by the broken line. At time ts2, the potential of node C is set to (Vrampres - ΔVoffset - ΔVsigs). As a result, the potential Vinp of the positive input terminal and the potential Vinn of the negative input terminal of the comparison circuit 304 have a relationship of Vinp < Vinn. Therefore, the output comp_o from the comparison circuit 304 changes to a high level, and the A / D conversion of ΔVsigs is completed.

[0046] At time t15, both the reference signal 1 and the reference signal 2 are set to be at the potential Vrampres. Accordingly, the output comp_o from the comparison circuit 304 changes to a low level. The period from time t14 to time t15 is sometimes referred to as the S conversion period.

[0047] In the present embodiment, the reference signal used during the S conversion period is switched depending on the result obtained during the signal level determination period. This means that the usage ratio between the reference signal 1 and the reference signal 2 during the S conversion period changes depending on the luminance of the light incident on the photodiode. For example, if the buffers 301 and 302 are circuits including source follower circuits (such as source follower amplifiers), the load connected to the output sides of the buffers 301 and 302 may affect the input sides. For this reason, if the loads connected to the output nodes of the buffers 301 and 302 do not match between the buffers 301 and 302, the load connected to the reference signal lines 321 and 322 changes every time the usage ratio between the reference signal 1 and the reference signal 2 changes. Therefore, during the S conversion period, the gradients A and B of the reference voltages 1 and 2 may change depending on the luminance. As a result, the degradation of the linearity of the A / D conversion and the occurrence of smear may degrade the image quality of the obtained image.

[0048] In contrast, in the A / D conversion circuit 104 according to the present embodiment, the output node of the buffer 301 or 302 connected to the reference signal line 321 or 322 that is not used for A / D conversion is connected to the load capacitance element 310. For example, if the reference signal 1 flowing through the reference signal line 321 is used for A / D conversion, the buffer 302 connected to the reference signal line 322 different from the buffer 301 connected to the reference signal line 321 is connected to the load capacitance element 310. This suppresses the change in the load connected to each of the reference signal lines 321 and 322 regardless of the change in the ratio between the reference signals 1 and 2 used for A / D conversion.

[0049] The capacitance value of the load capacitor element 310 is set taking into account parasitic capacitances in the layout of the photoelectric conversion device 100, input capacitance of the positive input terminal of the comparator circuit 304, etc. The capacitance value of the load capacitor element 310 is, for example, on the order of several hundred fF, but it depends on circuit constants and layout. The load capacitor element 310 can be formed using a metal-insulator-metal (MIM) structure or can be formed as a MOS capacitor. Alternatively, the load capacitor element 310 can be a capacitor having a PIP structure in which an insulating layer is sandwiched between multiple polysilicon layers. In this case, similarly, all other capacitor elements described in this specification and figures can be implemented by capacitors with MIM structures, MOS capacitors, or capacitors with PIP structures. It is assumed that in this specification, capacitors provided as structures are written as capacitor elements. In contrast, parasitic capacitances accompanying wiring, transistors, etc., are written as parasitic capacitances, without the term "element".

[0050] The A / D conversion circuit 104 with the above structure can minimize load changes at the output nodes connected to buffers 301 and 302. This enables accurate A / D conversion, such as suppressing linear degradation and ghosting. This results in suppressing image quality degradation of the image obtained using the photoelectric conversion device 100.

[0051] Figure 5 This is a circuit diagram showing a modification of the aforementioned A / D conversion circuit 104. Figure 3 In the A / D conversion circuit 104 shown, the connection between reference signal lines 321 and 322 and buffers 301 and 302 is fixed. Furthermore, switches 311 to 314, acting as connectors, are configured to switch the connection between the output nodes of buffers 301 and 302 and the input nodes of comparator circuit 304 and load capacitor element 310. In contrast, in Figure 5 In the arrangement shown, the output node of buffer 301 is connected to the input node of comparator circuit 304 via clamping capacitor element 307, and the output node of buffer 302 is connected to the output node of load capacitor element 310. That is, the connection relationship between the output nodes of buffers 301 and 302 and the input nodes of comparator circuit 304 and load capacitor element 310 is fixed. In contrast, switches 511 to 514, which serve as connectors, are configured to switch the connection between multiple reference signal lines 321 and 322 and the input nodes of buffers 301 and 302.

[0052] Switch 511 is positioned between reference signal line 322 and buffer 301. Switch 512 is positioned between reference signal line 321 and buffer 301. The output node of buffer 301 is connected to the positive input terminal of the comparator circuit 304 via clamping capacitor element 307. Switch 513 is positioned between reference signal line 322 and buffer 302. Switch 514 is positioned between reference signal line 321 and buffer 302. The output node of buffer 302 is connected to load capacitor element 310. Similar to switches 311 to 314, switches 511 to 514 are configured to the following connection states based on the determination result obtained by selector 303.

[0053] During the signal level determination period, if the output comp_o from comparator circuit 304 is high (pixel signal is less than the determination level), then selector 303 outputs a low level from time t13. Using this operation, switches 512 and 513 are set to the ON state, and switches 511 and 514 are set to the OFF state. As a result, reference signal line 321 is connected to buffer 301, and the potential of reference signal line 321 is supplied to node C via buffer 301. Reference signal line 322 is connected to load capacitor element 310 via buffer 302.

[0054] In contrast, during the signal level determination period, if the output comp_o from comparator circuit 304 is low (pixel signal greater than the determination level), then selector 303 outputs a high level from time t13. Using this operation, switches 511 and 514 are set to the ON state, and switches 512 and 513 are set to the OFF state. As a result, reference signal line 322 is connected to buffer 301, and the potential of reference signal line 322 is supplied to node C via buffer 301. Furthermore, reference signal line 321 is connected to load capacitor element 310 via buffer 302.

[0055] Using this operation, in Figure 5 In the A / D conversion circuit 104 shown, as in the embodiments above, during the S-conversion period, the reference signal lines 321 or 322 not used for A / D conversion are connected to the load capacitor element 310 via the buffer 302. This suppresses changes in the load connected to each of the reference signal lines 321 and 322 regardless of changes in the ratio between the reference signals 1 and 2 used for A / D conversion. That is, Figure 5 The arrangement shown can accurately perform A / D conversion, such as suppressing linear degradation and the occurrence of ghosting. This results in suppressing the degradation of image quality in images obtained using the photoelectric conversion device 100.

[0056] exist Figure 5In the arrangement shown, both reference signal 1 and reference signal 2, regardless of which signal is used, are supplied to the comparator circuit 304 via the same buffer. For example, considering the case of performing A / D conversion with high gain, it can be assumed that... Figure 5 The arrangement shown Figure 3 The arrangement shown is more suitable.

[0057] During the interval from time t4 to time t5, (Vrampres - ΔVoffset) is clamped in clamping capacitor element 307. Consider the case where the reference signal to be used is changed based on the result obtained during the signal level determination period, and the reference signal is supplied from different buffers. In this case, the A / D conversion may start from the potential of node C, which is shifted from the potential of Vrampres to the potential of Vbofst due to the influence of the buffer's offset potential Vbofst (Vrampres + Vbofst). In this case, the timing of the inversion of the comparator circuit 304 during the A / D conversion in the S-conversion period is slower when the potential Vbofst is added, and faster when the potential Vbofst is subtracted. As a result, the value obtained by the A / D conversion includes an error. The effect of the potential Vbofst increases when a high gain is applied with a reference signal having a small gradient. Accordingly, the buffer connected to the comparator circuit 304 is fixed to the buffer 301. Figure 5 The arrangement shown can be compared to Figure 3 The arrangement shown performs A / D conversion with high accuracy.

[0058] Figure 6 It is shown Figure 5 The circuit diagram of the modified A / D conversion circuit 104 shown is shown. Figure 6 The arrangement shown is similar to Figure 5 The difference in the arrangement shown lies in the arrangement of the clamping capacitor between buffer 301 and the positive input terminal, which serves as the input node of comparator circuit 304, and the arrangement of the load capacitor connected to buffer 302. Other arrangements may be the same as... Figure 5 The arrangements shown are similar, so each arrangement will be described by focusing on the different parts.

[0059] exist Figure 6 In the arrangement shown, the load capacitor element 610 connected to the output node of buffer 302 varies in capacitance. Load capacitor element 610 can also be referred to as a variable capacitor element. In addition to clamping capacitor element 307, this arrangement also provides clamping capacitor element 607. One of the two terminals of clamping capacitor element 607 is connected to the positive input terminal of comparator circuit 304. The other terminal of clamping capacitor element 607 is connected to buffer 301 via switch 611 and also connected to ground level via switch 612. Ground level can be equal to... Figure 2 The potential level of the power line GND connected to the power supply of the vertical readout circuit 102 is shown.

[0060] Switches 611 and 612 are controlled exclusively such that if switch 611 is set to the ON state, then switch 612 is set to the OFF state, and if switch 611 is set to the OFF state, then switch 612 is set to the ON state. That is, if switch 611 is set to the ON state and switch 612 is set to the OFF state, then clamping capacitor element 307 and clamping capacitor element 607 are connected in parallel between the positive input terminal of comparator circuit 304 and buffer 301. If switch 611 is set to the OFF state and switch 612 is set to the ON state, then clamping capacitor element 607 is connected to ground.

[0061] Consider the case where clamping capacitor element 307 and clamping capacitor element 607 have the same capacitance value. Compared to the case where switch 611 is set to the ON state and switch 612 is set to the OFF state, when switch 611 is set to the OFF state and switch 612 is set to the ON state, the gradient of the reference signal input to the positive input terminal of comparator circuit 304 can be reduced to approximately 1 / 2 for the same input reference signal. That is, the gain can be increased. In this case, the case where switch 611 is set to the ON state and switch 612 is set to the OFF state will be referred to as gain 1X mode, and the case where switch 611 is set to the OFF state and switch 612 is set to the ON state will be referred to as gain 2X mode.

[0062] Let Cp be the value of the parasitic capacitance to the output node of buffer 301, C1 be the value of the capacitance of each of clamping capacitor elements 307 and 607, and Cin be the value of the input capacitance of comparator circuit 304, then the capacitance value connected to the output node of buffer 301 in gain 1X mode is expressed as follows:

[0063] (2Cl x Cin) / (2Cl+Cin)+Cp...(1) In contrast, in gain 2X mode, the capacitance value of the output node connected to buffer 301 is expressed as follows:

[0064] (Cl 2 +ClxCin) / (2Cl+Cin)+Cp...(2)

[0065] Accordingly, the load to be connected to the output node of buffer 301 varies depending on the gain mode. For this reason, in Figure 6In the arrangement shown, the capacitance value of the load capacitor element 610 is variable, and the capacitance value of the load capacitor element 610 is changed according to the gain mode, taking into account changes in the gain mode of the load connected to the buffer 301. This allows for reduction of linear degradation and ghosting even when the gain is changed by using clamping capacitor elements 307 and 607.

[0066] The capacitance value of the load capacitor element 610 can be set to correct for load variations caused by manufacturing changes in the photoelectric conversion device 100. Figure 3 and Figure 5 The arrangement shown can use a load capacitor element 610 with a variable capacitance value instead of a load capacitor element 310.

[0067] Figure 6 The arrangement shown can also accurately perform A / D conversion and suppress image quality degradation of images obtained using the photoelectric conversion device 100. Furthermore, Figure 6 The arrangement shown provides clamping capacitor elements 307 and 607 as clamping capacitor elements to be used and is configured to be able to set two capacitance values ​​as clamping capacitor elements to be connected to the input node (positive input terminal) of the comparator circuit 304. This enables the comparator to... Figure 3 or Figure 5 The arrangement shown further modifies the gain used for A / D conversion. As described above, the capacitance value of clamping capacitor element 307 is set to be equal to the capacitance value of clamping capacitor element 607. However, this is not a limitation. Clamping capacitor elements 307 and 607 can have different capacitance values ​​depending on the specifications required by the photoelectric conversion device 100 (A / D conversion circuit 104). Furthermore, this arrangement can be provided with another clamping capacitor element and configured to allow selection of one of three or more capacitance values ​​for the clamping capacitor elements.

[0068] The following will refer to Figure 7 An application example of the photoelectric conversion device 100 according to this embodiment is described. Figure 7 This is a schematic diagram of equipment 9191 including photoelectric conversion device 100. (See diagram below.) Figure 7 As shown, the photoelectric conversion device 100 is housed in a package 920. The package 920 may include a substrate to which the photoelectric conversion device 100 is fixed and a cover member made of glass or the like facing the photoelectric conversion device 100. Furthermore, the package 920 may include bonding members such as solder wires and bumps that connect terminals provided on the substrate to pads provided on the photoelectric conversion device 100.

[0069] Equipment 9191 may include at least one of optical device 940, control device 950, processing device 960, display device 970, storage device 980, and mechanical device 990. Optical device 940 is implemented using, for example, lenses, shutters, and mirrors. Control device 950 controls photoelectric conversion device 100. Control device 950 is, for example, a semiconductor device such as an ASIC.

[0070] Processing device 960 processes signals output from photoelectric conversion device 100. Processing device 960 is a semiconductor device such as a CPU or ASIC used to form an analog front-end (AFE) or digital front-end (DFE). Display device 970 is an EL display device or liquid crystal display device that displays information (images) obtained by photoelectric conversion device 100. Storage device 980 is a magnetic or semiconductor device that stores information (images) obtained by photoelectric conversion device 100. Storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or hard disk drive.

[0071] Mechanical device 990 includes a moving or propulsive unit such as a motor or engine. In equipment 9191, signals output from photoelectric conversion device 100 are displayed on display device 970 or transmitted to external devices via communication devices (not shown) included in equipment 9191. Therefore, in addition to the memory circuitry and arithmetic circuitry included in photoelectric conversion device 100, equipment 9191 may also include storage device 980 and processing device 960. Mechanical device 990 can be controlled based on signals output from photoelectric conversion device 100.

[0072] Furthermore, the device 9191 is suitable for electronic equipment such as information terminals with shooting capabilities (e.g., smartphones or wearable devices) or cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, or surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 to perform zoom, focus, and shutter operations. Alternatively, the mechanical device 990 in the camera can move the photoelectric conversion device 100 to perform vibration-damping operation.

[0073] Furthermore, the equipment 9191 can also be applied to onboard cameras installed in transport equipment such as vehicles, ships, aircraft, or industrial robots. The mechanical device 990 in the transport equipment can be used as a mobile device. The equipment 9191 as transport equipment is suitable for transporting devices of the photoelectric conversion device 100 or devices using image capture functions to assist and / or automate driving (manipulation). The processing device 960 for assisting and / or automate driving (manipulation) can perform processing for operating the mechanical device 990 as a mobile device based on information obtained from the photoelectric conversion device 100. Besides transport equipment, the equipment 9191 incorporated into the photoelectric conversion device 100 can also be widely applied to equipment using object recognition, such as intelligent transportation systems (ITS). Alternatively, the equipment 9191 can be medical equipment such as endoscopes, measuring equipment such as distance measurement sensors, analytical equipment such as electron microscopes, or office equipment such as photocopiers.

[0074] Although the invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims is to be given the broadest interpretation in order to cover all such modifications and equivalent structures and functions.

Claims

1. A photoelectric conversion device, the photoelectric conversion device comprising a pixel array, a plurality of A / D conversion circuits, and a plurality of reference signal lines, the pixel array being provided with a plurality of pixels, the plurality of A / D conversion circuits being configured to convert pixel signals output from the pixel array into digital signals, and reference signals with different gradients being supplied to the plurality of reference signal lines. Each of the plurality of A / D conversion circuits includes a comparator circuit, a selector, and a connector. The comparator circuit is configured to compare the pixel signal with the reference signal. The selector is configured to select a reference signal line from the plurality of reference signal lines to which the reference signal for A / D conversion is supplied. The connector is configured to connect the reference signal line selected by the selector from the plurality of reference signal lines to the comparator circuit via a buffer and to connect the reference signal line not selected by the selector from the plurality of reference signal lines to a load capacitor element via a buffer different from the buffer.

2. The apparatus of claim 1, wherein the buffer and the other buffer comprise a source follower circuit.

3. The apparatus according to claim 1, wherein the capacitance value of the load capacitor element is variable.

4. The apparatus of claim 3 further includes a clamping capacitor element connected to the input node to which the reference signal of the comparator circuit is supplied. The clamping capacitor element is configured to have at least two capacitance values.

5. The apparatus of claim 1, wherein the selector determines the signal level of the pixel signal and selects the reference signal line to which the reference signal for A / D conversion is supplied from the plurality of reference signal lines.

6. The apparatus of claim 1, wherein a plurality of buffers, including the buffer and the other buffer, are provided. Each of the plurality of reference signal lines is connected to the input node of a corresponding one of the plurality of buffers so that one reference signal line corresponds to one buffer, and The connector is configured to switch the connection between the output node of each of the plurality of buffers and the input node of each of the comparator circuit and the load capacitor element.

7. The apparatus of claim 1, wherein the output node of the buffer is connected to the input node of the comparator circuit. The output node of the other buffer is connected to the output node of the load capacitor element, and The connector is configured to switch the connection between each of the plurality of reference signal lines and the input node of the corresponding one of the buffers and the other buffer.

8. The apparatus according to claim 1, wherein the load capacitor element is a grounded capacitor element.

9. An apparatus comprising: The photoelectric conversion device according to any one of claims 1 to 8; as well as A processor configured to process signals output from the photoelectric conversion device.

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