Semiconductor device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof and a memory system, the semiconductor device comprises a first semiconductor structure, the first semiconductor structure comprises a memory cell array, the memory cell array comprises a plurality of memory cells arranged in an array along a first transverse direction and a second transverse direction, each memory cell comprises a vertical transistor and a memory element coupled to one end of the vertical transistor; a plurality of contact structures located between the vertical transistor and the memory element; and in two contact structures adjacent to a first contact structure in the plurality of contact structures along the first transverse direction, the distance between any one of the two contact structures and the first contact structure is equal.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing the same, and a memory system. Background Technology

[0002] Semiconductor devices, such as Dynamic Random Access Memory (DRAM), are among the most important storage components in electronic systems. They typically employ a 1T1C structure, consisting of a transistor and a capacitor, as a single storage cell. This 1T1C structure allows DRAM to achieve high integration density and low cost, giving it an irreplaceable position in computer storage devices. With the rapid development of semiconductor technology, DRAM is rapidly evolving towards higher density and higher quality. Summary of the Invention

[0003] This disclosure presents a semiconductor device, a method for fabricating the same, and a memory system.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device including a first semiconductor structure, the first semiconductor structure including: a memory cell array including a plurality of memory cells arranged in an array along a first lateral direction and a second lateral direction, each memory cell including a vertical transistor and a memory element coupled to one end of the vertical transistor; a plurality of contact structures located between the vertical transistor and the memory element; and in two contact structures adjacent to the first contact structure in the plurality of contact structures along the first lateral direction, the distance between either of the two contact structures and the first contact structure is equal.

[0005] In one alternative embodiment, the vertical transistor includes: a semiconductor body extending in a vertical direction and a gate structure in contact with at least a portion of the side surface of the semiconductor body, the gate structure extending in a second lateral direction; the distance between adjacent semiconductor bodies is greater than or equal to the distance between adjacent contact structures.

[0006] In one alternative embodiment, the contact structure and the semiconductor body are aligned vertically along one sidewall of the first lateral direction, and the distance between adjacent semiconductor bodies along the other sidewall of the first lateral direction is greater than the distance between adjacent contact structures along the other sidewall of the first lateral direction.

[0007] In one alternative embodiment, the dimension of the contact structure along the first lateral direction is larger than the dimension of the semiconductor body along the first lateral direction.

[0008] In one alternative embodiment, the first semiconductor structure further includes: a plurality of bit lines extending along the first lateral direction and coupled to the other end of the vertical transistor; and a plurality of isolation structures located between adjacent groups of vertical transistors along the second lateral direction and extending along the second lateral direction.

[0009] In one optional embodiment, the plurality of isolation structures include: a first isolation structure and a second isolation structure alternately arranged along the first transverse direction; wherein the first isolation structure includes a first dielectric layer and / or a first air gap; and the second isolation structure includes a second air gap.

[0010] In one alternative implementation, a plurality of third air gaps are located between adjacent position lines and extend along a first lateral direction.

[0011] In one alternative implementation, the first air gap, the second air gap, and the third air gap are connected.

[0012] In one alternative embodiment, the gate structure includes a gate electrode and a gate dielectric between the gate electrode and the semiconductor body in the first lateral direction and the second lateral direction.

[0013] In one alternative embodiment, the vertical transistor further includes a source and a drain respectively disposed at two ends of the semiconductor body in the vertical direction; one of the source and the drain of the vertical transistor is coupled to the memory element in the corresponding memory cell; and the other of the source and the drain of the vertical transistor is coupled to a corresponding bit line.

[0014] In one alternative embodiment, the contact structure includes a first conductive layer and a second conductive layer; the first conductive layer includes a metal silicide, and the second conductive layer includes tungsten.

[0015] In one alternative implementation, the vertical transistor includes at least one of a gate-all-around (GAA) transistor, a tri-gate transistor, a dual-gate transistor, or a single-gate transistor.

[0016] In one alternative implementation, the storage element includes at least one of a capacitor, a ferroelectric capacitor, or a phase-change memory (PCM) element.

[0017] In one alternative embodiment, the storage element is a capacitor comprising a first electrode, a second electrode, and a capacitor dielectric.

[0018] In one alternative embodiment, the semiconductor device further includes a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked vertically, and the second semiconductor structure includes peripheral circuitry.

[0019] In one alternative implementation, the first semiconductor structure and the second semiconductor structure are formed on the same wafer; or, the first semiconductor structure and the second semiconductor structure are formed on different wafers.

[0020] Secondly, embodiments of this disclosure provide a method for fabricating a semiconductor device, the method comprising: forming a first semiconductor structure; forming the first semiconductor structure comprising: forming a memory cell array, the memory cell array comprising a plurality of memory cells arranged in an array along a first lateral direction and a second lateral direction, each memory cell comprising a vertical transistor and a memory element coupled to one end of the vertical transistor; forming the first semiconductor structure further comprising: forming a plurality of contact structures, the contact structures being located between the vertical transistor and the memory element; in two contact structures adjacent to the first contact structure in the plurality of contact structures along the first lateral direction, the distance between any one of the two contact structures and the first contact structure is equal.

[0021] In one alternative embodiment, forming the first semiconductor structure includes: etching a semiconductor substrate through a mask stack to form a semiconductor pillar array; the semiconductor pillar array includes rows of semiconductor pillars arranged along a second lateral direction, the rows of semiconductor pillars being separated by first spacer trenches; the mask stack includes a first mask layer and a second mask layer; etching the semiconductor pillars by removing an opening formed after removing the first mask layer to form a plurality of second spacer trenches extending along the second lateral direction, the plurality of second spacer trenches separating each semiconductor pillar in a corresponding row of semiconductor pillars into two semiconductor bodies.

[0022] In one alternative embodiment, forming a plurality of contact structures includes: etching back the second mask layer to make the etched second mask layer equally spaced along a first lateral direction; removing the etched second mask layer to form a first contact hole; enlarging the first contact hole to form a second contact hole, the second contact hole exposing at least the entire upper surface of the semiconductor body; and forming a contact structure in the second contact hole.

[0023] In one optional embodiment, etching the semiconductor pillar by removing the opening formed after removing the first mask layer includes: pushing the first mask layer back along the first spacer trench to increase the opening of the first spacer trench in the first mask layer; depositing a first sacrificial layer to fill the first spacer trench; removing the first mask layer to form an opening in the first sacrificial layer, and etching the semiconductor pillar through the opening.

[0024] In one alternative implementation, the first semiconductor structure is formed before removing the second mask layer after back etching to form the first contact hole, and further includes forming a second sacrificial layer and a second dielectric layer in the second spacer trench.

[0025] In one alternative embodiment, forming the first semiconductor structure further includes: removing the first sacrificial layer to form a third spacer trench; forming a word line structure in the third spacer trench; forming a second trench in the conductive structure; and forming the first isolation structure in the second trench, wherein the conductive structure is divided into two word lines by the first isolation structure.

[0026] In one alternative embodiment, forming a contact structure in the second contact hole includes: forming a first doped layer at the bottom of the second contact hole, the first doped layer being in contact with the upper surface of the semiconductor body.

[0027] In one alternative embodiment, forming a contact structure in the second contact hole further includes: forming a first conductive layer on the first doped layer; forming a second conductive layer on the first conductive layer; wherein the first conductive layer comprises a metal semiconductor compound, and the second conductive layer comprises a metal.

[0028] In one alternative implementation, forming a memory cell array includes forming a capacitor coupled to the contact structure, the capacitor being coupled to the semiconductor body through the contact structure.

[0029] In one alternative embodiment, forming the first semiconductor structure further includes: forming a second doped layer at the opposite end of the upper surface of the semiconductor body; and forming a bit line coupled to the second doped layer, the bit line extending along a first lateral direction.

[0030] In one alternative embodiment, forming the first semiconductor structure before forming a second doped layer at the opposite end of the upper surface of the semiconductor body further includes: removing the second sacrificial layer in the second spacer trench to form a second air gap.

[0031] In one alternative embodiment, forming the first semiconductor structure further includes forming a plurality of third air gaps between adjacent bit lines, the third air gaps extending along a first lateral direction.

[0032] Thirdly, embodiments of this disclosure provide a memory system, comprising: a semiconductor device, the semiconductor device including a first semiconductor structure, the first semiconductor structure including: a memory cell array including a plurality of memory cells arranged in an array along a first lateral direction and a second lateral direction, the memory cells including a vertical transistor and a memory element coupled to one end of the vertical transistor; a plurality of contact structures located between the vertical transistor and the memory element; in two contact structures adjacent to the first contact structure in the plurality of contact structures along the first lateral direction, the distance between either of the two contact structures and the first contact structure is equal; and a memory controller configured to control the semiconductor device.

[0033] In one alternative embodiment, the vertical transistor includes: a semiconductor body extending in a vertical direction and a gate structure in contact with at least a portion of the side surface of the semiconductor body, the gate structure extending in a second lateral direction; the distance between adjacent semiconductor bodies is greater than or equal to the distance between adjacent contact structures.

[0034] In one alternative embodiment, the contact structure and the semiconductor body are aligned vertically along one sidewall of the first lateral direction, and the distance between adjacent semiconductor bodies along the other sidewall of the first lateral direction is greater than the distance between adjacent contact structures along the other sidewall of the first lateral direction.

[0035] In one alternative embodiment, the dimension of the contact structure along the first lateral direction is larger than the dimension of the semiconductor body along the first lateral direction.

[0036] This disclosure provides a semiconductor device comprising a first semiconductor structure, the first semiconductor structure including: a memory cell array including a plurality of memory cells arranged in an array along a first lateral direction and a second lateral direction, each memory cell including a vertical transistor and a memory element coupled to one end of the vertical transistor; a plurality of contact structures located between the vertical transistor and the memory element; and in two contact structures adjacent to the first contact structure along the first lateral direction, the distance between either contact structure and the first contact structure is equal. In this disclosure, since the spacing between adjacent contact structures along the first lateral direction is equal, that is, the plurality of contact structures arranged along the first lateral direction are uniformly spaced, the subsequent uniformly arranged memory elements can be positively aligned with the contact structures in the vertical direction without offset alignment, thereby improving the connection window between the contact structures and the memory elements. Attached Figure Description

[0037] Figure 1 A schematic diagram of the structure of a semiconductor device provided in this disclosure embodiment. Figure 1 ;

[0038] Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0039] Figures 3a to 3s A cross-sectional schematic diagram of a process for forming a semiconductor body provided in an embodiment of this disclosure;

[0040] Figures 4a to 4k A cross-sectional schematic diagram of the process of forming a first isolation structure and a contact structure provided in an embodiment of this disclosure;

[0041] Figure 5 A schematic diagram of the structure of a semiconductor device provided in this disclosure embodiment. Figure 2 . Detailed Implementation

[0042] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0044] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0045] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0046] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0048] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0049] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements of dynamic random access memory for ions and leakage current, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0050] In some embodiments of this disclosure, whether planar transistors or buried transistors, the dynamic random access memory is composed of multiple memory cells. Each memory cell consists of a transistor and a capacitor controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0051] The following combination Figure 1 One architecture of dynamic random access memory is described in detail. In the introduction... Figure 1Before illustrating the semiconductor device, we first define the various directions that may be used in the following description. The extension direction of the semiconductor body is defined as the vertical direction (i.e., the Z-axis direction). In a plane perpendicular to the Z-axis direction, we define the intersecting first lateral direction (i.e., the X-axis direction) and the second lateral direction (i.e., the Y-axis direction). In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction can be mutually perpendicular.

[0052] A cross-sectional view of a semiconductor device 100 including a vertical transistor is provided in this embodiment of the disclosure; as shown... Figure 1 As shown, the semiconductor device 100 includes a second semiconductor structure 102 and a first semiconductor structure 104 stacked on top of the second semiconductor structure 102 along the Z-axis direction. The second semiconductor structure 102 and the first semiconductor structure 104 are connected via a bonding interface 106. The second semiconductor structure 102 and the first semiconductor structure 104 can be connected by methods such as hybrid bonding. In some embodiments, the first semiconductor structure 104 can be bonded to the top of the second semiconductor structure 102 in a face-to-face manner at the bonding interface 106. The second semiconductor structure 102 may include a first substrate 1010, a peripheral circuit 1012 located on one side of the first substrate 1010, and a first interconnect layer 1016 located on the side of the peripheral circuit 1012 away from the first substrate 1010. The first interconnect layer 1016 is used to transmit electrical signals of the peripheral circuit 1012. The peripheral circuit 1012 may include a plurality of transistors 1014. In some embodiments, trench isolation (such as shallow trench isolation (STI)) and doped regions (such as the well, source and drain of transistor 1014) may also be formed on or in the first substrate 1010.

[0053] The second semiconductor structure 102 may further include a first bonding layer 1018 located at the bonding interface 106 and on the side of the first interconnect layer 1016 away from the peripheral circuit 1012. The first bonding layer 1018 may include a plurality of first bonding contacts 1019 and a dielectric material electrically isolating the first bonding contacts 1019. The first bonding contacts 1019 in the first bonding layer 1018 and the surrounding dielectric material can be used for mixed bonding. Conversely, the first semiconductor structure 104 may also include a second bonding layer 1020 located at the bonding interface 106 and on the side of the first bonding layer 1018 away from the first interconnect layer 1016. The second bonding layer 1020 may include a plurality of second bonding contacts 1021 and a dielectric material electrically isolating the second bonding contacts 1021. The second bonding contacts 1021 in the second bonding layer 1020 and the surrounding dielectric material can be used for mixed bonding. Here, the second bonding contact 1021 contacts the first bonding contact 1019 at the bonding interface 106.

[0054] In some embodiments, the peripheral circuitry 1012 may further include word lines (WL) and word line drivers / row decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. In other embodiments, the peripheral circuitry 1012 may further include bit lines 1023 (BL) and bit line drivers / column decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. Here, the second interconnect layer 1022 includes bit lines 1023 above the second bonding layer 1020, and the bit lines 1023 are used to transmit electrical signals. In other embodiments, the stacked second semiconductor structure 102 and the first semiconductor structure 104 may not be connected by bonding, but rather integrated on the same substrate (only the first substrate, no second substrate), and directly connected through one or more interconnect layers between the second semiconductor structure 102 and the first semiconductor structure 104. In this case, the second semiconductor structure 102 does not have the first bonding layer 1018 and the first bonding contact 1019; the first semiconductor structure 104 does not have the second bonding layer 1020 and the second bonding contact 1019; and the bonding interface 106 between the second semiconductor structure 102 and the first semiconductor structure 104 also does not exist.

[0055] refer to Figure 1 The first semiconductor structure 104 further includes a memory cell array located on the second interconnect layer 1022. The memory cell array may include a plurality of memory cells 1024 arranged in an array along the X-axis and Y-axis directions, a second substrate 1048 located on the memory cells 1024, and a third interconnect layer 1050 located on the second substrate 1048. Figure 1 The cross section of the dynamic random access memory 100 can be cut along the bit line direction (X-axis direction), and a bit line 1023 in the second interconnect layer 1022 extending laterally in the X-axis direction can be coupled to a column of memory cells 1024.

[0056] Here, each memory cell 1024 may include a vertical transistor 1026 and a capacitor structure 1028 coupled to the vertical transistor 1026; the vertical transistor 1026 includes a semiconductor body 1030 extending vertically (in the Z-axis direction) and a gate structure 1036 contacting at least a portion of the side surface of the semiconductor body 1030 in the bit line direction (X-axis direction); in other embodiments, the gate structure may also completely surround the semiconductor body, partially surround the semiconductor body, or be located on two opposite sides of the semiconductor body, etc., which will not be elaborated here. Here, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 located between the gate electrode 1034 and the semiconductor body 1030 in the bit line direction (X-axis direction). In some embodiments, the gate dielectric 1032 is adjacent to one side surface of the semiconductor body 1030, and the gate electrode 1034 is adjacent to the gate dielectric 1032.

[0057] In some embodiments, the semiconductor body 1030 has two ends (upper end and lower end) in the vertical direction (Z-axis direction), and one end (e.g. Figure 1 The lower end of the semiconductor body 1030 extends in the vertical direction (Z-axis direction) beyond the gate dielectric 1032 into the interlayer dielectric (ILD) layer, while the other end of the semiconductor body 1030 (such as...) Figure 1 The upper end of the semiconductor body 1030 is flush with the corresponding end of the gate dielectric 1032. In other embodiments, both ends (upper and lower) of the semiconductor body 1030 extend in the vertical direction (Z-axis direction) beyond the gate electrode 1034 into the ILD layer. In other words, the semiconductor body 1030 may have a larger vertical dimension than the vertical dimension (e.g., depth in the Z-axis direction) of the gate electrode 1034, and neither the upper nor lower end of the semiconductor body 1030 is flush with the corresponding end of the gate electrode 1034. This avoids short circuits between the bit line 1023 and the word line / gate electrode 1034 or between the word line / gate electrode 1034 and the capacitor structure 1028.

[0058] The vertical transistor 1026 may further include a source 1038 and a drain 1040 respectively disposed at both ends (upper and lower ends) of the semiconductor body 1030 in the vertical direction (Z-axis direction). (The positions of the source and drain can be interchanged; here and below, the upper end is the source 1038 and the lower end is the drain 1040 as an example.) In some embodiments, the source 1038 is coupled to the capacitor 1028, and the drain 1040 is coupled to the bit line 1023.

[0059] Since the gate electrode can be part of a word line or extend as a word line in the word line direction, the first semiconductor structure 104 of the dynamic random access memory 100 can also include multiple word lines, each extending in the word line direction (Y-axis direction). Here, each word line 1034 can be coupled to a row of memory cells 1024.

[0060] Vertical transistor 1026 extends vertically through and contacts word line 1034, and its drain 1040 at its lower end contacts bit line 1023. Therefore, due to the vertical arrangement of vertical transistor 1026, word line 1034 and bit line 1023 can be arranged in different planes in the vertical direction, simplifying the wiring of word line 1034 and bit line 1023. Here, vertical transistor 1026 can be arranged in a mirror-symmetric manner to increase the density of memory cells 1024 in the bit line direction (X-axis direction). Two adjacent vertical transistors 1026 in the bit line direction are mirror-symmetric with respect to the second isolation structure 1060; that is, the first semiconductor structure 104 may include a plurality of second isolation structures 1060, each second isolation structure 1060 extending parallel to word line 1034 in the word line direction (Y-axis direction) and disposed between semiconductor bodies 1030 of two adjacent rows of vertical transistor 1026. In some embodiments, the rows of vertical transistors 1026 separated by the second isolation structure 1060 are mirror-symmetrical to each other with respect to the second isolation structure 1060. It should be understood that the second isolation structure 1060 may include air gaps, each air gap being laterally disposed between adjacent semiconductor bodies 1030. The first semiconductor structure 104 also includes a plurality of first isolation structures 1062, each first isolation structure 1062 extending parallel to the word line 1034 in the word line direction (Y-axis direction) and disposed between the word lines 1034 of two adjacent rows of vertical transistors 1026. It should be understood that the dimensions of the first isolation structure 1062 and word line 1034 in the bit line direction (X-axis direction) may be the same as or different from the dimensions of the second isolation structure 1060 in the bit line direction (X-axis direction). When the dimensions of the two in the bit line direction (X-axis direction) are different, the spacing between the multiple semiconductor bodies 1030 arranged along the bit line direction (X-axis direction) is different, that is, the multiple semiconductor bodies 1030 arranged along the bit line direction (X-axis direction) are not uniformly arranged.

[0061] like Figure 1 As shown, the capacitor structure 1028 is located above and in contact with the source 1038 (i.e., the upper end of the semiconductor body 1030) of the vertical transistor 1026. The capacitor structure 1028 can be a vertical capacitor.

[0062] In some embodiments, a contact structure 1064 is formed between the capacitor structure 1028 and the vertical transistor 1026 to reduce contact resistance. For example... Figure 1 As shown, the contact structure 1064 may include a first conductive layer and a second conductive layer stacked sequentially from bottom to top. The first conductive layer includes a metal semiconductor compound, and the second conductive layer includes a metal. Figure 1 As shown, the first semiconductor structure 104 may further include a capacitor contact 1047 that contacts a common plate of the second electrode for coupling the second electrode of the capacitor structure 1028 to the peripheral circuit 1012 or directly to ground. In some embodiments, the ILD layer forming the capacitor structure 1028 has the same dielectric material, such as silicon oxide, as the two ILD layers into which the semiconductor body 1030 extends. The construction of the capacitor structure 1028 may include any suitable structure and construction, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-planar capacitor.

[0063] like Figure 1 As shown, the vertical transistor 1026 extends vertically through and contacts the word line 1034. The drain 1040 at its lower end contacts the bit line 1023, and the source 1038 at its upper end contacts the capacitor structure 1028. That is, due to the vertical arrangement of the vertical transistor 1026, the bit line 1023 and the capacitor structure 1028 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 1026 of the memory cell 1024. In some embodiments, the bit line 1023 and the capacitor structure 1028 are arranged on opposite sides of the vertical transistor 1026 in the vertical direction. Compared to conventional memory cells where the bit line and capacitor structure are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 1023 and reduces the coupling capacitance between the bit line 1023 and the capacitor structure 1028.

[0064] In some embodiments, the vertical transistor 1026 is vertically disposed between the capacitor structure 1028 and the bonding interface 106. That is, the vertical transistor 1026 can be arranged closer to the peripheral circuitry 1012 and the bonding interface 106 of the second semiconductor structure 102 than the capacitor structure 1028. Since the bit line 1023 and the capacitor structure 1028 are coupled to opposite ends of the vertical transistor 1026, the bit line 1023 (as part of the second interconnect layer 1022) is vertically disposed between the vertical transistor 1026 and the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0065] In some embodiments, the first semiconductor structure 104 further includes a second substrate 1048 disposed above the memory cell 1024, and a third interconnect layer 1050 with pads leading out above the memory cell 1024. The third interconnect layer 1050 with pads leading out may include interconnects in one or more ILD layers, such as contact pads 1054.

[0066] In some embodiments, the first semiconductor structure 104 further includes one or more contacts 1052 extending through a portion of the third interconnect layer 1050 and a second substrate 1048 to couple the pads out of the third interconnect layer 1050 to the memory cell 1024 and the second interconnect layer 1022. Thus, the peripheral circuitry 1012 can be coupled to the memory cell 1024 via the first interconnect layer 1016 and the second interconnect layer 1022, as well as the second bonding layer 1020 and the first bonding layer 1018, and the peripheral circuitry 1012 and the memory cell 1024 can be coupled to external circuitry via the contacts 1052 and the pads out of the third interconnect layer 1050.

[0067] As mentioned above, in order to reduce the contact resistance between the capacitor structure 1028 and the vertical transistor 1026, a contact structure 1064 is provided between the capacitor structure 1028 and the vertical transistor 1026.

[0068] This disclosure provides a method for fabricating a semiconductor device. (See also...) Figure 2 , Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure; the method includes:

[0069] Step S200: Forming the first semiconductor structure;

[0070] Step S200 includes: Step S201: forming a memory cell array, the memory cell array including a plurality of memory cells arranged in an array along a first lateral direction and a second lateral direction, each memory cell including a vertical transistor and a memory element coupled to one end of the vertical transistor;

[0071] Step S200 further includes: Step S202: forming a plurality of contact structures, the contact structures being located between the vertical transistor and the memory element; in two contact structures adjacent to the first contact structure in the plurality of contact structures along the first lateral direction, the distance between any one of the two contact structures and the first contact structure is equal.

[0072] It should be understood that Figure 2 The steps shown are not exclusive, and other steps may be performed before, after, or between any step in the shown manufacturing method; Figure 2The steps shown can be adjusted in order according to actual needs. It should be noted that a semiconductor device may include a contact structure, a semiconductor body and a memory element, or multiple contact structures, multiple semiconductor bodies and multiple memory elements. Here and below, the example is a semiconductor device including multiple contact structures, multiple semiconductor bodies and multiple memory elements.

[0073] As mentioned earlier, there can be various relative positions between the gate structure and the semiconductor body in a semiconductor device, and different relative positions correspond to different specific fabrication methods. In this embodiment of the present disclosure, two gate structures corresponding to two adjacent semiconductor bodies are respectively arranged back-to-back. Figure 1 The example shown is a back-to-back arrangement. Based on this, a semiconductor device may include multiple contact structures, multiple semiconductor bodies, and multiple memory elements arranged in an array along the X-axis and Y-axis directions. However, it should be understood that the following methods for forming semiconductor structures are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0074] There are various methods for forming contact structures and semiconductor bodies. Several methods are illustrated by way of example in the embodiments of this disclosure. The formation process of multiple contact structures and multiple semiconductor bodies will be described in detail below with reference to the accompanying drawings.

[0075] In some embodiments, forming the first semiconductor structure includes: etching a semiconductor substrate through a mask stack to form a semiconductor pillar array; the semiconductor pillar array includes rows of semiconductor pillars arranged along the second lateral direction;

[0076] The mask stack includes a second mask layer and a second mask layer;

[0077] The semiconductor pillars are etched by removing the openings formed after removing the second mask layer to form a plurality of second spacer trenches extending along the second lateral direction, the plurality of second spacer trenches dividing each semiconductor pillar in the corresponding row of semiconductor pillars into two semiconductor bodies.

[0078] Figures 3a to 3s This is a cross-sectional schematic diagram illustrating the process of forming a semiconductor body according to an embodiment of this disclosure. The formation process of multiple semiconductor bodies will now be described in detail with reference to the accompanying drawings.

[0079] refer to Figure 3aAn initial stack 3010 and a patterned first photoresist layer 3002 are formed on a semiconductor substrate 3001. The initial stack 3010 includes a first oxide layer 3011, a second mask layer 3012, and a third mask layer 3013 stacked sequentially from bottom to top. The first oxide layer 201 can be formed by an oxidation process on the semiconductor substrate 3001. Methods for forming the second mask layer 202 and the third mask layer 203 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0080] In some embodiments, the third mask layer 3013 includes a second oxide layer 3013-1, a hard mask layer 3013-2, a core mold layer 3013-3, and an anti-reflection layer 3013-4; the material of the second oxide layer may be silicon oxide; the material of the hard mask layer may be amorphous silicon (α-Si) or polycrystalline silicon; the material of the core mold layer may be various types of carbon such as amorphous carbon (aC), spin-on carbon (SOC), ashable hard mask (AHM), and transparent carbon (TC); the material of the anti-reflection layer may be titanium nitride (TiN), silicon oxynitride (SiON), silicon carbide (SiC), or aluminum oxide (AlO).

[0081] Figures 3b to 3g This illustrates the process of forming a semiconductor wall using self-aligned quadruple patterning (SAQP); Reference Figure 3b Using the patterned first photoresist layer 3002 as a mask, the antireflective layer 3013-4 and the core mold layer 3013-3 are etched to transfer the pattern to the antireflective layer 3013-4 and the core mold layer 3013-3, forming the antireflective layer 3013-4a and the core mold layer 3013-3a, and then the patterned photoresist layer 3002 is removed; Reference Figure 3c A sidewall material layer 3003 is formed on the antireflective layer 3013-4a and the core mold layer 3013-3a; Reference Figure 3d The sidewall material layer 3003 is selectively etched to remove the sidewall material layer parallel to the semiconductor substrate surface, while retaining the sidewall material layer perpendicular to the semiconductor substrate surface, i.e., retaining sidewall 3003a. In some embodiments, an anisotropic blanket dry etching process can be used to achieve selective etching of the sidewall material layer 3003. (See reference...) Figure 3eUsing sidewall 3003a as a mask, the hard mask layer 3013-2 is etched to transfer the pattern to the hard mask layer 3013-2, forming the hard mask layer 3013-2a, and then the sidewall 3003a is removed; Reference Figure 3f Using hard mask layer 3013-2a as a mask, the first oxide layer 3011, the second mask layer 3012, and the second oxide layer 3013-1 are etched to transfer the pattern to the first oxide layer 3011, the second mask layer 3012, and the second oxide layer 3013-1, forming the first oxide layer 3011a, the second mask layer 3012a, and the second oxide layer 3013-1a; Reference Figure 3g The semiconductor substrate 3001 is etched using a hard mask layer 3013-2a, a first oxide layer 3011a, a second mask layer 3012a, and a second oxide layer 3013-1a to form semiconductor walls 3004, which are spaced apart along the Y-axis. It should be noted that since the hard mask layer is made of silicon, the hard mask layer 3013-2a is also removed during the etching of the semiconductor substrate.

[0082] refer to Figure 3h An insulating material is deposited and filled between the semiconductor walls 3004. Excess insulating material and the first oxide layer 3011a are removed by a chemical mechanical polishing (CMP) process to expose the second mask layer 3012a.

[0083] refer to Figure 3i Semiconductor walls 3004 are arranged at intervals along the X-axis and extend along the Y-axis. An insulating layer 3005 formed of insulating material separates adjacent semiconductor walls 3004. It should be noted that... Figure 3i for Figure 3h A top view, therefore Figure 3i Only the arrangement and extension of the second mask layer 3012a are shown. It can be understood that the arrangement and extension of the semiconductor wall 3004 are the same as those of the second mask layer 3012a.

[0084] refer to Figure 3j ,exist Figure 3h A patterned third oxide layer 3006 and a first mask layer 3007 are formed on the structure shown. The second mask layer 3012a and the semiconductor wall 3004 are etched using the patterned first mask layer 3007 and the third oxide layer 3006 as masks to form a plurality of first spacer trenches 3021 extending along the Y-axis direction. The plurality of first spacer trenches 3021 divide the multiple rows of semiconductor walls 3004 into an array of semiconductor pillars 3030.

[0085] In some embodiments, the second mask layer and the first mask layer constitute a mask stack.

[0086] It should be noted that, Figures 3a to 3i This is a cross-sectional view along the ZOY plane, from... Figure 3j All subsequent cross-sectional views of the manufacturing process are cross-sectional views along the ZOX plane.

[0087] refer to Figure 3k The array of semiconductor pillars 3030 includes rows 3031 of semiconductor pillars arranged along the Y-axis. It should be noted that... Figure 3k for Figure 3j A schematic diagram of the cross-section along the AA' direction, therefore Figure 3k Only the arrangement and extension of the second mask layer 3012a are shown. It can be understood that the arrangement and extension of the semiconductor pillars 3030 are the same as those of the second mask layer 3012a.

[0088] refer to Figure 3l The sidewalls of the semiconductor pillar 3030 exposed by the first spacer trench 3021 are oxidized to form the gate dielectric 3041 by a rapid thermal oxidation (RTO) process.

[0089] In some embodiments, etching the semiconductor pillar by removing the opening formed after removing the first mask layer includes: pushing the first mask layer back along the first spacer trench to increase the opening of the first spacer trench in the first mask layer; depositing a first sacrificial layer to fill the first spacer trench; removing the first mask layer to form an opening in the first sacrificial layer, and etching the semiconductor pillar through the opening.

[0090] refer to Figure 3m The first mask layer 3007 is pulled back along the first spacing trench 3021 to increase the opening of the first spacing trench 3021 in the first mask layer 3007. In other words, the size of the first mask layer 3007 in the X-axis direction is reduced by pulling back the first mask layer 3007. In some specific embodiments, the method of pulling back the first mask layer 3007 may include, but is not limited to, dry etching.

[0091] refer to Figure 3n A first sacrificial layer 3051 is deposited to fill the first spacer trench 3021. The material of the first sacrificial layer may be tungsten metal.

[0092] refer to Figure 3o Remove the first mask layer 3007 to form an opening 3052 in the first sacrificial layer 3051.

[0093] refer to Figure 3pThe semiconductor pillar 3030 is etched through the opening 3052 to form a plurality of second spacer trenches 3022 extending along the Y-axis direction. The plurality of second spacer trenches 3022 divide each semiconductor pillar 3030 in the corresponding semiconductor pillar row into two semiconductor bodies 3032.

[0094] In some embodiments, forming a plurality of contact structures includes: etching back the second mask layer to make the etched second mask layer equally spaced along a first lateral direction; removing the etched second mask layer to form a first contact hole; enlarging the first contact hole to form a second contact hole, the second contact hole exposing at least the entire upper surface of the semiconductor body; and forming a contact structure in the second contact hole.

[0095] refer to Figure 3q The first sacrificial layer 3051 and the second mask layer 3012a are etched back to ensure that the etched second mask layer 3012b is evenly spaced along the X-axis. It should be noted that during the etch-back process of the first sacrificial layer 3051 and the second mask layer 3012a, the third oxide layer 3006 is also etched back. In some specific embodiments, the method for etching back the first sacrificial layer 3051 and the second mask layer 3012a may include, but is not limited to, dry etching.

[0096] refer to Figure 3r and reference Figure 3s ,in, Figure 3r for Figure 3p A schematic diagram of the cross-section along the AA' direction. Figure 3s for Figure 3q A schematic diagram of the cross-section along the AA' direction. (From...) Figure 3r and Figure 3s The comparison shows that after the first sacrificial layer and the second mask layer are etched back, the spacing between adjacent etched second mask layers 3012b along the X-axis is equal. Specifically, refer to... Figure 3r The spacing between adjacent second mask layers 3012a along the X-axis is not equal, i.e., L2 is not equal to L1. (Reference) Figure 3s The spacing between adjacent second mask layers 3012b after etching back along the X-axis is equal, i.e., L3 equals L1. It should be noted that the "equal spacing" described here refers to the ideal state required by the process. It should be understood that there are slight deviations caused by manufacturing errors during the actual manufacturing process.

[0097] Figures 4a to 4e This is a cross-sectional schematic diagram illustrating the process of forming a first isolation structure according to an embodiment of this disclosure. The formation process of the first isolation structure will be described in detail below with reference to the accompanying drawings. It should be noted that... Figures 4a to 4k and Figures 3a to 3s It is a cross-sectional schematic diagram of a continuous manufacturing process.

[0098] In some embodiments, forming the first semiconductor structure before removing the etched second mask layer to form the first contact hole further includes forming a second sacrificial layer and a second dielectric layer in the second spacer trench.

[0099] In some embodiments, forming the first semiconductor structure further includes: removing the first sacrificial layer to form a third spacer trench; forming a word line structure in the third spacer trench; forming a second trench in the word line structure; and forming the first isolation structure in the second trench, wherein the word line structure is divided into two word lines by the first isolation structure.

[0100] refer to Figure 4a A fourth oxide layer 3052 and a second sacrificial layer 3053 are deposited in the second spacer trench 3022. It should be noted that... Figure 4a It is a continuation of Figure 3s The subsequent production process.

[0101] refer to Figure 4b The second sacrificial layer 3053 is etched back to remove a portion of it, forming the groove 3054. In some specific embodiments, the method for etching back the second sacrificial layer 3053 may include, but is not limited to, dry etching.

[0102] refer to Figure 4c A second dielectric layer material is deposited to form a second dielectric layer 3055 in the groove 3054.

[0103] It should be noted that during the actual deposition of the second dielectric layer material, the second dielectric layer material will cover the upper surface of the first sacrificial layer. Usually, after deposition is completed, CMP process is used to remove the excess second dielectric layer material to expose the upper surface of the first sacrificial layer 3051.

[0104] refer to Figure 4d The first sacrificial layer 3051 is removed to form the third spacer trench 3023.

[0105] refer to Figure 4e A word line structure is formed in the third interval groove 3023, and a second groove is formed in the word line structure; a first isolation structure 3061 is formed in the second groove, wherein the word line structure is divided into two word lines 3042 by the first isolation structure 3061. Figure 4e The first isolation structure 3061 shown may include a first isolation structure material between the two word lines 3042 and a first isolation structure material above the two word lines 3042. For example, the first isolation structure material is silicon oxide.

[0106] It should be noted that, from the appendix Figure 3a The subsequent cross-sectional diagrams of the manufacturing process represent intermediate stages. Some structural morphologies shown in these diagrams may not represent the final product form of the semiconductor device. For example, as shown in the diagram, the lower ends of the two word lines (gate electrodes) divided by the first isolation structure are connected. In the final product of the semiconductor device, the lower ends of the word lines (gate electrodes) are disconnected, forming a back-to-back configuration (e.g., ...). Figure 1 (As shown).

[0107] Figures 4f to 4k This is a cross-sectional schematic diagram illustrating the process of forming a contact structure according to an embodiment of this disclosure. The formation process of the first isolation structure will be described in detail below with reference to the accompanying drawings.

[0108] In some embodiments, forming a plurality of contact structures includes: removing the etched second mask layer to form a first contact hole; enlarging the first contact hole to form a second contact hole, the second contact hole exposing at least the entire upper surface of the semiconductor body; and forming a contact structure in the second contact hole.

[0109] In some embodiments, forming a contact structure in the second contact hole includes: forming a first doped layer at the bottom of the second contact hole, the first doped layer being in contact with the upper surface of the semiconductor body.

[0110] In some embodiments, forming a contact structure in the second contact hole further includes: forming a first conductive layer on the first doped layer; forming a second conductive layer on the first conductive layer; wherein the first conductive layer comprises a metal semiconductor compound, and the second conductive layer comprises a metal.

[0111] refer to Figure 4f Excess first isolation structure material is removed by CMP process to expose the etched second mask layer 3012b.

[0112] It should be noted that during the process of forming the first isolation structure in the second trench, the first isolation structure material will cover the upper surface of the second mask layer after back etching. Usually, after deposition is completed, CMP process is used to remove the excess first isolation structure material to expose the upper surface of the second mask layer after back etching.

[0113] refer to Figure 4g The second mask layer 3012b after etching is removed to form the first contact hole 3024.

[0114] refer to Figure 4hThe first contact hole 3024 is enlarged (CD) to form a second contact hole 3025, which exposes at least the entire upper surface of the semiconductor body 3032. The second contact holes 3025 are evenly spaced along the X-axis. In some embodiments, the method for enlarging the first contact hole 3024 may include, but is not limited to, dry etching.

[0115] In some embodiments, while enlarging the first contact hole 3024, a portion of the top of the semiconductor body 3032 is also etched, resulting in a reduction in the size of the semiconductor body 3032 along the Z-axis.

[0116] refer to Figure 4i A doped semiconductor material is deposited in the second contact hole 3025, and the doped semiconductor material is etched back to form a first doped layer 3071, which is in contact with the upper surface of the semiconductor body 3032. The doped semiconductor material includes doped polysilicon, specifically P-doped polysilicon.

[0117] refer to Figure 4j A first conductive layer 3072 is formed on the first doped layer 3071. The first conductive layer 3072 comprises a metal semiconductor compound, and in some specific embodiments, the metal element in the metal semiconductor compound includes, but is not limited to, nickel, cobalt, or titanium. In some embodiments, the first conductive layer can be formed by metallizing the semiconductor layer. Here, the semiconductor layer can be the first doped layer or a semiconductor layer formed on the first doped layer.

[0118] Understandably, since metal-semiconductor compounds can be formed by metallizing semiconductor layers, the contact structure and semiconductor body can achieve self-alignment.

[0119] refer to Figure 4k A second conductive layer is formed on the first conductive layer 3072, and the second conductive layer is located on the side of the first conductive layer away from the first doped layer. In some specific embodiments, the second conductive layer includes a first sub-layer 3073 and a second sub-layer 3074, wherein the first sub-layer 3073 surrounds the other surfaces of the second sub-layer 3074 except for its upper surface. The first sub-layer 3073 is in contact with the first conductive layer 3072. The material of the first sub-layer may be titanium nitride, and the material of the second sub-layer includes, but is not limited to, tungsten or copper.

[0120] In some embodiments, the first doped layer 3071, the first conductive layer 3072, the first sublayer 3073, and the second sublayer 3074 constitute a contact structure. In the contact structure, the first doped layer 3071 is in contact with the semiconductor substrate, and the second sublayer 3074 is in contact with the memory element.

[0121] like Figure 4k As shown, the distance between any two adjacent contact structures in the multiple contact structures is L, that is, the multiple contact structures arranged along the X-axis are evenly spaced.

[0122] In some embodiments, forming a memory cell array includes forming a capacitor coupled to the contact structure, the capacitor being coupled to the semiconductor body through the contact structure.

[0123] In some specific embodiments, the capacitor coupled to the contact structure includes forming a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), or a pillar-shaped capacitor (PIL). The shape of the capacitor can be selected according to actual needs, and this disclosure does not limit it.

[0124] In some embodiments, forming the first semiconductor structure further includes forming a capacitor contact coupled to a capacitor. The capacitor contact is coupled to a second electrode of the capacitor structure for coupling the second electrode of the capacitor structure to an external circuit or directly to ground.

[0125] In some embodiments, forming the first semiconductor structure further includes: performing a back-side thinning process on the semiconductor substrate to expose the opposite end of the upper surface of the gate dielectric and the semiconductor body. It should be noted that during the back-side thinning process on the semiconductor substrate, a fourth oxide layer and a second sacrificial layer are also exposed.

[0126] In some embodiments, forming the first semiconductor structure further includes: removing the fourth oxide layer and the second sacrificial layer from the second spacer trench to form a second air gap. Here, the second air gap serves as a second isolation structure. The second doped layer is used to form the drain.

[0127] In some embodiments, forming the first semiconductor structure further includes forming word lines on at least one side of the semiconductor body.

[0128] In some specific embodiments, forming word lines on at least one side of the semiconductor body includes: forming word lines located on one side of the semiconductor body; or forming word lines located on two opposite sides of the semiconductor body; or forming word lines surrounding the side of the semiconductor body.

[0129] It is understood that the contact structure in this disclosure can be applied to different word line (gate structure) scenarios. For example, the contact structure in this disclosure can be applied to a scenario where two word line structures corresponding to two adjacent semiconductor bodies are arranged back-to-back. The accompanying drawings in this disclosure illustrate a back-to-back arrangement scenario.

[0130] In some embodiments, forming the first semiconductor structure further includes forming a third doped layer at one end corresponding to the upper surface of the semiconductor body. Here, the third doped layer is used to form a source (the positions of the source and drain can be interchanged; here, the upper end of the semiconductor body is taken as the source and the lower end as the drain).

[0131] In some embodiments, forming the first semiconductor structure further includes: forming a second doped layer at an opposite end of the upper surface of the semiconductor body; and forming a bit line coupled to the second doped layer, the bit line extending along a first lateral direction. Here, the bit line is coupled to the drain of the semiconductor body.

[0132] In some embodiments, forming the first semiconductor structure further includes: forming a plurality of third air gaps between adjacent bit lines, the third air gaps extending along a first lateral direction.

[0133] In some embodiments, the first isolation structure includes a first dielectric layer and / or a first air gap.

[0134] In some embodiments, the first air gap, the second air gap, and the third air gap are connected.

[0135] In this embodiment, the first air gap, the second air gap, and the third air gap between two adjacent bit lines are connected. This not only increases the density of the semiconductor device and reduces the manufacturing process difficulty and cost, but also reduces the capacitive coupling effect between adjacent word lines, adjacent semiconductor bodies, and adjacent bit lines, thereby improving the performance of the semiconductor device and making it more conducive to future miniaturization of the semiconductor device.

[0136] In some embodiments, forming the first semiconductor structure further includes forming a bit line lead-out structure coupled to a bit line.

[0137] In some embodiments, forming the first semiconductor structure further includes: forming a second interconnect layer coupled to the bit line lead structure and the capacitor contacts; and forming a second bonding layer coupled to the second interconnect layer. The second bonding layer may include a plurality of second bonding contacts and a dielectric that electrically isolates the second bonding contacts.

[0138] In some embodiments, the method further includes: forming a second semiconductor structure; the second semiconductor structure includes peripheral circuitry, a first interconnect layer, and a first bonding layer. The first bonding layer may include a plurality of first bonding contacts and a dielectric material for electrically isolating the first bonding contacts.

[0139] In some embodiments, the method further includes: bonding the second semiconductor structure to the first semiconductor structure through a first bonding layer and a second bonding layer.

[0140] In this embodiment, self-alignment between the contact structure and the semiconductor body can be achieved, which increases the alignment accuracy between the contact structure and the semiconductor body, reduces the alignment difficulty between the two, improves the reliability of the semiconductor device, saves manufacturing time and cost, and improves process speed and efficiency. On the other hand, the metal semiconductor compound, as the material of the contact structure between the semiconductor body and the memory element, has a low resistivity, which can achieve better electrical connection between the semiconductor body and the memory element and improve the reliability of the semiconductor device.

[0141] In this embodiment of the present disclosure, since the spacing between adjacent contact structures along the first lateral direction is equal, that is, the multiple contact structures arranged along the first lateral direction are evenly spaced, the storage element that is subsequently formed can be aligned with the contact structure in the vertical direction (that is, the storage element can be formed on the contact structure in the correct orientation) without offset alignment, thereby improving the connection window between the contact structure and the storage element.

[0142] In this embodiment of the disclosure, since the dimension of the contact structure along the X-axis is larger than the dimension of the semiconductor body along the X-axis, the connection window between the contact structure and the memory element is further improved, and the contact resistance can also be further reduced.

[0143] Figure 5 A schematic diagram of the structure of a semiconductor device provided in this disclosure embodiment. Figure 2 ;like Figure 5 As shown, the semiconductor device 100 includes: a first semiconductor structure 104, the first semiconductor structure 104 including: a memory cell array including a plurality of memory cells 1024 arranged in an array along a first lateral direction and a second lateral direction, each memory cell 1024 including a vertical transistor 1026 and a memory element 1028 coupled to one end of the vertical transistor 1026; a plurality of contact structures 1064, the contact structures 1064 being located between the vertical transistor 1026 and the memory element 1028; in two contact structures adjacent to the first contact structure in the plurality of contact structures 1064 along the first lateral direction, the distance between any one of the two contact structures and the first contact structure is equal.

[0144] like Figure 5 As shown, the distance between any two adjacent contact structures 1064 in the plurality of contact structures 1064 is L. That is, the plurality of contact structures 1064 arranged along the first transverse direction (X-axis direction) are evenly spaced.

[0145] In some embodiments, the vertical transistor 1026 includes: a semiconductor body 1030 extending in a vertical direction and a gate structure 1036 in contact with at least a portion of the side surface of the semiconductor body 1030, the gate structure 1036 extending in a second lateral direction; the distance between adjacent semiconductor bodies 1030 is greater than or equal to the distance between adjacent contact structures 1064.

[0146] In some embodiments, the contact structure 1064 and the semiconductor body 1030 are aligned vertically along one sidewall of the first lateral direction, and the distance between adjacent semiconductor bodies 1030 along the other sidewall of the first lateral direction is greater than the distance between adjacent contact structures 1064 along the other sidewall of the first lateral direction.

[0147] In some embodiments, the dimension of the contact structure 1064 along the first lateral direction is larger than the dimension of the semiconductor body 1030 along the first lateral direction.

[0148] In some embodiments, the first semiconductor structure 104 further includes: a plurality of bit lines 1023 extending along the first lateral direction and coupled to the other end of the vertical transistor 1026; and a plurality of isolation structures located between adjacent vertical transistor groups along the second lateral direction and extending along the second lateral direction.

[0149] In some embodiments, the plurality of isolation structures include: a first isolation structure and a second isolation structure alternately arranged along the first transverse direction; wherein, the first isolation structure includes a first dielectric layer 1062-1 and / or a first air gap 1062-2; and the second isolation structure includes a second air gap 1060-1.

[0150] In some embodiments, a plurality of third air gaps are located between adjacent bit lines and extend along a first lateral direction.

[0151] In some embodiments, the first air gap 1062-2, the second air gap 1060-1, and the third air gap are connected.

[0152] In some embodiments, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 between the gate electrode 1034 and the semiconductor body 1030 in the first lateral direction and the second lateral direction.

[0153] In some embodiments, the vertical transistor 1026 further includes a source 1038 and a drain 1040 respectively disposed at two ends of the semiconductor body 1030 in the vertical direction; one of the source 1038 and the drain 1040 of the vertical transistor 1026 is coupled to the memory element 1028 in a corresponding memory cell; the other of the source 1038 and the drain 1040 of the vertical transistor 1026 is coupled to a corresponding bit line 1023. In some embodiments, the source 1038 is coupled to the memory element 1028, and the drain 1040 is coupled to the bit line 1023.

[0154] In some embodiments, the contact structure includes a first conductive layer and a second conductive layer; the first conductive layer includes a metal-semiconductor compound, and the second conductive layer includes a metal. The second conductive layer includes a first sublayer and a second sublayer, wherein the first sublayer surrounds the other surfaces of the second sublayer except for its upper surface. The first sublayer is in contact with the first conductive layer.

[0155] In some embodiments, the contact structure further includes a first doped layer; the first doped layer is located on the side of the first conductive layer away from the second conductive layer. The first doped layer in the contact structure contacts the vertical transistor 1026, and the second sub-layer in the contact structure contacts the storage element 1028.

[0156] In some embodiments, the vertical transistor 1026 includes at least one of a gate-all-around (GAA) transistor, a tri-gate transistor, a dual-gate transistor, or a single-gate transistor.

[0157] In some embodiments, the storage element 1028 includes at least one of a capacitor, a ferroelectric capacitor, or a phase-change memory (PCM) element.

[0158] In some embodiments, the storage element 1028 is a capacitor including a first electrode, a second electrode, and a capacitor dielectric.

[0159] In some embodiments, the semiconductor device 100 further includes a second semiconductor structure 102; the first semiconductor structure 104 and the second semiconductor structure 102 are stacked in a vertical direction, and the second semiconductor structure 102 includes peripheral circuitry 1012.

[0160] This disclosure further provides a memory system, including: a semiconductor device, the semiconductor device including a first semiconductor structure, the first semiconductor structure including: a memory cell array including a plurality of memory cells arranged in an array along a first lateral direction and a second lateral direction, the memory cells including a vertical transistor and a memory element coupled to one end of the vertical transistor; a plurality of contact structures located between the vertical transistor and the memory element; in two contact structures adjacent to the first contact structure along the first lateral direction, the distance between either of the two contact structures and the first contact structure is equal; and a memory controller configured to control the semiconductor device.

[0161] In some embodiments, the vertical transistor includes: a semiconductor body extending in a vertical direction and a gate structure in contact with at least a portion of the side of the semiconductor body, the gate structure extending in a second lateral direction; the distance between adjacent semiconductor bodies is greater than or equal to the distance between adjacent contact structures.

[0162] In some embodiments, the contact structure and the semiconductor body are aligned vertically along one sidewall of the first lateral direction, and the distance between adjacent semiconductor bodies along the other sidewall of the first lateral direction is greater than the distance between adjacent contact structures along the other sidewall of the first lateral direction.

[0163] In some embodiments, the dimension of the contact structure along the first lateral direction is larger than the dimension of the semiconductor body along the first lateral direction.

[0164] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0165] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0166] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes a first semiconductor structure, the first semiconductor structure comprising: The memory cell array includes a plurality of memory cells arranged in an array along a first lateral direction and a second lateral direction, each memory cell including a vertical transistor and a memory element coupled to one end of the vertical transistor; Multiple contact structures are located between the vertical transistor and the memory element; In two contact structures that are adjacent to the first contact structure in the first lateral direction, the distance between either of the two contact structures and the first contact structure is equal.

2. The semiconductor device according to claim 1, characterized in that, The vertical transistor includes: a semiconductor body extending in a vertical direction and a gate structure in contact with at least a portion of the side surface of the semiconductor body, the gate structure extending in a second lateral direction; The distance between adjacent semiconductor bodies is greater than or equal to the distance between adjacent contact structures.

3. The semiconductor device according to claim 2, characterized in that, The contact structure and the semiconductor body are aligned vertically along one sidewall of the first lateral direction, and the distance between adjacent semiconductor bodies along the other sidewall of the first lateral direction is greater than the distance between adjacent contact structures along the other sidewall of the first lateral direction.

4. The semiconductor device according to claim 2, characterized in that, The dimension of the contact structure along the first lateral direction is larger than the dimension of the semiconductor body along the first lateral direction.

5. The semiconductor device according to claim 2, characterized in that, The first semiconductor structure further includes: Multiple bit lines, the bit lines extending along the first lateral direction and coupled to the other end of the vertical transistor; Multiple isolation structures are located between adjacent vertical transistor groups along the second lateral direction and extend along the second lateral direction.

6. The semiconductor device according to claim 5, characterized in that, The plurality of isolation structures include: A first isolation structure and a second isolation structure are alternately arranged along the first transverse direction; wherein, the first isolation structure includes a first dielectric layer and / or a first air gap; and the second isolation structure includes a second air gap.

7. The semiconductor device according to claim 6, characterized in that, Multiple third air gaps are located between adjacent position lines and extend along a first lateral direction.

8. The semiconductor device according to claim 7, characterized in that, The first air gap, the second air gap, and the third air gap are connected.

9. The semiconductor device according to any one of claims 2 to 8, characterized in that, The gate structure includes a gate electrode and a gate dielectric between the gate electrode and the semiconductor body in the first lateral direction and the second lateral direction.

10. The semiconductor device according to any one of claims 2 to 8, characterized in that, The vertical transistor further includes a source and a drain respectively disposed at two ends of the semiconductor body in the vertical direction; one of the source and the drain of the vertical transistor is coupled to the memory element in the corresponding memory cell; the other of the source and the drain of the vertical transistor is coupled to a corresponding bit line.

11. The semiconductor device according to claim 1, characterized in that, The contact structure includes a first conductive layer and a second conductive layer; the first conductive layer includes a metal semiconductor compound, and the second conductive layer includes a metal.

12. The semiconductor device according to claim 1, characterized in that, The vertical transistor includes at least one of a gate-all-around (GAA) transistor, a tri-gate transistor, a dual-gate transistor, or a single-gate transistor.

13. The semiconductor device according to claim 1, characterized in that, The storage element includes at least one of a capacitor, a ferroelectric capacitor, or a phase-change memory (PCM) element.

14. The semiconductor device according to claim 13, wherein, The storage element is a capacitor comprising a first electrode, a second electrode, and a capacitor dielectric.

15. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked in a vertical direction, and the second semiconductor structure includes peripheral circuitry.

16. The semiconductor device according to claim 15, characterized in that, The first semiconductor structure and the second semiconductor structure are formed on the same substrate; or, The first semiconductor structure and the second semiconductor structure are formed on different substrates.

17. A method for fabricating a semiconductor device, characterized in that, The method includes: forming a first semiconductor structure; forming the first semiconductor structure includes: A memory cell array is formed, the memory cell array comprising a plurality of memory cells arranged in an array along a first lateral direction and a second lateral direction, each memory cell comprising a vertical transistor and a memory element coupled to one end of the vertical transistor; Forming the first semiconductor structure further includes: forming a plurality of contact structures, the contact structures being located between the vertical transistor and the memory element; and in two contact structures adjacent to the first contact structure in the plurality of contact structures along the first lateral direction, the distance between any one of the two contact structures and the first contact structure is equal.

18. The method according to claim 17, characterized in that, Forming the first semiconductor structure includes: etching a semiconductor substrate through a mask stack to form a semiconductor pillar array; the semiconductor pillar array includes rows of semiconductor pillars arranged along the second lateral direction, the rows of semiconductor pillars being separated by first spacer trenches; The mask stack includes a first mask layer and a second mask layer; The semiconductor pillars are etched by removing the openings formed after the first mask layer is removed to form a plurality of second spacer trenches extending in the second lateral direction, the plurality of second spacer trenches dividing each semiconductor pillar in the corresponding row of semiconductor pillars into two semiconductor bodies.

19. The method according to claim 18, characterized in that, Multiple contact structures are formed, including: The second mask layer is etched back so that the etched second mask layer is evenly spaced along the first lateral direction; Remove the etched second mask layer to form the first contact hole; The first contact hole is enlarged to form a second contact hole, the second contact hole exposing at least the entire upper surface of the semiconductor body; A contact structure is formed in the second contact hole.

20. The method according to claim 18, characterized in that, The etching of the semiconductor pillar by removing the opening formed after removing the first mask layer includes: The first mask layer is pushed back along the first spacing groove to increase the opening of the first spacing groove in the first mask layer; A first sacrificial layer is deposited to fill the first spacer trench; The first mask layer is removed to form an opening in the first sacrificial layer, through which the semiconductor pillar is etched.

21. The method according to claim 20, characterized in that, Before removing the second mask layer after back etching to form the first contact hole, forming the first semiconductor structure further includes: A second sacrificial layer and a second dielectric layer are formed in the second spacer trench.

22. The method according to claim 21, characterized in that, The formation of the first semiconductor structure further includes: Remove the first sacrificial layer to form a third spacer trench; A word line structure is formed in the third interval groove; A second groove is formed in the character line structure; The first isolation structure is formed in the second trench, wherein the word line structure is divided into two word lines by the first isolation structure.

23. The method according to claim 19, characterized in that, A contact structure is formed in the second contact hole, including: A first doped layer is formed at the bottom of the second contact hole, and the first doped layer is in contact with the upper surface of the semiconductor body.

24. The method according to claim 23, characterized in that, Forming a contact structure in the second contact hole further includes: A first conductive layer is formed on the first doped layer; A second conductive layer is formed on the first conductive layer; The first conductive layer comprises a metal semiconductor compound, and the second conductive layer comprises a metal.

25. The method according to claim 23, characterized in that, Forming a storage cell array includes: A capacitor is formed coupled to the contact structure, and the capacitor is coupled to the semiconductor body through the contact structure.

26. The method according to claim 25, characterized in that, The formation of the first semiconductor structure further includes: A second doped layer is formed at the opposite end of the upper surface of the semiconductor body; A bit line is formed that is coupled to the second doped layer, the bit line extending along a first lateral direction.

27. The method according to claim 26, characterized in that, The first semiconductor structure is formed before forming a second doped layer at the opposite end of the upper surface of the semiconductor body, and further includes: The second sacrificial layer in the second spacer trench is removed to form a second air gap.

28. The method according to claim 26, characterized in that, The formation of the first semiconductor structure further includes: Multiple third air gaps are formed between adjacent bit lines, and the third air gaps extend along the first lateral direction.

29. A memory system, characterized in that, include: A semiconductor device, the semiconductor device including a first semiconductor structure, the first semiconductor structure including: a memory cell array including a plurality of memory cells arranged in an array along a first lateral direction and a second lateral direction, the memory cell including a vertical transistor and a memory element coupled to one end of the vertical transistor; Multiple contact structures are located between the vertical transistor and the memory element; In two contact structures adjacent to the first contact structure in the first lateral direction among a plurality of contact structures, the distance between either of the two contact structures and the first contact structure is equal; and A memory controller configured to control the semiconductor device.

30. The memory system according to claim 29, characterized in that, The vertical transistor includes: a semiconductor body extending in a vertical direction and a gate structure in contact with at least a portion of the side surface of the semiconductor body, the gate structure extending in a second lateral direction; The distance between adjacent semiconductor bodies is greater than or equal to the distance between adjacent contact structures.

31. The memory system according to claim 29, characterized in that, The contact structure and the semiconductor body are aligned vertically along one sidewall of the first lateral direction, and the distance between adjacent semiconductor bodies along the other sidewall of the first lateral direction is greater than the distance between adjacent contact structures along the other sidewall of the first lateral direction.

32. The memory system according to claim 30, characterized in that, The dimension of the contact structure along the first lateral direction is larger than the dimension of the semiconductor body along the first lateral direction.

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