Preparation method of semiconductor device and semiconductor device
By forming a protective layer on top of the shielding gate and shielding gate leads and using isotropic etching technology, the leakage problem caused by the recess in the SGT MOSFET device was solved, improving the reliability and performance of the device.
Patent Information
- Application Number
- CN202510999614.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-04
- Filing Date
- 2025-07-21
- Publication Date
- 2025-10-28
AI Technical Summary
During the formation of the gate dielectric layer and shielding gate dielectric layer in SGT MOSFET devices, the recessed area can easily lead to leakage current in the shielding gate and shielding gate leads, affecting device performance.
A protective layer is formed on top of the shielding gate and shielding gate leads, and isotropic etching technology is used to form the shielding gate dielectric layer and shielding gate lead dielectric layer to prevent the formation of recesses.
It effectively prevents the formation of grooves on both sides of the shielding grid and shielding grid leads, solves the leakage problem of the device, and improves the reliability and performance of the device.
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Figure CN120857544A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology
[0002] SGT (Shielded Gate Trench) MOSFETs add a gate conductor, or shielding gate, below the control gate for isolation. The shielding gate is connected to the source electrode via shielding gate leads, thus achieving the function of shielding the gate and the drift region. This reduces Miller capacitance and gate charge, resulting in faster switching speed and lower switching losses.
[0003] In SGT MOSFET devices, the shielding gate dielectric layer needs to be thicker than the gate dielectric layer. This dictates that the gate dielectric layer and the shielding gate dielectric layer must be formed through different steps. During the formation of the gate dielectric layer and the shielding gate dielectric layer, a recess is formed at the top of both layers. In the subsequent formation of the control gate, this recess is filled with the gate conductor, making the shielding gate and its leads highly susceptible to leakage. Summary of the Invention
[0004] In view of the above problems, the purpose of this application is to provide a method for fabricating a semiconductor device and a semiconductor device, thereby solving the problem of device leakage.
[0005] According to one aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising: forming an insulating layer on a semiconductor layer, and forming a first trench and a second trench in the semiconductor layer, wherein the width of the second trench is greater than the width of the first trench; forming a first dielectric layer at the bottom and sidewalls of the first trench, the bottom and sidewalls of the second trench, and the surface of the insulating layer away from the semiconductor layer; forming a shielding gate at the lower part of the first trench, and forming a third protective layer on the shielding gate; forming a shielding gate lead in the second trench, and forming a second protective layer on the shielding gate lead; etching the first dielectric layer with the second and third protective layers as protective layers to form a shielding gate dielectric layer and a shielding gate lead dielectric layer, while removing the second and third protective layers; forming a control gate at the upper part of the first trench and forming a second dielectric layer that isolates the control gate and the semiconductor layer; and forming a source region adjacent to the first trench.
[0006] Optionally, a shielding gate is formed at the lower part of the first trench, and a third protective layer is formed on the shielding gate. A shielding gate lead is formed in the second trench, and a second protective layer is formed on the shielding gate lead. The method includes: forming a first conductor layer in the first trench and the second trench, wherein the top of the first conductor layer in the first trench and the second trench is higher than the surface of the semiconductor layer and lower than the surface of the insulating layer to form a first cavity in the first trench and a second cavity in the second trench; forming a first protective layer in the first cavity in the first trench; forming a second protective layer on top of the first conductor layer in the second trench, and forming a shielding gate lead with the remaining first conductor layer in the second trench; selectively removing the first protective layer in the first trench; using the second protective layer as the etched protective layer, removing a portion of the first conductor layer in the first trench, and forming a third protective layer on top of the portion of the first conductor layer in the first trench, with the remaining first conductor layer in the first trench forming a shielding gate and forming a third protective layer on top of the shielding gate.
[0007] Optionally, the method of forming a first protective layer in a first cavity in a first trench includes: forming a first protective layer located on the surface of a first dielectric layer above an insulating layer, filling the first cavity, and conformally covering the bottom and sidewalls of a second cavity; and removing the first protective layer above the insulating layer, as well as the first protective layer on the bottom and sidewalls of the second cavity, while retaining the first protective layer filling the interior of the first cavity.
[0008] Optionally, the width of the first trench is less than twice the thickness of the first protective layer, and the width of the second trench is greater than twice the thickness of the first protective layer.
[0009] Optionally, the first protective layer is a nitrided layer.
[0010] Optionally, wet etching is used to remove the first protective layer above the insulating layer, as well as the first protective layer at the bottom and sidewalls of the second cavity. During the etching process, the etchant isotropically etches the first protective layer.
[0011] Optionally, during the formation of the shielding gate dielectric layer and the shielding gate lead dielectric layer, a portion of the first dielectric layer is removed by wet etching. During the wet etching process, the etchant isotropically etches the first dielectric layer, the second protective layer, and the third protective layer.
[0012] Optionally, the first protective layer, the second protective layer, and the first dielectric layer are made of the same material and have the same thickness.
[0013] Optionally, the top of the formed shielding grid dielectric layer is flush with the top of the shielding grid, and the top of the formed shielding grid lead dielectric layer is flush with the top of the shielding grid lead.
[0014] According to another aspect of the present invention, a semiconductor device formed by the above-described preparation method is provided, wherein the top of the shielding gate dielectric layer of the semiconductor device is flush with the top of the shielding gate, and the top of the shielding gate lead dielectric layer is flush with the top of the shielding gate lead.
[0015] The unexpected technical effect of this application is:
[0016] In this embodiment, before forming the shielding gate dielectric layer and the shielding gate lead dielectric layer, protective layers are formed on the top of the shielding gate and the top of the shielding gate lead, respectively. During the etching process of the first dielectric layer to form the shielding gate dielectric layer and the shielding gate lead dielectric layer, the etchant isotropically etches the first dielectric layer, the protective layer on the top of the shielding gate, and the protective layer on the top of the shielding gate lead, to prevent the formation of depressions on the top of the shielding gate dielectric layer and the shielding gate lead dielectric layer. This further prevents the gate conductor from filling the depressions during the subsequent formation of the control gate, thus preventing the formation of protrusions on both sides of the shielding gate and both sides of the shielding gate lead, thereby solving the problem of device leakage.
[0017] In a preferred embodiment, the third protective layer on top of the shielding gate, the second protective layer on top of the shielding gate lead, and the first dielectric layer are all made of the same material and have the same thickness. The first dielectric layer, the second protective layer, and the third protective layer are etched simultaneously, ensuring the precision of wet etching and further preventing grooves from forming on both sides of the shielding gate and the shielding gate lead.
[0018] In a preferred embodiment, by setting a first trench and a second trench with different widths, and forming a first protective layer in the first trench and the second trench, the top of the first trench is filled with the first protective layer, while the sidewalls and bottom of the second trench are conformally covered by the first protective layer. By utilizing the width difference between the first trench and the second trench, as well as the conformal coverage characteristic of the first protective layer, the first protective layer can be selectively formed in the first trench using only a wet etching process, avoiding the use of photolithography.
[0019] In a preferred embodiment, the width of the first trench is less than twice the thickness of the first protective layer, and the width of the second trench is greater than twice the thickness of the first protective layer, so that the first trench is filled by the first protective layer, while the second protective layer retains the conformal coverage feature of the first protective layer. Attached Figure Description
[0020] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0021] Figures 1a to 1f The diagram illustrates the three-dimensional structure of each stage in the fabrication process of semiconductor devices using conventional techniques; wherein:
[0022] Figure 1aA three-dimensional structural schematic diagram is shown, in which an insulating layer is formed on the first surface of a semiconductor layer, and a first trench and a second trench are formed in the semiconductor layer.
[0023] Figure 1b A three-dimensional structural schematic diagram is shown, in which a shielding grid is formed in the first trench and shielding grid leads are formed in the second trench.
[0024] Figure 1c A three-dimensional structural schematic diagram of the shielding gate dielectric layer and the shielding gate lead dielectric layer is shown;
[0025] Figure 1d A three-dimensional structural schematic diagram of the formation of the second dielectric layer is shown;
[0026] Figure 1e A three-dimensional structural diagram of the formation of the second conductor layer is shown;
[0027] Figure 1f A three-dimensional structural diagram of the control grid is shown;
[0028] Figures 2a to 2q This application illustrates a three-dimensional structural diagram of each stage in the fabrication process of a semiconductor device according to an embodiment of the present application; wherein:
[0029] Figure 2a The diagram shows a three-dimensional structure in which an insulating layer is formed on the first surface of a semiconductor layer, and a first trench and a second trench are formed in the semiconductor layer.
[0030] Figure 2b A three-dimensional schematic diagram is shown showing the bottom and sidewalls of the first trench, the bottom and sidewalls of the second trench, and the surface of the insulating layer away from the semiconductor layer, forming a first dielectric layer.
[0031] Figure 2c A three-dimensional structural diagram of the formation of the first conductor layer is shown;
[0032] Figure 2d A three-dimensional structural diagram of the formation of the first protective layer is shown;
[0033] Figure 2e A three-dimensional structural diagram is shown with the first protective layer above the insulating layer removed, as well as the first protective layer at the bottom and sidewalls of the second cavity, while retaining the first protective layer filling the interior of the first cavity.
[0034] Figure 2f A three-dimensional structural schematic diagram of a second protective layer forming on top of the first conductor layer within the second trench is shown.
[0035] Figure 2g A three-dimensional structural schematic diagram of removing the first protective layer in the first trench is shown;
[0036] Figure 2h A three-dimensional structural schematic diagram of the first conductor layer with a portion of the first trench removed is shown;
[0037] Figure 2i A three-dimensional structural schematic diagram of a third protective layer forming on top of the first conductor layer in the first trench is shown;
[0038] Figure 2j A three-dimensional structural diagram is shown, in which the second and third protective layers are etched to form a shielding gate dielectric layer and a shielding gate lead dielectric layer, while the second and third protective layers are removed.
[0039] Figure 2k A three-dimensional structural schematic diagram of the region forming the second dielectric layer is shown;
[0040] Figure 2l A three-dimensional structural diagram of the formation of the second conductor layer is shown;
[0041] Figure 2m A three-dimensional structural diagram of the control grid is shown;
[0042] Figure 2n A three-dimensional structural diagram of the interlayer dielectric layer is shown;
[0043] Figure 2o A three-dimensional structural schematic diagram of the first contact hole, the second contact hole, and the third contact hole forming a through-layer interlayer dielectric layer is shown;
[0044] Figure 2p A three-dimensional structural schematic diagram showing the formation of the first contact structure, the second contact structure, and the third contact structure is shown.
[0045] Figure 2q A three-dimensional structural diagram of the interconnect layer is shown;
[0046] Figure 3 A schematic diagram showing the distribution of the device area and the shielding gate lead area in an embodiment of this application is shown. Detailed Implementation
[0047] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.
[0048] This application may be presented in various forms, some of which will be described below.
[0049] Figures 1a to 1f This diagram illustrates the three-dimensional structure of each stage in the fabrication process of semiconductor devices using conventional techniques. The following will combine... Figures 1a to 1fThe fabrication methods of semiconductor devices using traditional techniques are explained.
[0050] like Figure 1a As shown, an insulating layer 102 is formed on the first surface of the semiconductor layer 101, and a first trench 1031 and a second trench 1032 are formed in the semiconductor layer 101, wherein the widths of the first trench 1031 and the second trench 1032 are the same.
[0051] Next, a first dielectric layer 104 is formed, which covers the bottom and sidewalls of the first trench 1031, the bottom and sidewalls of the second trench 1032, and the surface of the insulating layer 102 away from the semiconductor layer 101.
[0052] Next, a first conductor layer 105 is formed. The first conductor layer 105 fills the first trench 1031 and the second trench 1032, and covers the surface of the first dielectric layer 104 above the insulating layer 102. The first conductor layer 105 is etched back to remove the portion of the first conductor layer 105 above the insulating layer 102, the portion of the first conductor layer 105 in the first trench 1031, and the portion of the first conductor layer 105 in the second trench 1032. The top of the remaining first conductor layer 105 in the first trench 1031 and the second trench 1032 is substantially flush with the top of the semiconductor layer 101.
[0053] like Figure 1b As shown, a shielding grid 105a is formed in the first trench 1031, and a shielding grid lead 105b is formed in the second trench 1032.
[0054] In this step, a patterned mask layer PR is formed. The patterned mask layer PR covers the surface of the first conductor layer 105 in the second trench 1032 and a portion of the surface of the first dielectric layer 104, exposing the surface of the first conductor layer 105 in the first trench 1031 and a portion of the surface of the first dielectric layer 104.
[0055] Next, the first conductor layer 105 in the first trench 1031 is etched via a patterned mask layer PR. The first conductor layer 105 at the bottom of the first trench 1031 is retained to form a shielding gate 105a, and the top of the remaining first conductor layer 105 in the second trench 1032 is approximately flush with the surface of the semiconductor layer 101 to form a shielding gate lead 105b.
[0056] Next, remove the patterned mask layer PR.
[0057] like Figure 1c As shown, a shielding gate dielectric layer 104a and a shielding gate lead dielectric layer 104b are formed.
[0058] In this step, wet etching is used to etch back the first dielectric layer 104, wherein the first dielectric layer 104 above the semiconductor layer 101 and the first dielectric layer 104 above the first trench 1031 are removed, the remaining first dielectric layer 104 in the first trench 1031 forms a shielding gate dielectric layer 104a, and the remaining first dielectric layer 104 in the second trench 1032 forms a shielding gate lead dielectric layer 104b. During the wet etching process, the etchant isotropically etches the first dielectric layer 104. While the etchant laterally etches the first dielectric layer 104 on the sidewall of the first trench 1031, it also etches downwards, causing the top of the shielding gate dielectric layer 104a to be lower than the top of the shielding gate 105a, thus forming a first recess S1 on both sides of the shielding gate 105a. Similarly, the top of the shielding gate lead dielectric layer 104b is lower than the top of the shielding gate lead 105b, thus forming a second recess S2 on both sides of the shielding gate lead 105b.
[0059] Next, the insulating layer 102 is removed to expose the surface of the semiconductor layer 101.
[0060] like Figure 1d As shown, a second dielectric layer 107 is formed, which conformally covers the surface of the semiconductor layer 101, the upper sidewall of the first trench 1031, the bottom and sidewall of the first recess S1, the top of the shielding gate 105a, the bottom and sidewall of the second recess S2, and the top of the shielding gate lead 105b.
[0061] like Figure 1e As shown, a second conductor layer 108 is formed. The second conductor layer 108 covers the surface of the second dielectric layer 107 above the semiconductor layer 101 and the surface of the second dielectric layer 107 above the shielding gate lead 105b, fills the upper part of the first trench 1031, and fills the first recess S1 and the second recess S2, respectively forming the first protrusion T1 and the second protrusion T2.
[0062] like Figure 1f As shown, a control gate 108a is formed.
[0063] In this step, the second conductor layer 108 above the semiconductor layer 101 and the second conductor layer 108 above the shielding gate lead 105b are removed, leaving the second conductor layer 108 in the first trench 1031. The remaining second conductor layer 108 fills the upper part of the first trench 1031 and is isolated from the semiconductor layer 101 via the second dielectric layer 107. The second conductor layer 108 on the upper part of the first trench 1031 constitutes the control gate 108a of the device.
[0064] Furthermore, the second conductor layer 108 in the first recess S1 and the second recess S2 is also retained, forming the first protrusion T1 and the second protrusion T2 respectively. The first protrusion T1 and the shielding gate 105a, and the second protrusion T2 and the shielding gate lead 105b are very easy to short-circuit, resulting in leakage.
[0065] Figures 2a to 2q This illustration shows a three-dimensional structural diagram of each stage in the fabrication process of the semiconductor device according to an embodiment of this application. The following will be combined with... Figures 2a to 2q The method for fabricating the semiconductor device according to the first embodiment of this application will be described.
[0066] like Figure 2a As shown, an insulating layer 202 is formed on the first surface of the semiconductor layer 201, and a first trench 2031 and a second trench 2032 are formed in the semiconductor layer 201, wherein the width of the second trench 2032 is greater than the width of the first trench 2031.
[0067] In this embodiment, the semiconductor layer 201 includes a substrate 2011 and an epitaxial layer 2012 located on the substrate 2011. The insulating layer 202 serves as a hard mask layer for the subsequent formation of the first trench 2031 and the second trench 2032, and includes a stacked oxide layer 2021 and a nitride layer 2022, wherein the oxide layer 2021 is located on the surface of the semiconductor layer 201, and the nitride layer 2022 is located on the surface of the oxide layer 2021 away from the semiconductor layer 201. In other embodiments, the insulating layer 202 may also include only one of the oxide layer and the nitride layer, or a composite layer of multiple oxide layers and multiple nitride layers; this embodiment does not limit this.
[0068] In this step, for example, a deposition process is used to sequentially form an oxide layer 2021 and a nitride layer 2022 on the surface of the semiconductor layer 201. Next, a mask is formed on the surface of the nitride layer 2022 away from the oxide layer 2021. A patterned mask is formed using photolithography. The nitride layer 2022, the oxide layer 2021, and at least a portion of the semiconductor layer 201 are sequentially etched through the patterned mask to form a first trench 2031 and a second trench 2032 in the semiconductor layer 201. The first trench 2031 and the second trench 2032 extend from the surface of the nitride layer 2022 away from the oxide layer 2021 toward the semiconductor layer 201, penetrating the nitride layer 2022 and the oxide layer 2021, and ending inside the semiconductor layer 201. The width of the first trench 2031 is smaller than the width of the second trench 2032.
[0069] like Figure 2b As shown, a first dielectric layer is formed at the bottom and sidewalls of the first trench, the bottom and sidewalls of the second trench, and the surface of the insulating layer away from the semiconductor layer.
[0070] In this step, for example, a deposition process is used to form a first dielectric layer 204, which conformally covers the bottom and sidewalls of the first trench 2031, the bottom and sidewalls of the second trench 2032, and the surface of the insulating layer 202 away from the semiconductor layer 201.
[0071] like Figures 2c to 2i As shown, a shielding grid 205a is formed in the lower part of the first trench 2031, and a third protective layer 2063 is formed on the shielding grid 205a. A shielding grid lead 205b is formed in the second trench 2032, and a second protective layer 2062 is formed on the shielding grid lead 205b.
[0072] Specifically, such as Figure 2c As shown, a first conductor layer 205 is formed. The first conductor layer 205 fills the first trench 2031 and the second trench 2032, and covers the surface of the first dielectric layer 204 above the insulating layer 202.
[0073] Next, the first conductor layer 205 located above the insulating layer 202, a portion of the first conductor layer 205 in the first trench 2031, and a portion of the first conductor layer 205 in the second trench 2032 are removed to form a first cavity 2031a in the first trench 2031 and a second cavity 2032a in the second trench 2032. The tops of the remaining first conductor layers 205 in the first trench 2031 and the second trench 2032 are approximately flush with the oxide layer 2021, that is, the tops of the remaining first conductor layers 205 in the first trench 2031 and the second trench 2032 are higher than the surface of the semiconductor layer 201 and lower than the surface of the insulating layer 202.
[0074] like Figure 2d As shown, the first protective layer 2061 is formed.
[0075] In this step, for example, a deposition process is used to form a first protective layer 2061. The first protective layer 2061 is located on the surface of the first dielectric layer 204 above the insulating layer 202, fills the first cavity 2031a, and conformally covers the bottom and sidewalls of the second cavity 2032a.
[0076] In this embodiment, the width of the first groove 2031 is less than twice the thickness of the first protective layer 2061, so that the first cavity 2031a above the first groove 2031 is filled by the first protective layer 2061. The width of the second groove 2032 is greater than twice the thickness of the first protective layer 2061, so that the first protective layer 2061 formed in the second cavity 1032a above the second groove 2032 is insufficient to fill the second cavity 1032a, but conformally covers the bottom and sidewalls of the second cavity 2032a.
[0077] In one embodiment, the first protective layer 2061 is, for example, a nitride layer, specifically a silicon nitride (SiN) layer.
[0078] like Figure 2e As shown, the first protective layer 2061 above the insulating layer 202, as well as the first protective layer 2061 at the bottom and sidewalls of the second cavity 2032a, are removed, while the first protective layer 2061 filling the interior of the first cavity 2031a is retained.
[0079] In this step, for example, a wet etching process is used to remove the first protective layer 2061 above the insulating layer 202, as well as the first protective layer 2061 at the bottom and sidewalls of the second trench 2032. During the wet etching process, the etchant isotropically etches the first protective layer 2061. Since the thickness of the first protective layer 2061 in the vertical direction of the first trench 2031 is much greater than the thickness of the first protective layer 2061 above the insulating layer 202 and the first protective layer 2061 at the bottom and sidewalls of the second trench 2032, the first protective layer 2061 in the first trench 2031 is retained when the first protective layer 2061 above the insulating layer 202 and the first protective layer 2061 at the bottom and sidewalls of the second trench 2032 are removed.
[0080] like Figure 2f As shown, a second protective layer 2062 is formed on top of the first conductor layer 205 within the second trench 2032.
[0081] The second protective layer 2062 is, for example, an oxide layer. In this step, for example, a thermal oxidation process is used to form the second protective layer 2062 on top of the first conductor layer 205 in the second trench 2032. Since the first conductor layer 205 in the first trench 2031 is covered by the first protective layer 2061, only the top of the first conductor layer 205 in the second trench 2032 is oxidized to form the second protective layer 2062.
[0082] Furthermore, the thickness of the second protective layer 2062 is the same as the thickness of the first dielectric layer 204.
[0083] After the above steps are completed, the remaining first conductor layer 205 in the second trench 2032 forms a shielding gate lead 205b. Since part of the first conductor layer 205 is oxidized to form a second protective layer 2062, the top of the remaining shielding gate lead 205b is approximately flush with the surface of the semiconductor layer 201.
[0084] like Figure 2g As shown, the first protective layer 2061 in the first trench 2031 is removed.
[0085] In this step, for example, a wet etching process is used to etch the first protective layer 2061 within the first trench 2031 to selectively remove the first protective layer 2061 within the first trench 2031. By utilizing different etching selectivity ratios for the first protective layer 2061 (nitride layer), the first dielectric layer 204 (oxide layer), and the second protective layer 2062 (oxide layer) in the above steps, only the first protective layer 2061 within the first trench 2031 is removed, while the first dielectric layer 204 (oxide layer) and the second protective layer 2062 (oxide layer) in the second trench 2032 are retained.
[0086] like Figure 2h As shown, a portion of the first conductor layer 205 in the first trench 2031 is removed.
[0087] In this step, the second protective layer 2062 is used as the etched protective layer to remove a portion of the first conductor layer 205 in the first trench 2031, leaving a portion of the first conductor layer 205 in the first trench 2031 intact. The shielding gate lead 205b in the second trench 2032 is unaffected by the protection of the second protective layer 2062.
[0088] like Figure 2i As shown, a third protective layer 2063 is formed on top of the first conductor layer 205 in the first trench 2031.
[0089] The third protective layer 2063 is made of the same material as the first dielectric layer 204 and the second protective layer 2062, for example, an oxide layer. In this step, for example, a thermal oxidation process is used to form the third protective layer 2063 on top of the first conductor layer 205 within the first trench 2031. Furthermore, the thickness of the third protective layer 2063 is the same as the thickness of the first dielectric layer 204.
[0090] After the above steps are completed, the remaining first conductor layer 205 in the first trench 2031 forms a shielding gate 205a. This completes the steps of forming a shielding gate 205a in the lower part of the first trench 2031, forming a third protective layer 2063 on the shielding gate 205a, forming a shielding gate lead 205b in the second trench 2032, and forming a second protective layer 2062 on the shielding gate lead 205b.
[0091] Although not shown in the figure, it should be understood that the shielding grid 205a at the lower part of the first trench 2031 is electrically connected to the shielding grid lead 205b in the second trench 2032.
[0092] like Figure 2jAs shown, the first dielectric layer 204 is etched using the second protective layer 2062 and the third protective layer 2063 as the etched protective layers to form the shielding gate dielectric layer 204a and the shielding gate lead dielectric layer 204b, while the second protective layer 2062 and the third protective layer 2063 are removed.
[0093] In this step, for example, a wet etching process is used to etch the first dielectric layer 204 to remove the first dielectric layer 204 on the top of the first trench 2031 and the first dielectric layer 204 on the surface of the insulating layer 202. During the wet etching process, the etchant isotropically etches the first dielectric layer 204, the second protective layer 2062, and the third protective layer 2063. Since the first dielectric layer 204, the second protective layer 2062, and the third protective layer 2063 have the same thickness, they are removed simultaneously. Due to the protection of the second protective layer 2062 and the third protective layer 2063, no grooves are formed on the top of the first dielectric layer 204 on both sides of the shielding gate 205a and the shielding gate lead 205b. After etching is completed, the remaining first dielectric layer 204 in the first trench 2031 is located between the shielding gate 205a and the semiconductor layer 201, forming the shielding gate dielectric layer 204a of the device. The first dielectric layer 204 in the second trench 2032 is the shielding gate lead dielectric layer 204b of the device. Furthermore, the top of the shielding gate dielectric layer 204a is flush with the top of the shielding gate 205a, and the top of the shielding gate lead 205b is flush with the top of the shielding gate lead dielectric layer 204b.
[0094] In this application, the presence of a second protective layer 2062 and a third protective layer 2063 prevents grooves from forming on both sides of the shielding gate 205a and the shielding gate lead 205b. Furthermore, since the first dielectric layer 204, the second protective layer 2062, and the third protective layer 2063 are of the same material and thickness, they are simultaneously etched, ensuring the precision of the wet etching process and further preventing grooves from forming on both sides of the shielding gate 205a and the shielding gate lead 205b.
[0095] Next, the insulating layer 202 is removed to expose the surface of the semiconductor layer 201.
[0096] like Figures 2k to 2m As shown, a control gate 208a is formed on the upper part of the first trench 2031, and a second dielectric layer is formed to isolate the control gate 208a and the semiconductor layer 201.
[0097] Specifically, such as Figure 2kAs shown, a second dielectric layer 207 is formed, which covers the upper sidewall of the first trench 2031, the top of the shielding gate 205a, the top of the shielding gate lead 205b, and the surface of the semiconductor layer 201.
[0098] like Figure 2l As shown, a second conductor layer 208 is formed.
[0099] In this step, a second conductor layer 208 is formed using a deposition process. The second conductor layer 208 covers the surface of the second dielectric layer 207 above the semiconductor layer 201, the surface of the second dielectric layer 207 above the shielding gate lead 205b, and fills the upper part of the first trench 2031.
[0100] like Figure 2m As shown, a control gate 208a is formed.
[0101] In this step, the second conductor layer 208 above the semiconductor layer 201 and the second conductor layer 208 above the shielding gate lead 205b are removed, leaving the second conductor layer 208 in the first trench 2031. The remaining second conductor layer 208 fills the upper part of the first trench 2031 and is isolated from the semiconductor layer 201 via the second dielectric layer 207. The second conductor layer 208 on the upper part of the first trench 2031 constitutes the control gate 208a of the device.
[0102] Although not shown in the figure, it should be understood that the step of forming a source region in the semiconductor layer 201 is also included, the source region being adjacent to the first trench 2031.
[0103] like Figure 2n As shown, an interlayer dielectric layer 209 is formed.
[0104] In this step, for example, a deposition process is used to form an interlayer dielectric layer 209. The interlayer dielectric layer 209 covers the surface of the second dielectric layer 207 above the semiconductor layer 201, the surface of the control gate 208a, and the surface of the second dielectric layer 207 above the shield gate lead 205b.
[0105] like Figure 2o As shown, a first contact hole 210a, a second contact hole 210b, and a third contact hole 210c are formed that penetrate the interlayer dielectric layer 209.
[0106] In this step, for example, photolithography and etching processes are used to form a first contact hole 210a, a second contact hole 210b, and a third contact hole 210c that penetrate the interlayer dielectric layer 209. The first contact hole 210a penetrates the interlayer dielectric layer 209 to reach the control gate 208a; the second contact hole 210b penetrates the interlayer dielectric layer 209 and the second dielectric layer 207 to reach the source region; and the third contact hole 210c penetrates the interlayer dielectric layer 209 and the second dielectric layer 207 to reach the shielding gate lead 205b.
[0107] like Figure 2p As shown, a third conductor layer is formed to fill the first contact hole 210a, the second contact hole 210b and the third contact hole 210c, so as to form the first contact structure 211a, the second contact structure 211b and the third contact structure 211c respectively.
[0108] like Figure 2q As shown, a fourth conductive layer is formed on the surface of the interlayer dielectric layer 209, the first contact structure 211a, the second contact structure 211b, and the third contact structure 211c, and the fourth conductive layer is patterned using photolithography and etching processes to form an interconnect layer 212.
[0109] Figure 3 A schematic diagram showing the distribution of the device region and the shielding gate lead region according to an embodiment of this application is provided. A first trench 2031 is distributed in the device region Z01, and a second trench 2032 is distributed in the shielding gate lead region Z02. The shielding gate lead region Z02 occupies a very small area, and the increase in the size of the second trench 2032 does not affect the overall device density.
[0110] The unexpected technical effect of this application is:
[0111] In this embodiment, before forming the shielding gate dielectric layer and the shielding gate lead dielectric layer, protective layers are formed on the top of the shielding gate and the top of the shielding gate lead, respectively. During the etching process of the first dielectric layer to form the shielding gate dielectric layer and the shielding gate lead dielectric layer, the etchant isotropically etches the first dielectric layer, the protective layer on the top of the shielding gate, and the protective layer on the top of the shielding gate lead, to prevent the formation of depressions on the top of the shielding gate dielectric layer and the shielding gate lead dielectric layer. This further prevents the gate conductor from filling the depressions during the subsequent formation of the control gate, thus preventing the formation of protrusions on both sides of the shielding gate and both sides of the shielding gate lead, thereby solving the problem of device leakage.
[0112] In a preferred embodiment, the third protective layer on top of the shielding gate, the second protective layer on top of the shielding gate lead, and the first dielectric layer are all made of the same material and have the same thickness. The first dielectric layer, the second protective layer, and the third protective layer are etched simultaneously, ensuring the precision of wet etching and further preventing grooves from forming on both sides of the shielding gate and the shielding gate lead.
[0113] In a preferred embodiment, by setting a first trench and a second trench with different widths, and forming a first protective layer in the first trench and the second trench, the top of the first trench is filled with the first protective layer, while the sidewalls and bottom of the second trench are conformally covered by the first protective layer. By utilizing the width difference between the first trench and the second trench, as well as the conformal coverage characteristic of the first protective layer, the first protective layer can be selectively formed in the first trench using only a wet etching process, avoiding the use of photolithography.
[0114] In a preferred embodiment, the width of the first trench is less than twice the thickness of the first protective layer, and the width of the second trench is greater than twice the thickness of the first protective layer, so that the first trench is filled by the first protective layer, while the second protective layer retains the conformal coverage feature of the first protective layer.
[0115] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.
Claims
1. A method for fabricating a semiconductor device, comprising: An insulating layer is formed on a semiconductor layer, and a first trench and a second trench are formed in the semiconductor layer, wherein the width of the second trench is greater than the width of the first trench. A first dielectric layer is formed at the bottom and sidewalls of the first trench, the bottom and sidewalls of the second trench, and the surface of the insulating layer away from the semiconductor layer. A shielding grid is formed at the bottom of the first trench, and a third protective layer is formed on the shielding grid. A shielding grid lead is formed in the second trench, and a second protective layer is formed on the shielding grid lead. The first dielectric layer is etched with the second and third protective layers as protective layers to form the shielding gate dielectric layer and the shielding gate lead dielectric layer, while the second and third protective layers are removed. A control gate is formed on the upper part of the first trench, and a second dielectric layer is formed to isolate the control gate and the semiconductor layer; and A source region is formed adjacent to the first trench.
2. The method according to claim 1, wherein, The method of forming a shielding grid at the lower part of the first trench and forming a third protective layer on the shielding grid, forming shielding grid leads in the second trench, and forming a second protective layer on the shielding grid leads includes: A first conductor layer is formed in a first trench and a second trench. The top of the first conductor layer in the first trench and the second trench is higher than the surface of the semiconductor layer and lower than the surface of the insulating layer, so as to form a first cavity in the first trench and a second cavity in the second trench. A first protective layer is formed in the first cavity within the first trench; A second protective layer is formed on top of the first conductor layer in the second trench, and the remaining first conductor layer in the second trench forms a shielding grid lead; Selectively remove the first protective layer in the first trench; Using the second protective layer as the etched protective layer, a portion of the first conductor layer in the first trench is removed, and a third protective layer is formed on top of the portion of the first conductor layer in the first trench. The remaining first conductor layer in the first trench forms a shielding gate.
3. The method according to claim 2, wherein, The method for forming a first protective layer in a first cavity within a first trench includes: A first protective layer is formed, located on the surface of a first dielectric layer above an insulating layer, filling the first cavity, and conformally covering the bottom and sidewalls of the second cavity; and Remove the first protective layer above the insulation layer, as well as the first protective layer at the bottom and sidewalls of the second cavity, while retaining the first protective layer filling the interior of the first cavity.
4. The method according to claim 3, wherein, The width of the first trench is less than twice the thickness of the first protective layer, and the width of the second trench is greater than twice the thickness of the first protective layer.
5. The method according to claim 3, wherein, The first protective layer is a nitrided layer.
6. The method according to claim 5, wherein, The first protective layer above the insulating layer, as well as the first protective layer on the bottom and sidewalls of the second cavity, are removed by wet etching. During the etching process, the etchant isotropically etches the first protective layer.
7. The method according to claim 1, wherein, During the formation of the shielding gate dielectric layer and the shielding gate lead dielectric layer, a portion of the first dielectric layer is removed by wet etching. During the wet etching process, the etchant isotropically etches the first dielectric layer, the second protective layer, and the third protective layer.
8. The method according to claim 7, wherein, The first protective layer, the second protective layer, and the first dielectric layer are made of the same material, and the first protective layer, the second protective layer, and the first dielectric layer are of the same thickness.
9. The method according to claim 1, wherein, The top of the formed shielding grid dielectric layer is flush with the top of the shielding grid, and the top of the formed shielding grid lead dielectric layer is flush with the top of the shielding grid lead.
10. A semiconductor device formed using the preparation method according to any one of claims 1 to 9, wherein, The top of the shielding gate dielectric layer of the semiconductor device is flush with the top of the shielding gate, and the top of the shielding gate lead dielectric layer is flush with the top of the shielding gate lead.