Preparation method of metal silicide barrier layer and semiconductor device

Abstract

The invention discloses a preparation method of a metal silicide barrier layer and a semiconductor device. The preparation method comprises the steps that a semiconductor device structure is prepared, the semiconductor device structure comprises a substrate, a gate structure located above the substrate, an oxide layer and a silicon nitride layer, the oxide layer covers the surface of the substrate and the surface of the gate structure, the oxide layer is processed through a density enhancement technology, and the silicon nitride layer is located on the side wall of the gate structure and covers the oxide layer; oxidizing the silicon nitride layer to oxidize a part of the silicon nitride layer into a silicon oxide layer; and synchronously removing the silicon oxide layer and the oxide layer located above the substrate and at the top of the gate structure through a wet etching process to obtain a metal silicide barrier layer, the metal silicide barrier layer comprising an oxide layer and a silicon nitride layer located on the side wall of the gate structure. According to the scheme of the embodiment of the invention, the metal silicide barrier layer with good morphology can be formed, so that the semiconductor device structure is prevented from being further damaged and the metal silicide is prevented from transversely diffusing to a channel.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor fabrication technology. More specifically, this disclosure relates to a method for fabricating a metal silicide barrier layer and a semiconductor device. Background Technology

[0002] In the metal silicide fabrication process of integrated circuits, metal silicides need to be formed in most active regions. However, some active regions cannot form metal silicides, such as high-resistivity polysilicon regions and isolated active regions. To ensure the accuracy of the metal silicide formation area and guarantee the stability of semiconductor devices, a silicide barrier layer (SAB) is usually formed in a predetermined area before metal silicide fabrication. This layer protects the sensitive areas of the semiconductor device during subsequent etching processes and provides a foundation for metal silicide formation.

[0003] In existing SAB fabrication processes, a combination of dry and wet etching is typically used to remove portions of the SAB, exposing the substrate region where metal silicides will be formed and the polysilicon gate. However, during the execution of existing processes, over-etching at the top and bottom of the SAB often occurs, resulting in recessed morphologies at the top and bottom of the SAB. This not only affects the accuracy of the metal silicide formation region but can also lead to semiconductor device failure.

[0004] In view of this, there is an urgent need to provide a method for fabricating metal silicide barrier layers in order to solve the problem of excessive etching at the top and bottom of SAB, improve the etching morphology of metal silicide barrier layers, and ensure the reliability of semiconductor devices. Summary of the Invention

[0005] In order to at least address one or more of the technical problems mentioned above, this disclosure proposes a method for preparing metal silicide barrier layers in several aspects.

[0006] In a first aspect, this disclosure provides a method for fabricating a metal silicide barrier layer, comprising: fabricating a semiconductor device structure, the semiconductor device structure comprising: a substrate, a gate structure located above the substrate, an oxide layer, and a silicon nitride layer, wherein the oxide layer covers the surfaces of the substrate and the gate structure, the oxide layer is subjected to a density enhancement process, and the silicon nitride layer is located on the sidewall of the gate structure and covers the oxide layer; oxidizing the silicon nitride layer to oxidize a portion of the silicon nitride layer to a silicon oxide layer; and simultaneously removing the silicon oxide layer and the oxide layer located above the substrate and on top of the gate structure by a wet etching process to obtain a metal silicide barrier layer, the metal silicide barrier layer comprising: an oxide layer and a silicon nitride layer located on the sidewall of the gate structure.

[0007] In some embodiments, the density enhancement process includes a high-density plasma process, wherein fabricating the semiconductor device structure includes: fabricating a gate structure on a substrate; depositing and growing an oxide layer on the surfaces of the substrate and the gate structure; increasing the density of the oxide layer by a high-density plasma process; depositing and growing a silicon nitride layer on the oxide layer; and removing the silicon nitride layer located above the substrate and on top of the gate structure by a dry etching process.

[0008] In some embodiments, the oxidation treatment of the silicon nitride layer includes: oxidizing the silicon nitride layer by a high-density plasma process.

[0009] In some embodiments, the fabrication method further includes, prior to the simultaneous removal of the silicon oxide layer and the oxide layer located above the substrate and on top of the gate structure via a wet etching process, introducing ions into the oxide layer in a direction perpendicular to the substrate to increase the etching rate of the oxide layer located above the substrate.

[0010] In some embodiments, increasing the density of the oxide layer by high-density plasma processing includes subjecting the oxide layer to high-density plasma treatment within a temperature range of 350°C to 550°C, a discharge power range of 6000W to 12000W, and a pressure range of 3mtorr to 10mtorr.

[0011] In some embodiments, the oxidation of the silicon nitride layer by high-density plasma process includes: performing high-density plasma oxidation treatment on the silicon nitride layer using oxygen-containing gas as the reaction medium in a temperature range of 350°C-550°C, a discharge power range of 10000W-18000W, and a pressure range of 3mtorr-20mtorr.

[0012] In some embodiments, the oxide thickness of the silicon nitride layer ranges from 5 nm to 15 nm, and the thickness of the silicon oxide layer ranges from 5 nm to 15 nm.

[0013] In some embodiments, introducing ions into the oxide layer in a direction perpendicular to the substrate includes introducing hydrogen ions into the oxide layer in a direction perpendicular to the substrate using an inductively coupled plasma process or a high-density plasma process.

[0014] In some embodiments, after increasing the density of the oxide layer through high-density plasma processing, the preparation method further includes: repeatedly and alternately performing the step of depositing and growing the oxide layer and the step of increasing the density of the oxide layer through high-density plasma processing until the thickness of the oxide layer reaches a preset value.

[0015] In a second aspect, this disclosure provides a semiconductor device comprising: a substrate, a gate structure located above the substrate, and a metal silicide barrier layer; wherein the metal silicide barrier layer covers the sidewalls of the gate structure, and the metal silicide barrier layer is formed by performing a preparation method as described in any one of the first aspects.

[0016] The unexpected technical effect of this invention is that, through the metal silicide barrier layer preparation method provided above, the embodiments disclosed herein improve the density of the oxide layer through a density enhancement process, reduce the wet etching rate of the oxide layer, and convert part of the silicon nitride layer into a silicon oxide layer through oxidation treatment. During wet etching, the etching rate of this part of the structure is higher than that of the unoxidized silicon nitride layer, thereby making the wet etching rate of the bottom and sidewalls of the gate structure uniform. That is, the wet etching rates of the oxide layer above the substrate and the silicon oxide layer on the sidewalls of the gate structure are similar, thus enabling simultaneous thinning during wet etching. Since the barrier layer material located on the sidewalls of the gate structure, above the substrate, and at the top of the gate structure is thinned simultaneously, after the silicon oxide layer on the sidewalls of the gate structure and the oxide layers located above the substrate and at the top of the gate structure are removed simultaneously by the wet etching process, over-etching will not occur at the top and bottom sidewalls of the gate structure. The resulting metal silicide barrier layer has a good morphology and will not produce a recessed morphology, thus ensuring the reliability of the semiconductor device. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein: Figure 1 A schematic diagram of a metal silicide barrier layer formed by an existing SAB fabrication process is shown. Figure 2 Another schematic diagram of a metal silicide barrier layer formed by an existing SAB fabrication process is shown; Figure 3 An exemplary flowchart illustrating a method for preparing a metal silicide barrier layer according to some embodiments of this disclosure is shown; Figure 4 A schematic flowchart of a method for preparing a metal silicide barrier layer according to some embodiments of this disclosure is shown; Figure 5 An exemplary flowchart illustrating a method for fabricating a semiconductor device structure according to some embodiments of this disclosure is shown; Figure 6 An exemplary flowchart illustrating a method for preparing a metal silicide barrier layer according to other embodiments of this disclosure is shown; Figure 7A schematic flowchart illustrating a method for preparing a metal silicide barrier layer according to other embodiments of this disclosure is shown. Detailed Implementation

[0018] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0019] It should be understood that the terms “comprising” and “including” used in this disclosure and claims indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0020] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0021] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0022] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0023] Exemplary application scenarios A silicide block layer (SAB) is a special structural layer used in semiconductor manufacturing to prevent the formation of metal silicides. Specifically, an SAB prevents the formation of metal silicides in specific areas, thereby maintaining the high resistance characteristics of these areas. For example, in the metal silicide fabrication process of integrated circuits, in addition to the active regions in most areas, there are some active regions where metal silicides cannot form, such as high-resistivity polysilicon regions and isolated active regions. These regions require the pre-formation of a silicide block layer for protection.

[0024] In existing SAB fabrication processes, a combination of dry and wet etching is typically used to etch SABs, removing portions to expose the substrate region where metal silicides need to be formed and the polysilicon gate. However, during the execution of existing processes, over-etching occurs at the top and bottom of the SAB, resulting in recessed morphologies.

[0025] Figure 1 This diagram illustrates a metal silicide barrier layer formed using existing SAB fabrication processes. Figure 2 Another schematic diagram of a metal silicide barrier layer formed by an existing SAB fabrication process is shown, such as... Figure 1 and Figure 2 As shown, existing SAB fabrication processes create a recessed region on top of the SAB, i.e., on top of the gate structure sidewall. Figure 1 and Figure 2 (as shown by the red dashed box in the image), this exposes the material inside the gate structure prematurely and may be further damaged in subsequent processes. For example... Figure 1 and Figure 2 As shown, a recessed region is also formed at the bottom of the SAB, that is, at the bottom of the gate structure sidewall. Figure 1 and Figure 2 (as shown in the purple dashed box in the image), which leads to an increase in the lateral width of the bottom opening between adjacent gate structures, causing the metal silicide to diffuse laterally into the channel during thermal processing, resulting in abnormal electrical testing of the semiconductor device.

[0026] Exemplary application scheme In view of this, the present disclosure provides a method for preparing a metal silicide barrier layer, which improves the density of the oxide layer through a density enhancement process and converts part of the silicon nitride layer into a silicon oxide layer through an oxidation process, thereby making the wet etching rate of the bottom and sidewalls of the gate structure uniform, so as to ensure that the two can be thinned synchronously during wet etching and reduce the risk of the appearance of recessed morphology.

[0027] Figure 3 An exemplary flowchart of a method 300 for preparing a metal silicide barrier layer according to some embodiments of this disclosure is shown, such as... Figure 3As shown, in step S301, a semiconductor device structure is prepared, which includes a substrate, a gate structure, an oxide layer, and a silicon nitride layer. In step S302, the silicon nitride layer is oxidized to partially oxidize it into a silicon oxide layer; In step S303, the silicon oxide layer and the oxide layer located above the substrate and on top of the gate structure are removed simultaneously by a wet etching process to obtain a metal silicide barrier layer.

[0028] In the semiconductor device structure shown in this embodiment, the gate structure is located above the substrate, the oxide layer covers the surface of the substrate and the gate structure, and the silicon nitride layer is located on the sidewall of the gate structure and covers the oxide layer. The oxide layer is treated with a density enhancement process, and the increase in the density of the oxide layer will lead to a decrease in the wet etching rate of the oxide.

[0029] Furthermore, in practical applications, the oxide layer may include a first oxide layer and a second oxide layer. The first oxide layer covers the substrate and is located between the substrate and the gate structure. The second oxide layer is also called a buffer oxide layer. Part of the buffer oxide layer covers the surface of the gate structure, while another part of the buffer oxide layer overlaps with the first oxide layer and covers the substrate.

[0030] In the fabrication process, the first oxide layer is formed using an atmospheric pressure furnace tube process. During fabrication, the silicon substrate is exposed to a high-temperature, oxygen-containing environment for a certain period, thereby growing a layer of silicon dioxide on the substrate surface that adheres well to the silicon substrate and has highly stable chemical and electrical insulation properties—the first oxide layer. Since the second oxide layer is fabricated without an exposed silicon substrate, it cannot be formed using an atmospheric pressure furnace tube process. Due to the different fabrication processes, the density of the second oxide layer is lower than that of the first oxide layer, and the wet etching rate of the second oxide layer is higher than that of the first oxide layer. During wet etching, the oxide layer on the top and sidewalls of the gate structure is prone to over-etching, leading to the formation of recessed morphologies. From the above fabrication process, it can be seen that in practical applications, the oxide layer material can be silicon dioxide; that is, both the first and second oxide layers can be made of silicon dioxide.

[0031] To address the aforementioned issues, this embodiment pre-processes the oxide layer with a density enhancement process during the fabrication of the semiconductor device structure. Specifically, the second oxide layer can be subjected to a density enhancement process to reduce its wet etching rate. Figure 4 A schematic flowchart illustrating the preparation method of the metal silicide barrier layer according to some embodiments of this disclosure is shown, such as... Figure 4As shown, in step a, the grown oxide layer can be subjected to a density enhancement process. In some embodiments, the density of the oxide layer can be increased by a high-density plasma process (HDP), such as high-density plasma chemical vapor deposition (HDP-CVD). This process achieves high-quality film deposition by generating high-energy and high-density plasma, and is particularly suitable for filling gaps with high aspect ratios. The high-density plasma provides high ion flux and energy, thereby significantly improving the density and quality of the film.

[0032] As an example, in some embodiments, when performing a density-enhancing process on the oxide layer, high-density plasma treatment can be carried out within a temperature range of 350℃-550℃, a discharge power range of 6000W-12000W, and a pressure range of 3mtorr-10mtorr. The aforementioned discharge power range refers to the discharge power of the RF source in the high-density plasma process equipment; the higher the discharge power, the higher the plasma density and temperature. It should be noted that this embodiment does not impose strict limitations on the gas used for high-density plasma treatment; argon or other gases can be used, and no further restrictions are imposed here.

[0033] After the aforementioned density enhancement process, the wet etching rate of the oxide layer at the top of the gate structure and above the substrate is uniformized, enabling simultaneous thinning. In existing SAB fabrication processes, the formation of top and bottom recesses is also due to the inability to simultaneously etch and thin the gate structure sidewalls with the top and bottom of the gate structure; in other words, the reaction rates of the structural layers at the gate sidewalls and the top and bottom of the gate structure with the wet etchant are inconsistent. Therefore, after uniformizing the wet etching rate of the oxide layer at the top of the gate structure and above the substrate through the density enhancement process, this embodiment also requires oxidation of the silicon nitride layer located on the gate structure sidewalls to oxidize a portion of the silicon nitride layer into a silicon oxide layer. This makes the wet etching rate of the structural layers at the gate structure sidewalls more consistent with the wet etching rate of the oxide layers at the top and bottom of the gate structure.

[0034] like Figure 4 As shown, after step a is completed, the oxide layer is prepared. Next, step b is performed to deposit and grow a silicon nitride layer on the surface of the oxide layer after the density enhancement process. Then, step c is performed to etch away the silicon nitride layer located above the substrate and on top of the gate structure, while retaining the silicon nitride layer at the sidewall positions of the gate structure, thereby preparing the semiconductor device structure in step S301. After the semiconductor device structure is prepared, step S302 is performed, the process of which is as follows: Figure 4 In step d, the exposed silicon nitride layer surface is oxidized into a silicon oxide layer through an oxidation process. Since the surface of the gate structure sidewall is sequentially covered with a second oxide layer and a silicon nitride layer, it exhibits an N / O structure. Figure 4 The blue dashed box in process c), where N represents nitride and O represents oxide, after the above oxidation treatment, an O / N / O structure can be formed at the sidewall position of the gate structure. Figure 4 (The blue dashed box in process d) indicates that the wet etching rate of the silicon oxide layer is higher than that of the silicon nitride layer and closer to that of the oxide layer.

[0035] In some embodiments, silicon nitride layers can be oxidized using a high-density plasma process. Furthermore, high-density plasma oxidation of the silicon nitride layer can be performed using oxygen-containing gas as the reaction medium within a temperature range of 350°C-550°C, a discharge power range of 10000W-18000W, and a pressure range of 3mtorr-20mtorr. The aforementioned discharge power range refers to the discharge power of the RF source in the high-density plasma process equipment; higher discharge power results in higher plasma density and temperature.

[0036] It should be noted that the oxidation treatment of silicon nitride layer can be carried out by using high-density plasma combined with oxygen-containing combination gas as an auxiliary gas, including combination gas of oxygen and argon, combination gas of nitrous oxide and argon, or other oxygen-containing combination gas. There are no excessive restrictions here.

[0037] The table below shows the wet etching rates of the oxide and silicon nitride layers before and after high-density plasma processing.

[0038]

[0039] In the table above, WER-before represents the wet etching rate of the structural layer before processing, and WER-after represents the wet etching rate of the structural layer after processing. The data were obtained experimentally using a 100:1 hydrofluoric acid solvent as the wet etching agent. It should be noted that the silicon nitride layer transforms into a silicon oxide layer after high-density plasma oxidation. Therefore, the WER-after row for the silicon nitride layer can essentially be understood as the wet etching rate of the silicon oxide layer, and the WER-before row for the silicon nitride layer essentially represents the wet etching rate of the silicon nitride layer.

[0040] According to the data in the table above, after the oxide layer is treated with high-density plasma and the silicon nitride layer is treated with high-density plasma oxidation, the wet etching rates of the oxide layer above the substrate, the oxide layer on the top of the gate structure, and the silicon oxide layer on the sidewall of the gate structure are similar. Thus, the three can be thinned simultaneously during wet etching, thereby effectively avoiding the occurrence of top and bottom recessed morphologies.

[0041] See Figure 3 and Figure 4 After step S302 is completed, step S303 can be executed, that is... Figure 4 In step e, a well-formed metal silicide barrier layer can be formed above the substrate and on the surface of the gate structure by wet etching. This barrier layer includes an oxide layer and a silicon nitride layer located on the sidewalls of the gate structure. In some embodiments, the metal silicide barrier layer may further include an oxide layer partially located above the substrate, which are located in active regions such as isolated active regions where metal silicides do not form. It is understood that the metal silicide barrier layer in this embodiment can be a composite structure layer formed of multiple materials.

[0042] It should be noted that, in some embodiments, to prevent voids and defects from forming between adjacent gate structures due to small spacing between them during subsequent thin film deposition, the structural layer on the sidewalls of the gate structure is etched before the deposition process to increase the spacing between adjacent gate structures. In this case, it is necessary to ensure that the structural layer on the sidewalls of the gate structure is a silicon nitride layer to avoid damage to the shallow trench isolation oxide caused by the etching process.

[0043] For the reasons mentioned above, during the oxidation treatment of the silicon nitride layer, only a portion of the silicon nitride layer is oxidized to form a silicon oxide layer, thus avoiding the complete oxidation of the silicon nitride layer. In some embodiments, the oxidation thickness of the silicon nitride layer can be controlled to be between 5 nm and 15 nm, meaning the thickness of the silicon oxide layer formed by the oxidation treatment is between 5 nm and 15 nm. As an example, this oxidation thickness range can be achieved by controlling the oxidation time.

[0044] In this embodiment, the high-density plasma process is performed on the oxide layer to reduce its wet etching rate, while the high-density plasma process is performed on the silicon nitride layer to increase its wet etching rate. Therefore, the oxide layer and the silicon nitride layer cannot be processed by the same high-density plasma process. In order to prevent the high-density plasma process on the oxide layer from increasing the density of the silicon nitride layer and further reducing its wet etching rate, the high-density plasma process is performed on the oxide layer after it is formed in this embodiment.

[0045] Based on this, some embodiments disclosed herein provide a method for fabricating a semiconductor device structure. Figure 5 An exemplary flowchart of a method 500 for fabricating a semiconductor device structure according to some embodiments of this disclosure is shown. It can be understood that the method for fabricating the semiconductor device structure is a specific implementation of the aforementioned step S301. Therefore, the foregoing combined with Figure 3 The described features can be applied similarly here.

[0046] like Figure 5 As shown, in step S501, a gate structure is fabricated on the substrate; In step S502, an oxide layer is deposited and grown on the surface of the substrate and the gate structure; In step S503, the density of the oxide layer is increased by high-density plasma processing. In step S504, a silicon nitride layer is deposited and grown on the oxide layer; In step S505, the silicon nitride layer located above the substrate and on top of the gate structure is removed by a dry etching process.

[0047] In this embodiment, the substrate can be made of silicon, and the gate structure includes a polysilicon gate. In some embodiments, a first oxide layer can be formed on the substrate first using an atmospheric pressure furnace tube process, and then step S501 is performed to form the gate structure. At this time, by performing step S502, a second oxide layer is formed above the exposed first oxide layer and on the surface of the gate structure. Since the first oxide layer and the second oxide layer can be made of the same material, such as silicon oxide, the first oxide layer and the second oxide layer can be regarded as the same structural layer, i.e., an oxide layer, the structure of which is as follows: Figure 4 The process shown in step a is as follows.

[0048] In this embodiment, it can be combined with Figure 4 To illustrate steps S503 to S505 above. Figure 5 Step S503 in the process is as follows Figure 4 As shown in step a, after the oxide layer is formed, its density can be enhanced by high-density plasma processing. Next, the following steps are performed: Figure 4 Step b, namely step S504 above, involves depositing and growing a silicon nitride layer on the oxide layer surface. Then, in... Figure 4 In process c, namely step S505 above, a portion of the silicon nitride layer is removed by a dry etching process, specifically including: removing the silicon nitride layer located above the substrate and on top of the gate structure, while retaining the silicon nitride layer on the sidewall of the gate structure.

[0049] As an example, when the density of the oxide layer is enhanced by high-density plasma processing, the oxide layer can be subjected to high-density plasma treatment within a temperature range of 350℃-550℃, a discharge power range of 6000W-12000W, and a pressure range of 3mtorr-10mtorr.

[0050] It should be noted that this embodiment does not impose strict restrictions on the gas used for high-density plasma processing; argon or other gases can be used, and no further restrictions are imposed here.

[0051] Furthermore, for some semiconductor devices with high oxide layer thickness requirements, in order to ensure the uniformity of oxide layer density after high-density plasma processing, steps S502 and S503 can be repeatedly and alternately executed until the oxide layer thickness reaches the preset value, and then step S504 is executed.

[0052] In other words, if a larger oxide layer is required, when fabricating the semiconductor device structure, an oxide layer with a thickness of 1 / 3 can be deposited and grown on the substrate and gate structure surface first. Then, the formed 1 / 3 thick oxide layer is subjected to a density enhancement process. Next, another 1 / 3 thick oxide layer is deposited and grown, and then a density enhancement process is performed again. Finally, the remaining 1 / 3 thick oxide layer is deposited and grown and subjected to a density enhancement process. This layered fabrication and cyclic processing method ensures the uniformity of the density of the final oxide layer.

[0053] It should be noted that the above description of the preparation method of the oxide layer is only an example provided in this embodiment. In actual applications, oxide layers of 1 / 4, 1 / 5 or other thickness ratios are deposited and grown each time to complete the layer preparation and cycle processing.

[0054] The method described in the previous embodiments can improve the density of the oxide layer through density enhancement process and convert part of the silicon nitride layer into silicon oxide layer through oxidation process, so as to make the wet etching rate of the bottom and sidewall of the gate structure uniform, so as to ensure that the two can be thinned at the same time during wet etching.

[0055] Furthermore, in order to shorten the overall fabrication time of the metal silicide barrier layer, some embodiments disclosed herein also provide a method for fabricating the metal silicide barrier layer. Figure 6 An exemplary flowchart of a method 600 for preparing a metal silicide barrier layer according to other embodiments of this disclosure is shown.

[0056] like Figure 6 As shown, in step S601, a semiconductor device structure is prepared, which includes a substrate, a gate structure, an oxide layer, and a silicon nitride layer. In step S602, the silicon nitride layer is oxidized to partially oxidize the silicon nitride layer into a silicon oxide layer; In step S603, ions are introduced into the oxide layer in a direction perpendicular to the substrate to increase the etching rate of the oxide layer located above the substrate. In step S604, the silicon oxide layer and the oxide layer located above the substrate and on top of the gate structure are removed simultaneously by a wet etching process to obtain a metal silicide barrier layer.

[0057] In this embodiment, the contents of steps S601 to S602 are the same as those of steps S301 to S302 in the previous embodiment, and will not be described again here.

[0058] During step S603, by introducing ions into the oxide layer in a direction perpendicular to the substrate, the reaction rate of the oxide layer at specific locations with the wet etchant can be altered, for example, the oxide layer located above the substrate and on top of the gate structure. Since the direction of ion introduction is fixed, the silicon oxide layer located on the sidewall of the gate structure is unaffected by the ions and maintains its wet etching rate.

[0059] As an example, during step S603, hydrogen ions can be introduced into the oxide layer in a direction perpendicular to the substrate using a hydrogen-containing gas through inductively coupled plasma (ICP) or high-density plasma (HDP) processes. For instance, hydrogen ions or hydroxide ions are formed using a hydrogen-containing gas and introduced into the oxide layer. ICP is a process that generates and maintains plasma using the principle of electromagnetic induction. Its basic principle relies on an RF power supply inputting energy into the gas through an inductor coil, thereby generating high-energy particles in the gas. Several parameters in the ICP process can affect the wet etching rate of the thin film, including ICP source power, RF bias power, etching gas ratio, and cavity pressure. By optimizing these parameters, the wet etching rate of the thin film can be controlled to the desired rate.

[0060] In some embodiments, the oxide layer may include a first oxide layer and a second oxide layer, wherein the preparation order and formation location of the first oxide layer and the second oxide layer have been described above. Figure 1 The embodiments described have been detailed in detail and will not be repeated here. Step S603 can improve the wet etching rate of the oxide layer, especially the wet etching rate of the first oxide layer, by introducing ions, that is, accelerate the etching of the oxide layer above the substrate.

[0061] In the metal silicide barrier layer fabrication process, the metal silicide barrier layer protects specific areas to prevent the formation of metal silicides in those areas, allowing metal silicides to form in the active areas not protected by the barrier layer. Therefore, during step S604 for wet etching, the etching stops above the substrate. In other words, wet etching needs to remove the oxide layer above a portion of the substrate to expose that portion for metal silicide formation. Thus, the etching rate of the oxide layer above the substrate significantly affects the overall fabrication time of the metal silicide barrier layer.

[0062] Based on the above factors, this embodiment introduces ions into the oxide layer in a direction perpendicular to the substrate to increase the etching rate of the oxide layer above the substrate, thereby shortening the time required for wet etching and thus shortening the overall time of the metal silicide barrier layer fabrication process.

[0063] For the purpose of facilitating understanding by those skilled in the art, Figure 7 A schematic flowchart illustrating the preparation method of the metal silicide barrier layer according to other embodiments of this disclosure is shown, such as... Figure 7 As shown, in step f, the grown oxide layer undergoes a density enhancement process, for example, using high-density plasma (HDP) to increase its density within a temperature range of 350°C-550°C, a discharge power range of 6000W-12000W, and a pressure range of 3mtorr-10mtorr. In step g, a silicon nitride layer is deposited and grown on the density-enhanced oxide layer. In step h, the silicon nitride layer located above the substrate and on top of the gate structure is removed using a dry etching process, leaving the remaining silicon nitride layer located at the sidewall position of the gate structure. In step i, the silicon nitride layer is oxidized to partially oxidize it into a silicon oxide layer, thereby forming an O / N / O structure at the sidewall position of the gate structure, where N represents nitride and O represents oxide. In step j, ions are introduced in a direction perpendicular to the substrate to increase the wet etching rate of the oxide layer above the substrate. For example, hydrogen ions can be introduced into the oxide layer in a direction perpendicular to the substrate using inductively coupled plasma (ICP) or high-density plasma (HDP) processes with hydrogen-containing gas. In step k, the oxide layer above the substrate, the silicon oxide layer located at the sidewall of the gate structure, and the oxide layer located on top of the gate structure are simultaneously thinned by a wet etching process, thereby forming a metal silicide barrier layer with a good morphology.

[0064] In summary, this disclosure provides a method for preparing a metal silicide barrier layer. It can improve the density of the oxide layer by using a density enhancement process, thereby reducing the wet etching rate of the oxide layer and facilitating the oxidation process to convert part of the silicon nitride layer into a silicon oxide layer. This increases the wet etching rate of the structural layer (i.e., the silicon oxide layer) on the sidewall of the gate structure to the same level as the oxide layer. As a result, the barrier layer material located on the sidewall of the gate structure, above the substrate, and at the top of the gate structure is thinned simultaneously, avoiding excessive etching at the top and bottom sidewalls of the gate structure to prevent the formation of recessed morphologies and effectively ensuring the reliability of the semiconductor device.

[0065] Furthermore, this disclosure also provides another method for preparing a metal silicide barrier layer, which increases the wet etching rate of the oxide layer above the substrate by introducing ions before wet etching, thereby effectively shortening the time of the entire metal silicide barrier layer preparation process and improving the preparation efficiency of the metal silicide barrier layer.

[0066] This disclosure also provides a semiconductor device comprising: a substrate, a gate structure located above the substrate, and a metal silicide barrier layer, wherein the metal silicide barrier layer covers the sidewalls of the gate structure, and the metal silicide barrier layer can be formed by performing the preparation method described in any of the preceding embodiments.

[0067] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

[0068] The collection and acquisition of various data disclosed herein comply with relevant laws and regulations and are authorized by the data providers. Any organization or individual that needs to obtain external data shall obtain authorization in accordance with the law and ensure data security. It is prohibited to illegally collect, use, process, or transmit unauthorized or unprotected data, or to illegally buy, sell, provide, or disclose unauthorized or unprotected data.

Claims

1. A method for preparing a metal silicide barrier layer, characterized in that, include: A semiconductor device structure is fabricated, the semiconductor device structure comprising: a substrate, a gate structure located above the substrate, an oxide layer, and a silicon nitride layer, wherein the oxide layer covers the surfaces of the substrate and the gate structure, the oxide layer is treated with a density enhancement process, and the silicon nitride layer is located on the sidewall of the gate structure and covers the oxide layer; Oxidation treatment of the silicon nitride layer to oxidize a portion of the silicon nitride layer into a silicon oxide layer; and The silicon oxide layer and the oxide layer located above the substrate and on top of the gate structure are simultaneously removed by a wet etching process to obtain a metal silicide barrier layer, which includes an oxide layer and a silicon nitride layer located on the sidewall of the gate structure.

2. The preparation method according to claim 1, characterized in that, The density enhancement process includes a high-density plasma process, wherein the fabrication of the semiconductor device structure includes: Fabricate a gate structure on a substrate; An oxide layer is deposited and grown on the surfaces of the substrate and the gate structure; The density of the oxide layer is increased by high-density plasma processing. A silicon nitride layer is deposited and grown on the oxide layer; and The silicon nitride layer located above the substrate and on top of the gate structure is removed by a dry etching process.

3. The preparation method according to claim 1 or 2, characterized in that, The oxidation treatment of the silicon nitride layer includes: The silicon nitride layer is oxidized using a high-density plasma process.

4. The preparation method according to claim 1, characterized in that, The fabrication method further includes, prior to the simultaneous removal of the silicon oxide layer and the oxide layer located above the substrate and on top of the gate structure via a wet etching process: Ions are introduced into the oxide layer in a direction perpendicular to the substrate to increase the etching rate of the oxide layer located above the substrate.

5. The preparation method according to claim 2, characterized in that, The high-density plasma process used to increase the density of the oxide layer includes: The oxide layer is subjected to high-density plasma treatment within a temperature range of 350℃-550℃, a discharge power range of 6000W-12000W, and a pressure range of 3mtorr-10mtorr.

6. The preparation method according to claim 3, characterized in that, The oxidation of the silicon nitride layer via high-density plasma process includes: The silicon nitride layer is subjected to high-density plasma oxidation treatment using oxygen-containing gas as the reaction medium within a temperature range of 350℃-550℃, a discharge power range of 10000W-18000W, and a pressure range of 3mtorr-20mtorr.

7. The preparation method according to claim 1, characterized in that, The silicon nitride layer has an oxidation thickness ranging from 5 nm to 15 nm, and the silicon oxide layer has a thickness ranging from 5 nm to 15 nm.

8. The preparation method according to claim 4, characterized in that, Introducing ions into the oxide layer in a direction perpendicular to the substrate includes: Hydrogen ions are introduced into the oxide layer using hydrogen-containing gas in a direction perpendicular to the substrate through inductively coupled plasma or high-density plasma processes.

9. The preparation method according to claim 2, characterized in that, After increasing the density of the oxide layer through a high-density plasma process, the preparation method further includes: The steps of depositing and growing an oxide layer and increasing the density of the oxide layer by high-density plasma processing are repeated alternately until the thickness of the oxide layer reaches a preset value.

10. A semiconductor device, characterized in that, include: Substrate, gate structure located above the substrate, and metal silicide barrier layer; The metal silicide barrier layer covers the sidewall of the gate structure, and the metal silicide barrier layer is formed by performing the preparation method according to any one of claims 1-9.

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