Formation method of gate-all-around transistor

Abstract

A forming method of a surrounding gate transistor comprises the steps that a substrate is provided, the substrate comprises a plurality of adjacent device regions, each device region comprises an NMOS region and a PMOS region, a laminated structure is arranged on the top of the substrate of the device region in a protruding mode, a first opening is formed between the laminated structures of the NMOS regions and the PMOS regions, a second opening is formed between the laminated structures of the junctions of the NMOS regions and the PMOS regions, and the first opening is communicated with the second opening; a third opening is formed between the laminated structures at the junction of the device regions, the deposition thickness of the first dielectric layer is controlled, so that the first dielectric layer fills the first opening and a space is left at the second opening and the third opening, and the residual space of the second opening is filled and a space is left at the third opening through dielectric wall deposition; the first dielectric layer and the dielectric wall deposition layer are used as hard templates to form the groove in a self-alignment etching mode, the size of the mask type power supply rail is accurately controlled through the deposition thickness of the first dielectric layer and the dielectric wall, and the size uniformity of the dielectric wall and the mask type power supply rail is improved.

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