Semiconductor structure

Abstract

The invention relates to a semiconductor structure which is provided with a first device region, a second device region, a diode region, an NLDMOS region and a PLDMOS region, the NLDMOS region and the PLDMOS region are located between the diode region and the first device region, the diode region is located between the second device region and the NLDMOS region and between the second device region and the PLDMOS region, a CMOS device is formed in the first device region, a high-voltage device is formed in the second device region, and the high-voltage device is formed in the second device region. A diode cathode is formed in the diode region, is electrically connected with an NLDMOS drain electrode of the NLDMOS region, and is electrically connected with a PLDMOS source electrode of the PLDMOS region; a diode anode; the semiconductor structure further comprises a conductive structure, the bottom of the conductive structure penetrates through the insulating buried layer so as to be electrically connected with the N well, and the top of the conductive structure is electrically connected with the anode of the diode. And an insulating portion surrounding a side surface of the conductive structure. According to the invention, high breakdown voltage can be obtained.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure. Background Technology

[0002] With the widespread application of VLSI in various fields, the requirements for high-voltage, high-power semiconductor devices are becoming increasingly stringent. Silicon carbide (SiC) devices, due to their numerous advantages over silicon-based devices, are gradually replacing silicon-based devices in various application scenarios. The widespread application of SiC devices has also driven the development of gate driver chips. Traditional isolation methods for driving SiC devices cannot achieve monolithic integration, facing issues of size, cost, and reliability. Therefore, monolithically integrated gate driver chips are mostly implemented based on bulk silicon high-voltage BCD (Bipolar-CMOS-DMOS) technology. However, the junction isolation between the substrate and active layer of bulk silicon devices, along with the low substrate doping concentration, results in poor negative transient voltage tolerance, making them unsuitable as gate drivers for SiC MOSFETs. Compared to bulk silicon structures, silicon-on-insulator (SOI) structures employ dielectric isolation, which completely isolates the electrical connection between the active layer and the substrate. This gives SOI devices advantages in terms of latch-up resistance, crosstalk resistance, and integration density. Its dielectric isolation characteristics also give it stronger negative transient voltage tolerance, so SOI-based high-voltage gate driver chips can drive silicon carbide devices.

[0003] The industry demands silicon-on-insulator integrated high-voltage devices with higher breakdown voltages. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure with high breakdown voltage.

[0005] A semiconductor structure includes a bottom semiconductor layer, an insulating buried layer, and a top semiconductor layer stacked sequentially. The bottom semiconductor layer includes a P-type substrate and an N-well. The semiconductor structure has a first device region, a second device region, a diode region, an NLDMOS region, and a PLDMOS region. The NLDMOS region and the PLDMOS region are located between the diode region and the first device region. The diode region is located between the second device region and the NLDMOS region and the PLDMOS region. A CMOS device is formed in the first device region, and a high-voltage device with a breakdown voltage greater than that of the CMOS device is formed in the second device region. The diode region includes: a diode cathode electrically connected to the drain of the NLDMOS region and electrically connected to the source of the PLDMOS region; and a diode anode. The semiconductor structure further includes: a conductive structure, the bottom of which penetrates the insulating buried layer and is electrically connected to the N-well; and the top of which is electrically connected to the diode anode; and an insulating portion surrounding the side of the conductive structure. The conductive structure and the insulating portion are located between the second device region and the NLDMOS region and the PLDMOS region.

[0006] In the above semiconductor structure, when a positive voltage is applied to the diode cathode, the diode, the bottom semiconductor layer, and the insulating buried layer all participate in the breakdown voltage, and the mutual depletion of the P-type substrate and the N-well further enhances the breakdown voltage, thus achieving a higher breakdown voltage.

[0007] In one embodiment, the NLDMOS in the NLDMOS region enables the voltage level to shift up between the CMOS device and the high-voltage device, and the PLDMOS enables the voltage level to shift down between the CMOS device and the high-voltage device.

[0008] In one embodiment, the NLDMOS source of the NLDMOS region and the PLDMOS drain of the PLDMOS region are electrically connected to the electrodes of the CMOS device, and the NLDMOS drain and the PLDMOS source are electrically connected to the electrodes of the high-voltage device.

[0009] In one embodiment, the diode region surrounds the second device region, and the semiconductor structure further has a bootstrap diode located outside the diode region, the bootstrap diode being located between the diode region and the first device region, the cathode of the bootstrap diode being electrically connected to the cathode of the diode, and the anode of the bootstrap diode being electrically connected to the electrode of the CMOS device.

[0010] In one embodiment, the semiconductor structure further includes a field oxide layer on the top semiconductor layer, and the bootstrap diode further includes a polysilicon structure on the field oxide layer, the polysilicon structure being electrically connected to the anode of the bootstrap diode.

[0011] In one embodiment, the semiconductor structure is a silicon-on-insulator structure, and the semiconductor structure further has at least two isolation trenches located on the side of the insulating portion away from the second device region, each isolation trench being filled with an insulating material extending to the bottom of the insulating buried layer, and adjacent isolation trenches being separated by a portion of silicon material in the top semiconductor layer.

[0012] In one embodiment, a first diode is formed in the diode region on the side of the conductive structure away from the first device region.

[0013] In one embodiment, a first diode is formed in the diode region on the side of the conductive structure away from the first device region, and a second diode is formed between the conductive structure and the NLDMOS region and the PLDMOS region.

[0014] In one embodiment, the conductive structure comprises a metal or alloy.

[0015] In one embodiment, the conductive structure comprises N-type doped polycrystalline silicon.

[0016] In one embodiment, the bottom semiconductor layer further includes an N-type region, the doping concentration of which is greater than that of the N-well, and the bottom of the conductive structure is in direct contact with the N-type region.

[0017] In one embodiment, the buried insulating layer is a buried oxide layer with a thickness of 3.5 micrometers to 4.5 micrometers.

[0018] In one embodiment, the number of isolation slots is 4. Attached Figure Description

[0019] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0020] Figure 1 This is a top view of a semiconductor structure in one embodiment of this application.

[0021] Figure 2a For along Figure 1 A sectional view of line A-A' in the middle. Figure 2b For along Figure 1 The sectional view of line B-B' in the middle, Figure 2c For along Figure 1 A cross-sectional view of line C-C' in the diagram.

[0022] Figure 3 This is a partial enlarged view of the structure near the isolation groove 146 in one embodiment of this application.

[0023] Figure 4 This is a schematic diagram of the semiconductor structure in one embodiment of this application. Detailed Implementation

[0024] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0026] It should be understood that when a component or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers. The term "connection" in this specification, if referring to the transmission of electrical signals or data between connected circuits, modules, units, etc., should be understood as "electrical connection," "communication connection," etc. It should be understood that although the terms first, second, third, etc., may be used to describe various components, parts, areas, layers, and / or portions, these components, parts, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, area, layer, or portion from another component, part, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer or portion discussed below may be represented as a second element, component, region, layer or portion.

[0027] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be understood that “at least one” means one or more, and “a plurality” means two or more. “At least a portion of an element” means part or all of an element. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0030] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0031] An exemplary SOI-LDMOS device can only achieve a breakdown voltage in the 600V range. The reason why the breakdown voltage cannot be further increased is that the presence of the buried oxide layer blocks the electrical connection between the top silicon layer and the substrate, preventing the substrate from mutually depleting with the top silicon layer, and thus the substrate cannot participate in the longitudinal breakdown voltage. Furthermore, the top silicon layer is limited by the critical breakdown electric field of silicon. While increasing the thickness of the top silicon layer can improve the longitudinal breakdown voltage to some extent, excessively thick top silicon layers bring about process and cost problems, and the improvement is limited, making it difficult to achieve a longitudinal breakdown voltage in the 2000V range.

[0032] This application proposes a semiconductor structure, see [link to relevant documentation] Figure 1 The semiconductor structure comprises a first device region, a second device region, a diode region, an NLDMOS region, and a PLDMOS region. The NLDMOS and PLDMOS regions are located between the diode region and the first device region, while the diode region is located between the second device region and the NLDMOS and PLDMOS regions. The first device region is a low-voltage device region, where a CMOS device is formed. The second device region is a floating high-voltage region, where a high-voltage device is formed, with a breakdown voltage greater than that of the CMOS device. The NLDMOS region contains NLDMOS (N-channel lateral double-diffused metal-oxide-semiconductor field-effect transistor), and the PLDMOS region contains PLDMOS (P-channel lateral double-diffused metal-oxide-semiconductor field-effect transistor). Signal transmission between the high-voltage device and the CMOS device is accomplished through high-voltage LDMOS devices (i.e., the aforementioned NLDMOS and PLDMOS), where the NLDMOS performs a voltage level upshift and the PLDMOS performs a voltage level downshift. Figure 1 The first device region located on the left, right and top sides of the outer periphery of the semiconductor structure is omitted.

[0033] Figure 2a For along Figure 1 A sectional view of line A-A' in the middle. Figure 2b For along Figure 1 A sectional view along line B-B' in the diagram. See also... Figure 2a and Figure 2bThe semiconductor structure includes a bottom semiconductor layer 110, an insulating buried layer 120, and a top semiconductor layer 130 stacked sequentially. The bottom semiconductor layer 110 includes a P-type substrate 112 and an N-well 114. A diode cathode 158 and a diode anode 156 are formed in the diode region. The diode cathode 158 is electrically connected to the drain 152 of the NLDMOS and to the source 153 of the PLDMOS. The semiconductor structure also includes a conductive structure 142 and an insulating portion 144. The bottom of the conductive structure 142 penetrates the insulating buried layer 120 to be electrically connected to the N-well 114, and the top of the conductive structure 142 is electrically connected to the diode anode 156. The insulating portion 144 surrounds the side of the conductive structure 142. The conductive structure 142 and the insulating portion 144 are located between the second device region and the NLDMOS region and the PLDMOS region.

[0034] In the above semiconductor structure, when a positive voltage is applied to the diode cathode 158, the potential of the substrate is led out through the N-well 114. The diode, the bottom semiconductor layer 110 and the insulating buried layer 120 all participate in the longitudinal breakdown voltage, and the P-type substrate 112 and the N-well 114 deplete each other to further enhance the breakdown voltage, so a higher breakdown voltage can be obtained.

[0035] Reference Figure 2a and Figure 2b In one embodiment of this application, the NLDMOS source 154 and PLDMOS drain 155 are electrically connected to the electrode 151 of the CMOS device, and the NLDMOS drain 152 and PLDMOS source 153 are electrically connected to the electrode 159 of the high-voltage device.

[0036] When the voltage across the diode cathode 158 is less than the diode's reverse breakdown voltage (voltage threshold), the diode is cut off. When the voltage across the diode cathode 158 is greater than the diode's reverse breakdown voltage, this voltage passes through the reverse-biased PN junction diode and reaches the bottom semiconductor layer 110. The potential of the bottom semiconductor layer 110 is the voltage drop remaining after subtracting the diode's reverse breakdown voltage from the voltage across the diode cathode 158. The potential difference across the buried insulating layer 120 is the diode's reverse breakdown voltage, thus avoiding the problem of the buried insulating layer 120 losing its high withstand voltage advantage due to the uniform potential across its layers. The withstand voltage (breakdown voltage) of NLDMOS and PLDMOS is the withstand voltage of the bottom semiconductor layer 110 plus the withstand voltage of the diode's lateral PN junction, thereby enabling the buried insulating layer 120 to participate in the withstand voltage, and the withstand voltage value is equal to the withstand voltage of the diode's lateral PN junction. Different withstand voltage requirements of the device can be achieved by adjusting the thickness of the buried insulating layer 120 and the withstand voltage of the lateral PN junction.

[0037] In one embodiment of this application, the diode region surrounds the second device region, and the semiconductor structure further has a BSD (Bootstrap Diode) located outside the diode region, with the bootstrap diode situated between the diode region and the first device region. Figure 2c For along Figure 1 The cross-sectional view along line C-C' shows that the cathode 157b of the bootstrap diode is electrically connected to the cathode 158 of the diode, and the anode 157a of the bootstrap diode is electrically connected to the electrode 159 of the CMOS device.

[0038] In half-bridge or full-bridge topologies, the source / emitter voltage of high-side power devices (such as MOSFETs / IGBTs) fluctuates with switching action (e.g., from ground potential to bus voltage). In this case, a conventional fixed power supply cannot directly power the high-side driver of the half-bridge / full-bridge topology. A bootstrap circuit can be constructed using a bootstrap diode and a bootstrap capacitor. This bootstrap circuit dynamically generates a floating power supply (often called a "bootstrap power supply") to power the high-side driver. The bootstrap diode in this bootstrap circuit acts as a charger for the bootstrap capacitor. Specifically, when the low-side power device is turned on, the power supply (such as VCC) charges the bootstrap capacitor through the bootstrap diode, thereby increasing the voltage across the bootstrap capacitor. The bootstrap diode allows current to flow from the power supply to the bootstrap capacitor, ensuring that the capacitor stores sufficient charge. During high-side conduction, the bootstrap capacitor acts as a temporary power supply to power the high-side driver. The unidirectional conduction characteristic of the bootstrap diode ensures that the bootstrap capacitor voltage is not pulled down by the bus high voltage or the power supply. Therefore, for applications where the semiconductor structure of this application is used in high-side drivers of half-bridge / full-bridge topologies, the bootstrap diode integrated in the semiconductor structure can be used to form the aforementioned bootstrap circuit. Thus, it is not necessary to introduce an additional bootstrap diode in the external circuit, reducing the use of external devices and lowering the complexity of circuit design.

[0039] In one embodiment of this application, the semiconductor structure further includes a field oxide layer 148 located on the top semiconductor layer. The bootstrap diode also includes a polysilicon structure 137 located on the field oxide layer 148, the polysilicon structure 137 being electrically connected to the anode 157a of the bootstrap diode.

[0040] In one embodiment of this application, the semiconductor structure is a silicon-on-insulator (SOI) structure, with a bottom semiconductor layer 110 as a bottom silicon layer, an insulating buried layer 120 as a buried oxide layer, and a top semiconductor layer 130 as a top silicon layer. The semiconductor structure also has at least two isolation trenches 146 located on the side of the insulating portion away from the second device region. Each isolation trench 146 is filled with an insulating material, the bottom of which extends to the insulating buried layer 120. Adjacent isolation trenches 146 are separated by a portion of silicon material in the top semiconductor layer 130. In one embodiment of this application, the insulating material filled in each isolation trench 146 may be silicon dioxide. Figure 3 This is a partial enlarged view of the structure near the isolation trench 146 in one embodiment of this application. The isolation trench 146 and the silicon material are distributed alternately—that is, the structure has an isolation trench 146-silicon material-isolation trench 146-silicon material-isolation trench 146…—which ensures that the isolation trench 146 will not be prematurely broken down during the withstand voltage process of the insulating buried layer 120.

[0041] In one embodiment of this application, the number of isolation trenches 146 is four. In another embodiment of this application, the conductive structure 142 may be formed by etching through an isolation trench closest to the diode region, the width of which is greater than the width of the other isolation trenches 146, for example, the width of the other isolation trenches 146 is 1 micrometer while the width of this isolation trench is 3 micrometers.

[0042] exist Figure 2a , Figure 2b and Figure 2c In the illustrated embodiment, the diode is disposed on the side of the conductive structure 142 near the second device region, and the insulating portion 144 isolates the NLDMOS / PLDMOS from the diode. (Refer to...) Figure 4 In another embodiment of this application, the semiconductor structure includes a first diode located on the side of the conductive structure 142 closer to the second device region, and a second diode located on the side of the conductive structure 142 farther from the second device region. The semiconductor structure also includes an isolation structure 147 located between the second diode and the NLDMOS and PLDMOS, with the second diode and the NLDMOS and PLDMOS being insulated from each other by the isolation structure 147. The cathodes of the first diode and the second diode ( Figure 4 (Not shown in the image) are both connected to the drain of the NLDMOS and the source of the PLDMOS ( Figure 4 Electrical connection (not shown), the anodes of the first diode and the second diode ( Figure 4 (Not shown in the image) are all electrically connected to the conductive structure 142.

[0043] In one embodiment of this application, the conductive structure 142 is made of a metal or alloy, such as tungsten. In another embodiment of this application, the conductive structure 142 is made of polycrystalline silicon, such as N-type doped polycrystalline silicon.

[0044] In one embodiment of this application, an N-type region 116 can be formed in the N-type substrate near the bottom of the conductive structure 142. The bottom of the conductive structure 142 is in direct contact with the N-type region 116. The doping concentration of the N-type region 116 is greater than the doping concentration of the N-well 114 to reduce contact resistance. Figure 4 In the embodiment shown, the N-well 114 is located in the P-type substrate 112, and the N-type region 116 is located in the N-well 114.

[0045] exist Figure 1 and Figure 4 In the illustrated embodiment, the insulating portion 144 forms a wall-like structure to isolate the NLDMOS / PLDMOS from the diode. In other embodiments, the insulating portion 144 may also be a discrete structure, with each conductive structure 142 surrounded by an insulating portion 144, and adjacent insulating portions 144 being separated by a portion of the top semiconductor layer 130; correspondingly, the semiconductor structure also includes an isolation structure located between the diode and the NLDMOS / PLDMOS, with the diode and NLDMOS / PLDMOS being isolated from each other by the isolation structure.

[0046] Reference Figure 1 In one embodiment of this application, the semiconductor structure further includes a high-voltage junction termination located outside the conductive structure 142 and between the conductive structure 142 and the first device region. A BSD is disposed in the high-voltage junction termination region.

[0047] exist Figure 4 In the illustrated embodiment, the semiconductor structure includes a plurality of conductive structures 142 arranged in a row, each conductive structure 142 being electrically connected to the anode 156 of the unit diode. Figure 1 In the embodiment shown, the conductive structure 142 is a wall-like structure.

[0048] In one embodiment of this application, the semiconductor structure further includes an interlayer dielectric (ILD) layer 160 covering the top semiconductor layer 130. The interlayer dielectric layer 160 has a plurality of contact holes, including source contact holes, drain contact holes, gate contact holes, anode contact holes, cathode contact holes, and contact holes of the conductive structure 142, etc. Each contact hole is filled with a conductive material (e.g., tungsten metal), thereby forming electrodes such as diode cathode 158, diode anode 156, NLDMOS drain 152, PLDMOS source 153, NLDMOS source 154, PLDMOS drain 155, electrode 151, and electrode 159. The semiconductor structure also includes a metal interconnect layer disposed on the interlayer dielectric layer 160, wherein the metal interconnects in the metal interconnect layer electrically connect the corresponding electrodes.

[0049] In the semiconductor structure of this application, the thickness of the buried insulating layer 120 and the thickness of the top semiconductor layer 130 can be adjusted according to different voltage levels and different device current density requirements.

[0050] In one embodiment of this application, the breakdown voltage of both NLDMOS and PLDMOS can reach the breakdown voltage of the high-voltage device in the second device region, for example, 2000V.

[0051] by Figure 2aThe structure shown is used as an example to illustrate the working principle of the substrate and buried oxide layer jointly bearing the longitudinal withstand voltage in this device. When the device is reverse biased (positive voltage is applied to the drain 152 of the NLDMOS, and the gate 136 and source 154 of the NLDMOS are grounded), the PN junction diode is in a reverse biased state, and its reverse breakdown voltage reflects the withstand voltage value of the buried oxide layer in the SOI-LDMOS device. By adjusting the high voltage N-well and P-well of the PN junction diode, a reverse breakdown voltage of 350V-450V is achieved, reflecting that the buried oxide layer (i.e., the insulating buried layer 120) in the device bears the withstand voltage value of 350V-450V. Since an excessively thick buried oxide layer will lead to a decrease in thermal conductivity, causing a local increase in the lattice temperature of the device, it will cause degradation of the electrical parameters of the device. At the same time, a thick buried oxide layer will also bring problems in terms of process and cost. Therefore, in one embodiment of this application, the thickness of the buried oxide layer corresponding to the 350V-450V withstand voltage is taken as 3.5μm-4.5μm. The SOI-LDMOS device is separated from the PN junction diode by multiple isolation trenches 146. The isolation trenches 146 and the N-type region in the top semiconductor layer 130 are spaced apart to ensure that the isolation trenches 146 will not break down prematurely during the withstand voltage test of the buried oxide layer. Part of the drain voltage drops to the PN junction diode, and the remaining voltage is transferred to the N-well 114 of the substrate through the conductive structure 142. At this time, the PN junction formed by the P-type substrate 112 and the N-well 114 is reverse biased. As the applied bias voltage increases, the space charge region of the lightly doped P-type substrate 112 extends downward. By setting an appropriate substrate resistivity and N-well doping concentration, the breakdown voltage of the PN junction formed by the P-type substrate 112 and the N-well 114 can reach 1700V. In summary, because both the bottom semiconductor layer 110 and the buried oxide layer participate in the withstand voltage test, the vertical breakdown voltage of the SOI-LDMOS device can reach 2000V and above.

[0052] In one embodiment of this application, a P-type substrate 112 is selected as the semiconductor structure. An N-well 114 is formed in the substrate by ion implantation. The length of the N-well 114 should be 40% to 80% of the total device length. A 3.5 μm thick buried oxide layer is then bonded, and a 6 μm thick P-type epitaxial layer is grown on top of it as the top semiconductor layer 130. Four deep oxide trenches are formed by etching the P-type epitaxial layer. The three deep oxide trenches (i.e., isolation trenches 146) near the NLDMOS / PLDMOS are each 1 μm wide, and the deep oxide trench near the second device region is 3 μm wide. The deep oxide trenches near the second device region are etched and filled with conductive material to form a conductive structure 142. The potential of the N-well 114 is led to the device surface through the conductive structure 142 and connected to the diode anode 156. The high-voltage N-well region of the diode region is completed by the N-type drift region and N-well region processes used in forming SOI-LDMOS devices, and the P-body region of the diode region is completed by the P-body region processes used in forming SOI-LDMOS devices. Metal layer 1 connects conductive structure 142 to diode anode 156, and metal layer 2 connects NLDMOS drain 152 to diode cathode 158.

[0053] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of these terms do not necessarily refer to the same embodiment or example.

[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A semiconductor structure comprising a bottom semiconductor layer, an insulating buried layer, and a top semiconductor layer stacked sequentially, characterized in that, The bottom semiconductor layer includes a P-type substrate and an N-well. The semiconductor structure has a first device region, a second device region, a diode region, an NLDMOS region, and a PLDMOS region. The NLDMOS region and the PLDMOS region are located between the diode region and the first device region. The diode region is located between the second device region and the NLDMOS region and the PLDMOS region. A CMOS device is formed in the first device region. A high-voltage device with a breakdown voltage greater than that of the CMOS device is formed in the second device region. The diode region contains: The cathode of the diode is electrically connected to the drain of the NLDMOS in the NLDMOS region and electrically connected to the source of the PLDMOS in the PLDMOS region. Diode anode; The semiconductor structure also includes: A conductive structure, wherein the bottom of the conductive structure penetrates the insulating buried layer to be electrically connected to the N-well, and the top of the conductive structure is electrically connected to the anode of the diode; An insulating portion that surrounds the side surface of the conductive structure; The conductive structure and insulating portion are located between the second device region and the NLDMOS region and PLDMOS region.

2. The semiconductor structure according to claim 1, characterized in that, The NLDMOS source of the NLDMOS region and the PLDMOS drain of the PLDMOS region are electrically connected to the electrodes of the CMOS device, and the NLDMOS drain and the PLDMOS source are electrically connected to the electrodes of the high-voltage device.

3. The semiconductor structure according to claim 1, characterized in that, The diode region surrounds the second device region, and the semiconductor structure further has a bootstrap diode located outside the diode region. The bootstrap diode is located between the diode region and the first device region. The cathode of the bootstrap diode is electrically connected to the cathode of the diode, and the anode of the bootstrap diode is electrically connected to the electrode of the CMOS device.

4. The semiconductor structure according to claim 3, characterized in that, It also includes a field oxide layer located on the top semiconductor layer, and the bootstrap diode further includes a polysilicon structure located on the field oxide layer, the polysilicon structure being electrically connected to the anode of the bootstrap diode.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure is a silicon-on-insulator structure, and the semiconductor structure also has at least two isolation trenches located on the side of the insulating portion away from the second device region. Each isolation trench is filled with an insulating material extending to the bottom of the insulating buried layer, and adjacent isolation trenches are separated by a portion of silicon material in the top semiconductor layer.

6. The semiconductor structure according to claim 1, characterized in that, A first diode is formed in the diode region on the side of the conductive structure away from the first device region; or The diode region includes a first diode located on the side of the conductive structure away from the first device region, and a second diode located between the conductive structure and the NLDMOS and PLDMOS regions.

7. The semiconductor structure according to claim 1, characterized in that, The conductive structure comprises a metal or alloy, or the conductive structure comprises N-type doped polycrystalline silicon.

8. The semiconductor structure according to claim 1 or 7, characterized in that, The bottom semiconductor layer also includes an N-type region, the doping concentration of which is greater than that of the N-well, and the bottom of the conductive structure is in direct contact with the N-type region.

9. The semiconductor structure according to claim 5, characterized in that, The insulating buried layer is a buried oxide layer with a thickness of 3.5 micrometers to 4.5 micrometers.

10. The semiconductor structure according to claim 5, characterized in that, The number of isolation slots is 4.

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