Multi-layer POLY structure TOPCON solar cell and preparation method thereof

Abstract

The invention discloses a multi-layer POLY-structured TOPCON solar cell and a preparation method thereof, and relates to the technical field of solar cells, the multi-layer POLY-structured TOPCON solar cell comprises an N-type silicon wafer, and the front surface of the N-type silicon wafer is sequentially provided with an aluminum oxide layer, a silicon oxynitride laminated passivation film and an electrode; and the back surface is of a multi-layer laminated POLY structure and comprises a tunneling oxide layer and alternative polycrystalline silicon layers and barrier oxide layers, and a silicon oxynitride laminated passive film and an electrode are arranged on the outer side of the back surface. During preparation, after an N-type silicon wafer is subjected to texturing, boron diffusion and other treatments, the multi-layer laminated POLY structure is prepared by using LPCVD or PECVD, and then the electrode is prepared through subsequent treatments. Through the multi-layer laminated POLY structure, the surface concentration is improved and the cell conversion efficiency is improved while high open voltage is not lost, the average Eta reaches 27.292%, the process is matched with a mainstream route, and mass production is facilitated.

Description

Technical Field

[0001] This invention relates to the field of solar energy equipment technology, specifically to a multilayer POLY structure TOPCON solar cell and its preparation method. Background Technology

[0002] With the increasing global demand for clean energy, improving the utilization efficiency of solar energy, as a clean and renewable energy source, has become a research hotspot. TOPCON (Tunnel Oxide Passivated Contact) solar cells have attracted much attention due to their high conversion efficiency.

[0003] Currently, the back-side structure of conventional TOPCON solar cells has certain limitations in improving cell performance. For example, common back-side structures struggle to achieve efficient passivation while ensuring good carrier transport, making it difficult to further optimize key electrical parameters such as open-circuit voltage, short-circuit current density, and fill factor, thus limiting the improvement of overall cell conversion efficiency. Furthermore, existing fabrication processes are complex and costly, hindering large-scale industrial production. Summary of the Invention

[0004] The purpose of this invention is to provide a multilayer POLY structure TOPCON solar cell and its preparation method to solve existing problems.

[0005] The technical solution of the present invention to solve the above-mentioned technical problems is as follows:

[0006] A multilayer POLY structure TOPCON solar cell includes an N-type silicon wafer. The front side of the N-type silicon wafer is sequentially provided with an aluminum oxide layer, a silicon oxynitride (SON) stacked passivation film, and an electrode. The back side is provided with a multilayer POLY structure. The multilayer POLY structure, from the side closest to the N-type silicon wafer to the outside, sequentially includes a tunneling oxide layer, n alternating polycrystalline silicon layers, and a barrier oxide layer (n is a positive integer). The tunneling oxide layer has a thickness of 1-2 nm, each polycrystalline silicon layer has a thickness of 5-50 nm, each barrier oxide layer has a thickness of 0.5-2 nm, and the overall thickness of the multilayer POLY structure is 60-200 nm. A SON stacked passivation film and an electrode are also provided on the outer side of the multilayer POLY structure. When the multilayer POLY structure is fabricated using PECVD, each polycrystalline silicon layer is formed by annealing amorphous silicon, and the phosphorus doping concentration of each amorphous silicon layer increases sequentially from the inside to the outside during fabrication.

[0007] This invention also discloses a method for fabricating a multilayer POLY structure TOPCON solar cell, as detailed below:

[0008] Step 1: Select an N-type silicon wafer with a thickness of 100-150nm and perform double-sided texturing on the silicon wafer.

[0009] Step 2: Perform double-intercalation single-sided boron diffusion.

[0010] Step 3: Perform BSG removal and backside alkaline polishing.

[0011] Step 4: Fabricate a multilayer POLY structure on the back side of a silicon wafer using LPCVD or PECVD. If using LPCVD, deposit a tunneling oxide layer using an O2 source, then deposit the first polycrystalline silicon layer using SiH4, followed by depositing the first barrier oxide layer using an O2 source, and so on, depositing the nth barrier oxide layer and polycrystalline silicon layer. If using PECVD, use SiH4, N2O, H2, and PH4 as gas sources. After depositing the tunneling oxide layer, deposit n amorphous silicon layers and n barrier oxide layers sequentially, with the phosphorus doping concentration of each amorphous silicon layer increasing sequentially from the inside to the outside. The multilayer POLY structure, from the side closest to the silicon wafer to the outside, includes a tunneling oxide layer, n alternating polycrystalline or amorphous silicon layers, and a barrier oxide layer. The thickness of the tunneling oxide layer is 1-2 nm, the thickness of each polycrystalline or amorphous silicon layer is 5-50 nm, the thickness of each barrier oxide layer is 0.5-2 nm, and the overall structure thickness is 60-200 nm.

[0012] Step 5: If step 4 uses LPCVD, a phosphorus diffusion device is used with phosphorus oxychloride or phosphorus pentoxide as the gas source to complete the preparation of the back N region and to fabricate a 40-90nm BSG layer as a protective layer; if step 4 uses PECVD, an annealing device is used to perform phosphorus doping activation and conversion of amorphous silicon to polycrystalline silicon structure to complete the preparation of the back N region.

[0013] Step 6: Perform PSG and RCA removal cleaning.

[0014] Step 7: ALD single-insertion double-sided aluminum oxide plating, with the thickness controlled between 3-15nm.

[0015] Step 8: Deposit silicon oxynitride stacked passivation films on the front and back sides using PECVD.

[0016] Step 9: Prepare the electrode.

[0017] The present invention has the following beneficial effects:

[0018] 1. Improved battery conversion efficiency: Through the design of a multi-layered POLY structure, the average conversion efficiency (Eta) of the TOPCON battery with a 3-layer POLY structure actually prepared reached 27.292%, and the efficiency is expected to be further improved as the number of layers increases.

[0019] 2. Optimized key electrical parameters: The average open-circuit voltage (Uoc) of the battery reached 0.7377V, and the short-circuit current density (Jsc) reached 42.44mA / cm². 2The fill factor (FF) reaches 87.17%, which significantly improves FF while ensuring high opening voltage.

[0020] 3. Feasible for mass production: The process improvement of the preparation method only requires modification of the formula file, which is compatible with the mainstream TOPCON route. It does not require large-scale adjustment of production equipment and is easy to industrialize and mass produce. Attached Figure Description

[0021] Figure 1 This is a structural diagram of the TOPCON battery with a three-layer structure according to the present invention. Detailed Implementation

[0022] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0023] Example 1: LPCVD fabrication of a 3-layer POLY structure (basic parameters)

[0024] A 120nm thick N-type silicon wafer is selected, and after double-sided texturing, double-intercalation single-sided boron diffusion is performed to remove BSG and back side alkaline polishing.

[0025] LPCVD fabrication of the back side structure: 1.5nm tunneling oxide layer → 10nm first layer of polysilicon → 1nm first layer of barrier oxide layer → 15nm second layer of polysilicon → 1nm second layer of barrier oxide layer → 20nm third layer of polysilicon → 1nm third layer of barrier oxide layer (total thickness 69.5nm).

[0026] Phosphorus diffusion was used to prepare the back N region and a 60nm BSG protective layer. Subsequently, the electrode was prepared by PSG removal, RCA cleaning, 8nm alumina coating, and PECVD deposition of a silicon oxynitride passivation film.

[0027] Example 2: PECVD preparation of a 3-layer POLY structure (gradient phosphorus doping)

[0028] A 130nm thick N-type silicon wafer was selected and subjected to double-sided texturing, boron diffusion, BSG removal, and alkaline polishing.

[0029] PECVD fabrication of the back side structure: 1.2nm tunneling oxide layer → 12nm first layer of amorphous silicon (low phosphorus concentration) → 0.8nm first layer of barrier oxide layer → 18nm second layer of amorphous silicon (medium phosphorus concentration) → 0.8nm second layer of barrier oxide layer → 25nm third layer of amorphous silicon (high phosphorus concentration) → 0.8nm third layer of barrier oxide layer (total thickness 76.6nm).

[0030] Annealing process is used to convert amorphous silicon to polycrystalline silicon and activate it with phosphorus doping. Subsequent processes are the same as in Example 1, with an alumina thickness of 10 nm.

[0031] Example 3: LPCVD fabrication of a 2-layer POLY structure (thin design)

[0032] A 100nm thick N-type silicon wafer was selected, and the basic pretreatment was the same as before.

[0033] LPCVD fabrication of the back side structure: 1nm tunneling oxide layer → 20nm first layer of polysilicon → 0.5nm first layer of barrier oxide layer → 30nm second layer of polysilicon layer → 0.5nm second layer of barrier oxide layer (total thickness 52nm).

[0034] Phosphorus diffusion was used to prepare the back N region and a 40nm BSG protective layer, with an alumina thickness of 3nm. The remaining processes were the same as in Example 1.

[0035] Example 4: PECVD preparation of a 4-layer POLY structure (high concentration gradient)

[0036] A 150nm thick N-type silicon wafer was selected, and the basic pretreatment was the same as before.

[0037] PECVD fabrication of the back side structure: 2nm tunneling oxide layer → 8nm first layer of amorphous silicon (low phosphorus) → 2nm first layer of barrier oxide layer → 12nm second layer of amorphous silicon (medium-low phosphorus) → 2nm second layer of barrier oxide layer → 15nm third layer of amorphous silicon (medium-high phosphorus) → 2nm third layer of barrier oxide layer → 20nm fourth layer of amorphous silicon (high phosphorus) → 2nm fourth layer of barrier oxide layer (total thickness 85nm).

[0038] After annealing, the alumina thickness is 15 nm, and the remaining processes are the same as in Example 2.

[0039] Example 5: Preparation of a 3-layer POLY structure using a hybrid process (LPCVD+PECVD)

[0040] A 140nm thick N-type silicon wafer was selected, and the basic pretreatment was the same as before.

[0041] Backside structure fabrication: LPCVD deposition of 1.8nm tunneling oxide layer and 25nm first layer of polycrystalline silicon → PECVD deposition of 1.2nm first layer of barrier oxide layer, 20nm second layer of amorphous silicon, 1.2nm second layer of barrier oxide layer, 15nm third layer of amorphous silicon, and 1.2nm third layer of barrier oxide layer (total thickness 65.4nm).

[0042] Annealing was used to activate doping, phosphorus diffusion was used to supplement the N region, a 50 nm BSG protective layer was prepared, the alumina thickness was 10 nm, and the remaining processes were the same as in Example 1.

[0043] Test data tables for each embodiment

[0044]

[0045] Note: In the table, Eta represents conversion efficiency, Jsc represents short-circuit current density, Uoc represents open-circuit voltage, FF represents fill factor, Rser represents series resistance, Rshunt represents parallel resistance, and Irev1 and Irev2 represent reverse saturation current. Data shows that the 4-layer structure (Example 4) exhibits the best performance, verifying that optimizing the multi-layer stacked POLY structure with increasing layer count can further improve battery efficiency.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multilayer POLY structure TOPCON solar cell, characterized in that, The device includes an N-type silicon wafer. The front side of the N-type silicon wafer is sequentially provided with an aluminum oxide layer, a silicon oxynitride stacked passivation film, and an electrode. The back side is provided with a multilayer stacked POLY structure. The multilayer stacked POLY structure, from the side closest to the N-type silicon wafer to the outside, sequentially includes a tunneling oxide layer, n alternating polycrystalline silicon layers, and a barrier oxide layer, where n is a positive integer. The thickness of the tunneling oxide layer is 1-2 nm, the thickness of each polycrystalline silicon layer is 5-50 nm, the thickness of each barrier oxide layer is 0.5-2 nm, and the overall thickness of the multilayer stacked POLY structure is 60-200 nm. The outer side of the multilayer stacked POLY structure is also provided with a silicon oxynitride stacked passivation film and an electrode.

2. The multilayer POLY structure TOPCON solar cell according to claim 1, characterized in that, The n=3 indicates that the multilayer POLY structure includes 3 polysilicon layers and 3 barrier oxide layers, which are arranged from the inside out as follows: 1st polysilicon layer, 1st barrier oxide layer, 2nd polysilicon layer, 2nd barrier oxide layer, 3rd polysilicon layer, and 3rd barrier oxide layer.

3. The multilayer POLY structure TOPCON solar cell according to claim 1, characterized in that, When the multilayer POLY structure is prepared by PECVD, each polycrystalline silicon layer is formed by annealing amorphous silicon, and the phosphorus doping concentration of each amorphous silicon layer increases sequentially from the inside to the outside during preparation.

4. The multilayer POLY structure TOPCON solar cell according to claim 1, characterized in that, The thickness of the alumina layer is 3-15 nm.

5. A method for fabricating a multilayer POLY structure TOPCON solar cell, characterized in that, Includes the following steps: Step 1: Select an N-type silicon wafer with a thickness of 100-150nm and perform double-sided texturing on the silicon wafer; Step 2: Perform double-intercalation single-sided boron diffusion; Step 3: Perform BSG removal and backside alkaline polishing; Step 4: Fabricate a multilayer POLY structure on the back side of a silicon wafer using LPCVD or PECVD. The multilayer POLY structure, from the side closest to the silicon wafer to the outside, includes a tunneling oxide layer, n alternating polycrystalline silicon or amorphous silicon layers, and a barrier oxide layer, where n is a positive integer. The thickness of the tunneling oxide layer is 1-2 nm, the thickness of each polycrystalline silicon or amorphous silicon layer is 5-50 nm, the thickness of each barrier oxide layer is 0.5-2 nm, and the overall structure thickness is 60-200 nm. Step 5: If step 4 uses LPCVD, a phosphorus diffusion device is used with phosphorus oxychloride or phosphorus pentoxide as the gas source to complete the preparation of the back N region and to fabricate a 40-90nm BSG layer as a protective layer; if step 4 uses PECVD, an annealing device is used to perform phosphorus doping activation and conversion of amorphous silicon to polycrystalline silicon structure to complete the preparation of the back N region. Step 6: Perform PSG and RCA removal cleaning; Step 7: ALD single-insertion double-sided aluminum oxide plating, with the thickness controlled between 3-15nm; Step 8: Deposit silicon oxynitride stacked passivation films on the front and back sides using PECVD; Step 9: Prepare the electrode.

6. The method for fabricating a multilayer POLY structure TOPCON solar cell according to claim 5, characterized in that, In step 4, when the multilayer POLY structure is prepared by LPCVD, the specific process is as follows: deposit a tunneling oxide layer by passing an O2 source, then deposit the first polycrystalline silicon layer by passing SiH4, then deposit the first barrier oxide layer by passing an O2 source again, and so on to deposit the nth barrier oxide layer and polycrystalline silicon layer.

7. The method for fabricating a multilayer POLY structure TOPCON solar cell according to claim 5, characterized in that, In step 4, when preparing the multilayer POLY structure using PECVD, SiH4, N2O, H2, and PH4 are used as gas sources. After depositing the tunneling oxide layer, n amorphous silicon layers and n barrier oxide layers are deposited sequentially, and the phosphorus doping concentration of each amorphous silicon layer increases sequentially from the inside to the outside.

8. The method for fabricating a multilayer POLY structure TOPCON solar cell according to claim 5, characterized in that, The n=3.

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