Electroluminescent display device

Abstract

Disclosed is an electroluminescent display device including: a substrate having a display area and a non-display area; a thin film transistor; the light emitting diode comprises a pixel driving electrode, a light emitting layer and a common electrode; the encapsulation layer is arranged on the light emitting diode and comprises a first inorganic layer, a second inorganic layer and an organic layer; a through hole disposed in the display area and penetrating the substrate and the encapsulation layer; a first inner dam surrounding the through hole; and a hole-trench disposed between the first inner dam and a set of adjacent pixels disposed closest to the first inner dam. Wherein the hole-trench includes: a bottom surface defined as a lowest surface of a recess formed in the substrate; an upper surface defined as an uppermost surface of a layer disposed below the bottom surface of the first inner dam; and a side wall defined as a side surface connecting the bottom surface and the upper surface. Wherein the light emitting layer directly contacts a bottom surface of the hole-trench, is disposed on an upper surface of the hole-trench, and is broken at a sidewall of the hole-trench.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 201911060462.1, filed on November 1, 2019, entitled "Electrically Light Emitting Display Device Having Through Holes in the Display Area". Technical Field

[0002] This disclosure relates to an electroluminescent display device having a through-hole in the display area, and more specifically, to an electroluminescent display device having a device arranged in the display area such that the device is, for example, a camera hole that receives light through a substrate, or a through-hole into which an additional device through the substrate can be inserted. Background Technology

[0003] In display devices, electroluminescent displays are self-emissive devices and offer superior viewing angles and contrast compared to other display devices. Furthermore, since electroluminescent displays do not require a separate backlight, they can be thin, light, and power-efficient. Additionally, organic light-emitting diode (OLED) displays are advantageous because they can be driven at low DC voltages, have fast response times, and are low-cost to manufacture.

[0004] An electroluminescent display device includes multiple electroluminescent diodes (LEDs). Each LED includes an anode electrode, a light-emitting layer formed on the anode electrode, and a cathode electrode formed on the light-emitting layer. When a high potential voltage is applied to the anode electrode and a low potential voltage is applied to the cathode electrode, holes in the anode electrode and electrons in the cathode electrode move to the light-emitting layer, respectively. When holes and electrons combine with each other in the light-emitting layer, excitons are formed during excitation, and light is generated due to the energy from the excitons. The electroluminescent display device displays images by electrically controlling the amount of light generated from the light-emitting layer of the multiple LEDs, which are individually divided into sections.

[0005] Due to their ultra-thin profile and excellent flexibility, electroluminescent displays are used in a wide variety of products across various fields. However, a drawback of electroluminescent displays is their susceptibility to water and oxygen. Therefore, in order to apply electroluminescent displays to various fields and develop them into various types of display devices, methods are needed to prevent water and oxygen from penetrating into the electroluminescent display. In particular, if the through-hole is located within the display area, a structure capable of preventing water and oxygen from penetrating into the area surrounding the through-hole needs to be developed. Summary of the Invention

[0006] The purpose of this disclosure is to provide an electroluminescent display device that maximizes the area of ​​the display region, wherein additional means (e.g., a camera aperture for receiving light through a substrate, or a through-hole for setting components through a substrate) are arranged in the display region for displaying images. Optionally, the purpose of this disclosure is to provide an electroluminescent display device having a structure in which water can be prevented from penetrating to the light-emitting diodes of the display elements arranged near the through-holes, even when through-holes are provided in the display region.

[0007] To achieve one of the above objectives, an electroluminescent display device according to one embodiment of the present disclosure includes a substrate, a through-hole, an inner dam, and a hole-trench. The substrate includes a display area with a plurality of pixels arranged for displaying an image and a non-display area surrounding the display area. The through-hole is arranged within the display area. The inner dam surrounds the through-hole. The hole-trench surrounds the inner dam and is formed as the substrate is partially recessed by a certain thickness.

[0008] For example, the display area includes light-emitting diodes (LEDs) for displaying image information, and driving elements for driving the LEDs. Through-holes are formed by removing the substrate, LEDs, and driving elements.

[0009] For example, a hole-trench includes a bottom surface, a top surface, and sidewalls. The bottom surface is defined at a location recessed to a certain depth relative to the top surface of the substrate. The top surface is defined on the top surface of the substrate. The sidewalls connect the bottom surface and the top surface. The light-emitting layer of the light-emitting diode is deposited on the bottom and top surfaces, excluding the sidewalls.

[0010] For example, a hole-trench has a well shape that is recessed by removing 20% ​​to 70% of the substrate in the thickness direction.

[0011] For example, the aperture-groove arrangement in the inner dam and the pixel is arranged between adjacent pixels close to the inner dam.

[0012] For example, the hole-groove has a closed curve shape that corresponds to the shape of the through hole.

[0013] For example, the hole-groove can have any of the following shapes surrounding the through hole: polygonal, circular, and elliptical.

[0014] For example, the width of the hole-groove is narrower than the width of the inner dam.

[0015] For example, an inner dam includes a first inner dam adjacent to the through-hole and a second inner dam surrounding the first inner dam.

[0016] For example, the hole-groove arrangement is between the first inner dam and the second inner dam.

[0017] For example, an electroluminescent display device further includes a thin-film transistor layer, a planarization layer, an anode electrode, and a dam. The thin-film transistor layer is formed on a substrate. The planarization layer covers the thin-film transistor layer. The anode electrode is connected to the thin-film transistors disposed in the thin-film transistor layer and is disposed on the planarization layer. The dam defines a light-emitting region in the anode electrode. A via-trench passes through the dam, the planarization layer, and the thin-film transistor layer, and is formed by removing a certain thickness from the substrate.

[0018] For example, the inner dam also includes spacers deposited on the leveling layer and the embankment, which surround the through-holes.

[0019] For example, an electroluminescent display device further includes an outer dam, a light-emitting layer, a cathode electrode, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The outer dam is disposed in the non-display area and surrounds the display area. The light-emitting layer covers the pixels, inner dam, and vias on the substrate between the outer dam and the via. The cathode electrode is deposited on the light-emitting layer. The encapsulation layer covers the cathode electrode.

[0020] For example, the via is not formed together with the substrate, thin-film transistor layer, planarization layer, light-emitting layer, cathode electrode, and encapsulation layer. The light-emitting layer is exposed from the sidewall of the via.

[0021] For example, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer deposited on the first inorganic encapsulation layer, and a second inorganic encapsulation layer deposited on the upper surface of the organic encapsulation layer.

[0022] In one embodiment of the electroluminescent display device according to this disclosure, since the through-hole is provided in the display area, the area ratio occupied by the non-display area is minimized, and the area ratio of the display area is maximized. In one embodiment of the electroluminescent display device according to this disclosure, since the inner dam and hole-groove are provided near the through-hole, water is prevented from seeping into the light-emitting diode from the outside. In one embodiment of the electroluminescent display device according to this disclosure, even if a hole is provided through the display panel in the display area, external water and particles are shielded from penetrating and diffusing into the display element, thereby ensuring product stability and lifespan.

[0023] In addition to the effects of this disclosure as described above, other purposes and features of this disclosure will be clearly understood by those skilled in the art from the following description of this disclosure. Attached Figure Description

[0024] This invention includes accompanying drawings to provide a further understanding of the present disclosure, and the drawings are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0025] Figure 1 This is a plan view illustrating an electroluminescent display device including a through-hole in the display area according to one embodiment of the present disclosure;

[0026] Figure 2 This is a planar enlarged view showing the structure of a through hole arranged in the display area in an electroluminescent display device according to one embodiment of the present disclosure;

[0027] Figure 3 It is along Figure 1 The cross-sectional view taken by line I-I' in the figure shows the structure of the portion in which through holes are arranged in an electroluminescent display device according to a preferred embodiment of the present disclosure;

[0028] Figure 4 It is along Figure 1 The cross-sectional view taken by line II-II' shows the structure of one side of the electroluminescent display device according to a preferred embodiment of the present disclosure;

[0029] Figure 5 This is a plan view illustrating the structure of through-holes and hole-trenches arranged in the display area of ​​an electroluminescent display device according to one embodiment of the present disclosure; and

[0030] Figure 6 This is a plan view showing the structure of through holes and hole-grooves arranged in the display area of ​​an electroluminescent display device according to another embodiment of the present disclosure. Detailed Implementation

[0031] The advantages and features of this disclosure and its implementation methods will be illustrated by the following description of embodiments with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.

[0032] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings describing embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of this disclosure.

[0033] When using the terms “including,” “having,” and “containing” as described in this disclosure, an additional part may be added unless “only” is used. Unless otherwise stated, singular terms may include plural forms.

[0034] When interpreting a component, although there is no explicit description, the component is interpreted as including a range of error.

[0035] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "beside," one or more parts may be arranged between two other parts, unless "immediately following" or "directly" is used.

[0036] When describing temporal relationships, such as when time sequence is described as "after", "following", "next", and "before", discontinuous cases can be included unless "immediately following" or "directly" is used.

[0037] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0038] The term "at least one" should be understood to include any and all combinations of one or more of the relevant listed items. For example, "at least one of the first, second, and third items" means a combination of all items proposed according to two or more of the first, second, and third items, as well as the first, second, or third item.

[0039] Features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may operate on each other in various ways and be technically driven, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other or may be performed together in an interdependent relationship.

[0040] In the following, examples of electroluminescent display devices according to this disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts.

[0041] In the following, an electroluminescent display device according to a preferred embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Figure 1 This is a plan view illustrating an electroluminescent display device including a through-hole in the display area according to the present disclosure. (Refer to...) Figure 1 The electroluminescent display device according to this disclosure includes a substrate SUB, a pixel P, a common power line CPL, an outer dam DMO, a driving section including a pad portion PP, a gate driving circuit 200 and a driving integrated circuit 300, and a through hole TH.

[0042] The substrate SUB is a base substrate (or base layer) and comprises either plastic or glass materials. Considering the characteristics of the display device, it is preferable that the substrate SUB is transparent. However, depending on the situation, for example in the case of a top-emitting display device, an opaque material may be used as the substrate SUB.

[0043] According to one example, the substrate SUB can have a rectangular shape, a rounded rectangular shape (each corner of which is chamfered with a certain radius of curvature), or a non-rectangular shape with at least six sides in a plane. In this case, the substrate SUB with a non-rectangular shape may include at least one protrusion or at least one notch.

[0044] According to one example, a substrate SUB can be divided into a display area AA and a non-display area IA. The display area AA is located in the central portion of the substrate SUB and can be defined as an area for displaying images. According to one example, the display area AA can have a rectangular shape, a rounded rectangular shape (each corner of which is chamfered with a certain radius of curvature), or a non-rectangular shape with at least six sides in a plane. In this case, the display area AA with a non-rectangular shape may include at least one protrusion or at least one notch.

[0045] A non-display area IA is disposed at the edge of the substrate SUB to surround the display area AA, and can be defined as an area where no image is displayed or a peripheral area. According to one example, the non-display area IA may include: a first non-display area IA1 disposed on a first edge of the substrate SUB; a second non-display area IA2 disposed on a second edge of the substrate SUB and parallel to the first non-display area IA1; a third non-display area IA3 disposed on a third edge of the substrate SUB; and a fourth non-display area IA4 disposed on a fourth edge of the substrate SUB and parallel to the third non-display area IA3. For example, the first non-display area IA1 may be, but is not limited to, the upper (or lower) edge of the substrate SUB; the second non-display area IA2 may be, but is not limited to, the lower (or upper) edge of the substrate SUB; the third non-display area IA3 may be, but is not limited to, the left (or right) edge of the substrate SUB; and the fourth non-display area IA4 may be, but is not limited to, the right (or left) edge of the substrate SUB.

[0046] Pixel P can be disposed on the display area AA of the substrate SUB. According to one example, pixel P may include multiple pixels arranged in a matrix and may be disposed in the display area AA of the substrate SUB. Pixel P may be defined by scan lines SL, data lines DL, and pixel drive power lines PL.

[0047] Scan lines SL extend longitudinally along a first direction X and are arranged at certain intervals along a second direction Y that intersects the first direction X. The display area AA of the substrate SUB includes a plurality of scan lines SL that are spaced apart from each other along the second direction Y and are parallel to the first direction X. In this case, the first direction X can be defined as the horizontal direction of the substrate SUB, and the second direction Y can be defined as the vertical direction of the substrate SUB, or vice versa, and is not limited to this case.

[0048] The data lines DL extend longitudinally along the second direction Y and are arranged at certain intervals along the first direction X. The display area AA of the substrate SUB includes a plurality of data lines DL that are spaced apart from each other along the first direction X and parallel to the second direction Y.

[0049] Pixel driving power lines PL can be arranged on the substrate SUB parallel to the data lines DL. The display area AA of the substrate SUB includes multiple pixel driving power lines PL parallel to the data lines DL. Optionally, the pixel driving power lines PL can be arranged parallel to the scan lines SL.

[0050] In one example, a pixel P can be arranged on a display area AA to have a stripe structure. In this case, a unit pixel can include red sub-pixels, green sub-pixels, and blue sub-pixels. Furthermore, a unit pixel can also include a white sub-pixel.

[0051] According to another example, pixel P can be arranged on display area AA to have a pentile structure. In this case, a unit pixel can include at least one red sub-pixel, at least two green sub-pixels, and at least one blue sub-pixel arranged in a polygonal shape in two dimensions. For example, a unit pixel with a pentile structure can be arranged such that one red sub-pixel, two green sub-pixels, and one blue sub-pixel have an octagonal shape in two dimensions. In this case, the blue sub-pixel can have the relatively largest aperture area (or light-emitting area), and the green sub-pixel can have the relatively smallest aperture area.

[0052] Pixel P may include: pixel circuit PC, which is electrically connected to adjacent scan line SL, data line DL and pixel drive power line PL; and light-emitting diode ED, which is electrically connected to pixel circuit PC.

[0053] The pixel circuit PC responds to a scan signal provided from at least one adjacent scan line SL and controls the current Ied flowing from the pixel drive power line PL to the light-emitting diode ED based on the data voltage provided from the adjacent data line DL.

[0054] A pixel circuit PC according to one example may include at least two thin-film transistors and a capacitor. For example, a pixel circuit PC according to one example may include: a driving thin-film transistor that provides a data current Ied based on a data voltage to a light-emitting diode ED; a switching thin-film transistor that provides a data voltage from a data line DL to the driving thin-film transistor; and a capacitor that stores the gate-source voltage of the driving thin-film transistor.

[0055] According to another example, the pixel circuit PC may include at least three thin-film transistors and at least one capacitor. For example, depending on the operation (or function) of each of the at least three thin-film transistors, the pixel circuit PC according to another example may include a current supply circuit, a data supply circuit, and a compensation circuit. In this case, the current supply circuit may include a driving thin-film transistor that provides a data current Ied based on a data voltage to a light-emitting diode ED. The data supply circuit may include at least one switching thin-film transistor that, in response to at least one scan signal, provides a data voltage from a data line DL to the current supply circuit. The compensation circuit may include at least one compensation thin-film transistor that, in response to at least one scan signal, compensates for changes in the characteristic values ​​(threshold voltage and / or mobility) of the driving thin-film transistor.

[0056] The light-emitting diode (ED) emits light with a brightness corresponding to the data current (Ied) supplied from the pixel circuit (PC). In this case, the data current (Ied) can flow from the pixel drive power line (PL) to the common power line (CPL) by driving the thin-film transistor (TFT) and the ED.

[0057] According to one example, a light-emitting diode ED may include: a pixel driving electrode AE ​​(or a first electrode or anode) electrically connected to a pixel circuit PC, a light-emitting layer EL formed on the pixel driving electrode, and a common electrode CE (or a second electrode or cathode) electrically connected to the light-emitting layer.

[0058] A common power line CPL is disposed on a non-display area IA of the substrate SUB and is electrically connected to a common electrode CE disposed on a display area AA. According to one example, the common power line CPL is disposed along second to fourth non-display areas IA2, IA3, and IA4 adjacent to the display area AA of the substrate SUB, having a certain linewidth, and enclosing, except for, the portion of the display area AA adjacent to the first non-display area IA1 of the substrate SUB. One end of the common power line CPL can be disposed on one side of the first non-display area IA1, and the other end of the common power line CPL can be disposed on the other side of the first non-display area IA1. One end and the other end of the common power line CPL can be arranged to enclose the second to fourth non-display areas IA2, IA3, and IA4. Therefore, according to one example, the common power line CPL can have a two-dimensional “∩” shape, wherein the side corresponding to the first non-display area IA1 of the substrate SUB is open.

[0059] An encapsulation layer can be formed on the substrate SUB to surround the upper surface and sides of the display area AA and the common power line CPL. Simultaneously, the encapsulation layer can expose one end and the other end of the common power line CPL in the first non-display area IA1. The encapsulation layer can prevent oxygen or water from penetrating into the light-emitting diode ED disposed in the display area AA. According to one example, the encapsulation layer may include at least one inorganic film. According to another example, the encapsulation layer may include multiple inorganic films and an organic film between the multiple inorganic films.

[0060] According to one embodiment of the present disclosure, the driving unit may include a pad portion PP, a gate driving circuit 200, and a driving integrated circuit 300.

[0061] The pad section PP may include multiple pads disposed in the non-display area IA of the substrate SUB. According to one example, the pad section may include multiple common power pads, multiple data input pads, multiple power pads, and multiple control signal input pads disposed in the first non-display area IA1 of the substrate SUB.

[0062] A gate driving circuit 200 is disposed in a third non-display area IA3 and / or a fourth non-display area IA4 of the substrate SUB, and is connected in a one-to-one relationship to a scan line SL disposed in the display area AA. Along with the manufacturing process of the pixel P (i.e., the thin-film transistor manufacturing process), the gate driving circuit 200 can be integrated with the third non-display area IA3 and / or the fourth non-display area IA4 of the substrate SUB. The gate driving circuit 200 generates scan signals based on gate control signals provided from the driver integrated circuit 300, and outputs scan signals according to a given order, thereby driving each of the plurality of scan lines SL in the given order. According to one example, the gate driving circuit 200 may include a shift register.

[0063] The outer dam DMO can have a closed-curve structure, wherein it is disposed in the first non-display area IA1, the second non-display area IA2, the third non-display area IA3, and the fourth non-display area IA4 of the substrate SUB to surround the outer periphery of the display area AA. For example, the outer dam DMO can be arranged outside the common power line CPL, and thus located on the outermost side above the substrate SUB. Preferably, the pad portion PP and the driver integrated circuit 300 are arranged in the outer region of the outer dam DMO.

[0064] although Figure 1 The diagram shows the outermost DMO (Damage Management Object) positioned on the outermost side, but the outer DMO is not limited to this configuration. Figure 1 Examples include: As another example, the outer dam DMO can be positioned between the power common line CPL and the gate drive circuit 200. As yet another example, the outer dam DMO can be positioned between the display area AA and the gate drive circuit 200.

[0065] The driver integrated circuit 300 is packaged in the chip package area defined in the first non-display area IA1 of the substrate SUB using a chip packaging (bonding) process. The input terminals of the driver integrated circuit 300 are electrically connected to the pad portion PP, and therefore electrically connected to a plurality of data lines DL and a plurality of pixel driving power lines PL disposed in the display area AA. The driver integrated circuit 300 receives various power supplies, timing synchronization signals, and digital image data input from the display driving circuit section (or main circuit) through the pad portion PP, controls the driving of the gate driving circuit 200 by generating a gate control signal based on the timing synchronization signal, and simultaneously converts the digital image data into analog pixel data voltages to provide the converted data voltages to the corresponding data lines DL.

[0066] A through-hole TH physically passes through the display device. For example, a through-hole TH can be formed to pass only through the display panel constituting the display device. In this case, the polarizer or cover glass bonded to the upper surface of the display panel can have a structure for covering the through-hole TH without being passed through by it. When a through-hole TH for transmitting light (e.g., a camera hole or a light sensor hole) is formed, the through-hole TH can pass only through the display panel without passing through the polarizer or cover glass. As another example, if an additional device is to be provided that completely passes through the display device, a through-hole TH can be provided to completely open the display panel, the optical film bonded to the upper part of the display panel, and the cover glass.

[0067] Since display elements cannot be arranged within the via TH, in conventional techniques, the via TH should be arranged in the non-display area IA. In this case, the width and length of the non-display area IA (corresponding to the width and length of the via TH) may be increased to ensure sufficient area for fabricating the via TH, thereby reducing the area ratio occupied by the display area AA in the display panel. The present disclosure is characterized in that the via TH is arranged within the display area AA. Instead of being arranged in the area within the display area AA corresponding to the via TH, the display element is arranged near the via TH, thereby maximizing the area ratio occupied by the display area AA in the display panel.

[0068] In the following text, reference will be made to Figure 2 The structural features of the through-hole, which are a key feature of this disclosure, will be described in more detail. Figure 2 This is a planar enlarged view showing the structure of through holes arranged in the display area of ​​an electroluminescent display device according to the present disclosure.

[0069] Reference Figure 2 The via TH is arranged within the display area AA. Pixel P is arranged near the via TH. Among pixels P, pixels P arranged close to the via TH can be defined as adjacent pixels Pc. A hole-boundary portion THB can be defined between adjacent pixels Pc and the via TH.

[0070] The inner dam DMI and the trench HTR are arranged within the via-boundary portion THB. Specifically, the inner dam DMI is arranged closest to the via TH. The inner dam DMI has a closed curve shape that surrounds the via TH and corresponds to the shape of the via TH. The trench HTR is arranged between the inner dam DMI and the adjacent pixel Pc. The trench HTR has a closed curve shape that surrounds the inner dam DMI and corresponds to the shape of the inner dam DMI. Therefore, although the inner dam DMI and the trench HTR can each have different closed curve shapes, they can also have closed curve shapes that are the same in shape but different in size. For example, the inner dam DMI and the trench HTR can have concentric circle shapes and can be arranged spaced apart from each other.

[0071] In the following text, reference will be made to Figure 3 and Figure 4 The cross-sectional structure of an electroluminescent display device including through holes in the display area according to a preferred embodiment of the present disclosure is described. Figure 3 It is along Figure 1 The cross-sectional view taken by line I-I' in the figure shows the structure of the portion in which through holes are arranged in an electroluminescent display device according to a preferred embodiment of the present disclosure. Figure 4 It is along Figure 1 The cross-sectional view taken by line II-II' shows the structure of one side of an electroluminescent display device according to a preferred embodiment of the present disclosure.

[0072] Reference Figure 3 and Figure 4 An electroluminescent display device according to a preferred embodiment of the present disclosure may include a substrate SUB, a pixel array layer 120, spacers SP, an encapsulation layer 130, and a through-hole TH.

[0073] The substrate SUB may include a display area AA and a non-display area IA surrounding the display area AA. The substrate SUB is a base layer and comprises either a plastic material or a glass material. According to one example, the substrate SUB may be made of opaque or colored polyimide material. The substrate SUB may be a flexible substrate or a rigid substrate. For example, a flexible substrate SUB made of glass material may be a thin glass substrate with a thickness of 100 micrometers or less, or a glass substrate etched to a thickness of 100 micrometers or less using a substrate etching process.

[0074] A buffer film (not shown) may be formed on the upper surface of the substrate SUB. The buffer film is formed on one surface of the substrate SUB to prevent water from penetrating through the easily permeable substrate SUB into the pixel array layer 120. According to one example, the buffer film may be made of multiple alternately deposited inorganic films. For example, the buffer film may be formed of a multilayer film of one or more inorganic films selected from alternately deposited silicon oxide (SiOx), silicon nitride (SiNx), and SiON. The buffer film may be omitted.

[0075] The pixel array layer 120 may include a thin film transistor layer, a planarization layer PLN, a embankment pattern BN, spacers SP, and light-emitting diodes ED.

[0076] Thin-film transistor layers are respectively disposed in the plurality of pixels P defined in the display area AA of the substrate SUB and in the gate driving circuit 200 defined in the fourth non-display area IA4 of the substrate SUB.

[0077] A thin-film transistor layer, according to one example, includes a thin-film transistor T, a gate insulating film GI, and an interlayer dielectric (ILD) film. In this case, Figure 2 The thin-film transistor T shown can be a driving thin-film transistor electrically connected to a light-emitting diode ED.

[0078] A thin-film transistor T includes a semiconductor A, a gate electrode G, a source electrode S, and a drain electrode D formed on a substrate SUB or a buffer film. Figure 3 and Figure 4 The diagram illustrates, but is not limited to, a top gate structure for a thin-film transistor T, wherein the gate electrode G is disposed above the semiconductor layer A. As another example, the thin-film transistor T may have a bottom gate structure with the gate electrode G disposed below the semiconductor layer A, or a dual-gate structure with the gate electrode G disposed above and below the semiconductor layer A.

[0079] Semiconductor layer A can be formed on substrate SUB or buffer film. Semiconductor layer A may include silicon-based semiconductor materials, oxide-based semiconductor materials, or organic-based semiconductor materials, and may have a single-layer structure or a multi-layer structure. An additional light-shielding layer for shielding external light entering semiconductor layer A can be formed between the buffer film and semiconductor layer A.

[0080] The gate insulating film GI can be formed on the entire substrate SUB to cover the semiconductor layer A. The gate insulating film GI can be formed from an inorganic film, such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multilayer film of SiOx and SiNx.

[0081] The gate electrode G can be formed on the gate insulating film GI to overlap with the semiconductor layer A. The gate electrode G can be formed together with the scan line SL. According to one example, the gate electrode G can be formed from a single layer or multiple layers of any one of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu or alloys thereof.

[0082] An interlayer dielectric (ILD) film can be formed on the entire substrate SUB to cover the gate electrode G and the gate insulating film GI. The interlayer dielectric (ILD) film provides a planarization plane on the gate electrode G and the gate insulating film GI.

[0083] The source electrode S and drain electrode D can be formed on an interlayer dielectric (ILD) film to overlap with the semiconductor layer A. The gate electrode G is positioned between the source electrode S and drain electrode D. The source electrode S and drain electrode D can be formed together with the data line DL, pixel drive power line PL, and common power line CPL. That is, the source electrode S, drain electrode D, data line DL, pixel drive power line PL, and common power line CPL are formed simultaneously through a patterning process targeting the source-drain electrode materials.

[0084] Each of the source electrode S and drain electrode D can be connected to the semiconductor layer A through electrode contact holes passing through the interlayer dielectric (ILD) film and the gate insulating film GI. The source electrode S and drain electrode D can be formed from a single layer or multiple layers of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or alloys thereof. In this case, Figure 2 The source electrode S of the thin-film transistor T shown can be electrically connected to the pixel driving power line PL.

[0085] As described above, the thin-film transistor T disposed in the pixel P of the substrate SUB constitutes the pixel circuit PC. Furthermore, the gate drive circuit 200 disposed in the fourth non-display area IA4 of the substrate SUB may include a thin-film transistor that is the same as or similar to the thin-film transistor T disposed in the pixel P.

[0086] A planarization layer PLN is formed over the entire substrate SUB to cover the thin-film transistor layer. The planarization layer PLN provides a planarized surface on the thin-film transistor layer. According to one example, the planarization layer PLN can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0087] According to another example, the planarization layer PLN may include a pixel contact hole PH for exposing the drain electrode D of a driving thin-film transistor disposed in pixel P.

[0088] The embankment pattern BN is disposed on the planarization layer PLN and defines the opening region (or light-emitting region) within the pixel P of the display area AA. The embankment pattern BN can be represented as a pixel-defining film.

[0089] A light-emitting diode (ED) includes a pixel driving electrode AE, an emissive layer EL, and a common electrode CE. The pixel driving electrode AE ​​is formed on a planarization layer PLN and is electrically connected to the drain electrode D of the driving thin-film transistor through a pixel contact hole PH disposed in the planarization layer PLN. In this case, the edge portions of the pixel driving electrode AE, except for the central portion overlapping with the opening region of the pixel P, can be covered by a dam pattern BN. The dam pattern BN defines the opening region of the pixel P by covering the edge portions of the pixel driving electrode AE.

[0090] According to one example, the pixel driving electrode AE ​​may include a highly reflective metallic material. For example, the pixel driving electrode AE ​​may be formed of a multilayer structure (e.g., a deposited structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a deposited structure of Al and ITO (ITO / Al / ITO), an APC (Ag / Pd / Cu) alloy, and a deposited structure of APC alloy and ITO (ITO / APC / ITO)), or may include a single-layer structure made of any one of Ag, Al, Mo, Au, Mg, Ca, and Ba, or an alloy of two or more of these materials.

[0091] The light-emitting layer EL is formed entirely on the display area AA of the substrate SUB to cover the pixel driving electrode AE ​​and the embankment pattern BN. According to one example, the light-emitting layer EL may include two or more light-emitting portions vertically deposited to emit white light. For example, according to one example, the light-emitting layer EL may include a first light-emitting portion and a second light-emitting portion for emitting white light by a combination of a first light and a second light. In this case, the first light-emitting portion emits a first light and may include any one of a blue light-emitting portion, a green light-emitting portion, a red light-emitting portion, a yellow light-emitting portion, and a yellow-green light-emitting portion. The second light-emitting portion may include a light-emitting portion from the blue, green, red, yellow, and yellow-green light-emitting portions for emitting a second light complementary to the first light.

[0092] According to another example, the emissive layer EL may include any one of a blue emissive layer, a green emissive layer, and a red emissive layer to emit light of a color corresponding to the color set in pixel P. For example, the emissive layer EL may include any one of an organic emissive layer, an inorganic emissive layer, and a quantum dot emissive layer, or may include a deposition or combination structure of an organic emissive layer (or an inorganic emissive layer) and a quantum dot emissive layer.

[0093] Additionally, according to one example, a light-emitting diode (ED) may also include a functional layer for improving the luminous efficiency and / or lifetime of the light-emitting layer (EL).

[0094] The common electrode CE is formed to be electrically connected to the light-emitting layer EL. The common electrode CE is formed on the entire display area AA of the substrate SUB, and is therefore connected to the light-emitting layer EL disposed in each pixel P.

[0095] According to one example, the common electrode CE may comprise a transparent conductive material or a semi-transmissive conductive material capable of transmitting light. If the common electrode CE is formed of a semi-transmissive conductive material, the luminous efficiency of light emitted from the light-emitting diode ED can be enhanced through a microcavity structure. According to one example, the semi-transmissive conductive material may comprise Mg, Ag, or an alloy of Mg and Ag. Additionally, a capping layer may be formed on the common electrode CE to improve the luminous efficiency by controlling the refractive index of light emitted from the light-emitting diode ED.

[0096] The spacers SP can be arranged in the open areas within the display area AA, i.e., the areas where no light-emitting diodes (EDs) are disposed. The spacers SP are designed to prevent the screen mask and the substrate from contacting each other during the deposition of the light-emitting layer EL. The spacers SP are disposed on the embankment pattern BN and can be deposited such that the light-emitting layer EL and the common electrode CE can cross / cover the spacers SP disposed within the display area AA.

[0097] Depending on the circumstances, the light-emitting layer EL and / or the common electrode CE may not cross the spacer SP. Since the spacer SP is only arranged in a portion of the dam pattern BN within the display area AA, the common electrode CE has the following structure: even if the common electrode CE does not cross the spacer SP, this structure is connected to the display area AA and completely covers the display area AA.

[0098] The encapsulation layer 130 is formed to surround the upper surface and sides of the pixel array layer 120. The encapsulation layer 130 is used to prevent oxygen or water from penetrating into the light-emitting diode (ED).

[0099] According to one example, the encapsulation layer 130 may include a first inorganic encapsulation layer PAS1, an organic encapsulation layer PCL on the first inorganic encapsulation layer PAS1, and a second inorganic encapsulation layer PAS2 on the organic encapsulation layer PCL. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 are used to shield against water or oxygen penetration into the light-emitting diode ED. Each of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be formed of an inorganic material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0100] The organic encapsulation layer PCL is surrounded by a first inorganic encapsulation layer PAS1 and a second inorganic encapsulation layer PAS2. The organic encapsulation layer PCL may be formed to be relatively thicker than the first inorganic encapsulation layer PAS1 and / or the second inorganic encapsulation layer PAS2 to adsorb and / or shield particles that may appear during manufacturing. The organic encapsulation layer PCL may be made of organic materials such as SiOCx (silicon-oxygen-carbon) acrylic or epoxy resin. The organic encapsulation layer PCL may be formed by a coating process (e.g., inkjet coating or slot coating).

[0101] The electroluminescent display device according to the first embodiment of this disclosure may further include a dam structure. The dam structure includes an outer dam DMO disposed outside the display area AA and an inner dam DMI disposed inside the display area AA. The outer dam DMO is disposed in the non-display area IA of the substrate SUB to prevent overflow of the organic encapsulation layer PCL. The inner dam DMI is arranged to surround the through-hole TH within the display area AA. Figure 4 Only the outer dam DMO is shown in the image. Figure 3 Only the inner dam DMI is shown in the image.

[0102] According to one example, the outer dam DMO can be arranged outside the display area AA. More specifically, the outer dam DMO can be arranged outside the gate drive circuit 200 (which is arranged outside the display area) and the common power line CPL (which is arranged outside the gate drive circuit 200). Depending on the situation, the outer dam DMO can be arranged to overlap with the outer side of the common power line CPL. In this case, the width of the non-display area IA where the gate drive circuit 200 and the common power line CPL are arranged can be reduced to reduce the bezel width.

[0103] According to a preferred embodiment of this disclosure, the dam structure including the inner dam DMI and the outer dam DMO can have a three-layer structure, wherein the corresponding elements are formed perpendicular to the substrate SUB. For example, the dam structure may include a first layer formed by a planarization layer PLN, a second layer formed by a dam pattern BN, and a third layer formed by spacers SP.

[0104] The first layer can have a patterned trapezoidal cross-sectional structure of the planarization layer PLN. The second layer can have a trapezoidal cross-sectional structure deposited on the first layer. The third layer can have a trapezoidal cross-sectional structure deposited on the second layer. If the organic encapsulation layer PCL is thin to facilitate control of the PCL's extension, a high dam structure is not required. In this case, the third layer can be omitted.

[0105] The dam structure is completely covered by a first inorganic encapsulation layer PAS1 and / or a second inorganic encapsulation layer PAS2. An organic encapsulation layer PCL may contact a portion of the inner wall of the dam structure. For example, the height from the edge region of the organic encapsulation layer PCL to the upper surface may be higher than the first layer of the dam structure DM and lower than the second layer of the dam structure DM. Alternatively, the height from the edge region of the organic encapsulation layer PCL to the upper surface may be higher than the second layer of the dam structure DM and lower than the third layer of the dam structure DM.

[0106] Preferably, the height from the edge region of the organic encapsulation layer PCL to the upper surface can be less than the entire height of the dam structure. Therefore, the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 are in surface contact with each other on the upper surface and outer wall of the dam structure.

[0107] Will refer again Figure 2 and Figure 3 The structure of the inner dam DMI according to an embodiment of the present disclosure is described in more detail. According to one embodiment of the present disclosure, the inner dam DMI is arranged between a via TH within a display area AA and an adjacent pixel Pc surrounding the via TH. Therefore, unlike the outer dam DMI, some elements of the light-emitting diode ED can be deposited on the inner dam DMI. For example, the light-emitting layer EL and the common electrode CE can be deposited across the inner dam DMI.

[0108] The inner dam DMI can have a positive conical shape. While a positive conical shape prevents the organic encapsulation layer (PCL) from being lost near the via (TH), the luminescent layer (EL) may be exposed from the sidewall of the TH, making it susceptible to water seepage. To avoid this, the inner dam DMI can have an inverted conical shape. If the inner dam DMI has an inverted conical shape, the luminescent layer (EL) can have a discontinuous structure at the lower end of the inner dam DMI. In this case, water that has seeped through the via (TH) can be prevented from diffusing to adjacent pixels (Pc) located near the TH. This portion is exposed through the via (TH) of the luminescent layer (EL).

[0109] To ensure the maximum display area ratio of the display area AA, it is preferable to arrange the inner dam DMI very close to the through hole TH. Therefore, the inverted cone shape of the inner dam DMI cannot completely block water seepage. In this disclosure, a hole-groove HTR is also provided to completely block water seepage through the light-emitting layer EL exposed on the side of the through hole TH, preventing it from spreading to adjacent pixels Pc, regardless of whether the inner dam DMI is a regular cone shape or an inverted cone shape.

[0110] The via-groove HTR has a closed curve shape corresponding to the shape of the via TH. For example, if the via TH has a circular shape, then the via-groove HTR can have a circular shape. Alternatively, the via-groove HTR can have an elliptical shape surrounding the via TH, regardless of the shape of the via TH. As another example, if the via TH has a polygonal shape, such as a rectangle, hexagon, or octagon, then the via-groove HTR can have any of the polygonal, circular, and elliptical shapes surrounding the via TH. In the following description, for convenience, it will be based on the condition that the via TH has a circular shape, the via-groove HTR has a circular shape surrounding the via TH, and is concentric with the via TH.

[0111] Preferably, the via-trench HTR is disposed between the inner dam DMI and the adjacent pixel Pc. The cross-section of the via-trench HTR can have a well shape, from which a certain thickness of the substrate SUB is partially removed. More specifically, the via-trench HTR can be formed by forming a pixel array layer 120, forming an anode electrode AE, and patterning a dam BN for defining the light-emitting area on the substrate SUB, and then etching the pixel array layer 120 and the substrate SUB together.

[0112] The via-trench (HTR) includes a bottom surface BS, a top surface US, and a sidewall SW connecting the bottom surface BS and the top surface US. The bottom surface BS can be defined as the lowest surface of the recessed portion formed in the substrate SUB. The top surface US can be defined as the uppermost surface of the substrate SUB when the via-trench HTR is formed. For example, since the via-trench HTR is formed in the planarization layer PLN exposed after the embankment BN is patterned, the upper surface of the planarization layer PLN can be defined as the top surface US. The sidewall SW can be defined as the side of the via-trench HTR connecting the bottom surface BS and the top surface US.

[0113] After forming the via-trench HTR, an emissive layer EL is deposited. The emissive layer EL is deposited on the bottom surface BS of the via-trench HTR and in the outer periphery of the top surface US of the via-trench HTR. However, since the emissive layer is not deposited on the sidewalls SW of the via-trench HTR, the emissive layer EL has a disconnected structure through the via-trench HTR. Therefore, even if water penetrates into the emissive layer EL exposed on the side of the via TH, the via-trench HTR can completely block water diffusion to adjacent pixels Pc arranged near the via TH.

[0114] Since the via-trench (HTR) is formed to allow the light-emitting layer (EL) to be disconnected through the HTR, it is preferable that the HTR has sufficient depth. Considering process tolerances, it is preferable that the HTR completely surrounds the via (TH) and has a well shape from which the substrate (SUB) is removed by a predetermined thickness. Depending on the situation, the HTR can disconnect the EL even if it is shallow, but it is preferable to have a depth 20% or more greater than the thickness of the substrate (SUB) to ensure a reliable disconnection structure.

[0115] Additionally, a common electrode CE is deposited on the light-emitting layer EL. An encapsulation layer 130 is deposited on the common electrode CE. Specifically, a first inorganic encapsulation layer PAS1 is deposited first on the encapsulation layer 130. The first inorganic encapsulation layer PAS1 can be deposited along the upper surface US, bottom surface BS, and sidewall SW of the via-trench HTR. Therefore, water that permeates through the light-emitting layer EL exposed to the sidewall SW of the via TH is completely shielded by the via-trench HTR and the first inorganic film PAS1 covering the via-trench HTR.

[0116] If the depth of the via-trench (HTR) is too deep, the substrate SUB may be damaged by the HTR. In this case, the function of the via-trench HTR in preventing water penetration may be significantly degraded. To prevent functional degradation of the via-trench HTR, the depth of the HTR should be sufficient to maintain the rigidity of the portion of the substrate SUB in which the HTR is formed. For example, preferably, the maximum depth of the via-trench HTR does not exceed 70% of the thickness of the substrate SUB.

[0117] In the following text, reference will be made to Figure 5 and Figure 6 Describes hole-grooves surrounding through holes according to various embodiments of this disclosure. Figure 5 This is a plan view illustrating the structure of through holes and hole-trenches arranged in the display area of ​​an electroluminescent display device according to one embodiment of the present disclosure. Figure 6 This is a plan view illustrating the structure of through-holes and hole-trenches arranged in the display area of ​​an electroluminescent display device according to another embodiment of the present disclosure. For convenience, in Figure 5 and Figure 6 Only the through-hole (TH), orifice-groove (HTR), and inner dam (DMI) are shown. Although in Figure 5 and Figure 6 The reference numerals not marked in the figure but mentioned in the following description are the same as those in the figure. Figures 1 to 3 The same as shown.

[0118] Reference Figure 5An electroluminescent display device according to one embodiment of the present disclosure includes a through-hole TH in a display area. A first inner dam DMI1 surrounds the outer periphery of the through-hole TH. A second inner dam DMI2 surrounds the outer periphery of the first inner dam DMI1. A hole-groove HTR is arranged between the first inner dam DMI1 and the second inner dam DMI2. Although not shown, a pixel P including an adjacent pixel Pc is arranged near the second inner dam DMI2.

[0119] According to Figure 5 In one embodiment, multiple inner dams, including a first inner dam DMI1 and a second inner dam DMI2, are arranged to enhance their functionality. Additionally, a hole-groove HTR is arranged between the first inner dam DMI1 and the second inner dam DMI2. Preferably, the width of the hole-groove HTR is narrower than the width of the first inner dam DMI1 and the width of the second inner dam DMI2. Meanwhile, the first inner dam DMI1 and the second inner dam DMI2 may have the same width, or their respective widths may differ from each other.

[0120] Preferably, if possible, the aperture-boundary portion THB, defined as the area between the via TH and the adjacent pixel Pc, has a narrow region. If the aperture-boundary portion THB is too wide, it may interfere with display functionality. A first inner dam DMI1, a second inner dam DMI2, and an aperture-trench HTR are arranged within the aperture-boundary portion THB. In this case, the first inner dam DMI1 and the second inner dam DMI2 are designed to prevent the organic encapsulation layer PCL from overflowing to the outside and are limiting in setting their narrow width values. On the other hand, the aperture-trench HTR is designed to disconnect the light-emitting layer EL, and the disconnection of the light-emitting layer EL is primarily related to the depth of the aperture-trench HTR. Therefore, to ensure that the width of the aperture-boundary portion THB is as small as possible, it is preferable that the width of the aperture-trench HTR is not greater than the width of the first inner dam DMI1 and / or the second inner dam DMI2.

[0121] Reference Figure 6 According to another embodiment of the present disclosure, an electroluminescent display device includes a through-hole TH within a display area. A first inner dam DMI1 surrounds the outer periphery of the through-hole TH. A second inner dam DMI2 surrounds the outer periphery of the first inner dam DMI1. A hole-trench HTR is arranged near the second inner dam DMI2. Although not shown, a pixel P, including an adjacent pixel Pc, is arranged near the hole-trench HTR.

[0122] according to Figure 6Multiple inner dams, including a first inner dam DMI1 and a second inner dam DMI2, are arranged to enhance their function. Additionally, a borehole-groove HTR is arranged to surround the second inner dam DMI2. Preferably, the width of the borehole-groove HTR is narrower than the width of the first inner dam DMI1 and the width of the second inner dam DMI2. The first inner dam DMI1 and the second inner dam DMI2 may have the same width, or their respective widths may differ from each other.

[0123] An electroluminescent display device according to one embodiment of this disclosure can be applied to a variety of products, such as televisions, laptops, monitors, refrigerators, microwave ovens, washing machines, and cameras, as well as portable electronic devices, such as electronic diaries, e-books, PMPs (portable multimedia players), navigators, UMPCs (ultra-mobile PCs), smartphones, mobile communication terminals, mobile phones, tablet computers (personal computers), smartwatches, watch phones, and wearable devices.

[0124] In addition, this disclosure also includes the following implementation methods.

[0125] Embodiment 1. An electroluminescent display device, comprising: a substrate having a display area and a non-display area surrounding the display area, the display area having a plurality of pixels for displaying an image; a through hole disposed in the display area; an inner dam surrounding the through hole; and a hole-groove surrounding the inner dam, the hole-groove being formed as the substrate is partially recessed by a certain thickness.

[0126] Embodiment 2. The electroluminescent display device according to Embodiment 1, wherein the display area includes: a light-emitting diode for displaying image information; and a driving element for driving the light-emitting diode, and wherein the through-hole is formed by removing the substrate, the light-emitting diode and the driving element.

[0127] Embodiment 3. The electroluminescent display device according to Embodiment 2, wherein the hole-trench comprises: a bottom surface defined at a position recessed to a certain depth than the upper surface of the substrate; an upper surface defined on the upper surface of the substrate; and a sidewall for connecting the bottom surface and the upper surface, wherein the light-emitting layer of the light-emitting diode is disposed on the bottom surface and the upper surface except for the sidewall.

[0128] Embodiment 4. The electroluminescent display device according to Embodiment 1, wherein the hole-trench has a well shape, the well shape being formed by removing at least 20% and at most 70% of the thickness of the substrate.

[0129] Embodiment 5. The electroluminescent display device according to Embodiment 1, wherein the hole-groove arrangement in the inner dam and the pixel is arranged between adjacent pixels close to the inner dam.

[0130] Embodiment 6. The electroluminescent display device according to Embodiment 1, wherein the hole-groove has a closed curve shape corresponding to the shape of the through hole.

[0131] Embodiment 7. The electroluminescent display device according to Embodiment 1, wherein the hole-groove has any one of a polygonal shape, a circular shape, and an elliptical shape surrounding the through hole.

[0132] Implementation Method 8. The electroluminescent display device according to Implementation Method 1, wherein the width of the hole-groove is narrower than the width of the inner dam.

[0133] Implementation 9. The electroluminescent display device according to Implementation 1, wherein the inner dam includes: a first inner dam adjacent to the through hole; and a second inner dam surrounding the first inner dam.

[0134] Implementation 10. The electroluminescent display device according to Implementation 9, wherein the hole-groove is arranged between the first inner dam and the second inner dam.

[0135] Embodiment 11. The electroluminescent display device according to Embodiment 1 further includes: a thin-film transistor layer formed on the substrate; a planarization layer covering the thin-film transistor layer; an anode electrode connected to a thin-film transistor disposed in the thin-film transistor layer and disposed on the planarization layer; and a dam defining a light-emitting region in the anode electrode, wherein the hole-trench passes through the dam, the planarization layer and the thin-film transistor layer, and the hole-trench is formed by removing a certain thickness from the substrate.

[0136] Embodiment 12. The electroluminescent display device according to Embodiment 11, wherein the inner dam further includes spacers arranged on the planarization layer and the embankment, the spacers surrounding the through hole.

[0137] Embodiment 13. The electroluminescent display device according to Embodiment 11 further includes: an outer dam disposed in the non-display area and surrounding the display area; a light-emitting layer covering the pixel, the inner dam, and the hole-trench on the substrate between the outer dam and the through hole; a cathode electrode disposed on the light-emitting layer; and an encapsulation layer covering the cathode electrode.

[0138] Embodiment 14. The electroluminescent display device according to Embodiment 13, wherein the light-emitting layer is exposed from the sidewall of the through hole.

[0139] Embodiment 15. The electroluminescent display device according to Embodiment 14, wherein the encapsulation layer comprises: a first inorganic encapsulation layer; an organic encapsulation layer disposed on the first inorganic encapsulation layer; and a second inorganic encapsulation layer disposed on the upper surface of the organic encapsulation layer.

[0140] It will be apparent to those skilled in the art that the above disclosure is not limited to the embodiments and drawings described above, and that various substitutions, modifications, and variations can be made without departing from the spirit or scope of the disclosure. Therefore, the scope of the disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of the disclosure.

[0141] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents granted by such claims. Therefore, the claims are not limited by this disclosure.

Claims

1. An electroluminescent display device, comprising: A substrate having a display area and a non-display area adjacent to the display area, the display area having a plurality of pixels for displaying an image; Thin-film transistors on the substrate; A light-emitting diode, which is electrically connected to the thin-film transistor, and includes a pixel driving electrode, a light-emitting layer, and a common electrode; An encapsulation layer disposed on the light-emitting diode includes a first inorganic layer, a second inorganic layer on the first inorganic layer, and an organic layer between the first inorganic layer and the second inorganic layer. A through-hole is provided in the display area, the through-hole penetrating the substrate and the encapsulation layer; A first inner dam surrounding the through-hole; as well as A hole-groove is disposed between the first inner dam and a group of adjacent pixels arranged closest to the first inner dam among the plurality of pixels. The hole-trench includes: The bottom surface is defined as the lowest surface of the recess formed in the substrate; The upper surface, defined as the uppermost surface of the layer disposed below the bottom surface of the first inner dam; and The sidewall is defined as a side surface connecting the bottom surface of the hole-groove and the upper surface of the hole-groove, and The light-emitting layer is in direct contact with the bottom surface of the hole-groove, is disposed on the upper surface of the hole-groove, and is disconnected at the sidewall of the hole-groove.

2. The electroluminescent display device according to claim 1, wherein, The first inorganic layer covers the bottom surface of the hole-trench and the sidewalls of the hole-trench.

3. The electroluminescent display device according to claim 2, wherein, The organic layer is disposed in the pore-trench to fill the interior portion of the pore-trench and is in contact with the first inorganic layer covering the bottom surface of the pore-trench.

4. The electroluminescent display device according to claim 3, wherein, The second inorganic layer is disposed on the organic layer and covers the first inner dam.

5. The electroluminescent display device according to claim 4, wherein, The second inorganic layer is in contact with the first inorganic layer on the upper surface and outer wall of the first inner dam.

6. The electroluminescent display device according to claim 3, wherein, The organic layer is in contact with a portion of the inner wall of the first inner dam.

7. The electroluminescent display device according to claim 1, wherein, The first inner dam is disposed between the hole-groove and the through hole.

8. The electroluminescent display device according to claim 1, wherein, The width of the hole-groove is narrower than the width of the first inner dam.

9. The electroluminescent display device according to claim 1, wherein, The common electrode is disposed on the bottom surface and the upper surface of the hole-trench, and is disconnected at the sidewall of the hole-trench.

10. The electroluminescent display device according to claim 1, wherein, The common electrode and the light-emitting layer are disposed between the bottom surface of the hole-trench and the first inorganic layer.

11. An electroluminescent display device, comprising: A substrate having a display area and a non-display area; Multiple pixels for displaying images and located in the display area, each pixel including a light-emitting diode, the light-emitting diode including a pixel driving electrode, a light-emitting layer and a common electrode; Encapsulation layer on the light-emitting diode; Through-holes in the display area; as well as Hole-groove disposed between the plurality of pixels and the via. The hole-trench includes: The bottom surface is defined as the lowest surface of the hole-trench formed in the substrate; The upper surface, defined as the uppermost surface of the layer having the entrance to the hole-groove; and The sidewall is defined as a side surface connecting the bottom surface of the hole-groove and the upper surface of the hole-groove, and The light-emitting layer is in direct contact with the bottom surface of the hole-groove, is disposed on the upper surface of the hole-groove, and is disconnected at the sidewall of the hole-groove.

12. The electroluminescent display device according to claim 11, wherein, The sidewalls of the hole-groove are completely perpendicular to at least one of the bottom and top surfaces of the hole-groove.

13. The electroluminescent display device according to claim 12, wherein, The width of the hole-groove is constant in the depth direction.

14. The electroluminescent display device according to claim 11, further comprising a first inner dam between the through hole and the hole-groove. in, The common electrode is on the upper surface and sidewall of the first inner dam and is disconnected at the entrance of the hole-groove.

15. The electroluminescent display device according to claim 11, wherein, The common electrode is disconnected at the hole-groove, and the disconnected end of the common electrode is tapered at the entrance of the hole-groove.

16. The electroluminescent display device according to claim 11, wherein, The common electrode on the bottom surface of the hole-trench completely covers the bottom surface of the hole-trench.

17. The electroluminescent display device according to claim 11, wherein, The encapsulation layer includes an inorganic layer and an organic layer on the inorganic layer, and The inorganic layer covering the sidewalls of the hole-groove is completely parallel to the sidewalls of the hole-groove.

18. The electroluminescent display device according to claim 17, wherein, Only the light-emitting layer, the common electrode, the inorganic layer, and the organic layer are located within the hole-trench.

19. The electroluminescent display device according to claim 11, wherein, The hole-groove is located in the display area.

20. The electroluminescent display device according to claim 11, wherein, The common electrode is disposed on the light-emitting layer at the bottom surface and the upper surface of the hole-trench, and the common electrode is disconnected at the sidewall of the hole-trench.

21. An electroluminescent display device, comprising: A substrate having a display area and a non-display area; A plurality of pixels configured to display an image and located in the display area, each of the plurality of pixels including a light-emitting diode having a pixel driving electrode, a light-emitting layer and a common electrode; An encapsulation layer disposed on the light-emitting diode; Through-holes in the display area; as well as Hole-groove disposed between the plurality of pixels and the via. The hole-trench includes: The bottom surface is defined as the lowest surface of the hole-trench formed in the substrate; The upper surface, defined as the uppermost surface of the layer having the entrance to the hole-groove; and The sidewall is defined as a side surface connecting the bottom surface of the hole-groove and the upper surface of the hole-groove, and In this embodiment, at least one of the light-emitting layer and the common electrode is disposed between the bottom surface of the hole-trench and the encapsulation layer, disposed on the upper surface of the hole-trench, and disconnected at the sidewall of the hole-trench.

22. The electroluminescent display device according to claim 21, wherein, The sidewalls of the hole-groove are completely perpendicular to at least one of the bottom surface and the top surface.

23. The electroluminescent display device according to claim 22, wherein, The width of the hole-groove is constant in the depth direction.

24. The electroluminescent display device according to claim 21, further comprising a first inner dam disposed between the through hole and the hole-groove. in, The common electrode is disposed on the upper surface of the first inner dam and on the side wall of the first inner dam, and the common electrode is disconnected at the entrance of the hole-groove.

25. The electroluminescent display device according to claim 24, further comprising a second inner dam surrounding the hole-groove.

26. The electroluminescent display device according to claim 24 further includes a second inner dam disposed between the first inner dam and the hole-groove.

27. The electroluminescent display device according to claim 21, wherein, The common electrode is disconnected at the hole-trench, and the disconnected end of the common circuit is tapered at the entrance of the hole-trench.

28. The electroluminescent display device according to claim 21, wherein, The portion of the common electrode disposed on the bottom surface of the hole-trench completely covers the bottom surface of the hole-trench.

29. The electroluminescent display device according to claim 21, wherein, The encapsulation layer includes an inorganic layer and an organic layer disposed on the inorganic layer, and The inorganic layer covering most of the sidewalls of the hole-trench is completely parallel to the sidewalls of the hole-trench.

30. The electroluminescent display device according to claim 29, wherein, Only the light-emitting layer, the common electrode, the inorganic layer, and the organic layer are located within the hole-trench.

31. The electroluminescent display device according to claim 21, wherein, The hole-groove is located in the display area.

32. The electroluminescent display device according to claim 21, wherein, The common electrode is disposed on the light-emitting layer at the bottom surface and the upper surface of the hole-groove, and the common electrode is disconnected at the sidewall of the hole-groove.

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