Display panel, display module and display device

Abstract

The invention discloses a display panel, a display module and a display device, and relates to the technical field of display. The at least two first electrode patterns in the display panel are connected, and one of the at least two connected first electrode patterns is connected with one first pixel circuit, so that one first pixel circuit can drive the two first electrode patterns. Meanwhile, the at least two second electrode patterns are connected, and one of the at least two connected second electrode patterns is connected with one second pixel circuit, so that one second pixel circuit can drive the two second electrode patterns. Therefore, under the condition that the number of the electrode patterns is the same, the scheme that one pixel circuit drives two electrode patterns is adopted, the number of pixel circuits needing to be designed in the second display area can be reduced, then the space occupied by each pixel circuit can be increased, and the process preparation difficulty is low.

Description

[0001] This application is a divisional application of Chinese application No. 202211193942.7, filed on September 28, 2022, entitled "Display Panel, Display Module and Display Device". Technical Field

[0002] This application relates to the field of display technology, and in particular to a display panel, display module and display device. Background Technology

[0003] Organic light-emitting diode (OLED) display panels have been widely used due to their advantages such as self-illumination, low driving voltage, and fast response speed. OLED display panels generally include multiple pixel units, each pixel unit comprising a light-emitting device and pixel circuitry connected to that light-emitting device.

[0004] In related technologies, to increase the screen-to-body ratio of a display panel, the camera of the display device can be placed in the display area of ​​the display panel. Furthermore, to increase the transmittance of the area where the camera is located, the pixel circuits of each pixel unit in that area (i.e., the camera area) are typically placed in a non-camera area. The pixel circuits located in the non-camera area are connected to the light-emitting devices located in the camera area via connecting traces, thereby providing driving signals to the light-emitting devices in the camera area to drive them to emit light.

[0005] However, since the pixel circuits connected to the light-emitting devices in the camera area need to be designed in the non-camera area, there may be a large number of pixel circuits that need to be designed in the non-camera area, which in turn will result in too little space for each pixel circuit and make it difficult to manufacture. Summary of the Invention

[0006] This application provides a display panel, a display module, and a display device, which can solve the problem of difficulty in manufacturing display panels in related technologies. The technical solution is as follows:

[0007] On one hand, a display panel is provided, the display panel comprising:

[0008] A substrate having a first display area and a second display area at least partially surrounding the first display area;

[0009] A driving circuit layer located on one side of the substrate, the driving circuit layer including a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area;

[0010] And a first electrode layer, the first electrode layer including at least a plurality of first type electrode patterns, the plurality of first type electrode patterns including a plurality of first electrode patterns located in the first display area and a plurality of second electrode patterns located in the second display area;

[0011] Wherein, at least two of the first electrode patterns are connected to one of the plurality of first pixel circuits, and at least two of the second electrode patterns are connected to one of the plurality of second pixel circuits.

[0012] Optionally, the display panel further includes:

[0013] Multiple first connection traces are located in the first display area;

[0014] Multiple second connection traces extend from the second display area to the first display area along the pixel row direction, and are located in both the first display area and the second display area;

[0015] Multiple third connection traces are located in the second display area;

[0016] Wherein, at least two first electrode patterns are connected by a first connection trace, and one of the at least two first electrode patterns is connected to a first pixel circuit by a second connection trace, at least two second electrode patterns are connected by a third connection trace, and one of the at least two second electrode patterns is connected to a second pixel circuit.

[0017] Optionally, the display panel further includes multiple fourth connection traces and multiple fifth connection traces, all of which extend from the second display area to the first display area along the pixel row direction; the first electrode layer further includes multiple second type electrode patterns and multiple third type electrode patterns;

[0018] The plurality of second-type electrode patterns include a plurality of third electrode patterns located in the first display area and a plurality of fourth electrode patterns located in the second display area. The third electrode pattern is connected to a first pixel circuit through a fourth connection trace, and the fourth electrode pattern is connected to a second pixel circuit.

[0019] The plurality of third-type electrode patterns include a plurality of fifth electrode patterns located in the first display area and a plurality of sixth electrode patterns located in the second display area; the fifth electrode patterns are connected to a first pixel circuit through the fifth connection trace.

[0020] Optionally, two adjacent first pixel circuits and three second pixel circuits constitute a circuit group; at least two second electrode patterns constitute an electrode pattern group, an adjacent electrode pattern group, a fourth electrode pattern and a sixth electrode pattern constitute a pattern group;

[0021] Each pattern group corresponds to one circuit group, and for the corresponding pattern group and circuit group, the area where the orthographic projection of the pattern group is located on the substrate overlaps with the area where the orthographic projection of the circuit group is located on the substrate.

[0022] Optionally, for each circuit group and a pattern group corresponding to the circuit group, of the three second pixel circuits included in the circuit group, the first second pixel circuit is connected to a second electrode pattern of the electrode pattern group in the pattern group, the second second pixel circuit is connected to a fourth electrode pattern in the pattern group, and the third second pixel circuit is connected to a sixth electrode pattern in the pattern group.

[0023] Optionally, a portion of the circuit group in the display panel includes two first pixel circuits connected to an electrode pattern located in the first display area, and another portion of the circuit group in the display panel includes two first pixel circuits connected to a fixed voltage terminal.

[0024] Optionally, the circuit group to which the first pixel circuit connected to the electrode pattern of the first display area belongs is closer to the first display area than the circuit group to which the first pixel circuit connected to the fixed voltage terminal belongs.

[0025] Optionally, the display panel includes red sub-pixels, green sub-pixels, and blue sub-pixels, wherein the sub-pixel to which the first type of electrode pattern belongs is a green sub-pixel, the sub-pixel to which the second type of electrode pattern belongs is a red sub-pixel, and the sub-pixel to which the third type of electrode pattern belongs is a blue sub-pixel.

[0026] Optionally, the length of any of the second connection traces along the pixel row direction is less than the length of the fourth connection trace along the pixel row direction and less than the length of the fifth connection trace along the pixel row direction.

[0027] Optionally, for each of the plurality of second connection traces, the plurality of fourth connection traces, and the plurality of fifth connection traces, the length of the connection trace along the pixel row direction is positively correlated with the distance between the electrode pattern located in the first display area and the second display area along the pixel row direction to which the connection trace is connected.

[0028] Optionally, the second display area includes a first sub-display area, a second sub-display area, and a third sub-display area. The first sub-display area and the first display area are arranged along the pixel column direction, the second sub-display area and the first display area are arranged along the pixel row direction, and the third sub-display area and the first sub-display area are arranged along the pixel row direction, and together with the second sub-display area, they are arranged along the pixel column direction.

[0029] The display panel further includes: a plurality of first data lines located in the first sub-display area, a plurality of second data lines located in the second sub-display area and the third sub-display area, and a plurality of first adapter lines located in the first sub-display area and the third sub-display area; the plurality of first data lines are arranged along the pixel row direction and extend along the pixel column direction, the plurality of second data lines are arranged along the pixel row direction and extend along the pixel column direction, and the plurality of first adapter lines are arranged along the pixel column direction and extend along the pixel row direction;

[0030] A first end of each of the first data lines is connected to a data driving circuit, a second end of each of the first data lines is connected to a first end of a first adapter line, and a second end of each of the first adapter lines is connected to a first end of a second data line; wherein, each of the first data lines is also connected to a column of second pixel circuits located in the first sub-display area for connecting a first target electrode pattern, and each of the second data lines is also connected to a column of first pixel circuits located in the second sub-display area for connecting a second target electrode pattern; the first target electrode pattern is at least one of a fourth electrode pattern and a sixth electrode pattern, and the second target electrode pattern is at least one of a third electrode pattern and a fifth electrode pattern.

[0031] Optionally, the first target electrode pattern is a fourth electrode pattern or a sixth electrode pattern, and the second target electrode pattern is a third electrode pattern or a fifth electrode pattern; the display panel further includes: multiple third data lines located in the first sub-display area, and multiple fourth data lines located in the second sub-display area and the third sub-display area;

[0032] The plurality of third data lines are arranged along the pixel row direction and extend along the pixel column direction. The first end of each third data line is used to connect to the data driving circuit, and each third data line is also connected to a column of second pixel circuits located in the first sub-display area for connecting the second electrode pattern.

[0033] The plurality of fourth data lines are arranged along the pixel row direction and extend along the pixel column direction. The first end of each fourth data line is used to connect to the data driving circuit, and each fourth data line is also connected to a column of first pixel circuits located in the second sub-display area for connecting the first electrode pattern.

[0034] Optionally, the second display area further includes: a fourth sub-display area and a fifth sub-display area, wherein the fourth sub-display area is located on the side of the first display area away from the first sub-display area, and the fifth sub-display area and the fourth sub-display area are arranged along the pixel row direction; the plurality of second data lines are also located in the fifth sub-display area; the display panel further includes: a plurality of second adapter cables, and a plurality of fifth data lines located in the fourth sub-display area;

[0035] The plurality of fifth data lines are arranged along the pixel row direction and extend along the pixel column direction, and the plurality of second adapter lines are arranged along the pixel column direction and extend along the pixel row direction; the second end of each second data line is connected to the first end of a second adapter line, and the second end of each second adapter line is connected to the first end of the fifth data line; the fifth data line is also connected to a column of second pixel circuits located in the fourth sub-display area for connecting the first target electrode pattern.

[0036] Optionally, the display panel further includes: a plurality of first dummy data lines located in the third sub-display area;

[0037] The plurality of first dummy data lines are arranged along the pixel row direction and extend along the pixel column direction. The first dummy data lines are used to connect to a fixed voltage terminal, and the first dummy data lines are also connected to a column of first pixel circuits located in the third sub-display area.

[0038] Optionally, the second display area further includes: a sixth sub-display area, the sixth sub-display area being located on the side of the third sub-display area away from the first sub-display area; the display panel further includes: a plurality of seventh data lines located in the sixth sub-display area, and a plurality of second dummy data lines located in the sixth sub-display area;

[0039] The plurality of seventh data lines are arranged along the pixel row direction and extend along the pixel column direction. Each of the seventh data lines is used to connect to the data driving circuit, and each of the seventh data lines is also connected to a column of second pixel circuits located in the sixth sub-display area.

[0040] The plurality of second dummy data lines are arranged along the pixel row direction and extend along the pixel column direction. Each second dummy data line is used to connect to a fixed voltage terminal, and the second dummy data line is also connected to a column of first pixel circuits located in the sixth display area.

[0041] Optionally, the third connection trace is located on the same layer as the first electrode layer, and both the first connection trace and the second connection trace are located between the driving circuit layer and the first electrode layer.

[0042] On the other hand, a display module is provided, characterized in that the display module includes a data driving circuit and a display panel as described above;

[0043] The data driving circuit is connected to the first data line, the third data line, the fourth data line, and the seventh data line in the display panel.

[0044] In another aspect, a display device is provided, the display device including the display module and optical sensor described above, wherein the orthographic projection of the optical sensor on the display panel at least partially overlaps with a first display area of ​​the display panel.

[0045] The beneficial effects of the technical solution provided in this application include at least the following:

[0046] This application provides a display panel, a display module, and a display device. Since at least two first electrode patterns are connected in the display panel, and one of the connected first electrode patterns is connected to a first pixel circuit, one first pixel circuit can drive two first electrode patterns. Simultaneously, since at least two second electrode patterns are connected, and one of the connected second electrode patterns is connected to a second pixel circuit, one second pixel circuit can drive two second electrode patterns. Therefore, with the same number of electrode patterns, using a scheme where one pixel circuit drives two electrode patterns reduces the number of pixel circuits required in the second display area, thereby increasing the space occupied by each pixel circuit and reducing the difficulty of fabrication. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a partial structural diagram of a display panel provided in an embodiment of this application;

[0049] Figure 2 yes Figure 1 A partially enlarged schematic diagram of the display panel shown;

[0050] Figure 3 This is a top view of a substrate provided in an embodiment of this application;

[0051] Figure 4 This is a partial cross-sectional view of a display panel provided in an embodiment of this application;

[0052] Figure 5 This is a partial schematic diagram of the first electrode layer in a second display area provided in an embodiment of this application;

[0053] Figure 6 This is a partial schematic diagram of a first electrode layer in a first display area provided in an embodiment of this application;

[0054] Figure 7 This is a partial schematic diagram of a first pattern row in a first display area provided in an embodiment of this application;

[0055] Figure 8 This is a partial structural diagram of another display panel provided in an embodiment of this application;

[0056] Figure 9 yes Figure 8 A partially enlarged schematic diagram of the display panel shown;

[0057] Figure 10 This is a schematic diagram of a data cable, adapter cable, and dummy data cable for a display panel provided in an embodiment of this application;

[0058] Figure 11 This is a schematic diagram of another display panel data cable, adapter cable, and dummy data cable provided in an embodiment of this application;

[0059] Figure 12 This is a schematic diagram provided in an embodiment of the present application, showing a display panel in which the first pixel circuit is not designed;

[0060] Figure 13 This is a schematic diagram of a two-to-one pixel circuit design provided in an embodiment of this application;

[0061] Figure 14 This is a schematic diagram of a circuit assembly provided in an embodiment of this application;

[0062] Figure 15 This is a schematic diagram of another circuit assembly provided in an embodiment of this application;

[0063] Figure 16 This is an equivalent circuit diagram of a first pixel circuit or a second pixel circuit provided in an embodiment of this application;

[0064] Figure 17 This is a partial schematic diagram of a semiconductor layer in a display panel provided in an embodiment of this application;

[0065] Figure 18 This is a partial schematic diagram of the first gate layer in a display panel provided in an embodiment of this application;

[0066] Figure 19 This is a schematic diagram of a partial superposition of a semiconductor layer and a first gate layer in a display panel, provided by an embodiment of this application.

[0067] Figure 20 This is a partial schematic diagram of the second gate layer in a display panel provided in an embodiment of this application;

[0068] Figure 21 This is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, and a second gate layer in a display panel provided in an embodiment of this application;

[0069] Figure 22 This is a partial schematic diagram of an interlayer dielectric layer in a display panel provided in an embodiment of this application;

[0070] Figure 23 This is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, and an interlayer dielectric layer in a display panel provided in an embodiment of this application;

[0071] Figure 24 This is a partial schematic diagram of the first source-drain layer in a display panel provided in an embodiment of this application;

[0072] Figure 25 This is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, and a first source / drain layer in a display panel, provided in an embodiment of this application.

[0073] Figure 26 This is a partial schematic diagram of a passivation layer in a display panel provided in an embodiment of this application;

[0074] Figure 27 This is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source / drain layer, and a passivation layer in a display panel, provided in an embodiment of this application.

[0075] Figure 28 This is a partial schematic diagram of an intermediate source / drain layer in a display panel provided in an embodiment of this application;

[0076] Figure 29 This is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, and an intermediate source-drain layer in a display panel, provided by an embodiment of this application.

[0077] Figure 30 This is a partial schematic diagram of a first planarization layer in a display panel provided in an embodiment of this application;

[0078] Figure 31 This is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, an intermediate source-drain layer, and a first planarization layer in a display panel, provided by an embodiment of this application.

[0079] Figure 32 This is a partial schematic diagram of a second source / drain layer in a display panel provided in an embodiment of this application;

[0080] Figure 33 This is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, an intermediate source-drain layer, a first planarization layer, and a second source-drain layer in a display panel, provided by an embodiment of this application.

[0081] Figure 34 This is a partial schematic diagram of a second planarization layer in a display panel provided in an embodiment of this application;

[0082] Figure 35 This is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, an intermediate source-drain layer, a first planarization layer, a second source-drain layer, and a second planarization layer in a display panel, provided by an embodiment of this application.

[0083] Figure 36 This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application;

[0084] Figure 37 This is a partial schematic diagram of the first conductive layer in a display panel provided in an embodiment of this application;

[0085] Figure 38 This is a partial superimposed schematic diagram of a first conductive layer formed in a display panel, provided in an embodiment of this application;

[0086] Figure 39 This is a partial schematic diagram of the first insulating layer in a display panel provided in an embodiment of this application;

[0087] Figure 40 This is a partial superimposed schematic diagram of a first insulating layer formed in a display panel, provided in an embodiment of this application;

[0088] Figure 41 This is a partial schematic diagram of a second conductive layer in a display panel provided in an embodiment of this application;

[0089] Figure 42This is a partial superimposed schematic diagram of a second conductive layer formed in a display panel, provided in an embodiment of this application;

[0090] Figure 43 This is a partial schematic diagram of a second insulating layer in a display panel provided in an embodiment of this application;

[0091] Figure 44 This is a partial superimposed schematic diagram of a second insulating layer formed in a display panel, provided by an embodiment of this application;

[0092] Figure 45 This is a partial schematic diagram of a third conductive layer in a display panel provided in an embodiment of this application;

[0093] Figure 46 This is a partial superimposed schematic diagram of a third conductive layer formed in a display panel, provided by an embodiment of this application;

[0094] Figure 47 This is a partial schematic diagram of a third insulating layer in a display panel provided in an embodiment of this application;

[0095] Figure 48 This is a partial superimposed schematic diagram of a third insulating layer formed in a display panel, provided in an embodiment of this application;

[0096] Figure 49 This is a partial schematic diagram of the first electrode layer in a display panel provided in an embodiment of this application;

[0097] Figure 50 This is a partial superimposed schematic diagram of a first electrode layer formed in a display panel, provided by an embodiment of this application;

[0098] Figure 51 This is a partial schematic diagram of a pixel delimiting layer in a display panel provided in an embodiment of this application;

[0099] Figure 52 This is a partial overlay diagram provided in an embodiment of the present application, showing a pixel delimiting layer formed in a display panel.

[0100] Figure 53 This is a partial schematic diagram of a conductive layer in a display panel provided in an embodiment of this application;

[0101] Figure 54 This is a schematic diagram of the structure of a display module provided in an embodiment of this application;

[0102] Figure 55 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0103] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0104] This application provides a display panel, which can be, for example, an organic light-emitting diode (OLED) display panel, a micro organic light-emitting diode (Micro OLED) display panel, a quantum dot organic light-emitting diode (QLED) display panel, a mini light-emitting diode (Mini LED) display panel, or a micro light-emitting diode (Micro LED) display panel, etc. The following description uses an OLED display panel as an example.

[0105] Figure 1 This is a partial structural diagram of a display panel provided in an embodiment of this application. Figure 2 yes Figure 1 A partially enlarged schematic diagram of the display panel shown. Figure 3 This is a top view of a substrate provided in an embodiment of this application. Figure 4 This is a partial cross-sectional view of a display panel provided in an embodiment of this application. Combined with... Figures 1 to 4 The display panel 10 may include a substrate 101, a driving circuit layer 102 located on one side of the substrate 101, and a first electrode layer 103.

[0106] The substrate 101 has a first display area 101a and a second display area 101b that at least partially surrounds the first display area 101a. The first display area 101a can be an under-display camera area (full display with camera, FDC). The first display area 101a can be a circular area or a square area.

[0107] The driving circuit layer 102 includes a plurality of first pixel circuits A1 and a plurality of second pixel circuits A2 located in the second display area 101b. Figure 3 The diagram shows a first pixel circuit A1 and a second pixel circuit A2.

[0108] The first electrode layer 103 includes at least a plurality of first-type electrode patterns 1031, including a plurality of first electrode patterns 1031a located in the first display area 101a and a plurality of second electrode patterns 1031b located in the second display area 101b. The display panel 10 includes a plurality of sub-pixels of different colors. Each sub-pixel may include a light-emitting device and a pixel circuit for controlling the light emission of the light-emitting device. The brightness (grayscale) of the sub-pixels of different colors can be adjusted through the pixel circuit. Multiple colors can be displayed through color combination and superposition, thereby achieving full-color display of the display panel 10. The light-emitting device may include an electrode pattern. The colors of the light emitted by the sub-pixels to which the plurality of first-type electrode patterns 1031 belong may be the same.

[0109] At least two first electrode patterns 1031a are connected to one of a plurality of first pixel circuits A1. This allows one first pixel circuit A1 to provide data driving signals to the two first electrode patterns 1031a. Furthermore, at least two second electrode patterns 1031b are connected to one of a plurality of second pixel circuits A2. This allows one second pixel circuit A2 to provide data driving signals to the two second electrode patterns 1031b.

[0110] In this embodiment, at least two first electrode patterns 1031a in the first display area 101a can be driven by a first pixel circuit A1 located in the second display area 101b, and at least two second electrode patterns 1031b in the second display area 101b can be driven by a second pixel circuit A2 located in the second display area 101b. Therefore, when the number of electrode patterns is the same, using one pixel circuit to drive two electrode patterns reduces the number of pixel circuits required in the second display area 101b compared to using one pixel circuit to drive one electrode pattern, thereby increasing the space occupied by each pixel circuit and reducing the difficulty of fabrication.

[0111] In summary, the embodiments of this application provide a display panel. Since at least two first electrode patterns are connected in the display panel, and one of the connected first electrode patterns is connected to a first pixel circuit, one first pixel circuit can drive two first electrode patterns. Simultaneously, since at least two second electrode patterns are connected, and one of the connected second electrode patterns is connected to a second pixel circuit, one second pixel circuit can drive two second electrode patterns. Therefore, with the same number of electrode patterns, using a scheme where one pixel circuit drives two electrode patterns reduces the number of pixel circuits required in the second display area, thereby increasing the space occupied by each pixel circuit and reducing the difficulty of fabrication.

[0112] In some embodiments, the portions of the substrate 101 and the driving circuit layer 102 located in the first display area 101a have higher light transmittance. For example, the substrate 101 can be a transparent glass substrate, providing high transparency. The driving circuit layer 102 does not have any circuit structures in the first display area 101a (i.e., both the first pixel circuit A1 and the second pixel circuit A2 are located in the second display area 101b, but not in the first display area 101a), maintaining sufficient transparency for the driving circuit layer 102. In the display device, a sensor, such as a camera, proximity sensor, 3D sensing module, or other optical sensor, can be disposed on the side of the substrate 101 away from the driving circuit layer 102, and the orthographic projection of the sensor onto the substrate 101 is located in the first display area 101a. The photosensitive surface of the optical sensor faces the display surface of the display panel 10 and is used to receive ambient light from the display surface of the display panel 10. For example, the first electrode pattern 1031a located in the first display area 101a of the first electrode layer 103 is made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), thereby making the light transmittance of the first display area 101a high, suitable for placing devices with high transmittance requirements such as cameras. Thus, the display panel 10 can achieve full-screen display in the display area. An optical sensor is set in the first display area 101a, and the optical sensor can receive external light through the film layer in the first display area 101a to achieve corresponding functions.

[0113] refer to Figure 1 and Figure 2 The display panel 10 may further include: multiple first connection lines L1, multiple second connection lines L2, and multiple third connection lines L3. The multiple first connection lines L1 are located in the first display area 101a. The multiple second connection lines L2 extend from the second display area 101b to the first display area 101a along the pixel row direction X, and are located in both the first display area 101a and the second display area 101b. The multiple third connection lines L3 are located in the second display area 101b.

[0114] At least two first electrode patterns 1031a are connected by a first connection trace L1, and one of the at least two first electrode patterns 1031a is connected to a first pixel circuit A1 via a second connection trace L2. This allows the first pixel circuit A1 to provide data driving signals to the two first electrode patterns 1031a. Furthermore, at least two second electrode patterns 1031b are connected by a third connection trace L3, and one of the at least two second electrode patterns 1031b is connected to a second pixel circuit A2. This allows the second pixel circuit A2 to provide data driving signals to the two second electrode patterns 1031b.

[0115] In the embodiments of this application, reference is made to Figure 1 and Figure 2 The display panel 10 also includes multiple fourth connection traces L4 and multiple fifth connection traces L5. Both the multiple fourth connection traces L4 and the multiple fifth connection traces L5 extend along the pixel row direction X from the second display area 101b to the first display area 101a. Figure 1 , Figure 5 as well as Figure 6 The first electrode layer 103 further includes a plurality of second-type electrode patterns 1032 and a plurality of third-type electrode patterns 1033. The plurality of second-type electrode patterns 1032 include a plurality of third-type electrode patterns 1032a located in the first display area 101a and a plurality of fourth-type electrode patterns 1032b located in the second display area 101b. The plurality of third-type electrode patterns 1033 include a plurality of fifth-type electrode patterns 1033a located in the first display area 101a and a plurality of sixth-type electrode patterns 1033b located in the second display area 101b.

[0116] In this configuration, the third electrode pattern 1032a is connected to a first pixel circuit A1 via a fourth connection trace L4, and the fourth electrode pattern 1032b is connected to a second pixel circuit A2. The fifth electrode pattern 1033a is connected to a first pixel circuit A1 via a fifth connection trace L5, and the sixth electrode pattern 1033b is connected to a second pixel circuit A2. That is, each of the multiple third electrode patterns 1032a and multiple fifth electrode patterns 1033a is driven by a first pixel circuit A1. Each of the multiple fourth electrode patterns 1032b and multiple sixth electrode patterns 1033b is driven by a second pixel circuit A2.

[0117] In the embodiments of this application, reference is made to Figure 7In the first display area 101a, multiple first electrode patterns 1031a, multiple third electrode patterns 1032a, and multiple fifth electrode patterns 1033a can be arranged in multiple rows. A row of electrode patterns is referred to as a first pattern row M. At least one first pattern row M includes at least two first electrode patterns 1031a, at least one third electrode pattern 1032a, and at least one fifth electrode pattern 1033a arranged in a row. At least two first electrode patterns 1031a in the first pattern row M are connected via a first connection trace L1.

[0118] Optionally, the first pattern row M is arranged cyclically in the order of third electrode pattern 1032a, first electrode pattern 1031a, fifth electrode pattern 1033a, and first electrode pattern 1031a. For example, multiple first pattern rows M are arranged in multiple rows, each first pattern row M including a first sub-pattern row M1 and a second sub-pattern row M2 arranged in parallel. In the first sub-pattern row M1, the third electrode pattern 1032a and the fifth electrode pattern 1033a are alternately arranged, and in the second sub-pattern row M2, multiple first electrode patterns 1031a are arranged sequentially. The number of first electrode patterns 1031a in the second sub-pattern row M2 is the same as the total number of third electrode patterns 1032a and fifth electrode patterns 1033a in the second sub-pattern row M2, and the first electrode pattern 1031a is located on the central axis of the adjacent third electrode pattern 1032a and fifth electrode pattern 1033a.

[0119] Additionally, in the second display area 101b, multiple second electrode patterns 1031b, multiple fourth electrode patterns 1032b, and multiple sixth electrode patterns 1033b can be arranged in multiple rows. A row of electrode patterns is called a second pattern row (not shown in the figure). At least one second pattern row includes at least two second electrode patterns 1031b, at least one fourth electrode pattern 1032b, and at least one sixth electrode pattern 1033b arranged in a row. At least two second electrode patterns 1031b in a second pattern row are connected via a third connection trace L3.

[0120] Optionally, the second pattern rows are arranged cyclically in the order of fourth electrode pattern 1032b, second electrode pattern 1031b, sixth electrode pattern 1033b, and second electrode pattern 1031b. For example, multiple second pattern rows are arranged in multiple rows, each second pattern row including a third sub-pattern row and a fourth sub-pattern row arranged in parallel. In the third sub-pattern row, the fourth electrode pattern 1032b and the sixth electrode pattern 1033b are alternately arranged, and in the fourth sub-pattern row, multiple second electrode patterns 1031b are arranged sequentially. The number of second electrode patterns 1031b in the fourth sub-pattern row is the same as the total number of fourth electrode patterns 1032b and sixth electrode patterns 1033b in the third sub-pattern row, and the second electrode patterns 1031b are located on the central axis of their adjacent fourth electrode patterns 1032b and sixth electrode patterns 1033b.

[0121] Of course, the multiple first electrode patterns 1031a, multiple third electrode patterns 1032a, and multiple fifth electrode patterns 1033a can also be arranged in multiple columns, and the multiple second electrode patterns 1031b, multiple fourth electrode patterns 1032b, and multiple sixth patterns can also be arranged in multiple columns. The arrangement in multiple columns is similar to the arrangement in multiple rows, and will not be described again in the embodiments of this application.

[0122] In this embodiment, the sub-pixels belonging to multiple second-type electrode patterns 1032 can emit light of the same color, and the sub-pixels belonging to multiple third-type electrode patterns 1033 can emit light of the same color. For example, the sub-pixels belonging to multiple first-type electrode patterns 1031 can be green sub-pixels, emitting green light. The sub-pixels belonging to multiple second-type electrode patterns 1032 can be either red or blue sub-pixels, and the sub-pixels belonging to multiple third-type electrode patterns 1033 can be either red or blue sub-pixels. For instance, the sub-pixels belonging to multiple second-type electrode patterns 1032 can be red sub-pixels, and the sub-pixels belonging to multiple third-type electrode patterns 1032 can be blue sub-pixels. The red sub-pixels emit red light, and the blue sub-pixels emit blue light. That is, in this embodiment, one pixel circuit is used to drive two green sub-pixels, and one pixel circuit is used to drive one red sub-pixel or one blue sub-pixel.

[0123] In the embodiments of this application, reference is made to Figure 1Two adjacent first pixel circuits A1 and three adjacent second pixel circuits A2 constitute a circuit group A. At least two second electrode patterns 1031b constitute an electrode pattern group, and an adjacent electrode pattern group, a fourth electrode pattern 1032b, and a sixth electrode pattern 1033b constitute a pattern group B. Each pattern group B corresponds to a circuit group A, and for the corresponding pattern group B and circuit group A, the area where the orthographic projection of pattern group B is located on the substrate 101 overlaps with the area where the orthographic projection of circuit group A is located on the substrate 101.

[0124] Optionally, each circuit group A and its corresponding pattern group B occupy space equivalent to that of pattern group B (four electrode patterns). That is, five pixel circuits are arranged below the four electrode patterns.

[0125] For each circuit group A and its corresponding pattern group B, of the three second pixel circuits A2 included in circuit group A, the first second pixel circuit A2 is connected to a second electrode pattern 1031b of the electrode pattern group in pattern group B, the second second pixel circuit A2 is connected to a fourth electrode pattern 1032b of pattern group B, and the third second pixel circuit A2 is connected to a sixth electrode pattern 1033b of pattern group B. That is, of the five pixel circuits included in each circuit group A, three of the second pixel circuits A2 can serve as pixel circuits driving the four electrode patterns in pattern group B located in the second display area 101b.

[0126] Furthermore, in a portion of the circuit groups A in the display panel 10, two first pixel circuits A1 are connected to the electrode pattern located in the first display area 101a, while in another portion of the circuit groups A, two first pixel circuits A1 are connected to a fixed voltage terminal. That is, in some circuit groups A of the display panel 10, two first pixel circuits A1 can function as pixel circuits driving the electrode pattern located in the first display area 101a, while the two first pixel circuits A1 in the remaining circuit groups A are not connected to the electrode pattern in the first display area 101a, but rather function as dummy pixel circuits connected to the fixed voltage terminal. Because the dummy pixel circuits are connected to the fixed voltage terminal, the dummy pixel circuits can avoid affecting the signals transmitted by the various signal lines in the display panel 10, thus ensuring the display effect of the display panel 10.

[0127] In this embodiment, the circuit group A to which the first pixel circuit A1, connected to the electrode pattern of the first display area 101a, belongs, is closer to the first display area 101a than the circuit group A to which the first pixel circuit A1, connected to the fixed voltage terminal, belongs. This allows for a shorter length of the second connection trace L2 connecting the electrode pattern in the first display area 101a and the first pixel circuit A1 in the second display area 101b, improving the reliability of signal transmission via the second connection trace L2 and ensuring the display effect of the display panel 10.

[0128] In this embodiment, a first pixel circuit A1 provides data driving signals to two first electrode patterns 1031a. If the length of the second connection trace L2 connecting the first pixel circuit A1 and the two first electrode patterns 1031a is too long, it is easily subject to resistor-capacitor interference, causing the sub-pixel to which the first electrode pattern 1031a belongs to to fail to light up at low gray levels.

[0129] Therefore, refer to Figure 1 and Figure 2 The length of any second connection trace L2 along the pixel row direction X is less than the length of the fourth connection trace L4 along the pixel row direction X, and less than the length of the fifth connection trace L5 along the pixel row direction X. That is, relative to the third electrode pattern 1032a and the fifth electrode pattern 1033a, the first electrode pattern 1031a can preferentially be connected to the first pixel circuit A1 of the second display area 101b via the second connection trace L2. This reduces the length of the second connection trace L2 connected to the first electrode pattern 1031a, weakens the interference intensity of the second connection trace L2 caused by resistors and capacitors, and ensures that each sub-pixel in the first display area 101a can be displayed normally at low grayscale levels.

[0130] Of course, for reference Figure 8 and Figure 9 Each of the multiple second connection lines L2, multiple fourth connection lines L4, and multiple fifth connection lines L5 has a length along the pixel row direction X that is positively correlated with the distance along the pixel row direction X between the electrode pattern located in the first display area 101a and the second display area 101b to which the connection line is connected. That is, the electrode pattern located in the first display area 101a is sequentially connected to the first pixel circuit A1 of the second display area 101b via the second connection lines L2.

[0131] refer to Figure 3The second display area 101b may include a first sub-display area 101b1, a second sub-display area 101b2, and a third sub-display area 101b3. The first sub-display area 101b1 and the first display area 101a are arranged along the pixel column direction Y, the second sub-display area 101b2 and the first display area 101a are arranged along the pixel row direction X, and the third sub-display area 101b3 and the first sub-display area 101b1 are arranged along the pixel row direction X, and the second sub-display area 101b2 is arranged along the pixel column direction Y.

[0132] The second display area 101b may include one first sub-display area 101b1, two second sub-display areas 101b2, and two third sub-display areas 101b3. The first sub-display area 101b1 may be located below the first display area 101a. The two second sub-display areas 101b2 may be located on both sides of the first display area 101a along the pixel row direction X, and the two third sub-display areas 101b3 may be located on both sides of the first sub-display area 101b1 along the pixel row direction X. Both the second sub-display areas 101b2 and the third sub-display areas 101b3 can serve as transition display areas for the display panel.

[0133] refer to Figure 10 The display panel 10 may further include: multiple first data lines S1 located in the first sub-display area 101b1, multiple second data lines S2 located in the second sub-display area 101b2 and the third sub-display area 101b3, and multiple first adapter lines Z1 located in the first sub-display area 101b1 and the third sub-display area 101b3.

[0134] In this configuration, multiple first data lines S1 are arranged along the pixel row direction X and extend along the pixel column direction Y; multiple second data lines S2 are arranged along the pixel row direction X and extend along the pixel column direction Y; and multiple first adapter lines Z1 are arranged along the pixel column direction Y and extend along the pixel row direction X. The first end of each first data line S1 is connected to the data driving circuit; the second end of each first data line S1 is connected to the first end of a first adapter line Z1; and the second end of each first adapter line Z1 is connected to the first end of a second data line S2. This allows the data driving signal provided by the data driving circuit to be transmitted through the first data lines S1, the first adapter lines Z1, and the second data lines S2, and the data driving signal transmitted by a connected first data line S1, a first adapter line Z1, and a second data line S2 is the same.

[0135] Compared to the boundary of the third sub-display area 101b3, which is farther away from the boundary of the second sub-display area 101b2, the first end of the second data line S2 is closer to the boundary of the third sub-display area 101b3, which is closer to the boundary of the second sub-display area 101b2. That is, the length of the second data line S2 along the pixel column direction Y can be slightly greater than the length of the second sub-display area 101b2 along the pixel column direction Y, as long as the first end of the second data line S2 can be located in the third sub-display area 101b3, thus facilitating the connection between the first end of the second data line S2 in the third sub-display area 101b3 and the second end of the first adapter cable Z1 in the third sub-display area 101b3.

[0136] Each first data line S1 is also connected to a column of second pixel circuits A2 located in the first sub-display area 101b1 for connecting the first target electrode pattern, and each second data line S2 is also connected to a column of first pixel circuits A1 located in the second sub-display area 101b2 for connecting the second target electrode pattern.

[0137] For the first data line S1 and the second data line S2 connected by a first adapter cable Z1, the first data line S1 is connected to a column of first target electrode patterns via a column of second pixel circuits A2, and the second data line S2 is connected to a column of second target electrode patterns via a column of first pixel circuits A1, which can be arranged along the pixel column direction Y. This allows electrode patterns located in the same column in the first display area 101a and the first sub-display area 101b1 to receive the same data driving signal.

[0138] In the embodiments of this application, the first target electrode pattern is at least one of the fourth electrode pattern 1032b and the sixth electrode pattern 1033b, and the second target electrode pattern is at least one of the third electrode pattern 1032a and the fifth electrode pattern 1033a.

[0139] As a first optional implementation, the first target electrode pattern is either the fourth electrode pattern 1032b or the sixth electrode pattern 1033b, and the second target electrode pattern is either the third electrode pattern 1032a or the fifth electrode pattern 1033a. (See reference) Figure 10The display panel 10 may further include: a plurality of third data lines S3 located in the first sub-display area 101b1, and a plurality of fourth data lines S4 located in the second display area 101b and the third sub-display area 101b3. The plurality of third data lines S3 are arranged along the pixel row direction X and extend along the pixel column direction Y, and the plurality of fourth data lines S4 are arranged along the pixel row direction X and extend along the pixel column direction Y. The first end of each third data line S3 and the first end of each fourth data line S4 are used to connect to a data driving circuit. Each third data line S3 is also connected to a column of second pixel circuits A2 located in the first sub-display area 101b1 for connecting the second electrode pattern 1031b, and each fourth data line S4 is also connected to a column of first pixel circuits A1 located in the second sub-display area 101b2 for connecting the first electrode pattern 1031a.

[0140] That is, the data driving signal provided by the data driving circuit can be transmitted through the third data line S3 to a column of second pixel circuits A2 located in the first sub-display area 101b1, thereby driving a column of second electrode patterns 1031b connected to the column of second pixel circuits A2. Furthermore, the data driving signal provided by the data driving circuit can be transmitted through the fourth data line S4 to a column of first pixel circuits A1 located in the second sub-display area 101b2, thereby driving a column of first electrode patterns 1031a connected to the column of first pixel circuits A1.

[0141] In this first implementation, the data driving signals obtained from the second type of electrode patterns 1032 (third electrode pattern 1032a and fourth electrode pattern 1032b) located in the same column on the display panel 10 are transmitted via a first adapter cable Z1. The data driving signals obtained from the third type of electrode patterns 1033 (fifth electrode pattern 1033a and sixth electrode pattern 1033b) located in the same column are also transmitted via the first adapter cable Z1. The data driving signals obtained from the first type of electrode patterns 1031 (first electrode pattern 1031a and second electrode pattern 1031b) located in the same column are transmitted directly via the data line (third data line S3 or fourth data line S4) connected to the data driving circuit, without the need for the first adapter cable Z1. This reduces the length of the data line connected to the first type of electrode pattern 1031 (in the transmission scheme, the length of the data line is the total length of the connected data lines and the adapter cable), thereby reducing the resistance and capacitance of the data line, improving the driving capability of the pixel circuit, and optimizing the display effect.

[0142] refer to Figure 3The second display area 101b may further include a fourth sub-display area 101b4 and a fifth sub-display area 101b5. The fourth sub-display area 101b4 is located on the side of the first display area 101a away from the first sub-display area 101b1, and the fifth sub-display area 101b5 and the fourth sub-display area 101b4 are arranged along the pixel row direction X. For example, the second display area 101b may include one fourth sub-display area 101b4 and two fifth sub-display areas 101b5. The fourth sub-display area 101b4 may be located above the first display area 101a, and the two fifth sub-display areas 101b5 are respectively located on both sides of the fourth sub-display area 101b4 along the pixel row direction X. This fifth sub-display area 101b5 may be referred to as a transition display area.

[0143] Optionally, the first display area 101a can be located inside the second display area 101b, and the second display area 101b can completely surround the first display area 101a. Therefore, in order to transmit data drive signals to the fourth sub-display area 101b4, which is away from the first sub-display area 101b1 and located away from the first sub-display area 101b1, the display panel 10 can include: multiple second adapter lines Z2, multiple third adapter lines Z3, multiple fifth data lines S5, and multiple sixth data lines S6 located in the fourth sub-display area 101b4. The multiple fifth data lines S5 are arranged along the pixel row direction X and extend along the pixel column direction Y, and the multiple sixth data lines S6 are arranged along the pixel row direction X and extend along the pixel column direction Y. The multiple second adapter lines Z2 are arranged along the pixel column direction Y and extend along the pixel row direction X, and the multiple third adapter lines Z3 are arranged along the pixel column direction Y and extend along the pixel row direction X.

[0144] The second end of each second data line S2 is connected to the first end of a second adapter line Z2, and the second end of each second adapter line Z2 is connected to the first end of a fifth data line S5. The fifth data line S5 is also connected to a column of second pixel circuits A2 located in the fourth sub-display area 101b4 for connecting the first target electrode pattern. The second end of each fourth data line S4 is connected to the first end of a third adapter line Z3, and the second end of each third adapter line Z3 is connected to the first end of a sixth data line S6. The sixth data line S6 is also connected to a column of second pixel circuits A2 located in the fourth sub-display area 101b4 for connecting the second electrode pattern 1031b. Thus, the data driving circuit can sequentially provide data driving signals to the column of second pixel circuits A2 located in the fourth sub-display area 101b4 for connecting the first target electrode pattern via the first data line S1, the first adapter line Z1, the second data line S2, the second adapter line Z2, and the fifth data line S5. The data driving circuit sequentially provides data driving signals to a column of second pixel circuits A2 located in the fourth sub-display area 101b4, which are used to connect to the second electrode pattern 1031b, via the fourth data line S4, the third adapter line Z3, and the sixth data line S6. That is, in this scheme, each second pixel circuit A2 in the fourth sub-display area 101b4 needs to obtain data driving signals through adapter signals.

[0145] refer to Figure 3 The substrate 101 also has a peripheral region 101c surrounding the second display area 101b. The second ends of multiple second data lines S2, multiple second adapter lines Z2, the first ends of multiple fifth data lines S5, the second ends of multiple fourth data lines S4, multiple third adapter lines Z3, and the first ends of multiple sixth data lines S6 can all be located in the peripheral region 101c, and in the area of ​​the fourth sub-display area 101b4 away from the first display area 101a. That is, the connection points of the second data lines S2 and the second adapter lines Z2, the connection points of the second adapter lines Z2 and the fifth data lines S5, the connection points of the fourth data lines S4 and the third adapter lines Z3, and the connection points of the third adapter lines Z3 and the sixth data lines S6 can all be located in the peripheral region 101c.

[0146] As a second optional implementation, the first target electrode pattern is one of the second electrode pattern 1031b, the fourth electrode pattern 1032b and the sixth electrode pattern 1033b, and the second target electrode pattern is one of the first electrode pattern 1031a, the third electrode pattern 1032a and the fifth electrode pattern 1033a.

[0147] In this second implementation, the data driving signals obtained from the second type of electrode patterns 1032 (third electrode pattern 1032a and fourth electrode pattern 1032b) located in the same column on the display panel 10 are transmitted via the first adapter cable Z1. The data driving signals obtained from the third type of electrode patterns 1033 (fifth electrode pattern 1033a and sixth electrode pattern 1033b) located in the same column are transmitted via the first adapter cable Z1. The data driving signals obtained from the first type of electrode patterns 1031 (first electrode pattern 1031a and second electrode pattern 1031b) located in the same column are transmitted via the first adapter cable Z1.

[0148] If the second display area 101b completely surrounds the first display area 101a, refer to Figure 11 The second display area 101b also includes a fourth sub-display area 101b4 and a fifth sub-display area 101b5. In order to transmit data drive signals to the fourth sub-display area 101b4, which is away from the first sub-display area 101b1, the display panel 10 may include multiple second adapter cables Z2 and multiple fifth data lines S5 located in the fourth sub-display area 101b4.

[0149] Multiple fifth data lines S5 are arranged along the pixel row direction X and extend along the pixel column direction Y. Multiple second adapter lines Z2 are arranged along the pixel column direction Y and extend along the pixel row direction X. The second end of each second data line S2 is connected to the first end of a second adapter line Z2, and the second end of each second adapter line Z2 is connected to the first end of the fifth data line S5. The fifth data line S5 is also connected to a column of second pixel circuits A2 located in the fourth sub-display area 101b4 for connecting the first target electrode pattern. Thus, the data driving circuit can sequentially provide data driving signals to the column of second pixel circuits A2 located in the fourth sub-display area 101b4 for connecting the first target electrode pattern through the first data line S1, the first adapter line Z1, the second data line S2, the second adapter line Z2, and the fifth data line S5.

[0150] refer to Figure 11 The substrate 101 also has a peripheral region 101c surrounding the second display area 101b. The second ends of the plurality of second data lines S2, the plurality of second adapter lines Z2, and the first ends of the plurality of fifth data lines S5 can all be located in the peripheral region 101c, and in the area of ​​the fourth sub-display area 101b4 away from the first display area 101a. That is, the connection points of the second data lines S2 and the second adapter lines Z2, as well as the connection points of the second adapter lines Z2 and the fifth data lines S5, can all be located in the peripheral region 101c.

[0151] In this embodiment, the display panel 10 further includes a plurality of first dummy data lines D1 located in the third sub-display area 101b3. These first dummy data lines D1 can be arranged along the pixel row direction X and extend along the pixel column direction Y. One end of each first dummy data line D1 is used to connect to a fixed voltage terminal, and the first dummy data line D1 is also connected to a column of first pixel circuits A1 located in the third sub-display area 101b3.

[0152] The first pixel circuit A1 located in the third sub-display area 101b3 can be a dummy pixel circuit, which refers to a pixel circuit that is not connected to any electrode pattern. The fixed voltage terminal can provide a fixed voltage signal to the dummy pixel circuit through the first dummy data line D1, thereby avoiding the dummy pixel circuit from affecting the signals transmitted by the various signal lines in the display panel 10 and ensuring the display effect of the display panel 10.

[0153] Optionally, the first dummy data line D1 can be configured on the same layer as other data lines mentioned in the above embodiments (such as the second data line S2), or it can be configured on a different layer. This application does not limit this. If the first dummy data line D1 is configured on the same layer as other data lines mentioned in the above embodiments, there can be a gap between the first dummy data line D1 and other data lines, thereby avoiding mutual interference between the first dummy data line D1 and other data lines, so that the first dummy data line D1 transmits a fixed voltage signal, while other data lines transmit data drive signals.

[0154] In the first implementation described above, among the multiple first dummy data lines D1 located in the third sub-display area 101b3 of the display panel 10, a portion of the first dummy data lines D1 can be arranged on the same layer as other data lines, while another portion of the first dummy data lines D1 can be arranged on a different layer than other data lines. Optionally, each first dummy data line D1 arranged on the same layer as other data lines can be collinear with a second data line S2 and have a gap between them. Meanwhile, since the fourth data line S4 is located in the third sub-display area 101b3 and needs to pass through the third sub-display area 101b3 to connect with the data driving circuit, in order to avoid the fourth data line S4, the first dummy data lines D1 arranged on a different layer from the fourth data line S4 need to be designed to connect with a column of first pixel circuits A1 located in the third sub-display area 101b3. Among them, the column of first pixel circuits A1 located in the third sub-display area 101b3 and the first pixel circuits A1 located in the second sub-display area 101b2 connected to the fourth data line S4 are located in the same column.

[0155] In the second implementation described above, among the multiple first dummy data lines D1 located in the third sub-display area 101b3 of the display panel 10, all the first dummy data lines D1 can be set on the same layer as other data lines, or they can be set on different layers.

[0156] In this embodiment, the second display area 101b further includes a sixth sub-display area 101b6. This sixth sub-display area 101b6 can be referred to as the normal display area. Optionally, the second display area 101b includes two sixth sub-display areas 101b6, which can be located on both sides of the first third sub-display area 101b3, the first sub-display area 101b1, and the second third sub-display area 101b3 along the pixel row direction X, and on both sides of the first second sub-display area 101b2, the first display area 101a, and the second second sub-display area 101b2 along the pixel row direction X.

[0157] The display panel 10 may further include: a plurality of seventh data lines S7 located in the sixth sub-display area 101b6, and a plurality of second dummy data lines D2 located in the sixth sub-display area 101b6. One end of each seventh data line S7 is used to connect to a data driving circuit, and each seventh data line S7 is also connected to a column of second pixel circuits A2 located in the sixth sub-display area 101b6. This allows the data driving circuit to provide a data driving signal to the second pixel circuits A2 through the seventh data lines S7. One end of each second dummy data line D2 is used to connect to a fixed voltage terminal, and each second dummy data line D2 is also connected to a column of first pixel circuits A1 located in the sixth sub-display area 101b6. This allows the fixed voltage terminal to provide a fixed voltage signal to the first pixel circuits A1 through the second dummy data lines D2. The first pixel circuits A1 located in the sixth sub-display area 101b6 may be dummy pixel circuits.

[0158] In this embodiment, the third connection trace L3 can be disposed on a different layer from both the first connection trace L1 and the second connection trace L2. For example, refer to... Figure 4 The display panel 10 may include a connection layer 104 located between the driving circuit layer 102 and the first electrode layer 103. A first connection trace L1 and a second connection trace L2 may be located on this connection layer 104, meaning both the first connection trace L1 and the second connection trace L2 may be located between the driving circuit layer 102 and the first electrode layer 103. A third connection trace L3 is located on the first electrode layer 103.

[0159] Optionally, the electrode pattern included in the first electrode layer 103 can be a stacked structure of a first film layer, a second film layer, and a third film layer. The materials of the first film layer and the third film layer can be indium tin oxide (ITO), and the material of the second film layer can be silver (Ag), that is, the electrode pattern can be a stack of ITO / Ag / ITO. The third connection trace L3 located in the first electrode layer 103 can mean that the third connection trace L3 is the same as the electrode pattern, and is also a stack of ITO / Ag / ITO; or, the third connection trace L3 can be a layer of ITO (such as the first film layer or the third film layer) included in the electrode pattern.

[0160] Optionally, the connection layer 104 may include at least one conductive layer and at least one insulating layer, and each conductive layer has an insulating layer disposed on the side away from the substrate 101.

[0161] For example, the connection layer 104 may include: a first conductive layer 1041, a first insulating layer 1042, a second conductive layer 1043, a second insulating layer 1044, a third conductive layer 1045, and a third insulating layer 1046, sequentially stacked on the side of the driving circuit layer 102 away from the substrate 101. Each of the first conductive layer 1041, the second conductive layer 1043, and the third conductive layer 1045 includes multiple first connection traces L1 and / or multiple second connection traces L2. The first insulating layer 1042 has a first via, the second insulating layer 1044 has a second via, and the third insulating layer 1046 has a third via. The first conductive layer 1041 is electrically connected to the second conductive layer 1043 through the first via, the second conductive layer 1043 is electrically connected to the third conductive layer 1045 through the second via, and the third conductive layer 1045 is electrically connected to the first electrode layer 103 through the third via.

[0162] In this embodiment, the connecting traces (second connecting trace L2, fourth connecting trace L4 and fifth connecting trace L5) used to connect the first pixel circuit A1 located in the second display area 101b and the electrode pattern of the first display area 101a can be evenly distributed on the three conductive layers. By reasonably arranging the position of the connecting traces, the problem of short circuit or crosstalk caused by the small spacing between adjacent connecting traces can be avoided.

[0163] It should be noted that when the area of ​​the first display area 101a is small, or when the fabrication process for the connecting traces (second connecting trace L2, fourth connecting trace L4 and fifth connecting trace L5) used to connect the first pixel circuit A1 located in the second display area 101b and the electrode pattern of the first display area 101a has high precision and the width of the connecting traces can be reduced, all connecting traces can be arranged in two conductive layers or even in one conductive layer. This can reduce the number of masks used in the fabrication process, simplify the process, improve the light transmittance of the first display area 101a and reduce the overall thickness of the display panel 10, thereby achieving a thinner and lighter display panel 10.

[0164] refer to Figure 4 Each conductive layer is also provided with a connection portion, which can be used to connect the connection trace to the pixel circuit, or to connect the connection trace located on different layers, or to connect the connection trace to the electrode pattern in the first electrode layer 103. For example, the first conductive layer 1041 may include a plurality of first connection portions 1041a, the second conductive layer 1043 may include a plurality of second connection portions 1043a, and the third conductive layer 1045 may include a plurality of third connection portions 1045a.

[0165] Figure 4In this example, the first connection trace L1 is located in the third conductive layer 1045, and the second connection trace L2 is located in the first conductive layer 1041. In the second display area 101b, the second pixel circuit A2 is connected to the first connection portion 1041a, the first connection portion 1041a is connected to the second connection portion 1043a, the second connection portion 1043a is connected to the third connection portion 1045a, and the third connection portion 1045a is connected to an electrode pattern (the second electrode pattern 1031b, the fourth electrode pattern 1032b, or the sixth electrode pattern 1033b). If the third connection portion 1045a is connected to a second electrode pattern 1031b, then the third connection portion 1045a is also connected to the third connection trace L3, the third connection trace L3 is connected to another third connection portion 1045a, and this other third connection portion 1045a is connected to another second electrode pattern 1031b. In the first display area 101a, the second connection trace L2 is connected to the first pixel circuit A1 through a first connection portion 1041a. The second connection trace L2 is connected to the second connection portion 1043a through another first connection portion 1041a. The second connection portion 1043a is connected to the third connection portion 1045a. The third connection portion 1045a is connected to an electrode pattern (first electrode pattern 1031a, third electrode pattern 1032a, or fifth electrode pattern 1033a). If the third connection portion 1045a is connected to a first electrode pattern 1031a, then the third connection portion 1045a is also connected to the first connection trace L1. The first connection trace L1 is connected to another third connection portion 1045a, and this other third connection portion 1045a is connected to another second electrode pattern 1031b.

[0166] The orthographic projection of the third connecting portion 1045a on the substrate 101 at least partially overlaps with the orthographic projection of the electrode pattern connected to the third connecting portion 1045a on the substrate 101, thereby connecting the electrode pattern to the third connecting portion 1045a through a third via penetrating the third insulating layer 1046. The orthographic projections of the connected second connecting portion 1043a and the third connecting portion 1045a on the substrate 101 at least partially overlap, thereby connecting the third connecting portion 1045a to the second connecting portion 1043a through a second via penetrating the second insulating layer 1044. The orthographic projections of the connected first connecting portion 1041a and the second connecting portion 1043a on the substrate 101 at least partially overlap, thereby connecting the second connecting portion 1043a to the first connecting portion 1041a through a first via penetrating the first insulating layer 1042. The first connection portion 1041a and the pixel circuit's orthographic projection on the substrate 101 at least partially overlap, thereby enabling the first connection portion 1041a to connect with the pixel circuit. Thus, by providing connection portions in each conductive layer, the connection between the pixel circuit and the electrode pattern can be made more stable.

[0167] Optionally, the first conductive layer 1041, the second conductive layer 1043, and the third conductive layer 1045 all comprise a transparent conductive material. For example, the materials of the first conductive layer 1041, the second conductive layer 1043, and the third conductive layer 1045 can be indium tin oxide or indium zinc oxide. The insulating layers included in the connecting layer 104 comprise transparent insulating materials. For example, the materials of the first insulating layer 1042, the second insulating layer 1044, and the third insulating layer 1046 can be polyimide (PI).

[0168] In the embodiments of this application, reference is made to Figure 4 The display panel 10 also includes a light-emitting film layer 105, a pixel defining layer 106, a second electrode layer 107, an encapsulation layer 108, and a buffer layer 109. The encapsulation layer 108 covers the side of the second electrode layer 107 away from the substrate 101, thus encapsulating the display panel 10. The buffer layer 109 may be located between the substrate 101 and the driving circuit layer 102.

[0169] The first electrode layer 103, pixel defining layer 106, light-emitting film layer 105, and second electrode layer 107 can constitute multiple light-emitting devices, such as multiple OLEDs. The light-emitting film layer 105 includes multiple light-emitting layers 1051, the pixel defining layer 106 has multiple openings, each opening exposing an electrode pattern in the first electrode layer 103, each light-emitting layer 1051 located within an opening and in contact with the electrode pattern, and the portion of the second electrode layer 107 located within an opening serves as the second electrode of the light-emitting device. Thus, the sequentially stacked electrode pattern (anode), light-emitting layer 1051, and second electrode (cathode) constitute the light-emitting device.

[0170] The pixel circuit in the driving circuit layer 102 can be electrically connected to the light-emitting device. For example, the pixel circuit can be electrically connected to the electrode pattern of the first electrode layer 103 in the light-emitting device to control the light-emitting device to emit light.

[0171] In some embodiments, the driving circuit layer 102 includes a semiconductor layer 10201, a first gate insulator (GI) 10202, a first gate layer 10203, a second gate insulator 10204, a second gate layer 10205, an inter-level dielectric (ILD) 10206, a first source-drain layer 10207, a passivation layer (PVX) 10208, an intermediate source-drain layer 10209, a first planarization layer (PLN) 10210, a second source-drain layer 10211, and a second planarization layer 10212, which are sequentially stacked on the substrate 101. The plurality of pixel circuits in the driving circuit layer 102 are arranged in an array, and each pixel circuit includes a plurality of thin-film transistors. The first conductive layer 1041 in the aforementioned connection layer 104 is located on the side of the second planarization layer 10212 away from the substrate 101. The first insulating layer 1042 can be referred to as the third planarization layer, the second insulating layer 1044 can be referred to as the fourth planarization layer, and the third insulating layer 1046 can be referred to as the fifth planarization layer. The pixel circuit in the driving circuit layer 102 can be electrically connected to the light-emitting device through the connection layer 104.

[0172] Optionally, the first source-drain layer 10207 may include the source and drain of the thin-film transistors in each pixel circuit, and the source and drain may be spaced apart. Of course, the first source-drain layer 10207 may also include the adapter lines (first adapter line Z1, second adapter line Z2, and third adapter line Z3) described in the above embodiments. The intermediate source-drain layer 10209 may include power traces (e.g., VDD traces) for providing power signals to the display panel 10. Alternatively, the intermediate source-drain layer 10209 may also include the adapter lines (first adapter line Z1, second adapter line Z2, and third adapter line Z3) described in the above embodiments. The second source-drain layer may include the data lines (first data line S1, second data line S2, third data line S3, fourth data line S4, fifth data line S5, sixth data line S6, and seventh data line S7) and dummy data lines (first dummy data line D1 and second dummy data line D2) described in the above embodiments.

[0173] It should be noted that for the design of pixel circuits in display panels with higher pixel resolution (pixels per inch, PPI), if the sixth sub-display area (normal display area) of the second display area only contains pixel circuits for driving the electrode patterns located in the second display area, and no dummy pixel circuits are set up, and each pixel circuit drives one electrode pattern, then refer to... Figure 12Each pixel circuit can occupy a relatively large space in the pixel row direction, up to 29.8 μm (micrometers). However, in this scheme, to improve the transmittance of the first display area, the pixel circuits used to drive the electrode patterns in the first display area need to be located in the second sub-display area (transition display area) of the second display area. This may result in different pixel circuit arrangements in different sub-areas of the second display area, leading to poor uniformity of the pixel circuits in the display panel.

[0174] Therefore, in order to improve the design uniformity of pixel circuits in the display panel, dummy pixel circuits can be designed in the sixth sub-display area, for example... Figure 13 In this design, one first pixel circuit (a dummy pixel circuit) is designed for every two second pixel circuits, i.e., a two-to-one pixel circuit design (a two-to-one pixel circuit design can mean that where two second pixel circuits would normally be required, an additional dummy pixel circuit is designed instead). Compared to... Figure 12 In contrast, where four pixel circuits would normally be required, six pixel circuits need to be designed instead. However, in this approach, each pixel circuit occupies a relatively small space of 19.8 μm in the pixel row direction, making it difficult to fabricate.

[0175] In this embodiment, since two second electrode patterns are driven by a single second pixel circuit, the number of pixel circuits required can be reduced. Compared to... Figure 13 In terms of Figure 14 In this design, where six pixel circuits would normally be required, only five are needed. Each pixel circuit can occupy a relatively large space (23.83 μm) in the pixel row direction, making fabrication easier. Furthermore, the pixel circuits in each sub-region of the second display area are arranged differently, resulting in better uniformity of the pixel circuits across the display panel.

[0176] refer to Figure 14 The three second pixel circuits and two first pixel circuits in a five-pixel circuit (one circuit group) can be arranged in the manner of second pixel circuit, second pixel circuit, first pixel circuit, second pixel circuit, and first pixel circuit. Of course, refer to... Figure 15 The three second pixel circuits and two first pixel circuits in the five pixel circuits can also be arranged in the manner of second pixel circuit, second pixel circuit, second pixel circuit, first pixel circuit, and first pixel circuit. Of course, other arrangements are also possible, and this application does not limit them.

[0177] In the embodiments of this application, the equivalent circuit diagrams of the first pixel circuit and the second pixel circuit can be referred to Figure 16The pixel circuit may include multiple thin-film transistors and a storage capacitor. The multiple thin-film transistors include a first data reset control transistor T1, a threshold compensation transistor T2, a drive transistor T3, a write transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a third reset control transistor T7.

[0178] The storage capacitor Cst may include two capacitor plates Cst1 and Cst2. In the embodiments of the application, capacitor plate Cst1 may be referred to as one end, first end, first pole or first storage capacitor electrode of storage capacitor Cst, and capacitor plate Cst2 may be referred to as the other end, second end, second pole or second storage capacitor electrode of storage capacitor Cst.

[0179] Specifically, the first terminal of the first reset control transistor T1 is electrically connected to the reset power supply signal line to receive the reset signal Vinit; the second terminal of the first reset control transistor T1 is electrically connected to the gate of the driving transistor T3; and the gate of the first reset control transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset. The first terminal of the threshold compensation transistor T2 is connected to the first terminal of the driving transistor T3; the gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive the scan signal Gate; and the second terminal of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3. The first terminal of the data writing transistor T4 is connected to the second terminal of the driving transistor T3; the gate of the data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; and the second terminal of the data writing transistor T4 is connected to the data line to receive the data drive signal Data. The first terminal of the first light-emitting control transistor T5 is electrically connected to the first power supply signal line; the second terminal of the first light-emitting control transistor T5 is electrically connected to the second terminal of the driving transistor T3; and the gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM. The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM. The first terminal of the third reset control transistor T7 is connected to the reset power supply signal line to receive the reset signal Vinit, and the second terminal of the third reset control transistor T7 is connected to the electrode pattern of the light-emitting device. The gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset. The first terminal of the storage capacitor Cst is electrically connected to the first power supply signal line, and the second terminal of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3. Additionally, the cathode of the light-emitting device can be electrically connected to the second power supply signal line. The first power supply signal line refers to the signal line of the output voltage signal VDD, and the second power supply signal line refers to the signal line of the output voltage signal VSS.

[0180] Figure 17This is a partial schematic diagram of the semiconductor layer in the display panel provided in an embodiment of this application. (Reference) Figure 17 The semiconductor layer may have a curved or bent shape. The semiconductor layer includes semiconductor patterns (channel regions) and doped region patterns (source and drain doped regions) of each transistor, and the active layer patterns and doped region patterns of each transistor in the same pixel circuit are integrally formed.

[0181] It should be noted that the semiconductor layer may include an integrally formed low-temperature polycrystalline silicon layer, and the source and drain regions may be conductiveized through doping to achieve electrical connections between the various structures. That is, the semiconductor layer of each transistor in each pixel circuit is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., source and drain regions) and a semiconductor pattern, with the semiconductor patterns of different transistors separated from each other.

[0182] The semiconductor layer can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source and drain regions mentioned above can be regions doped with n-type or p-type impurities.

[0183] Figure 18 This is a partial superimposed schematic diagram of the first gate layer in the display panel provided in the embodiments of this application.

[0184] The display panel includes a first gate insulating layer located on the side of the semiconductor layer away from the substrate, which is used to insulate the semiconductor layer from the subsequently formed first gate layer. Figure 18 The diagram illustrates a first gate layer comprising the display panel. The first gate layer is disposed on a first gate insulating layer, thereby isolating it from the semiconductor layer. The first gate layer may include a second storage capacitor electrode Cst2, multiple scan signal lines g1 extending along the pixel row direction X, multiple reset control signal lines g2, multiple light emission control signal lines g3, and the first gate layer also includes the gates of various transistors.

[0185] For example, combining Figures 17 to 19 The gate of the data writing transistor T4 can be the portion where the scan signal line g1 overlaps with the semiconductor layer; the gate of the second light-emitting control transistor T6 can be the first portion where the light-emitting control signal line g3 overlaps with the semiconductor layer, and the gate of the first light-emitting control transistor T5 can be the second portion where the light-emitting control signal line g3 overlaps with the semiconductor layer. The gate of the first reset control transistor T1 is the first portion where the reset control signal line g2 overlaps with the semiconductor layer, and the gate of the third reset control transistor T7 is the second portion where the reset control signal line g2 overlaps with the semiconductor layer. The gate of the threshold compensation transistor T2 can be the portion where the protruding structure P protruding from the scan signal line g1 overlaps with the semiconductor layer. Figure 18 As shown, the gate of the driving transistor T3 can be the second storage capacitor electrode Cst2.

[0186] It should be noted that, Figure 19 The dashed rectangles in the diagram illustrate the various portions where the first gate layer overlaps with the semiconductor layer. As the channel region of each transistor, the semiconductor layers on both sides of each channel region are conductiveized through processes such as ion doping, serving as the first and second electrodes of each transistor. The source and drain of a transistor can be structurally symmetrical, so their physical structures can be indistinguishable. In the embodiments of this application, to distinguish the transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode and the other as the second electrode. Therefore, in the embodiments of this application, the first and second electrodes of all or some transistors can be interchanged as needed.

[0187] like Figure 18 and Figure 19 As shown, the scan signal line g1, reset control signal line g2, and light emission control signal line g3 are arranged along the pixel column direction Y. In the pixel column direction Y, the second storage capacitor electrode Cst2 (i.e., the gate of the driving transistor T3) is located between the scan signal line g1 and the light emission control signal line g3. The protruding structure P extending from the scan signal line g1 is located on the side of the scan signal line g1 closest to the light emission control signal line g3.

[0188] In addition, a second gate insulating layer may be formed on the first gate layer to insulate the first gate layer from the subsequently formed second gate layer.

[0189] Figure 20 This is a partial schematic diagram of the second gate layer in a display panel provided in an embodiment of this application. Figure 21 This is a partial superimposed schematic diagram of the semiconductor layer, the first gate layer, and the second gate layer in the display panel provided in this application embodiment. Figure 20 and Figure 21 As shown, the second gate layer includes a first storage capacitor electrode Cst1, a plurality of first reset power supply signal lines g4 extending along the pixel row direction X, and a plurality of second reset power supply signal lines g5 extending along the pixel row direction X. The first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 at least partially overlap to form a storage capacitor Cst.

[0190] Additionally, an interlayer dielectric layer may be formed on the aforementioned second gate layer to insulate it from the subsequently formed first source / drain layer. (See reference) Figure 22 and Figure 23 To facilitate the illustration of the various vias in the interlayer dielectric (ILD), Figures 22 to 23Vias are represented by filled patterns. Areas without filled patterns represent regions where the interlayer dielectric layer contains solid material. It should be noted that each via in this interlayer dielectric layer is used to connect subsequently formed films to the side of the interlayer dielectric layer closest to the substrate. In other words, each via is used for film layer connection.

[0191] Figure 24 This is a partial schematic diagram of the first source-drain layer in the display panel provided in the embodiments of this application. Figure 25 This is a partial superimposed schematic diagram of the semiconductor layer, first gate layer, second gate layer, interlayer dielectric layer, and first source / drain layer in the display panel provided in the embodiments of this application. Figure 24 and Figure 25 As shown, the first source-drain layer includes a first connection structure h1, a second connection structure h2, a third connection structure h3, a fourth connection structure h4, a fifth connection structure h5, and a sixth connection structure h6. The first connection structure h1 is configured to connect the source (or drain) of the threshold compensation transistor T2 and the gate of the driving transistor T3. The second connection structure h2 is configured to connect the second light-emitting control transistor T6. The third connection structure h3 is configured to connect the source (or drain) of the third reset control transistor T7 and the reset power supply signal line g4. The fourth connection structure h4 is configured to connect the VDD signal line and the source (or drain) of the first light-emitting control transistor T5. The fifth connection structure h5 is configured to connect the source (or drain) of the data writing transistor T4 and the data line g6. The sixth connection structure h6 is configured to connect the second reset power supply signal line g5.

[0192] Additionally, a passivation layer may be formed on the first source / drain layer to insulate it from the subsequently formed intermediate source / drain layer. (See reference) Figure 26 and Figure 27 To facilitate the illustration of the various vias in the passivation layer (PVX), Figures 26 to 27 The vias are represented by filled patterns. Areas without filled patterns represent regions where the passivation layer contains solid material. It should be noted that each via in the passivation layer is used to connect the subsequently formed film layer to the side of the passivation layer closest to the substrate. In other words, each via is a via for film layer connection.

[0193] Figure 28 This is a partial schematic diagram of the intermediate source / drain layer in the display panel provided in an embodiment of this application. Figure 29 This is a partial superimposed schematic diagram of the semiconductor layer, first gate layer, second gate layer, interlayer dielectric layer, first source / drain layer, passivation layer, and intermediate source / drain layer in the display panel provided in the embodiments of this application. Figure 28 and Figure 29As shown, the intermediate source-drain layer includes a first signal line VDD1, a seventh connection structure h7, and an eighth connection structure h8. The first signal line VDD1 is configured to be connected to the fourth connection structure h4, the seventh connection structure h7 is configured to be connected to the second connection structure h2, and the eighth connection structure h8 is configured to be connected to the fifth connection structure h5.

[0194] Additionally, a first planarization layer (PLN1) may be formed on the aforementioned intermediate source / drain layer to insulate it from the subsequently formed second source / drain layer. (See reference) Figure 30 and Figure 31 To facilitate the illustration of the various vias in the first planarization layer, Figures 30 to 31 The vias are represented by filled patterns. Areas without filled patterns represent regions where the first planarization layer has solid material. It should be noted that each via in the first planarization layer is used to connect subsequently formed films to the side of the first planarization layer closest to the substrate. That is, each via is used for film layer connection.

[0195] Figure 32 This is a partial schematic diagram of the second source / drain layer in the display panel provided in the embodiments of this application. Figure 33 This is a schematic diagram showing the stacked structure of the semiconductor layer, first gate layer, second gate layer, interlayer dielectric layer, first source / drain layer, passivation layer, intermediate source / drain layer, and second source / drain layer in the display panel provided in this application embodiment. Figure 32 and Figure 33 As shown, the second source-drain layer includes a second signal line VDD2, a data line g6, and a ninth connection structure h9. The second signal line VDD2 is configured to connect to the first signal line VDD1, the data line g6 is configured to connect to the eighth connection structure h8, and the ninth connection structure h9 is configured to connect to the seventh connection structure h7. The traces used to transmit the VDD signal include the first signal line VDD1 and the second signal line VDD2.

[0196] Additionally, a second planarization layer (PLN2) may be formed on the aforementioned second source / drain layer to insulate the intermediate source / drain layer from the first conductive layer in the subsequently formed interconnect layer. (See reference) Figure 34 and Figure 35 To facilitate the illustration of the various vias in the second planarization layer, Figures 34 to 35 The vias are represented by filled patterns. Areas without filled patterns represent areas of solid material in the second planarization layer. It should be noted that each via in the second planarization layer is used to connect subsequently formed films to the side of the second planarization layer closest to the substrate. In other words, each via is a via for film layer connection.

[0197] In summary, the embodiments of this application provide a display panel. Since at least two first electrode patterns are connected in the display panel, and one of the connected first electrode patterns is connected to a first pixel circuit, one first pixel circuit can drive two first electrode patterns. Simultaneously, since at least two second electrode patterns are connected, and one of the connected second electrode patterns is connected to a second pixel circuit, one second pixel circuit can drive two second electrode patterns. Therefore, with the same number of electrode patterns, using a scheme where one pixel circuit drives two electrode patterns reduces the number of pixel circuits required in the second display area, thereby increasing the space occupied by each pixel circuit and reducing the difficulty of fabrication.

[0198] Figure 36 This is a flowchart illustrating a method for fabricating a display panel according to an embodiment of this application. This method can be used to fabricate the display panel provided in the above embodiment. (Reference) Figure 36 The method may include:

[0199] Step S101: A buffer layer, a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, an intermediate source-drain layer, a first planarization layer, a second source-drain layer, and a second planarization layer are sequentially formed on one side of the substrate.

[0200] In this embodiment, when fabricating a display panel, a substrate can be obtained first. This substrate can be a transparent glass substrate or a flexible substrate. Accordingly, the resulting display panel can be a flexible display panel. Then, a buffer layer and various film layers in the driving circuit layer can be formed on one side of the substrate. The various film layers in the driving circuit layer can be referenced... Figures 17 to 35 The embodiments described in this application will not be repeated here.

[0201] Step S102: A first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, and a third insulating layer are sequentially formed on the side of the second planarization layer away from the substrate.

[0202] refer to Figure 37 and Figure 38 A first conductive layer is formed on the side of the second planarization layer away from the substrate, and the first conductive layer may include a plurality of first interconnections. (Reference) Figure 39 and Figure 40 A first insulating layer (third planarization layer PLN3) is formed on the side of the first conductive layer away from the substrate. For clarity, the various first vias in the first insulating layer are shown below. Figure 39 and Figure 40The first via is represented by a filled pattern. Other areas without filled patterns represent areas where the first insulating layer has solid material. It should be noted that each first via in the first insulating layer is used to connect a subsequently formed film layer to the side of the first insulating layer closest to the substrate. That is, each first via is a via for film layer connection.

[0203] refer to Figure 41 and Figure 42 A second conductive layer is formed on the side of the first insulating layer away from the substrate, and the second conductive layer may include a plurality of second connection portions. (Reference) Figure 43 and Figure 44 A second insulating layer (fourth planarization layer PLN4) is formed on the side of the second conductive layer away from the substrate. To facilitate illustration of the various second vias in the second insulating layer, Figure 43 and Figure 44 The second vias are represented by a filled pattern. Other areas without filled patterns represent regions of the second insulating layer containing solid material. It should be noted that each second via in the second insulating layer is used to connect a subsequently formed film layer to the side of the second insulating layer closest to the substrate. That is, each second via is a via for film layer connection.

[0204] refer to Figure 45 and Figure 46 A third conductive layer is formed on the side of the second insulating layer away from the substrate, and this third conductive layer may have multiple third connecting portions. (Reference) Figure 47 and Figure 48 A third insulating layer (fifth planarization layer PLN5) is formed on the side of the third conductive layer away from the substrate. To facilitate illustration of the various second vias in the third insulating layer, Figure 47 and Figure 48 The third via is represented by a filled pattern. Other areas without filled patterns represent areas where the third insulating layer has solid material. It should be noted that each third via in the third insulating layer is used to connect a subsequently formed film layer to the side of the third insulating layer closest to the substrate 101. That is, each third via is a via for film layer connection.

[0205] Step S103: A first electrode layer, a pixel defining layer, a light-emitting film layer, a second electrode layer, and an encapsulation layer are formed on the side of the third insulating layer away from the substrate.

[0206] refer to Figure 49 and Figure 50 A first electrode layer is formed on the side of the third insulating layer away from the substrate. The first electrode layer may include multiple electrode patterns, each of which can serve as the anode of a pixel device. Figure 49 and Figure 50The diagram shows the second electrode pattern, the fourth electrode pattern, and the sixth electrode pattern.

[0207] refer to Figure 51 and Figure 52 A pixel defining layer is formed on the side of the first electrode layer away from the substrate. This pixel defining layer may have multiple openings, each exposing an electrode pattern in the first electrode layer. For clarity, the openings in the pixel defining layer are shown below. Figure 51 and Figure 52 The openings are represented by filled patterns, while other areas without filled patterns represent areas where the pixel defining layer has solid material. It should be noted that each opening in the pixel defining layer is for connecting the subsequently formed film layer to the side of the pixel defining layer closest to the substrate. That is, each opening is for allowing the light-emitting layer in the light-emitting film layer to contact the electrode pattern in the first electrode layer.

[0208] After the pixel defining layer is formed, a light-emitting film layer, a second electrode layer, and an encapsulation layer can be formed on the side of the pixel defining layer away from the substrate. The embodiments of this application will not be described in detail here.

[0209] It should be noted that the method for preparing the display panel provided in this application mainly takes other areas (such as the first sub-display area, the third sub-display area, the fourth sub-display area, the fifth sub-display area, and the sixth sub-display area) in the second display area as examples. Figures 17 to 51 Both examples include one circuit group A along the pixel row direction and two circuit groups A along the pixel column direction.

[0210] For the second sub-display area (transition display area) within the second display area, the difference between it and the film layers in other areas of the second display area is mainly in the individual conductive layers. (Reference) Figure 53 In addition to the connecting portion, the portion of the conductive layer located in the second sub-display area also includes a second connecting trace, a fourth connecting trace, or a fifth connecting trace. That is, the portion of the conductive layer located in the second sub-display area may include connecting traces for connecting the pixel circuitry located in the second sub-display area and the electrode pattern located in the first display area. Figure 53 The conductive layer in the image can be a first conductive layer, a second conductive layer, or a third conductive layer. Correspondingly, Figure 53 The connecting part can be a first connecting part, a second connecting part, or a third connecting part.

[0211] In summary, the embodiments of this application provide a method for fabricating a display panel. Since at least two first electrode patterns are connected in the fabricated display panel, and one of the connected first electrode patterns is connected to a first pixel circuit, one first pixel circuit can drive two first electrode patterns. Simultaneously, since at least two second electrode patterns are connected, and one of the connected second electrode patterns is connected to a second pixel circuit, one second pixel circuit can drive two second electrode patterns. Therefore, with the same number of electrode patterns, using a scheme where one pixel circuit drives two electrode patterns reduces the number of pixel circuits required in the second display area, thereby increasing the space occupied by each pixel circuit and lowering the fabrication difficulty.

[0212] Figure 54 This is a schematic diagram of the structure of a display module provided in an embodiment of this application. Figure 54 The display device may include a data driving circuit 20 and the display panel 10 provided in the above embodiments. The data driving circuit 20 can be connected to the first data line S1, the third data line S3, the fourth data line S4, and the seventh data line S7 in the display panel 10, directly providing data driving signals to these data lines. Figure 54 Each of the above schematically shows a first data line S1, a third data line S3, a fourth data line S4, and a seventh data line S7.

[0213] Furthermore, the second data line S2 is connected to the first data line S1 via the first adapter Z1, and the fifth data line S5 is connected to the second data line S2 via the second adapter Z2. Therefore, the data driving circuit 20 provides data driving signals to the second data line S2 and the fifth data line S5 through the first data line S1. The sixth data line S6 is connected to the fourth data line S4 via the third adapter Z3. Therefore, the data driving circuit 20 provides data driving signals to the sixth data line S6 through the fourth data line S4.

[0214] Since the display module can have essentially the same technical effects as the display panel described in the previous embodiments, for the sake of brevity, the technical effects of the display device will not be described again here.

[0215] refer to Figure 55This application provides a display device that may include the display module 01 and electrical components such as the sensor 02 provided in the above embodiments, for example, an optical sensor. Taking a mobile phone as an example, the display device includes optical sensors such as a front-facing camera, a proximity sensor, and a 3D sensing module. These optical components need to receive light from the display surface of the display device to achieve corresponding functions. In the display device, the optical sensor is usually installed on the non-display surface side of the display module 01, with the photosensitive surface of the optical sensor facing the display module 01. The orthographic projection of the optical sensor 02 onto the display panel 10 at least partially overlaps with the first display area 101a in the display panel 10.

[0216] In the embodiments of this application, the display device can be any product or component with display function, such as an active-matrix organic light-emitting diode (AMOLED) display device, a passive-matrix organic light-emitting diode (PMOLED) display device, a quantum dot light-emitting diode (QLED) display device, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame or navigator.

[0217] Since the display device can have essentially the same technical effects as the display panel described in the previous embodiments, for the sake of brevity, the technical effects of the display device will not be described again here.

[0218] The terminology used in the embodiments section of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," "third," and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising" or "including," and similar terms mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The terms "connected," "linked," and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0219] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel (10) includes: A substrate (101) having a first display area (101a) and a second display area (101b) at least partially surrounding the first display area (101a); A driving circuit layer (102) is located on one side of the substrate (101), the driving circuit layer (102) including a plurality of first pixel circuits (A1) located in the second display area (101b); And a first electrode layer (103), the first electrode layer (103) includes at least a plurality of first type electrode patterns (1031), the plurality of first type electrode patterns (1031) including a plurality of first electrode patterns (1031a) located in the first display area (101a); At least two of the first electrode patterns (1031a) are connected to one of the plurality of first pixel circuits (A1).

2. The display panel according to claim 1, characterized in that, The display panel (10) also includes: Multiple first connection traces (L1) are located in the first display area (101a); Multiple second connection traces (L2) extend from the second display area (101b) to the first display area (101a) along the pixel row direction (X); At least two of the first electrode patterns (1031a) are connected by a first connection trace (L1), and one of the first electrode patterns (1031a) is connected to a first pixel circuit (A1) by a second connection trace (L2).

3. The display panel according to claim 2, characterized in that, The display panel (10) further includes multiple fourth connection traces (L4) and multiple fifth connection traces (L5), which extend from the second display area (101b) to the first display area (101a) along the pixel row direction (X); the first electrode layer (103) further includes multiple second type electrode patterns (1032) and multiple third type electrode patterns (1033); The plurality of second type electrode patterns (1032) include a plurality of third electrode patterns (1032a) located in the first display area (101a), and the third electrode patterns (1032a) are connected to a first pixel circuit (A1) through a fourth connection trace (L4). The plurality of third-type electrode patterns (1033) include a plurality of fifth electrode patterns (1033a) located in the first display area (101a), the fifth electrode patterns (1033a) being connected to a first pixel circuit (A1) via the fifth connection trace (L5).

4. The display panel according to claim 3, characterized in that, In the first display area (101a), a plurality of first electrode patterns (1031a), a plurality of third electrode patterns (1032a) and a plurality of fifth electrode patterns (1033a) are arranged in multiple rows. The plurality of electrode patterns arranged in a row are called a first pattern row (M). At least one first pattern row (M) includes at least two first electrode patterns (1031a), at least one third electrode pattern (1032a) and at least one fifth electrode pattern (1033a) arranged in a row. Wherein, at least two first electrode patterns (1031a) in the first pattern row (M) are connected through the first connection trace (L1).

5. The display panel according to claim 4, characterized in that, The electrode patterns in the first pattern row (M) are arranged cyclically in the order of the third electrode pattern (1032a), the first electrode pattern (1031a), the fifth electrode pattern (1033a), and the first electrode pattern (1031a).

6. The display panel according to claim 4, characterized in that, The first pattern row (M) is arranged in multiple rows, and at least one first pattern row (M) includes a first sub-pattern row (M1) and a second sub-pattern row (M2) arranged in parallel. The third electrode pattern (1032a) and the fifth electrode pattern (1033a) in the first sub-pattern row (M1) are arranged in an overlapping manner; In the second sub-pattern row (M2), multiple first electrode patterns (1031a) are arranged sequentially.

7. The display panel according to any one of claims 1 to 6, characterized in that, The first display area (101a) is a circular area or a square area; The second display area (101b) includes at least one first sub-display area (101b1) and two second sub-display areas (101b2). The first sub-display area (101b1) and the first display area (101a) are arranged along the pixel column direction (Y), and the two second sub-display areas (101b2) are respectively located on both sides of the first display area (101a) along the pixel row direction (X).

8. The display panel according to any one of claims 1 to 6, characterized in that, The display panel (10) includes multiple sub-pixels of different colors. Each sub-pixel includes a light-emitting device and a pixel circuit for controlling the light-emitting device. The light emitted by the sub-pixels to which the multiple first-type electrode patterns (1031) belong is of the same color.

9. The display panel according to any one of claims 1 to 6, characterized in that, The first electrode pattern (1031a) located in the first display area (101a) of the first electrode layer (103) includes a transparent conductive material.

10. The display panel according to claim 3, characterized in that, The display panel includes red sub-pixels, green sub-pixels, and blue sub-pixels. The sub-pixels to which the first type of electrode pattern belongs are green sub-pixels, the sub-pixels to which the second type of electrode pattern belongs are red sub-pixels, and the sub-pixels to which the third type of electrode pattern belongs are blue sub-pixels.

11. A display module, characterized in that, The display module includes a data driving circuit (20) and a display panel (10) as described in any one of claims 1 to 10; The data driving circuit (20) is connected to the display panel (10) and is used to provide data driving signals to the display panel (10).

12. A display device, characterized in that, The display device includes the display module (01) as described in claim 11 and an optical sensor (02), wherein the orthographic projection of the optical sensor (02) on the display panel (10) at least partially overlaps with the first display area (101a) in the display panel (10).

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