Array substrate, manufacturing method thereof and display device

Abstract

The invention provides an array substrate and a manufacturing method thereof and a display device, the array substrate comprises a first thin film transistor and a second thin film transistor, a first active layer, a first electrode and a second electrode of the first thin film transistor are all arranged on a first material layer, and the first electrode and the second electrode are in direct contact and electrically connected with the first active layer. A second active layer, a third electrode and a fourth electrode of the second thin film transistor and a first grid electrode of the first thin film transistor are all arranged on the second material layer, and the third electrode and the fourth electrode are in direct contact and electrically connected with the second active layer. The first grid electrode of one first thin film transistor is electrically connected with the fourth electrode of the adjacent second thin film transistor in a same-layer contact mode. The first thin film and the second thin film are stacked up and down, so that the arrangement density of the transistors can be improved, and the resolution of the array substrate is improved. The first grid electrode and the fourth electrode are electrically connected in a contact mode, source and drain electrodes of the thin film transistors of the same type are electrically connected in a contact mode, through hole arrangement is reduced, and the resolution ratio of the array substrate is greatly improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a method for manufacturing the same, and a display device. Background Technology

[0002] Organic electroluminescent display panels have gradually become the mainstream in the display field due to their excellent performance such as low power consumption, high color saturation, wide viewing angle, thinness, and flexibility. They can be widely used in terminal products such as smartphones, tablets, and televisions.

[0003] However, the connection structure of the current display panel driving circuit is relatively complex, requiring a large number of thin-film transistors, which seriously restricts the further improvement of the display panel resolution. Therefore, it is urgent to optimize the layout of thin-film transistors. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate, its fabrication method, and a display device, thereby simplifying the connection structure of thin-film transistors and improving the resolution of the array substrate. The specific technical solution is as follows:

[0005] This application provides an array substrate, comprising: a substrate; an insulating buffer layer formed on one side of the substrate; and a first thin-film transistor, including a first active layer, a first electrode, a second electrode, a first gate, and a first gate insulating layer disposed between the first active layer and the first gate. The first active layer, the first electrode, and the second electrode are all disposed on a first material layer, and the first gate is disposed on a second material layer. The first gate is disposed opposite to the first active layer along the thickness direction of the array substrate. The first material layer is disposed on the side of the insulating buffer layer away from the substrate. The first electrode and the second electrode are located on opposite sides of the first active layer. The first material layer includes at least one first semiconductor region and a first conductor region located around the first semiconductor region. The first active layer is located in the first semiconductor region, and the first electrode and the second electrode are located in the first conductor region and are adjacent to the first active layer. The first and second thin-film transistors are directly contacted and electrically connected; the second thin-film transistor includes a second active layer, a third electrode, a fourth electrode, a second gate, and a second gate insulating layer disposed between the second active layer and the second gate. The second active layer, the third electrode, and the fourth electrode are all disposed on the second material layer, and the third electrode and the fourth electrode are located on opposite sides of the second active layer. The second gate is disposed opposite to the second active layer along the thickness direction of the array substrate. The second material layer includes a second conductor region where the first gate is located, at least one second semiconductor region, and a third conductor region located around the second semiconductor region. The second active layer is located in the second semiconductor region, and the third electrode and the fourth electrode are located in the third conductor region and are directly contacted and electrically connected to the second active layer. The first gate of one of the first thin-film transistors and the fourth electrode of the adjacent second thin-film transistor are contacted and electrically connected in the same layer.

[0006] In addition, the array substrate provided in the first aspect of this application may also have the following technical features:

[0007] In some embodiments, the array substrate includes a plurality of pixel driving circuits, each pixel driving circuit including a driving transistor and a first switching transistor, the driving transistor being a first thin-film transistor, the first switching transistor being a second thin-film transistor, and the gate of the driving transistor being electrically connected to the drain of the first switching transistor in the same layer.

[0008] In some embodiments, each pixel driving circuit further includes a second switching transistor, the second switching transistor being the first thin-film transistor, and the source or drain of the driving transistor being directly contacted and electrically connected to the drain or source of the second switching transistor.

[0009] In some embodiments, the first switching transistor and the second switching transistor are provided in multiples, and the source or drain of one of the adjacent first switching transistors is directly contacted and electrically connected to the drain of the other, and the source or drain of one of the adjacent second switching transistors is directly contacted and electrically connected to the drain or source of the other.

[0010] In some embodiments, the array substrate includes at least one first transition metal, which is disposed on the same layer as the second gate; one end of the first transition metal is electrically connected to the first conductor region, the second conductor region, or the third conductor region through a first connection portion, the first connection portion penetrating through the second gate insulating layer and the first gate insulating layer along the thickness direction of the array substrate, or penetrating through the second gate insulating layer along the thickness direction of the array substrate; the other end of the first transition metal is electrically connected to the trace to be transitioned.

[0011] In some embodiments, a third gate insulating layer is provided on the side of the first gate of the driving transistor away from the substrate, and a storage capacitor electrode is provided on the side of the third gate insulating layer away from the substrate. The orthographic projection of the storage capacitor electrode on the substrate overlaps with the orthographic projection of the first gate of the driving transistor on the substrate, and the storage capacitor electrode and the first gate of the driving transistor constitute a storage capacitor.

[0012] In some embodiments, the array substrate includes an interlayer insulating layer disposed on the side of the storage capacitor electrode away from the substrate and at least one second transition metal disposed on the side of the interlayer insulating layer away from the substrate; one end of the second transition metal is electrically connected to the first transition metal via a second connection portion, the first transition metal is electrically connected to the first conductor region, the second conductor region, or the third conductor region, and the second connection portion penetrates the interlayer insulating layer and the third gate insulating layer along the thickness direction of the array substrate; or the second transition metal is electrically connected to the first conductor region, the second conductor region, or the third conductor region via a third connection portion, the third connection portion penetrating the interlayer insulating layer, the third gate insulating layer, the second gate insulating layer, and the first gate insulating layer along the thickness direction of the array substrate, or penetrating the interlayer insulating layer, the third gate insulating layer, and the second gate insulating layer along the thickness direction of the array substrate; the other end of the second transition metal is electrically connected to the trace to be transitioned.

[0013] In some embodiments, the array substrate includes an interlayer insulating layer disposed on the side of the storage capacitor electrode away from the substrate and a third transition metal disposed on the side of the interlayer insulating layer away from the second substrate. One end of the third transition metal is electrically connected to the storage capacitor electrode via the fourth connection portion, and the other end is electrically connected to the first gate via the fifth connection portion. The fourth connection portion penetrates the interlayer insulating layer along the thickness direction of the array substrate, and the fifth connection portion penetrates the interlayer insulating layer, the third gate insulating layer, and the second gate insulating layer along the thickness direction of the array substrate.

[0014] In some embodiments, the first material layer is a monocrystalline silicon layer, and the second material layer is a polycrystalline silicon layer or an amorphous silicon layer.

[0015] In some embodiments, a buried oxide layer is further included between the single-crystal silicon layer and the insulating buffer layer, and the single-crystal silicon layer, the buried oxide layer, and the substrate constitute silicon-on-insulator.

[0016] In some embodiments, the first conductor region, the second conductor region, and the third conductor region are heavily doped regions.

[0017] A second aspect of this application provides a method for manufacturing an array substrate, comprising the following steps:

[0018] An insulating buffer layer is formed on one side of the substrate.

[0019] A first material layer is formed on the side of the insulating buffer layer away from the substrate. The first material layer is patterned using a photolithography-etching process to form at least one first semiconductor region and a first conductor region located around the first semiconductor region. The first semiconductor region forms the first active layer of the first thin film transistor. The first conductor regions located on opposite sides of the first active layer form the first electrode and the second electrode of the first thin film transistor. The first electrode and the second electrode are in direct contact with and electrically connected to the first active layer.

[0020] A first gate insulating layer is formed on the side of the material layer away from the substrate.

[0021] A second material layer is formed on the side of the gate insulating layer away from the substrate. The second material layer is patterned using a photolithography-etching process to form a second conductor region, a second semiconductor region, and a third conductor region located around the second semiconductor region. The second conductor region is disposed opposite to the first active layer along the thickness direction of the array substrate to form the first gate of the first thin film transistor. The second semiconductor region forms the second active layer of the second thin film transistor. The third conductor regions located on opposite sides of the second active layer form the third and fourth electrodes of the second thin film transistor. The third and fourth electrodes are in direct contact and electrically connected to the second active layer.

[0022] A second gate insulating layer is formed on the side of the second material layer away from the substrate.

[0023] A second gate is formed on the side of the second gate insulating layer away from the substrate, and the second gate is disposed opposite to the second active layer along the thickness direction of the array substrate.

[0024] The first gate of one of the first thin-film transistors is electrically connected to the fourth electrode of the adjacent second thin-film transistor in the same layer.

[0025] In some embodiments, the step of forming the first material layer is as follows:

[0026] A wafer is provided, and the wafer is thermally oxidized at room temperature to form an oxide layer on the outer surface of the wafer, and a predetermined dose of hydrogen ions is implanted to form a weakening layer within a predetermined depth of the wafer.

[0027] The wafer is bonded to the insulating buffer layer at room temperature, with the weakening layer positioned close to the insulating buffer layer.

[0028] The bonded wafer, the insulating buffer layer, and the substrate are subjected to low-temperature annealing, so that the first portion of the wafer located on the side of the weakening layer away from the insulating buffer layer is peeled off along the weakening layer to remove the first portion.

[0029] The remaining wafer, the insulating buffer layer, and the substrate are subjected to high-temperature annealing.

[0030] The remaining wafer surface away from the insulating buffer layer is polished to form the first material layer and obtain silicon on insulator. The oxide layer of the first material layer near the insulating buffer layer is the buried oxide layer of the silicon on insulator, and the substrate is the base of the silicon on insulator.

[0031] In some embodiments, the step of forming the second conductor region and the third conductor region in the second material layer is as follows:

[0032] Using the second gate as a mask, self-aligned ion implantation is performed on the patterned second material layer to form a second conductor region and a third conductor region.

[0033] A third aspect of this application provides a display device, the display device comprising the array substrate described above.

[0034] Beneficial effects of the embodiments in this application:

[0035] The array substrate, its fabrication method, and display device provided in this application embodiment are characterized by the following: the first gate of the first thin-film transistor of the array substrate is disposed on the same layer as the third electrode, second active layer, and fourth electrode of the second thin-film transistor. Furthermore, the first gate of one of the first thin-film transistors is directly electrically connected to the fourth electrode of its adjacent second thin-film transistor. This is because both the first gate and the fourth electrode are disposed on the second material layer, and their continuous arrangement allows for direct electrical connection without vias, thus effectively reducing the need for vias. Similarly, the first active layer, first electrode, and second electrode of the first thin-film transistor are all disposed on the first material layer, and their continuous arrangement allows for direct electrical connection without vias, further reducing the need for vias and improving the resolution of the array substrate. Simultaneously, the first and second thin-film transistors are stacked vertically along the thickness direction of the array substrate, increasing their arrangement density and further enhancing the resolution of the array substrate.

[0036] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0038] Figure 1 This is a schematic diagram of the structure of an array substrate provided in one embodiment of the present application, wherein the first thin-film transistor and the second thin-film transistor are mainly labeled.

[0039] Figure 2 for Figure 1 The array substrate, with the first and second material layers as the main components, is marked.

[0040] Figure 3A schematic diagram of the pixel driving circuit of the array substrate in one embodiment is provided for the purpose of this application.

[0041] Figure 4 This is a schematic diagram of the structure of the array substrate provided in one embodiment of the present application;

[0042] Figure 5 A schematic diagram illustrating the steps of forming a buffer insulating layer on an array substrate according to an embodiment of this application;

[0043] Figure 6 A schematic diagram illustrating the steps of thermal oxidation and hydrogen implantation of a wafer when forming a first material layer on an array substrate provided in an embodiment of this application;

[0044] Figure 7 This is a schematic diagram of bonding a wafer to a substrate and then removing the first part by low-temperature annealing.

[0045] Figure 8 This is a schematic diagram illustrating the polishing and patterning of the surface of a single-crystal silicon layer.

[0046] Figure 9 A schematic diagram of forming a first gate insulating layer on the surface of a first material layer;

[0047] Figure 10 A schematic diagram showing the formation of a second material layer on the surface of the first gate insulating layer;

[0048] Figure 11 This is a schematic diagram illustrating the patterning of the second material layer;

[0049] Figure 12 A schematic diagram showing the formation of a second gate insulating layer on the surface of a second material layer;

[0050] Figure 13 A schematic diagram for forming the second gate and the first transition metal;

[0051] Figure 14 This is a schematic diagram of conductor-forming the second material layer using the second gate and the first transition metal as masks.

[0052] Figure 15 This is a schematic diagram showing the formation of the third gate insulating layer, storage capacitor electrode, and interlayer insulating layer with vias.

[0053] The attached figures are labeled as follows:

[0054] Substrate 100; Insulating buffer layer 110;

[0055] First thin-film transistor 200; first material layer 210; first active layer 210a; first electrode 210b; second electrode 210c; first semiconductor region 2101; first conductor region 2102; first gate insulating layer 220; first gate 230; third gate insulating layer 240; storage capacitor electrode 250; interlayer insulating layer 260; via 2601; second transition metal 270; second connection portion 2701; third transition metal 280; fourth connection portion 2801; fifth connection portion 2802;

[0056] Second thin-film transistor 300; second material layer 310; second active layer 310a; third electrode 310b, fourth electrode 310c; second conductor region 3101; second semiconductor region 3102; third conductor region 3103; second gate insulating layer 320; second gate 330; first transition metal 340; first connection portion 3401; thickness direction H;

[0057] Wafer 400; Buried oxide layer 410; Weakening layer 420; First part 430;

[0058] Transistor T1; Transistor T2; Transistor T3; Transistor T4; Transistor T5; Transistor T6; Transistor T7; Connection point A. Detailed Implementation

[0059] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0060] This application provides an array substrate, such as... Figure 1 and Figure 2 As shown, where Figure 1 The markings are primarily based on the angles of the first thin-film transistor 200 and the second thin-film transistor 300. Figure 2The designation is primarily based on the angles of the first material layer 210 and the second material layer 310. The array substrate includes: a substrate 100, an insulating buffer layer 110 formed on one side of the substrate 100, multiple sets of first thin-film transistors 200, and multiple sets of second thin-film transistors 300. The first thin-film transistor 200 includes a first active layer 210a, a first electrode 210b, a second electrode 210c, a first gate 230, and a first gate insulating layer 220 disposed between the first active layer 210a and the first gate 230. The first active layer 210a, the first electrode 210b, and the second electrode 210c are all disposed on the first material layer 210. The first gate 230 is disposed on the second material layer 310. The first gate 230 is disposed opposite to the first active layer 210a along the thickness direction H of the array substrate. The first material layer 210 is disposed on the side of the insulating buffer layer 110 away from the substrate 100. The first electrode 210b and the second electrode 210c are located on opposite sides of the first active layer 210a. The first material layer 210 includes at least one first semiconductor region 2101 and a first conductor region 2102 located around the first semiconductor region 2101. The first active layer 210a is located in the first semiconductor region 2101, and the first electrode 210b and the second electrode 210c are located in the first conductor region 2102 and are in direct contact with and electrically connected to the first active layer 210a. The second thin-film transistor 300 includes a second active layer 310a, a third electrode 310b, a fourth electrode 310c, a second gate 330, and a second gate insulating layer 320 disposed between the second active layer 310a and the second gate 330. The second active layer 310a, the third electrode 310b, and the fourth electrode 310c are all disposed on the second material layer 310, and the third electrode 310b and the fourth electrode 310c are located on opposite sides of the second active layer 310a. The second gate 330 is disposed opposite to the second active layer 310a along the thickness direction H of the array substrate. The second material layer 310 includes a second conductor region 3101 where the first gate 230 is located, at least one second semiconductor region 3102, and a third conductor region 3103 located around the second semiconductor region 3102. The second active layer 310a is located in the second semiconductor region 3102, and the third electrode 310b and the fourth electrode 310c are located in the third conductor region 3103 and are in direct contact with and electrically connected to the second active layer 310a. The first gate 230 of one of the first thin film transistors 200 and the fourth electrode 310c of the adjacent second thin film transistor 300 are connected in the same layer.

[0061] In this configuration, one of the first electrode 210b and the second electrode 210c serves as either the source or drain of the first thin-film transistor 200, and the other serves as either the drain or source of the first thin-film transistor 200. For example, when the first electrode 210b is the source of the first thin-film transistor 200, the second electrode 210c serves as the drain of the first thin-film transistor 200. Similarly, one of the third electrode 310b and the fourth electrode 310c serves as either the source or drain of the second thin-film transistor 300, and the other serves as either the drain or source of the second thin-film transistor 300. For example, when the third electrode 310b is the source of the second thin-film transistor 300, the fourth electrode 310c serves as the drain of the second thin-film transistor. Furthermore, it should be noted that the first gate 230 of the first thin-film transistor 200 can be electrically connected to the fourth electrode 310c of an adjacent second thin-film transistor 300 via a co-layer contact, or it can be electrically connected to the fourth electrodes 310c of two second thin-film transistors 300 via a co-layer contact. When the fourth electrode 310c of the two second thin-film transistors 300 is electrically connected in the same layer, the fourth electrode 310c can be the source of the two second thin-film transistors 300 or the drain of the two second thin-film transistors 300, or one can be the source of the second thin-film transistor 300 and the other can be the drain of the second thin-film transistor 300.

[0062] The first gate 230 of the first thin-film transistor 200 is disposed on the same layer as the third electrode 310b, the second active layer 310a, and the fourth electrode 310c of the second thin-film transistor 300. Furthermore, the first gate 230 of one of the first thin-film transistors 200 is directly electrically connected to the fourth electrode 310c of its adjacent second thin-film transistor 300. This is because both the first gate 230 and the fourth electrode 310c are disposed on the second material layer 310, and their continuous arrangement allows for direct electrical connection without the need for vias 2601, thus effectively reducing the number of vias 2601. Similarly, the first active layer 210a, the first electrode 210b, and the second electrode 210c of the first thin-film transistor 200 are all disposed on the first material layer 210, and their continuous arrangement allows for direct electrical connection without the need for vias 2601, further reducing the number of vias 2601 and thus improving the resolution of the array substrate. Meanwhile, the first thin-film transistor 200 and the second thin-film transistor 300 are stacked vertically in the thickness direction H of the array substrate, which can increase the arrangement density of the first thin-film transistor 200 and the second thin-film transistor 300, and is beneficial to further improve the resolution of the array substrate.

[0063] In addition, such as Figure 2As shown, the first electrode 210b, the first active layer 210a, and the second electrode 210c of the first thin-film transistor 200 are all located in the same material layer, namely the first material layer 210. The first gate 230 of the first thin-film transistor 200, the third electrode 310b, the second active layer 310a, and the fourth electrode 310c of the second thin-film transistor 300 are all located in the same material layer, namely the second material layer 310. This greatly reduces the number of film layers on the array substrate, which is beneficial to simplify the design process and reduce the overall thickness of the array substrate. The reduction in the number of film layers can also improve the light extraction efficiency of the array substrate, thereby improving the display brightness of the array substrate.

[0064] The second gate 330 can be a gate made of a metallic material, such as molybdenum, titanium, tungsten, nickel, tungsten-rhenium alloy, or tungsten-molybdenum alloy. The buffer insulating layer can be silicon nitride, silicon oxide, or a composite layer of silicon nitride and silicon oxide. The buffer insulating layer is used to prevent moisture, metal ions, etc., from entering the device, ensuring the stability of the device.

[0065] A first gate insulating layer 220 is deposited on the side of the first material layer 210 away from the substrate 100. The first gate insulating layer 220 is mostly a silicon oxide layer, and its thickness is generally 50nm-200nm, such as 50nm, 80nm, 100nm, 150nm, 200nm, etc. The specific thickness can be determined according to the device V. th (Threshold voltage) or I on The requirements for (on-state current) are adjusted. A second gate insulating layer 320 is deposited on the side of the second material layer 310 away from the substrate 100. The second gate insulating layer 320 is generally a silicon oxide layer with a thickness of 50nm-200nm, such as 50nm, 80nm, 100nm, 150nm, 200nm, etc.

[0066] In some embodiments, combined with Figure 1 , Figure 2 and Figure 3 As shown, the array substrate includes multiple pixel driving circuits. Each pixel driving circuit includes a driving transistor and a first switching transistor. The driving transistor is a first thin-film transistor 200, and the first switching transistor is a second thin-film transistor 300. The gate of the driving transistor and the drain of the first switching transistor are electrically connected in the same layer.

[0067] The driving transistor and the switching transistor are a first thin-film transistor 200 and a second thin-film transistor 300, respectively. Since the first active layer 210a of the first thin-film transistor 200 and the second active layer 310a of the second thin-film transistor are respectively made of a first material layer 210 and a second material layer 310, they can be different types of thin-film transistors, facilitating the selection of appropriate materials based on the characteristics of the driving transistor and the switching transistor. Furthermore, the gate of the driving transistor and the drain of the first switching transistor are electrically connected in the same layer, that is, the first gate 230 of the first thin-film transistor 200 and the fourth electrode 310c of the second thin-film transistor 300 are electrically connected in the same layer, eliminating the need for electrical connection through via 2601. This reduces the number of vias 2601, which is beneficial for improving the pixel resolution of the array substrate and simplifying the structure.

[0068] Optionally, each pixel driving circuit further includes a second switching transistor, which is a first thin-film transistor 200, and the source or drain of the driving transistor is directly contacted and electrically connected to the drain or source of the second switching transistor.

[0069] The first switching transistor is a second thin-film transistor 300, and the second switching transistor is a first thin-film transistor 200. This allows the first and second switching transistors of the pixel driving circuit to be distributed on the second material layer 310 and the first material layer 210, respectively, making full use of the stacked space. The source or drain of the driving transistor is directly contacted and electrically connected to the drain or source of the second switching transistor. That is, the first electrode 210b or the second electrode 210c of one of the two adjacent first thin-film transistors 200 is directly contacted and electrically connected to the second electrode 210c or the first electrode 210b of the other first thin-film transistor 200. The two do not need to be electrically connected through via 2601, which reduces the setting of via 2601, which is beneficial to improving the pixel resolution of the array substrate and simplifies the structure.

[0070] Optionally, there are multiple first switching transistors and second switching transistors, and the source or drain of one of the adjacent first switching transistors is directly contacted and electrically connected to the drain of the other, and the source or drain of one of the adjacent second switching transistors is directly contacted and electrically connected to the drain or source of the other.

[0071] Adjacent first thin-film transistors 200 are electrically connected through direct contact between their source and drain, and adjacent second thin-film transistors 300 are also electrically connected through direct contact between their source and drain. There is no need for electrical connection through via 2601, which reduces the number of vias 2601, which is beneficial to improving the pixel resolution of the array substrate and simplifies the structure.

[0072] The pixel driving circuit provided in this embodiment can be as follows: Figure 3The 7T1C structure shown can also be 2T1C or other structures, and this application does not limit this. When the pixel driving circuit is a 2T1C structure, that is, the pixel driving circuit includes one driving transistor and one switching transistor, wherein the driving transistor is the first thin-film transistor 200, and when there is only one switching transistor, the switching transistor is the first switching transistor, which is also the second thin-film transistor 300. When the pixel driving circuit... Figure 3 In the 7T1C structure shown, the pixel driving circuit includes a driving transistor and multiple switching transistors, wherein the driving transistor is the first thin-film transistor 200, which is... Figure 3 Transistor T3 in the middle, Figure 3 The connection point A indicated by the middle arrow is... Figure 1 , Figure 2 The position where the first gate 230 and the fourth gate 310c are directly connected is from Figure 3 This means that the gate of transistor T3 is electrically connected to the source or drain of transistor T4, and the source or drain of transistor T2. The multiple switching transistors in the 7T1C structure include both the first and second switching transistors, that is, both the second thin-film transistor 300 and the first thin-film transistor 200. The number of second thin-film transistors 300 and first thin-film transistors 200 can be determined by considering spatial arrangement and functional requirements. Figure 3 T1-T7 are transistor numbers, representing transistors T1 through T7 respectively. Transistors T1, T3, T5, and T6 have direct electrical connections between their sources and drains, therefore they can all be located on the first material layer 210, i.e., the first thin-film transistor 200. Transistors T2, T4, and T7 have direct electrical connections between their sources and drains, therefore they can all be located on the second material layer 310, i.e., the second thin-film transistor 300. Figure 3In this configuration, the gate of transistor T1 is connected to the EM (control) signal. One of the sources and drains of transistor T1 is electrically connected to VDD (input voltage), and the other is electrically connected to one of the sources and drains of transistor T3. The other source and drain of transistor T3 is electrically connected to one of the sources and drains of transistor T6. The other source and drain of transistor T6 is connected to the DATA (data) signal, and its gate is connected to the GATE (gate drive) signal. The gate of transistor T3 is electrically connected to one of the sources and drains of transistors T2 and T4, and this connection can be made directly without vias. The gate of transistor T2 is connected to the GATE signal. One of the sources and drains of transistor T2 and one of the sources and drains of transistor T3 are electrically connected to one of the sources and drains of transistor T5. The gate of transistor T5 is connected to the EM signal. The other of the sources and drains of transistor T5 is electrically connected to VSS (output voltage) and one of the sources and drains of transistor T7, respectively. The gate of transistor T7 is connected to the RST (Reset) signal. The other of the sources and drains of transistor T7 is electrically connected to the INT (Initial) signal and the other of the sources and drains of transistor T4, respectively. The gate of transistor T4 is connected to the RST signal.

[0073] like Figure 1 , Figure 2 As shown, the array substrate includes at least one first transition metal 340, which is disposed on the same layer as the second gate 330. One end of the first transition metal 340 is electrically connected to the first conductor region 2102, the second conductor region 3101, or the third conductor region 3103 through a first connection portion 3401. The first connection portion 3401 penetrates the second gate insulating layer 320 and the first gate insulating layer 220 along the thickness direction H of the array substrate, or penetrates the second gate insulating layer 320 along the thickness direction H of the array substrate. The other end of the first transition metal 340 is electrically connected to the trace to be transitioned.

[0074] One end of the first transition metal 340 can be electrically connected to the first conductor region 2102 through the first connection portion 3401. At this time, the first connection portion 3401 needs to penetrate the second gate insulating layer 320 and the first gate insulating layer 220. The other end of the first transition metal 340 can be electrically connected to the trace to be transitioned, such as the anode trace.

[0075] One end of the first adapter metal 340 can also be electrically connected to the second conductor region 3101 through the first connection part 3401. At this time, the first connection part 3401 needs to penetrate the second gate insulating layer 320. The other end of the first adapter metal 340 can be electrically connected to the trace to be transferred.

[0076] One end of the first adapter metal 340 can also be electrically connected to the third conductor region 3103 through the first connection part 3401. At this time, the first connection part 3401 needs to penetrate the second gate insulating layer 320. The other end of the first adapter metal 340 can be electrically connected to the trace to be transferred.

[0077] The first transition metal 340 and the second gate 330 are arranged on the same layer, which can simplify the manufacturing process.

[0078] In some embodiments, such as Figure 1 , Figure 2 As shown, a third gate insulating layer 240 is provided on the side of the first gate 230 of the driving transistor away from the substrate 100. A storage capacitor electrode 250 is provided on the side of the third gate insulating layer 240 away from the substrate 100. The orthographic projection of the storage capacitor electrode 250 on the substrate 100 overlaps with the orthographic projection of the first gate 230 of the driving transistor on the substrate 100. The storage capacitor electrode 250 and the first gate 230 of the driving transistor constitute a storage capacitor.

[0079] The storage capacitor is used to store data signals. After the scanning signal pulse of the pixel unit ends, the storage capacitor can still maintain the voltage of the first gate 230 of the driving transistor.

[0080] A third gate insulating layer 240 is deposited on the side of the second gate 330 away from the substrate 100. The third gate insulating layer 240 is generally silicon oxide.

[0081] In some embodiments, such as Figure 1 , Figure 2 As shown, the array substrate includes an interlayer insulating layer 260 disposed on the side of the storage capacitor electrode 250 away from the substrate 100 and at least one second transition metal 270 disposed on the side of the interlayer insulating layer 260 away from the substrate 100. One end of the second transition metal 270 is electrically connected to the first transition metal 340 via the second connecting portion 2701. The first transition metal 340 is electrically connected to the first conductor region 2102, the second conductor region 3101, or the third conductor region 3103. The second connecting portion 2701 penetrates the interlayer insulating layer 260 and the third gate insulating layer 240 along the thickness direction H of the array substrate. Alternatively, the second transition metal 270 is electrically connected to the first conductor region 2102, the second conductor region 3101, or the third conductor region 3103 via the third connecting portion (not shown in the figure). The third connecting portion penetrates the interlayer insulating layer 260, the third gate insulating layer 240, the second gate insulating layer 320, and the first gate insulating layer 220 along the thickness direction H of the array substrate. Or, it penetrates the interlayer insulating layer 260, the third gate insulating layer 240, and the second gate insulating layer 320 along the thickness direction H of the array substrate. The other end of the second transition metal 270 is electrically connected to the trace to be transitioned.

[0082] The array substrate includes a first transition metal 340 and a second transition metal 270, which can distribute the traces that need to be transitioned on the two transition metal layers, reduce the number of transition metals set on the same layer, thereby helping to optimize the layout of the array substrate and improve the pixel resolution of the array substrate.

[0083] The second transition metal 270 can be electrically connected to the first transition metal 340 through the second connection part 2701. At this time, the second connection part 2701 needs to penetrate the interlayer insulating layer 260 and the third gate insulating layer 240. The other end of the second transition metal 270 can be electrically connected to the trace to be transferred, such as the anode trace, and then electrically connected to the first conductor region 2102, the second conductor region 3101, or the third conductor region 3103 through the first transition metal 340.

[0084] One end of the second transition metal 270 can be electrically connected to the first conductor region 2102 through the third connection portion. At this time, the third connection portion needs to penetrate the interlayer insulating layer 260, the third gate insulating layer 240, the second gate insulating layer 320 and the first gate insulating layer 220. The other end of the second transition metal 270 can be electrically connected to the trace to be transitioned, such as the anode trace.

[0085] One end of the second transition metal 270 can also be electrically connected to the second conductor region 3101 through the third connection portion. In this case, the third connection portion needs to penetrate the interlayer insulating layer 260, the third gate insulating layer 240 and the second gate insulating layer 320. The other end of the second transition metal 270 can be electrically connected to the trace to be transitioned.

[0086] One end of the second adapter metal 270 can also be electrically connected to the third conductor region 3103 through the third connection portion. In this case, the third connection portion needs to penetrate the interlayer insulating layer 260, the third gate insulating layer 240 and the second gate insulating layer 320. The other end of the second adapter metal 270 can be electrically connected to the trace to be transferred.

[0087] It should be noted that the second adapter metal 270 and the first adapter metal 340 can be set simultaneously or individually.

[0088] In some embodiments, such as Figure 1 , Figure 2As shown, the array substrate includes an interlayer insulating layer 260 disposed on the side of the storage capacitor electrode 250 away from the substrate 100 and a third transition metal 280 disposed on the side of the interlayer insulating layer 260 away from the second substrate 100. One end of the third transition metal 280 is electrically connected to the storage capacitor electrode 250 via a fourth connection portion 2801, and the other end is electrically connected to the first gate 230 via a fifth connection portion 2802. The fourth connection portion 2801 penetrates the interlayer insulating layer 260 along the thickness direction H of the array substrate, and the fifth connection portion 2802 penetrates the interlayer insulating layer 260, the third gate insulating layer 240 and the second gate insulating layer 320 along the thickness direction H of the array substrate.

[0089] In this embodiment, the third transition metal 280 is used for interconnection between the storage capacitor electrode 250 and the first gate 230, so that one electrode of the storage capacitor is at the same potential as the first gate 230, thereby increasing the storage capacity of the storage capacitor.

[0090] Optionally, such as Figure 1 , Figure 2 As shown, the first material layer 210 is a monocrystalline silicon layer, and the second material layer 310 is a polycrystalline silicon layer or an amorphous silicon layer.

[0091] The thickness of the monocrystalline silicon layer ranges from 10nm to 100nm, for example, it can be 10nm, 20nm, 50nm, 80nm, 100nm, etc. Because monocrystalline silicon has a high carrier mobility, which is beneficial for carrier transport, monocrystalline silicon thin-film transistors have a fast response speed and improved performance. While maintaining the same response speed, compared to polycrystalline silicon or amorphous silicon thin-film transistors, the aspect ratio of the active layer of a monocrystalline silicon thin-film transistor can be made smaller, thus reducing the size of the transistor and improving the resolution of the array substrate.

[0092] Thin-film transistors using monocrystalline silicon offer advantages such as uniform characteristics, stabilization, and high performance, meeting the requirements for uniformity in driving transistors, as well as high on-state current and low on-state resistance.

[0093] For the second thin-film transistor 300, there are no high requirements for on-state current, so amorphous silicon or polycrystalline silicon thin-film transistors can be used. Furthermore, the fabrication processes for amorphous silicon and polycrystalline silicon are simpler than those for monocrystalline silicon. Therefore, using amorphous silicon or monocrystalline silicon thin-film transistors for thin-film transistors with less stringent requirements helps reduce costs.

[0094] To further improve the control accuracy and stability of the drive circuit, the second material layer 310 can be a low-temperature polycrystalline silicon (LTPS) layer. LTPS thin-film transistors have higher carrier mobility, providing shorter response times and higher refresh rates. Compared with traditional monocrystalline silicon fabrication processes, LTPS fabrication has lower costs, higher production efficiency, and a simpler process flow. LTPS also has a faster curing speed, which can accelerate the production cycle and increase delivery speed.

[0095] Therefore, the first material layer 210 uses monocrystalline silicon and the second material layer 310 uses low-temperature polycrystalline silicon, which not only improves the overall performance of the thin-film transistor, but also helps to save costs.

[0096] In some embodiments, such as Figure 4 As shown, a buried oxide layer 410 is also included between the single crystal silicon layer and the insulating buffer layer. The single crystal silicon layer, the buried oxide layer 410 and the substrate 100 constitute silicon-on-insulator.

[0097] Silicon-on-Insulator (SOI) materials offer unparalleled advantages over bulk silicon: they enable dielectric isolation of components in integrated circuits, completely eliminating the parasitic latch-up effect present in bulk silicon CMOS circuits. Integrated circuits made with this material also exhibit advantages such as low parasitic capacitance, high integration density, high speed, simple fabrication process, minimal short-channel effect, and suitability for low-voltage, low-power circuits. Specifically, the buried oxide layer 410 reduces the parasitic capacitance between the first electrode 210b and the second electrode 210c, and effectively suppresses electron flow from the first electrode 210b to the second electrode 210c, thereby significantly reducing leakage current that leads to performance degradation.

[0098] like Figure 2 As shown, the first conductor region 2102 of the first material layer 210, the second conductor region 3101 and the third conductor region 3103 of the second material layer 310 are heavily doped regions.

[0099] By designating the first conductor region 2102, the second conductor region 3101, and the third conductor region 3103 as heavily doped regions, the resistivity of the connecting wire is greatly reduced.

[0100] The formation of the second conductor region 3101 and the third conductor region 3103 can be achieved by self-aligned ion implantation of the second material layer 310 using the second gate 330 as a mask. This not only allows for the fabrication of the third electrode 310b and the fourth electrode 310c of the second thin-film transistor 300, but also enables the heavy doping of the first gate 230 of the first thin-film transistor 200 and the connection line connecting the first gate 230 and the fourth electrode 310c, significantly reducing the resistivity of the connection line.

[0101] A second aspect of this application provides a method for manufacturing an array substrate, which includes the following steps:

[0102] S1: An insulating buffer layer 110 is formed on one side of the substrate 100, such as... Figure 5 As shown.

[0103] S2: A first material layer 210 is formed on the side of the insulating buffer layer 110 away from the substrate 100. The first material layer 210 is patterned using a photolithography-etching process to form at least one first semiconductor region 2101 and a first conductor region 2102 located around the first semiconductor region 2101. The first semiconductor region 2101 forms the first active layer 210a of the first thin-film transistor 200. The first conductor regions 2102 located on opposite sides of the first active layer 210a form the first electrode 210b and the second electrode 210c of the first thin-film transistor 200. The first electrode 210b and the second electrode 210c are in direct contact with and electrically connected to the first active layer 210a. Figures 6-8 As shown.

[0104] S3: A first gate insulating layer 220 is formed on the side of a material layer away from the substrate 100, such as... Figure 9 As shown.

[0105] S4: A second material layer 310 is formed on the side of the gate insulating layer away from the substrate 100. The second material layer 310 is patterned using a photolithography-etching process to form a second conductor region 3101, a second semiconductor region 3102, and a third conductor region 3103 located around the second semiconductor region 3102. The second conductor region 3101 is disposed opposite to the first active layer 210a along the thickness direction H of the array substrate to form the first gate 230 of the first thin-film transistor 200. The second semiconductor region 3102 forms the second active layer 310a of the second thin-film transistor 300. The third conductor regions 3103 located on opposite sides of the second active layer 310a form the third electrode 310b and the fourth electrode 310c of the second thin-film transistor 300. The third electrode 310b and the fourth electrode 310c are directly contacted and electrically connected to the second active layer 310a. Figure 10 , Figure 11 As shown.

[0106] S5: A second gate insulating layer 320 is formed on the side of the second material layer 310 away from the substrate 100, such as... Figure 12 As shown.

[0107] S6: A second gate 330 is formed on the side of the second gate insulating layer 320 away from the substrate 100. The second gate 330 is disposed opposite to the second active layer 310a along the thickness direction H of the array substrate. Figure 13 , Figure 14 As shown.

[0108] The first gate 230 of one of the first thin film transistors 200 is electrically connected to the fourth terminal 310c of the adjacent second thin film transistor 300 in the same layer.

[0109] In this embodiment, the photolithography-etching process refers to depositing photoresist, developing and exposing the photoresist to form a photomask, and then using the photomask to etch the areas that need to be etched. The specific etching process can be dry etching or wet etching.

[0110] In the array substrate fabricated by this method, the first electrode 210b, second electrode 210c, and first active layer 210a of the first thin-film transistor 200 are all formed on the first material layer 210, requiring only one deposition process, which simplifies the fabrication process. Similarly, the third electrode 310b, fourth electrode 310c, second active layer 310a, and first gate 230 of the second thin-film transistor 300 are all formed on the second material layer 310, which can also be completed in a single deposition process, further simplifying the fabrication. Furthermore, since the first gate 230 and fourth electrode 310c are fabricated on the same layer, they can be directly electrically connected through the continuous arrangement of the second material layer 310, without the need for vias 2601, thus effectively reducing the number of vias 2601. Additionally, the source and drain electrodes of the first and second thin-film transistors 200 and 300 can also be directly contacted and electrically connected without the need for vias 2601, further reducing the number of vias 2601 and thus improving the resolution of the array substrate. Meanwhile, the first thin-film transistor 200 and the second thin-film transistor 300 are stacked vertically in the thickness direction H of the array substrate, which can increase the arrangement density of the first thin-film transistor 200 and the second thin-film transistor 300, and is beneficial to further improve the resolution of the array substrate.

[0111] Optionally, the steps for forming the first material layer 210 are as follows:

[0112] S21: Provide a wafer 400, perform thermal oxidation on the wafer 400 at room temperature to form an oxide layer on the outer surface of the wafer 400, and implant a predetermined amount of hydrogen ions to form a weakening layer 420 within a predetermined depth of the wafer 400, such as... Figure 6 As shown.

[0113] S22: Following the method of bringing the weakening layer 420 close to the insulating buffer layer 110, the wafer 400 and the insulating buffer layer 110 are bonded at room temperature, such as... Figure 7 As shown.

[0114] S23: The bonded wafer 400, insulating buffer layer 110, and substrate 100 are subjected to low-temperature annealing, causing the first portion 430 of the wafer 400 located on the side of the weakening layer 420 away from the insulating buffer layer to be peeled off along the weakening layer 420, removing the first portion 430, as shown. Figure 7 As shown.

[0115] S24: Perform high-temperature annealing on the remaining wafer 400, insulating buffer layer 110, and substrate 100.

[0116] S25: Polish the surface of the remaining wafer 400 away from the insulating buffer layer 110 to form a first material layer 210, thus obtaining silicon-on-insulator (SiO2). The oxide layer on the side of the first material layer 210 closest to the insulating buffer layer 110 is the buried oxide layer 410 of SiO2, and the substrate 100 is the substrate of SiO2. Figure 8 As shown.

[0117] The above-described manufacturing process can be called the Smart-cut process, which has the advantage of low injection dosage; for example, the injection dosage of hydrogen ions can be 10. 16 cm -2 Furthermore, this process can be completed using a conventional ion implanter. The buried oxide layer 410 is formed by thermal oxidation, exhibiting a good Si / SiO2 interface and high oxide layer quality. The stripped substrate can continue to serve as a bonding substrate, significantly reducing production costs.

[0118] Optionally, the step of forming the second material layer 310 is as follows:

[0119] S41: An amorphous silicon (α-Si) layer is deposited on the side of the first gate insulating layer 220 away from the substrate 100, and the amorphous silicon is crystallized using excimer laser annealing (ELA) to form a second material layer 310 of low-temperature polycrystalline silicon, and then patterned, such as... Figure 10 , Figure 11 As shown.

[0120] By using the ELA process to convert a-Si into low-temperature polycrystalline silicon, LTPS is more ordered than traditional TFT-a-Si, so electrons can easily pass through the circuit, i.e., the electron mobility is improved, which can significantly improve the performance of thin-film transistors.

[0121] Optionally, after forming the second gate 330, the step of forming the second conductor region 3101 and the third conductor region 3103 on the second material layer 310 is as follows:

[0122] S61: Using the second gate 330 as a mask, self-aligned ion implantation is performed on the patterned second material layer 310 to form the second conductor region 3101 and the third conductor region 3103, as follows: Figure 14 As shown.

[0123] Using the second gate 330 as a mask to perform self-aligned ion implantation on the second material layer 310 eliminates the need for a dedicated mask, reducing production costs. Furthermore, it allows for simultaneous conductor formation of the second conductor region 3101 and the third conductor region 3103, thereby improving production efficiency.

[0124] After forming the second gate 330, the following steps are also included:

[0125] S7: A third gate insulating layer 240 is formed on the side of the second gate 330 away from the substrate 100, and a storage capacitor electrode 250 is formed on the side of the third gate insulating layer 240 away from the substrate 100. The orthographic projection of the storage capacitor electrode 250 onto the substrate 100 overlaps with the orthographic projection of the first gate 230 onto the substrate 100. An interlayer insulating layer 260 is formed on the side of the storage capacitor electrode 250 away from the substrate 100, and the interlayer insulating layer 260 is etched to form vias 2601 for the second connection portion 2701, the fourth connection portion 2801, and the fifth connection portion 2802, as shown. Figure 15 As shown.

[0126] S8: A metal layer is deposited on the side away from the interlayer insulating layer 260, and patterned to form a second transition metal 270 and a third transition metal 280, such as... Figure 4 As shown.

[0127] A third aspect of this application provides a display device, which includes the array substrate described above. The display device can be a mobile phone, computer, television, or other product with display functionality. Because the array substrate of the display device employs a stacked arrangement of first thin-film transistors 200 and second thin-film transistors 300, the arrangement density of the first and second thin-film transistors 200 and 300 can be increased, which is beneficial for further improving the resolution of the array substrate. Furthermore, the first gate 230 of one of the first thin-film transistors 200 and the fourth electrode 310c of the adjacent second thin-film transistor 300 are electrically connected at the same layer, which reduces the number of vias 2601. Additionally, there is no need for vias 2601 to electrically connect the source and drain of thin-film transistors of the same type, greatly reducing the number of vias 2601 and simplifying the connection structure of the thin-film transistors, thereby improving the resolution of the array substrate.

[0128] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0129] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0130] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. An array substrate, characterized in that, include: Substrate; An insulating buffer layer is formed on one side of the substrate. A first thin-film transistor includes a first active layer, a first electrode, a second electrode, a first gate, and a first gate insulating layer disposed between the first active layer and the first gate. The first active layer, the first electrode, and the second electrode are all disposed on a first material layer, and the first gate is disposed on a second material layer. The first gate is disposed opposite to the first active layer along the thickness direction of the array substrate. The first material layer is disposed on the side of the insulating buffer layer away from the substrate. The first electrode and the second electrode are located on opposite sides of the first active layer. The first material layer includes at least one first semiconductor region and a first conductor region located around the first semiconductor region. The first active layer is located in the first semiconductor region, and the first electrode and the second electrode are located in the first conductor region and are in direct contact with and electrically connected to the first active layer. The second thin-film transistor includes a second active layer, a third electrode, a fourth electrode, a second gate, and a second gate insulating layer disposed between the second active layer and the second gate. The second active layer, the third electrode, and the fourth electrode are all disposed on the second material layer, and the third electrode and the fourth electrode are located on opposite sides of the second active layer. The second gate is disposed opposite to the second active layer along the thickness direction of the array substrate. The second material layer includes a second conductor region where the first gate is located, at least one second semiconductor region, and a third conductor region located around the second semiconductor region. The second active layer is located in the second semiconductor region, and the third electrode and the fourth electrode are located in the third conductor region and are in direct contact with and electrically connected to the second active layer. The first gate of one of the first thin-film transistors and the fourth electrode of the adjacent second thin-film transistor are electrically connected in the same layer.

2. The array substrate according to claim 1, characterized in that, The array substrate includes multiple pixel driving circuits, each pixel driving circuit including a driving transistor and a first switching transistor. The driving transistor is a first thin-film transistor, and the first switching transistor is a second thin-film transistor. The gate of the driving transistor and the drain of the first switching transistor are connected in the same layer.

3. The array substrate according to claim 2, characterized in that, Each of the pixel driving circuits further includes a second switching transistor, which is the first thin-film transistor, and the source or drain of the driving transistor is directly contacted and electrically connected to the drain or source of the second switching transistor.

4. The array substrate according to claim 3, characterized in that, The first switching transistor and the second switching transistor are provided in multiples. The source or drain of one of the adjacent first switching transistors is directly contacted and electrically connected to the drain of the other. The source or drain of one of the adjacent second switching transistors is directly contacted and electrically connected to the drain or source of the other.

5. The array substrate according to any one of claims 1-4, characterized in that, The array substrate includes at least one first transition metal, which is disposed on the same layer as the second gate. One end of the first adapter metal is electrically connected to the first conductor region, the second conductor region, or the third conductor region through a first connecting portion. The first connecting portion penetrates the second gate insulating layer and the first gate insulating layer along the thickness direction of the array substrate, or penetrates the second gate insulating layer along the thickness direction of the array substrate. The other end of the first adapter metal is electrically connected to the trace to be transferred.

6. The array substrate according to claim 5, characterized in that, The first gate of the driving transistor has a third gate insulating layer on the side away from the substrate. The third gate insulating layer has a storage capacitor electrode on the side away from the substrate. The orthographic projection of the storage capacitor electrode on the substrate overlaps with the orthographic projection of the first gate of the driving transistor on the substrate. The storage capacitor electrode and the first gate of the driving transistor constitute a storage capacitor.

7. The array substrate according to claim 6, characterized in that, The array substrate includes an interlayer insulating layer disposed on the side of the storage capacitor electrode away from the substrate and at least one second transition metal disposed on the side of the interlayer insulating layer away from the substrate. One end of the second adapter metal is electrically connected to the first adapter metal through a second connecting portion. The first adapter metal is electrically connected to the first conductor region, the second conductor region, or the third conductor region. The second connecting portion penetrates the interlayer insulating layer and the third gate insulating layer along the thickness direction of the array substrate. Alternatively, the second transition metal can be electrically connected to the first conductor region, the second conductor region, or the third conductor region via a third connection portion, wherein the third connection portion penetrates the interlayer insulating layer, the third gate insulating layer, the second gate insulating layer, and the first gate insulating layer along the thickness direction of the array substrate, or penetrates the interlayer insulating layer, the third gate insulating layer, and the second gate insulating layer along the thickness direction of the array substrate. The other end of the second adapter metal is electrically connected to the trace to be transferred.

8. The array substrate according to claim 7, characterized in that, The array substrate includes an interlayer insulating layer disposed on the side of the storage capacitor electrode away from the substrate and a third transition metal disposed on the side of the interlayer insulating layer away from the second substrate. One end of the third transition metal is electrically connected to the storage capacitor electrode through the fourth connection portion, and the other end is electrically connected to the first gate through the fifth connection portion. The fourth connection portion penetrates the interlayer insulating layer along the thickness direction of the array substrate, and the fifth connection portion penetrates the interlayer insulating layer, the third gate insulating layer and the second gate insulating layer along the thickness direction of the array substrate.

9. The array substrate according to any one of claims 1-4, characterized in that, The first material layer is a monocrystalline silicon layer, and the second material layer is a polycrystalline silicon layer or an amorphous silicon layer.

10. The array substrate according to claim 9, characterized in that, A buried oxide layer is also included between the single crystal silicon layer and the insulating buffer layer, and the single crystal silicon layer, the buried oxide layer and the substrate constitute silicon-on-insulator.

11. The array substrate according to claim 9, characterized in that, The first conductor region, the second conductor region, and the third conductor region are heavily doped regions.

12. A method for manufacturing an array substrate, used to manufacture the array substrate according to any one of claims 1-11, characterized in that, Includes the following steps: An insulating buffer layer is formed on one side of the substrate. A first material layer is formed on the side of the insulating buffer layer away from the substrate. The first material layer is patterned using a photolithography-etching process to form at least one first semiconductor region and a first conductor region located around the first semiconductor region. The first semiconductor region forms the first active layer of the first thin film transistor. The first conductor regions located on opposite sides of the first active layer form the first electrode and the second electrode of the first thin film transistor. The first electrode and the second electrode are in direct contact with and electrically connected to the first active layer. A first gate insulating layer is formed on the side of the material layer away from the substrate. A second material layer is formed on the side of the gate insulating layer away from the substrate. The second material layer is patterned using a photolithography-etching process to form a second conductor region, a second semiconductor region, and a third conductor region located around the second semiconductor region. The second conductor region is disposed opposite to the first active layer along the thickness direction of the array substrate to form the first gate of the first thin film transistor. The second semiconductor region forms the second active layer of the second thin film transistor. The third conductor regions located on opposite sides of the second active layer form the third and fourth electrodes of the second thin film transistor. The third and fourth electrodes are in direct contact and electrically connected to the second active layer. A second gate insulating layer is formed on the side of the second material layer away from the substrate. A second gate is formed on the side of the second gate insulating layer away from the substrate, and the second gate is disposed opposite to the second active layer along the thickness direction of the array substrate; The first gate of one of the first thin-film transistors is electrically connected to the fourth electrode of the adjacent second thin-film transistor in the same layer.

13. The array substrate according to claim 12, characterized in that, The steps for forming the first material layer are as follows: A wafer is provided, and the wafer is thermally oxidized at room temperature to form an oxide layer on the outer surface of the wafer, and a predetermined dose of hydrogen ions is implanted to form a weakening layer within a predetermined depth of the wafer. The wafer and the insulating buffer layer are bonded at room temperature in such a manner that the weakening layer is close to the insulating buffer layer; The bonded wafer, the insulating buffer layer, and the substrate are subjected to low-temperature annealing, so that the first portion of the wafer located on the side of the weakening layer away from the insulating buffer layer is peeled off along the weakening layer to remove the first portion; The remaining wafer, the insulating buffer layer, and the substrate are subjected to high-temperature annealing. The remaining wafer surface away from the insulating buffer layer is polished to form the first material layer and obtain silicon on insulator. The oxide layer of the first material layer near the insulating buffer layer is the buried oxide layer of the silicon on insulator, and the substrate is the base of the silicon on insulator.

14. The array substrate according to claim 12, characterized in that, The steps for forming the second conductor region and the third conductor region in the second material layer are as follows: Using the second gate as a mask, self-aligned ion implantation is performed on the patterned second material layer to form a second conductor region and a third conductor region.

15. A display device, characterized in that, The display device includes an array substrate according to any one of claims 1-11.

Images