A current flow direction detection circuit, circuitry, and electronic device

Abstract

The application provides a current flow direction detection circuit, circuit system and electronic equipment. The current flow direction detection circuit comprises a comparison module, a first common-source amplifier, a voltage clamping module, a second common-source amplifier and a current flow direction detection module. The comparison module compares the drain voltage of the source voltage of a power tube, and changes the size of the comparison output voltage according to the comparison result. The first common-source amplifier inversely amplifies the voltage change of the comparison output voltage and outputs a first amplified voltage. The voltage clamping module clamps the difference between the first amplified voltage and the comparison output voltage within a set range. The difference between the maximum value and the minimum value of the set range is less than the power supply voltage. Therefore, when the second amplified voltage output by the second common-source amplifier is reversed, it does not need to wait for the charging and discharging time of the power supply voltage, thereby accelerating the output reversal of the second amplified voltage, and reducing the output reversal delay of the current flow direction detection circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and more particularly to a current flow direction detection circuit, circuit system, and electronic device. Background Technology

[0002] In existing automotive and industrial analog chips, integrated power transistors are often used as switches in low-side driving or DC-DC conversion scenarios. Taking an NMOS transistor as an example, the current flowing through an N-type power transistor can flow in the forward direction, that is, from the drain to the source of the NMOS transistor, or it can flow in the reverse direction, that is, from the source to the drain of the NMOS transistor.

[0003] However, in practical applications, engineers prefer that the current in a power transistor flows in only one direction. For example, in low-side drive applications, the current in the low-side power transistor typically flows from the drain to the source; in synchronous buck DC-DC applications, the current in the low-side power transistor flows from the source to the drain. If the current flow in the power transistor is opposite to the expected direction, it will cause a degrade in circuit performance or even damage the power transistor. Therefore, existing technologies typically use current flow detection circuits to detect the current flow direction in the power transistor.

[0004] However, existing current flow detection circuits have a high output reversal delay, making them unsuitable for high-frequency switching scenarios of power transistors. Summary of the Invention

[0005] The present invention provides a current flow direction detection circuit, a circuit system, and an electronic device to solve the above-mentioned technical problems, thereby reducing the output delay of the current flow direction detection circuit.

[0006] According to a first aspect of the present invention, a current flow direction detection circuit is provided for detecting the current flow direction of a power transistor, the current flow direction detection circuit comprising: A comparison module is used to compare the source voltage and drain voltage of the power transistor and change the magnitude of the comparison output voltage according to the comparison result. A first common-source amplifier is used to invert and amplify the voltage change of the comparison output voltage, and output a first amplified voltage. A voltage clamping module, wherein the first end of the voltage clamping module is connected to the output end of the comparator module, and the second end of the voltage clamping module is connected to the output end of the first common source amplifier. The voltage clamping module clamps the difference between the first amplified voltage and the comparator output voltage within a set range, wherein the difference between the maximum and minimum values ​​of the set range is less than the power supply voltage. The second common-source amplifier is used to invert and amplify the first amplified voltage and output the second amplified voltage. A current flow direction detection module detects the current flow direction of the power transistor based on the second amplified voltage.

[0007] Optionally, if the power transistor is an NMOS transistor, then the comparison module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first bias current unit. The drain of the first PMOS transistor is connected to the positive terminal of the first bias current unit, and the negative terminal of the first bias current unit is connected to the analog ground. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and the gate of the third PMOS transistor. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the power supply voltage. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and the drain of the second NMOS transistor. The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, and the channel width-to-length ratio of the second PMOS transistor is twice the channel width-to-length ratio of the third PMOS transistor. The gate of the first NMOS transistor is connected to its own drain, the drain of the second NMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor. The source of the first NMOS transistor is connected to the drain of the power transistor. The source of the second NMOS transistor is connected to the source of the third NMOS transistor, and the source of the second NMOS transistor is also connected to the source of the power transistor. The first NMOS transistor, the second NMOS transistor, and the third NMOS transistor have the same channel width-to-length ratio.

[0008] Optionally, the comparison module further includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a first resistor; the source of the fourth PMOS transistor is connected to the drain of the first PMOS transistor, the drain of the fourth PMOS transistor is connected to the first terminal of the first resistor and the gate of the first PMOS transistor, and the gate of the fourth PMOS transistor is connected to the second terminal of the first resistor, the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor; the second terminal of the first resistor is connected to the positive terminal of the first bias current unit; the source of the fifth PMOS transistor is connected to the drain of the second PMOS transistor, and the drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor; the source of the sixth PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the sixth PMOS transistor is connected to the drain of the third NMOS transistor.

[0009] Optionally, the first common-source amplifier includes a first common-source amplifying PMOS transistor and a second bias current unit. The source of the first common-source amplifying PMOS transistor is connected to the power supply voltage, and the gate of the first common-source amplifying PMOS transistor is connected to the drain of the third NMOS transistor. The drain of the first common-source amplifying PMOS transistor serves as the output terminal of the first common-source amplifier, outputting the first amplified voltage. The first common-source amplifying PMOS transistor is also connected to the positive terminal of the second bias current unit, and the negative terminal of the second bias current unit is connected to the analog ground terminal. The output current of the second bias current unit is less than the output current of the third PMOS transistor.

[0010] Optionally, the voltage clamping module includes at least one first clamping PMOS transistor and at least one second clamping PMOS transistor; The drain of the first clamping PMOS transistor is connected to the output of the comparator module. The drain of each clamping PMOS transistor is connected to the source of the preceding adjacent clamping PMOS transistor, and the gate of each clamping PMOS transistor is connected to its own drain. The source of the last clamping PMOS transistor is connected to the drain of the first common-source amplifier PMOS transistor. The sum of the on-state voltages of all clamping PMOS transistors is equal to the maximum value of the set range. The source of the first second-clamp PMOS transistor is connected to the output of the comparator module. The source of each second-clamp PMOS transistor is connected to the drain of the preceding adjacent second-clamp PMOS transistor, and the gate of each second-clamp PMOS transistor is connected to its own drain. The drain of the last second-clamp PMOS transistor is connected to the drain of the first common-source amplifier PMOS transistor. The sum of the on-state voltages of all second-clamp PMOS transistors is equal to the absolute value of the minimum value of the set range.

[0011] Optionally, the second common-source amplifier includes a second common-source amplifying PMOS transistor and a third bias current unit; the source of the second common-source amplifying PMOS transistor is connected to the power supply voltage, the drain of the second common-source amplifying PMOS transistor is connected to the positive terminal of the third bias current unit and outputs the second amplified voltage, and the gate of the second common-source amplifying PMOS transistor is connected to the drain of the first common-source amplifying PMOS transistor; the negative terminal of the third bias current unit is connected to the analog ground terminal.

[0012] Optionally, the first bias current unit includes a bias current source, a first bias NMOS transistor, and a second bias NMOS transistor; the current flow detection circuit further includes a third bias NMOS transistor, a fourth bias NMOS transistor, a first bias PMOS transistor, and a second bias PMOS transistor; the second bias current unit includes a fifth bias NMOS transistor; and the third bias current unit includes a sixth bias NMOS transistor. The positive terminal of the bias current source is connected to the power supply voltage, and the negative terminal of the bias current source is connected to the drain of the first bias NMOS transistor. The drain of the first bias NMOS transistor is connected to its own gate, the gate of the second bias NMOS transistor, and the gate of the third bias NMOS transistor. The sources of the first bias NMOS transistor, the second bias NMOS transistor, and the third bias NMOS transistor are all connected to the analog ground terminal. The drain of the first biased PMOS transistor is connected to the drain of the third biased NMOS transistor, its own gate, and the gate of the second biased PMOS transistor. The source of the first biased PMOS transistor and the source of the second biased PMOS transistor are both connected to the built-in power supply voltage. The drain of the second biased PMOS transistor is connected to the drain of the fourth biased PMOS transistor. The gate of the fourth bias NMOS transistor is connected to its own drain, the gate of the fifth bias NMOS transistor, and the gate of the sixth bias NMOS transistor. The drain of the fifth bias NMOS transistor is connected to the drain of the first common-source amplifier PMOS transistor, and the drain of the sixth bias NMOS transistor is connected to the drain of the second common-source amplifier PMOS transistor. The sources of the fourth, fifth, and sixth bias NMOS transistors are all connected to the analog ground terminal.

[0013] Optionally, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all replaced with NPN transistors, the gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all replaced with the bases of NPN transistors, the drains of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all replaced with the collectors of NPN transistors, and the sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all replaced with the emitters of NPN transistors.

[0014] Optionally, if the power transistor is a PMOS transistor, then the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all replaced with NMOS transistors, and the source of the replaced NMOS transistor is connected to the analog ground terminal; the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all replaced with PMOS transistors, and the source of the PMOS transistor replacing the first NMOS transistor is connected to the source of the power transistor, and the source of the PMOS transistor replacing the second NMOS transistor and the third NMOS transistor is connected to the drain of the power transistor.

[0015] Optionally, both the first common-source PMOS transistor and the second common-source PMOS transistor can be replaced with NMOS transistors, and the source of the replaced NMOS transistor is connected to the analog ground terminal; The first bias NMOS transistor, the second bias NMOS transistor, the third bias NMOS transistor, the fourth bias NMOS transistor, the fifth bias NMOS transistor, and the sixth bias NMOS transistor are all replaced with PMOS transistors, and the replaced PMOS transistors are connected to the power supply voltage; the first bias PMOS transistor and the second bias PMOS transistor are both replaced with NMOS transistors, and the source of the replaced NMOS transistors is connected to the analog ground terminal.

[0016] According to a second aspect of the present invention, a circuit system is provided, including the current flow direction detection circuit provided in the first aspect of the present invention.

[0017] According to a third aspect of the present invention, an electronic device is provided, comprising the circuit system provided in the second aspect of the present invention.

[0018] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the current flow detection circuit provided by this invention, a comparison module is used to compare the source voltage and drain voltage of the power transistor, and changes the magnitude of the comparison output voltage according to the comparison result. A first common-source amplifier is used to invert and amplify the voltage change of the comparison output voltage, and outputs a first amplified voltage. Since the first terminal of the voltage clamping module is connected to the output terminal of the comparison module, and the second terminal of the voltage clamping module is connected to the output terminal of the first common-source amplifier, and the voltage clamping module clamps the difference between the first amplified voltage and the comparison output voltage within a set range, the difference between the maximum and minimum values ​​of the set range is less than the power supply voltage. Therefore, when the second amplified voltage output by the second common-source amplifier reverses, it does not need to wait for the charging and discharging time of the power supply voltage, thereby accelerating the output reversal of the second amplified voltage and reducing the output reversal delay of the current flow detection circuit.

[0019] Furthermore, by setting the source of the NMOS as the input terminal of the comparator module, the impact of the voltage difference between the power ground and the analog ground on the drain voltage of the third NMOS transistor is greatly reduced, which greatly reduces the error of the comparator output voltage and thus improves the accuracy of current flow detection of the power transistor.

[0020] Furthermore, the present invention sets the second NMOS transistor and the third NMOS transistor together as the reference input transistor of the comparator module, and sets the second NMOS transistor and the third NMOS transistor to form a current mirror structure, so that the leakage current flowing through the third NMOS transistor is in a controllable state, thereby reducing the impact of the leakage current of the first amplification voltage on the circuit.

[0021] Furthermore, the comparison module is additionally equipped with a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a first resistor, so that the fifth PMOS transistor and the second PMOS transistor form a common source and common gate structure, and the sixth PMOS transistor and the third PMOS transistor also form a common source and common gate structure. This improves the output current accuracy of the drain of the fifth PMOS transistor and the output current accuracy of the drain of the sixth PMOS transistor, that is, it improves the accuracy of the comparison output voltage, and further improves the detection accuracy of the current direction detection circuit for the current direction of the power transistor.

[0022] Furthermore, to prevent gate interference from the fifth and sixth biased NMOS transistors from being transmitted to the second biased NMOS transistor and affecting its output current accuracy, this invention sets up a current mirror structure composed of the first and second biased PMOS transistors as a bridge structure between the third and fourth biased NMOS transistors. This blocks gate interference from the fourth biased NMOS transistor, improves the output current accuracy of the second biased NMOS transistor, and further improves the accuracy of the first output voltage, that is, further improves the accuracy of the current direction detection circuit in detecting the current direction of the power transistor. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of a current flow direction detection circuit; Figure 2 This is a schematic diagram of the module structure of the current flow direction detection circuit provided in the first embodiment of the present invention; Figure 3 This is a schematic diagram of the current flow direction detection circuit provided in the first embodiment of the present invention. Figure 1 ; Figure 4 This is a schematic diagram of the current flow direction detection circuit provided in the first embodiment of the present invention. Figure 2 ; Figure 5 This is a schematic diagram of the circuit structure of the current flow direction detection circuit provided in the second embodiment of the present invention; Figure 6 This is a schematic diagram of the circuit structure of the current flow direction detection circuit provided in the third embodiment of the present invention; Figure 7 This is a schematic diagram of the circuit structure of the current flow direction detection circuit provided in the fourth embodiment of the present invention. Detailed Implementation

[0025] As described in the background section, existing current flow detection circuits suffer from high output reversal delays, making them unsuitable for high-frequency switching of power transistors. The following example, using an NMOS transistor as a low-side driver for a power transistor, illustrates the problems with the existing technology.

[0026] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of a current flow direction detection circuit.

[0027] Please refer to Figure 1 This embodiment is used to detect the current flow direction of the NMOS power transistor m1 in the low-side drive structure 200.

[0028] The low-side drive structure 200 includes an NMOS power transistor m1 and a load. The drain of the NMOS power transistor m1 is connected to the first terminal of the load, the source of the NMOS power transistor m1 is connected to the power ground terminal, and the gate of the NMOS power transistor m1 is connected to the drive voltage. The other terminal of the load is connected to the power supply voltage VCC.

[0029] This embodiment includes a comparison output structure 300; the comparison output structure 300 includes a bias current source i1, a first input MOSFET m2, a second input MOSFET m3, a first load MOSFET m4, a second load MOSFET m5, an output MOSFET m6, and an output current source i2. The first input MOSFET m2 and the second input MOSFET m3 form an input pair. The gate of the first input MOSFET m2 serves as the detection terminal and is connected to the drain of the NMOS power transistor m1. The gate of the second input MOSFET m3 serves as the detection terminal and is connected to the source of the NMOS power transistor m1. The first load MOSFET m4 and the second load MOSFET m5 form a load structure. The bias current source i1 provides bias current to the first input MOSFET m2 and the second input MOSFET m3. The output current source i2 and the output MOSFET m6 form the output structure.

[0030] Since the NMOS power transistor m1 can be considered as a small resistor when it is turned on, a voltage difference will be formed between the source and drain of the NMOS power transistor m1 when current flows through it. If the drain voltage is greater than the source voltage, it means that the current flows through the NMOS power transistor m1 in the forward direction. If the drain voltage is less than the source voltage, it means that the current flows through the NMOS power transistor m1 in the reverse direction.

[0031] When the drain voltage of NMOS power transistor m1 is greater than the source voltage, the second input MOS transistor m3 is turned on, the first input MOS transistor m2 is turned off, and the drain of the second input MOS transistor m3 is pulled up to the power supply voltage VCC. The drain voltage of the second input MOS transistor m3 acts on the gate of the output MOS transistor m6, causing the drain of the output MOS transistor m6 to be pulled down to ground, thereby causing the output structure to output a low level.

[0032] When the drain voltage of NMOS power transistor m1 is less than the source voltage, the second input MOS transistor m3 is turned off, and the first input MOS transistor m2 is turned on, thereby turning on the first load MOS transistor m4 and the second load MOS transistor m5. The drain of the second input MOS transistor m3 is pulled down to ground. The drain voltage of the second input MOS transistor m3 acts on the gate of the output MOS transistor m6, causing the drain of the output MOS transistor m6 to be pulled up to the power supply voltage VCC by the output current source i2, thus causing the output structure to output a high level. Therefore, by comparing the output voltage of the output structure 300, the direction of current flowing through the NMOS power transistor m1 can be determined.

[0033] The problem with the above embodiments is that: 1. When the current flow direction of NMOS power transistor m1 changes, for example, from forward to reverse, the drain voltage of the second input MOSFET m3 will be pulled down from the power supply voltage VCC to ground. When the current flow direction of NMOS power transistor m1 changes from reverse to forward, the drain voltage of the second input MOSFET m3 will be pulled up from ground to the power supply voltage VCC. Therefore, the range of the drain voltage of the second input MOSFET m3 is between ground and the power supply voltage VCC. However, the level flipping of the drain voltage of the output MOSFET m6 only requires the gate voltage of the output MOSFET m6 to change within 1V, that is, the drain voltage of the second input MOSFET m3 can change from ground to 1V to achieve the level flipping of the drain voltage of the output MOSFET m6, resulting in the (VCC-1V) voltage being charged and discharged meaninglessly.

[0034] Based on circuit principles, the formula for the output inversion delay of the output structure is as follows: T = (VCC - 1V) / I Formula (1) Where T is used to characterize the output inversion delay of the output structure; VCC is used to characterize the power supply voltage; and I is used to characterize the output current of the bias current source.

[0035] Therefore, when the current flowing through the NMOS power transistor m1 reverses, the comparator output structure 300 will generate an output reversal delay of approximately (VCC-1V) / I, making the comparator output structure 300 unsuitable for high-frequency switching of the NMOS power transistor m1.

[0036] 2. Because the gate of the second input MOSFET m3 is connected to the source of the NMOS power transistor m1, and the source of the NMOS power transistor m1 is connected to the power ground, the gate of the second input MOSFET m3 is connected to the power ground, while the drain of the second input MOSFET m3 is coupled to the analog ground. The voltage difference between the power ground and the analog ground (typically between tens of mV and hundreds of mV) will couple to the gate-source voltage of the second input MOSFET m3, causing a large deviation in the drain voltage of the second input MOSFET m3. This affects the timing of the level inversion of the drain of the output MOSFET m6, and thus greatly reduces the accuracy of current flow detection of the NMOS power transistor m1.

[0037] Furthermore, replacing the reference terminal with an analog ground terminal instead of the power ground terminal can lead to misjudgment of the current flow direction detection of the NMOS power transistor m1. This is because when the forward current flowing through the NMOS power transistor m1 is small, while the negative voltage at the power ground terminal is large, the drain of the NMOS power transistor m1 will also be negative, causing the comparator output structure 300 to output a high level, thus leading to misjudgment of the current flow direction of the NMOS power transistor m1.

[0038] In view of this, the technical solution of the present invention provides a novel current flow direction detection circuit, including a comparison module, a first common-source amplifier, a voltage clamping module, a second common-source amplifier, and a current flow direction detection module. Since the voltage clamping module clamps the absolute difference between the comparison output voltage from the comparison module and the first amplified voltage from the first common-source amplifier to a set range, and twice the set range is less than the power supply voltage, the second amplified voltage output from the second common-source amplifier does not need to wait for a charging / discharging time equal to the power supply voltage when reversal occurs, thereby accelerating the output reversal of the second amplified voltage and reducing the output reversal delay of the current flow direction detection circuit.

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0042] [First Embodiment] Figure 2 This is a schematic diagram of the module structure of the current flow direction detection circuit provided in the first embodiment. Figure 3 This is a schematic diagram of the circuit structure of the current flow direction detection circuit provided in the first embodiment.

[0043] Please refer to Figure 2 The current flow detection circuit provided in this embodiment is used to detect the current flow direction of the power transistor M0 in the low-side drive circuit. The drain of the power transistor M0 is connected to one end of the load, and the source of the power transistor M0 is connected to the power ground terminal POWER-GND. The other end of the load is connected to the power supply voltage VCC.

[0044] It should be noted that in the low-side drive circuit, the power transistor M0 is usually an NMOS transistor. Therefore, in this embodiment, the power transistor M0 refers to an NMOS transistor.

[0045] The current flow direction detection circuit provided in this embodiment includes a comparison module 10, a first common-source amplifier 20, a voltage clamping module 30, a second common-source amplifier 40, and a current flow direction detection module 50.

[0046] The comparison module 10 compares the source voltage and drain voltage of the power transistor M0, and changes the magnitude of the comparison output voltage V1 according to the comparison result.

[0047] Please refer to Figure 2 and Figure 3Specifically, the comparison module 10 includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a first NMOS transistor M4, a second NMOS transistor M5, a third NMOS transistor M6, and a first bias current unit 11.

[0048] The first bias current unit 11 is used to provide a first bias current.

[0049] The drain of the first PMOS transistor M1 is connected to the positive terminal of the first bias current unit 11, and the negative terminal of the first bias current unit 11 is connected to the analog ground AN-GND. The gate of the first PMOS transistor M1 is connected to the gate of the second PMOS transistor M2 and the gate of the third PMOS transistor M3. The sources of the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3 are all connected to the power supply voltage VCC. The drain of the second PMOS transistor M2 is connected to the drain of the first NMOS transistor M4 and the second NMOS transistor M5. The drain of the third PMOS transistor M3 is connected to the drain of the third NMOS transistor M6. The first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3 form a current mirror structure. The first bias current is mirrored to the second PMOS transistor M2 and the third PMOS transistor M3 through this current mirror structure, so that the second PMOS transistor M2 serves as the current source for the first NMOS transistor M4 and the second NMOS transistor, and the third PMOS transistor M3 serves as the current source for the third NMOS transistor M6. Furthermore, since the first NMOS transistor M4, the second NMOS transistor M5, and the third NMOS transistor M6 have the same channel width-to-length ratio, and since the second PMOS transistor M2 serves as the current source for both the first NMOS transistor M4 and the second NMOS transistor M5, and the third PMOS transistor M3 serves only as the current source for the third NMOS transistor M6, the current output by the second PMOS transistor M2 is twice that of the third PMOS transistor M3. Therefore, the channel width-to-length ratio of the second PMOS transistor M2 needs to be twice that of the third PMOS transistor M3.

[0050] The gate of the first NMOS transistor M4 is connected to its own drain, the drain of the second NMOS transistor M5, the gate of the second NMOS transistor M5, and the gate of the third NMOS transistor M6. The source of the first NMOS transistor M4 serves as a probe terminal and is connected to the drain of the power transistor M0. The source of the second NMOS transistor M5 is connected to the source of the third NMOS transistor M6, and the source of the second NMOS transistor M5 serves as a reference terminal and is connected to the source of the power transistor M0; that is, the source of the second NMOS transistor M5 is connected to the power ground terminal POWER-GND.

[0051] According to the working principle of NMOS transistors, the higher the gate-source voltage of an NMOS transistor, the greater the current flowing through it. Therefore, with the first NMOS transistor M4, the second NMOS transistor M5, and the third NMOS transistor M6 having a fixed gate voltage, the smaller the source voltage of the NMOS transistor, the greater the current flowing through it.

[0052] Therefore, when the drain voltage of power transistor M0 is greater than the source voltage, it means that the current flowing through power transistor M0 is in the forward direction. At this time, the gate-source voltage of the second NMOS transistor M5 and the third NMOS transistor M6 is greater than the gate-source voltage of the first NMOS transistor M4. As a result, the current flowing through the second NMOS transistor M5 and the third NMOS transistor M6 increases, thereby pulling down the drain voltage of the third NMOS transistor M6.

[0053] When the drain voltage of power transistor M0 is less than its source voltage, it indicates that the current flowing through power transistor M0 is flowing in the reverse direction. At this time, the gate-source voltages of the second NMOS transistor M5 and the third NMOS transistor M6 are less than the gate-source voltage of the first NMOS transistor M4. Therefore, the current flowing through the second NMOS transistor M5 and the third NMOS transistor M6 decreases, thereby causing the drain voltage of the third NMOS transistor M6 to be pulled high by the current output by the third PMOS transistor M3. It should be noted that the drain voltage of the third NMOS transistor M6 represents the comparison output voltage V1 of the comparison module 10.

[0054] In existing comparators, the gate of the PMOS input transistor is used as the signal input terminal. However, when the PMOS input terminal is connected to the power ground terminal POWER-GND, the voltage difference between the power ground terminal POWER-GND and the comparator's analog ground terminal AN-GND is easily coupled to the drain of the PMOS input transistor through the gate-drain capacitance, resulting in a large error in the drain output voltage of the PMOS input transistor.

[0055] In this embodiment, the sources of the first NMOS transistor M4, the second NMOS transistor M5, and the third NMOS transistor M6 are each used as signal input terminals. When the sources of the second NMOS transistor M5 and the third NMOS transistor M6 are connected to the power ground terminal POWER-GND, the voltage difference between the power ground terminal POWER-GND and the analog ground terminal AN-GND of the comparator module 10 is difficult to couple to the drain of the NMOS transistor through the source-drain capacitance of the NMOS transistor. This greatly reduces the impact of the voltage difference between the power ground terminal POWER-GND and the analog ground terminal AN-GND on the drain voltage of the third NMOS transistor M6, that is, it greatly reduces the error of the comparison output voltage V1, thereby improving the accuracy of current flow detection of the power transistor M0.

[0056] Since the first terminal of the voltage clamping module 30 is connected to the output terminal of the comparator module 10, i.e., the drain of the third PMOS transistor M3 or the drain of the third NMOS transistor M6, and the second terminal of the voltage clamping module 30 is connected to the output terminal of the first common-source amplifier 20, the first amplified voltage V2 output by the first common-source amplifier 20 leaks to the drain of the third NMOS transistor M6 through the voltage clamping module 30. Therefore, in this embodiment, the second NMOS transistor M5 and the third NMOS transistor M6 are set together as the reference input transistor of the comparator module 10, and the drain of the second NMOS transistor M5 is connected to its own gate and the gate of the third NMOS transistor M6 respectively, and the source of the second NMOS transistor M5 and the source of the third NMOS transistor M6 are connected to the power ground terminal POWER-GND, so that the second NMOS transistor M5 and the third NMOS transistor M6 form a current mirror structure. Since the second NMOS transistor M5 and the third NMOS transistor M6 have the same width-to-length ratio, the current flowing through the second NMOS transistor M5 is equal to the current flowing through the third NMOS transistor M6. This makes the leakage current flowing through the third NMOS transistor M6 controllable, thereby reducing the impact of the leakage current of the first amplification voltage V2 on the circuit. For example, by controlling the current flowing through the second NMOS transistor M5, the leakage current flowing through the third NMOS transistor M6 can be controlled to be around 2mA.

[0057] Please refer to Figure 4 In other embodiments, the first NMOS transistor M4, the second NMOS transistor M5, and the third NMOS transistor M6 can all be replaced with NPN transistors to accelerate the response speed of the comparison output voltage V1 as the current flow direction of the power transistor M0 changes. Specifically, the gates of the first NMOS transistor M4, the second NMOS transistor M5, and the third NMOS transistor M6 are all replaced with the bases of NPN transistors, the drains of the first NMOS transistor M4, the second NMOS transistor M5, and the third NMOS transistor M6 are all replaced with the collectors of NPN transistors, and the sources of the first NMOS transistor M4, the second NMOS transistor M5, and the third NMOS transistor M6 are all replaced with the emitters of NPN transistors.

[0058] Please continue to refer to this. Figure 1 The first common-source amplifier 20 is used to invert and amplify the voltage change of the comparison output voltage V1, and output the first amplified voltage V2.

[0059] Please continue to refer to this. Figure 2 and Figure 3The first common-source amplifier 20 includes a first common-source PMOS transistor M7 and a second bias current unit 21. The source of the first common-source PMOS transistor M7 is connected to the power supply voltage VCC, and the gate of the first common-source PMOS transistor M7 is connected to the drain of the third NMOS transistor M6. The drain of the first common-source PMOS transistor M7 serves as the output terminal of the first common-source amplifier 20, outputting the first amplified voltage V2. The first common-source PMOS transistor M7 is also connected to the positive terminal of the second bias current unit 21, and the negative terminal of the second bias current unit 21 is connected to the analog ground AN-GND. The first common-source PMOS transistor M7 is used to inversely amplify the change in the comparison output voltage V1, and applies the result of the inverse amplification to its own drain voltage to obtain the first amplified voltage V2. For example, when the comparison output voltage V1 decreases by 50mV, and the amplification factor of the first common-source PMOS transistor M7 is 20 times, the first common-source PMOS transistor M7 will amplify the 50mV decrease in the comparison output voltage V1 by 20 times, and this amplification will be added to the drain of the first common-source PMOS transistor M7, thereby increasing the drain voltage of the first common-source PMOS transistor M7 by 1V. Therefore, when the current flow direction of the power transistor M0 changes, only a small amount of charging or discharging of the drain of the third NMOS transistor M6 is needed to be amplified in reverse by the first common-source PMOS transistor M7, thus greatly reducing the charging and discharging time of the drain of the third NMOS transistor M6 when the current flow direction of the power transistor M0 changes.

[0060] Please continue to refer to this. Figure 1 The first end of the voltage clamping module 30 is connected to the output end of the comparison module 10, and the second end of the voltage clamping module 30 is connected to the output end of the first common source amplifier 20. The voltage clamping module 30 is used to clamp the variation range of the first amplified voltage V2 to within a set range, which is less than the power supply voltage VCC.

[0061] The voltage clamping module includes at least one first clamping PMOS transistor and at least one second clamping PMOS transistor.

[0062] The drain of the first clamping PMOS transistor is connected to the output of the comparator module. The drain of each clamping PMOS transistor is connected to the source of the preceding clamping PMOS transistor, and the gate of each clamping PMOS transistor is connected to its own drain. The source of the last clamping PMOS transistor is connected to the drain of the first common-source amplifier PMOS transistor. The sum of the on-state voltages of all clamping PMOS transistors is equal to the maximum value of the set range.

[0063] The source of the first second-clamp PMOS transistor is connected to the output of the comparator module. The source of each second-clamp PMOS transistor is connected to the drain of the preceding adjacent second-clamp PMOS transistor, and the gate of each second-clamp PMOS transistor is connected to its own drain. The drain of the last second-clamp PMOS transistor is connected to the drain of the first common-source amplifier PMOS transistor. The sum of the on-state voltages of all second-clamp PMOS transistors is equal to the absolute value of the minimum value of the set range.

[0064] Please continue to refer to this. Figure 2 and Figure 3 In this embodiment, the voltage clamping module 30 includes a first clamping PMOS transistor M9 and a second clamping PMOS transistor M10. The gate of the first clamping PMOS transistor M9 is connected to its own drain, the source of the second clamping PMOS transistor M10, and the drain of the third NMOS transistor M6. The source of the first clamping PMOS transistor M9 is connected to the drain of the first common-source amplifier PMOS transistor M7, the drain of the second clamping PMOS transistor M10, and the gate of the second clamping PMOS transistor M10. It can be understood that the first clamping PMOS transistor M9 is equivalent to a diode with its positive terminal connected to the drain of the third NMOS transistor M6 and its negative terminal connected to the drain of the first common-source amplifier PMOS transistor M7; the second clamping PMOS transistor M10 is equivalent to a diode with its positive terminal connected to the drain of the first common-source amplifier PMOS transistor M7 and its negative terminal connected to the drain of the third NMOS transistor M6. Since the forward voltage drop of the diode is 0.7V, the first clamping PMOS transistor M9 is used to clamp the voltage difference between the drain of the third NMOS transistor M6 and the drain of the first common-source amplifier PMOS transistor M7 to within 0.7V, while the second clamping PMOS transistor M10 is used to clamp the voltage difference between the drain of the first common-source amplifier PMOS transistor M7 and the drain of the third NMOS transistor M6 to within 0.7V. This can be understood as the drain voltage of the third NMOS transistor M6 being at most 0.7V greater than the drain voltage of the first common-source amplifier PMOS transistor M7, and the drain voltage of the first common-source amplifier PMOS transistor M7 being at most 0.7V greater than the drain voltage of the third NMOS transistor M6. Therefore, the setting range of the first amplification voltage V2 is 0~1.4V, which not only meets the voltage change requirement for level inversion of the second amplification voltage Vout, but also greatly reduces the charging and discharging time of the drain of the first common-source amplifier PMOS transistor M7.

[0065] When the current direction of power transistor M0 changes, the delay of the second amplified voltage Vout inverting its level is affected by the combined drain charging and discharging time of the third NMOS transistor M6 and the drain charging and discharging time of the first common-source amplified PMOS transistor M7. Therefore, with the drain charging and discharging time of the third NMOS transistor M6 and the drain charging and discharging time of the first common-source amplified PMOS transistor M7 both reduced, the delay of the second amplified voltage Vout inverting its level is also greatly reduced, thereby greatly reducing the output delay of the current direction detection circuit when the current direction of power transistor M0 changes.

[0066] It should be added that, in order to ensure that the first clamping PMOS transistor M9 and the second clamping PMOS transistor M10 can clamp the drain voltage of the first common-source amplifier PMOS transistor M7, the output current of the third PMOS transistor M3 needs to be set to be greater than the output current of the second bias current unit 21.

[0067] Please continue to refer to this. Figure 1 The second common-source amplifier 40 is used to invert the first amplified voltage V2 and output the second amplified voltage Vout.

[0068] Please continue to refer to this. Figure 2 and Figure 3 The second common-source amplifier 40 includes a second common-source amplifier PMOS transistor M8 and a third bias current unit 31.

[0069] The source of the second common-source PMOS transistor M8 is connected to the power supply voltage VCC. The drain of the second common-source PMOS transistor M8 is connected to the positive terminal of the third bias current unit 31 and outputs the second amplified voltage Vout. The gate of the second common-source PMOS transistor M8 is connected to the drain of the first common-source PMOS transistor M7 to access the first amplified voltage V2. The negative terminal of the third bias current unit 31 is connected to the analog ground AN-GND.

[0070] The current flow direction detection module 50 is used to detect the current flow direction of the power transistor M0 based on the second amplified voltage Vout.

[0071] Specifically, the current flow direction detection module 50 can be an MCU or other conventional data detection chip, which is not limited here.

[0072] In summary, the current flow detection circuit provided in this embodiment amplifies the voltage change of the comparison output voltage V1 by inverting it using the first common-source amplifying PMOS transistor M7, thereby reducing the charging and discharging time of the drain of the third NMOS transistor M6. Furthermore, the absolute value of the voltage difference between the drain voltages of the first common-source amplifying PMOS transistor M7 and the third NMOS transistor M6 is clamped within a set range by the first clamping PMOS transistor M9 and the second clamping PMOS transistor M10, thus limiting the voltage change range of the first amplified voltage V2 to twice the set range. Since twice the set range is less than the power supply voltage VCC, the charging and discharging time of the drain of the first common-source amplifying PMOS transistor M7 is reduced. Combined with the reduced charging and discharging time of the drain of the third NMOS transistor M6, this significantly reduces the output delay of the current flow detection circuit when the current flow direction of the power transistor M0 changes.

[0073] Furthermore, by setting the source of the NMOS as the input terminal of the comparator module 10, the influence of the voltage difference between the power ground terminal POWER-GND and the analog ground terminal AN-GND on the drain voltage of the third NMOS transistor M6 is greatly reduced, that is, the error of the comparator output voltage V1 is greatly reduced, thereby improving the accuracy of current flow direction detection of the power transistor M0.

[0074] Furthermore, in this embodiment, the second NMOS transistor M5 and the third NMOS transistor M6 are set together as the reference input transistor of the comparison module 10, and the second NMOS transistor M5 and the third NMOS transistor M6 are set to form a current mirror structure, so that the leakage current flowing through the third NMOS transistor M6 is in a controllable state, thereby reducing the impact of the leakage current of the first amplification voltage V2 on the circuit.

[0075] [Second Embodiment] This embodiment is an improved version of the first embodiment. Please refer to it. Figure 5 The difference between this embodiment and the first embodiment is that this embodiment additionally provides a fourth PMOS transistor M11, a fifth PMOS transistor M12, a sixth PMOS transistor M13, and a first resistor R.

[0076] Please refer to Figure 5The source of the fourth PMOS transistor M11 is connected to the drain of the first PMOS transistor M1. The drain of the fourth PMOS transistor M11 is connected to the first terminal of the first resistor R and the gate of the first PMOS transistor M1. The gate of the fourth PMOS transistor M11 is connected to the second terminal of the first resistor R, the gate of the fifth PMOS transistor M12, and the gate of the sixth PMOS transistor M13. The second terminal of the first resistor R is connected to the positive terminal of the first bias current unit 11. The source of the fifth PMOS transistor M12 is connected to the drain of the second PMOS transistor M2, and the drain of the fifth PMOS transistor M12 is connected to the drain of the second NMOS transistor M5. The source of the sixth PMOS transistor M13 is connected to the drain of the third PMOS transistor M3, and the drain of the sixth PMOS transistor M13 is connected to the drain of the third NMOS transistor M6.

[0077] The fifth PMOS transistor M12 and the second PMOS transistor M2 form a common source and common gate structure, and the sixth PMOS transistor M13 and the third PMOS transistor M3 also form a common source and common gate structure to improve the output current accuracy of the drain of the fifth PMOS transistor M12 and the output current accuracy of the drain of the sixth PMOS transistor M13, thereby improving the accuracy of the comparison output voltage V1, and further improving the detection accuracy of the current direction detection circuit for the current direction of the power transistor M0.

[0078] Since the fourth PMOS transistor M11, the fifth PMOS transistor M12, and the sixth PMOS transistor M13 also form a current mirror structure, the fourth PMOS transistor M11 and the first resistor R are used together to mirror the current output by the first bias current unit 11 to the fifth PMOS transistor M12 and the sixth PMOS transistor M13.

[0079] [Third Embodiment] This embodiment is an improved version of the second embodiment. Please refer to it. Figure 6 The difference between this embodiment and the second embodiment is that in this embodiment, the first bias current unit 11, the second bias current unit 21, and the third bias current unit 31, which serve as ideal current sources, are replaced with specific circuit structures. Please refer to Figure 6 The first bias current unit 11 includes a bias current source I1, a first bias NMOS transistor M14, and a second bias NMOS transistor M15. The second bias current unit 21 includes a fifth bias NMOS transistor M18. The third bias current unit 31 includes a sixth bias NMOS transistor M19. The current flow detection circuit also includes a third bias NMOS transistor M16, a fourth bias NMOS transistor M17, a first bias PMOS transistor M20, and a second bias PMOS transistor M21.

[0080] The positive terminal of bias current source I1 is connected to the power supply voltage VCC, and the negative terminal of bias current source I1 is connected to the drain of the first bias NMOS transistor M14. The drain of the first bias NMOS transistor M14 is connected to its own gate, the gate of the second bias NMOS transistor M15, and the gate of the third bias NMOS transistor M16, respectively. The sources of the first bias NMOS transistor M14, the second bias NMOS transistor M15, and the third bias NMOS transistor M16 are all connected to the analog ground terminal AN-GND. The current mirror structure formed by the first bias NMOS transistor M14, the second bias NMOS transistor M15, and the third bias NMOS transistor M16 is used to mirror the current output from bias current source I1 to the second bias NMOS transistor M15 and the third bias NMOS transistor M16. The second bias NMOS transistor M15 replaces the first bias current unit 11 in the second embodiment to provide bias current for the first PMOS transistor M1 and the fourth PMOS transistor M11.

[0081] The drain of the first biased PMOS transistor M20 is connected to the drain of the third biased NMOS transistor M16, its own gate, and the gate of the second biased PMOS transistor M21. The sources of both the first biased PMOS transistor M20 and the second biased PMOS transistor M21 are connected to the built-in power supply voltage AVDD. The drain of the second biased PMOS transistor M21 is connected to the drain of the fourth biased PMOS transistor. The first biased PMOS transistor M20 and the second biased PMOS transistor M21 also form a current mirror structure to mirror the current flowing through the third biased NMOS transistor M16 to the fourth biased NMOS transistor M17.

[0082] The gate of the fourth bias NMOS transistor M17 is connected to its own drain, the gate of the fifth bias NMOS transistor M18, and the gate of the sixth bias NMOS transistor M19. The drain of the fifth bias NMOS transistor M18 is connected to the drain of the first common-source amplifier PMOS transistor M7, and the drain of the sixth bias NMOS transistor M19 is connected to the drain of the second common-source amplifier PMOS transistor M8. The sources of the fourth bias NMOS transistor M17, the fifth bias NMOS transistor M18, and the sixth bias NMOS transistor M19 are all connected to the analog ground terminal AN-GND. The fourth bias NMOS transistor M17, the fifth bias NMOS transistor M18, and the sixth bias NMOS transistor M19 also form a current mirror structure to mirror the current flowing through the fourth bias NMOS transistor M17 to the fifth bias NMOS transistor M18 and the sixth bias NMOS transistor M19. The fifth bias NMOS transistor M18 replaces the second bias current unit 21 to provide bias current for the first common-source amplifier PMOS transistor M7; the sixth bias NMOS transistor M19 replaces the third bias current unit 31 to provide bias current for the second common-source amplifier PMOS transistor M8.

[0083] In practical applications, when the drain of the first common-source amplifier PMOS transistor M7 and the drain of the second common-source amplifier PMOS transistor M8 experience a voltage level reversal, the voltage changes of the drain of the fifth bias NMOS transistor M18 and the drain of the sixth bias NMOS transistor M19 will be transmitted to their respective gates through their gate-drain capacitances. This results in errors in the bias current output by the fifth bias NMOS transistor M18 and the bias current output by the sixth bias NMOS transistor M19.

[0084] To prevent gate interference from the fifth bias NMOS transistor M18 and the sixth bias NMOS transistor M19 from being transmitted to the second bias NMOS transistor M15 and affecting the current accuracy of the second bias NMOS transistor M15, this embodiment sets up a current mirror structure composed of the first bias PMOS transistor M20 and the second bias PMOS transistor M21 as a bridge structure for the third bias NMOS transistor M16 and the fourth bias NMOS transistor M17. This blocks the gate interference of the fourth bias NMOS transistor M17, improves the output current accuracy of the second bias NMOS transistor M15, and further improves the accuracy of the first output voltage, that is, further improves the accuracy of the current direction detection circuit in detecting the current direction of the power transistor M0.

[0085] [Fourth Embodiment] This embodiment is an alternative to the third embodiment; please refer to it. Figure 6 The difference between this embodiment and the third embodiment is that the power transistor M0 is replaced with a PMOS transistor for use in high-side drive scenarios.

[0086] Therefore, the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3 are all replaced with NMOS transistors, and the source of the NMOS transistors is connected to the analog ground terminal AN-GND; the first NMOS transistor M4, the second NMOS transistor M5, and the third NMOS transistor M6 are all replaced with PMOS transistors, and the source of the PMOS transistor replacing the first NMOS transistor M4 is connected to the source of the power transistor M0, and the sources of the PMOS transistors replacing the second NMOS transistor M5 and the third NMOS transistor M6 are connected to the drain of the power transistor M0.

[0087] The fourth PMOS transistor M11, the fifth PMOS transistor M12, and the sixth PMOS transistor M13 are all replaced with NMOS transistors.

[0088] Both the first common-source PMOS transistor M7 and the second common-source PMOS transistor M8 are replaced with NMOS transistors, and the source of the replaced NMOS transistor is connected to the analog ground terminal AN-GND.

[0089] The first bias NMOS transistor M14, the second bias NMOS transistor M15, the third bias NMOS transistor M16, the fourth bias NMOS transistor M17, the fifth bias NMOS transistor M18, and the sixth bias NMOS transistor M19 are all replaced with PMOS transistors, and the replaced PMOS transistors are connected to the power supply voltage VCC.

[0090] Both the first bias PMOS transistor M20 and the second bias PMOS transistor M21 are replaced with NMOS transistors, and the source of the replaced NMOS transistor is connected to the analog ground terminal AN-GND.

[0091] Since replacing all the original PMOS transistors with NMOS transistors and all the original NMOS transistors with PMOS transistors to detect the current flow direction of P-type power transistors is a conventional technique in this field, and the working principle and technical effect of the replaced circuit structure are the same as those in the above embodiments, the connection relationship, working principle and technical effect of the replaced circuit will not be described in detail.

[0092] In other embodiments, a circuit system is also provided, including the current flow direction detection circuit provided in any of the above embodiments.

[0093] In other embodiments, an electronic device including the circuit system is also provided.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A current flow direction detection circuit, characterized in that, A circuit for detecting the current flow direction of a power transistor, the current flow direction detection circuit comprising: A comparison module is used to compare the source voltage and drain voltage of the power transistor and change the magnitude of the comparison output voltage according to the comparison result. A first common-source amplifier is used to invert and amplify the voltage change of the comparison output voltage, and output a first amplified voltage. A voltage clamping module, wherein the first end of the voltage clamping module is connected to the output end of the comparator module, and the second end of the voltage clamping module is connected to the output end of the first common source amplifier. The voltage clamping module clamps the difference between the first amplified voltage and the comparator output voltage within a set range, wherein the difference between the maximum and minimum values ​​of the set range is less than the power supply voltage. The second common-source amplifier is used to invert and amplify the first amplified voltage and output the second amplified voltage. A current flow direction detection module detects the current flow direction of the power transistor based on the second amplified voltage.

2. The current flow direction detection circuit according to claim 1, characterized in that, If the power transistor is an NMOS transistor, then the comparison module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first bias current unit; The drain of the first PMOS transistor is connected to the positive terminal of the first bias current unit, and the negative terminal of the first bias current unit is connected to the analog ground. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and the gate of the third PMOS transistor. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the power supply voltage. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and the drain of the second NMOS transistor. The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, and the channel width-to-length ratio of the second PMOS transistor is twice the channel width-to-length ratio of the third PMOS transistor. The gate of the first NMOS transistor is connected to its own drain, the drain of the second NMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor. The source of the first NMOS transistor is connected to the drain of the power transistor. The source of the second NMOS transistor is connected to the source of the third NMOS transistor, and the source of the second NMOS transistor is also connected to the source of the power transistor. The first NMOS transistor, the second NMOS transistor, and the third NMOS transistor have the same channel width-to-length ratio.

3. The current flow direction detection circuit according to claim 2, characterized in that, The comparison module further includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a first resistor; the source of the fourth PMOS transistor is connected to the drain of the first PMOS transistor, the drain of the fourth PMOS transistor is connected to the first terminal of the first resistor and the gate of the first PMOS transistor, the gate of the fourth PMOS transistor is connected to the second terminal of the first resistor, the gate of the fifth PMOS transistor, and the gate of the sixth PMOS transistor; the second terminal of the first resistor is connected to the positive terminal of the first bias current unit; the source of the fifth PMOS transistor is connected to the drain of the second PMOS transistor, and the drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor; the source of the sixth PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the sixth PMOS transistor is connected to the drain of the third NMOS transistor.

4. The current flow direction detection circuit according to claim 2, characterized in that, The first common-source amplifier includes a first common-source amplifying PMOS transistor and a second bias current unit. The source of the first common-source amplifying PMOS transistor is connected to the power supply voltage, and the gate of the first common-source amplifying PMOS transistor is connected to the drain of the third NMOS transistor. The drain of the first common-source amplifying PMOS transistor serves as the output terminal of the first common-source amplifier, outputting the first amplified voltage. The first common-source amplifying PMOS transistor is also connected to the positive terminal of the second bias current unit, and the negative terminal of the second bias current unit is connected to the analog ground terminal. The output current of the second bias current unit is less than the output current of the third PMOS transistor.

5. The current flow direction detection circuit according to claim 4, characterized in that, The voltage clamping module includes at least one first clamping PMOS transistor and at least one second clamping PMOS transistor; The drain of the first clamping PMOS transistor is connected to the output of the comparator module. The drain of each clamping PMOS transistor is connected to the source of the preceding adjacent clamping PMOS transistor, and the gate of each clamping PMOS transistor is connected to its own drain. The source of the last clamping PMOS transistor is connected to the drain of the first common-source amplifier PMOS transistor. The sum of the on-state voltages of all clamping PMOS transistors is equal to the maximum value of the set range. The source of the first second-clamp PMOS transistor is connected to the output of the comparator module. The source of each second-clamp PMOS transistor is connected to the drain of the preceding adjacent second-clamp PMOS transistor, and the gate of each second-clamp PMOS transistor is connected to its own drain. The drain of the last second-clamp PMOS transistor is connected to the drain of the first common-source amplifier PMOS transistor. The sum of the on-state voltages of all second-clamp PMOS transistors is equal to the absolute value of the minimum value of the set range.

6. The current flow direction detection circuit according to claim 4, characterized in that, The second common-source amplifier includes a second common-source PMOS transistor and a third bias current unit; the source of the second common-source PMOS transistor is connected to the power supply voltage, the drain of the second common-source PMOS transistor is connected to the positive terminal of the third bias current unit and outputs the second amplified voltage, and the gate of the second common-source PMOS transistor is connected to the drain of the first common-source PMOS transistor; the negative terminal of the third bias current unit is connected to the analog ground.

7. The current flow direction detection circuit according to claim 6, characterized in that, The first bias current unit includes a bias current source, a first bias NMOS transistor, and a second bias NMOS transistor; the current flow detection circuit further includes a third bias NMOS transistor, a fourth bias NMOS transistor, a first bias PMOS transistor, and a second bias PMOS transistor; the second bias current unit includes a fifth bias NMOS transistor; the third bias current unit includes a sixth bias NMOS transistor; The positive terminal of the bias current source is connected to the power supply voltage, and the negative terminal of the bias current source is connected to the drain of the first bias NMOS transistor. The drain of the first bias NMOS transistor is connected to its own gate, the gate of the second bias NMOS transistor, and the gate of the third bias NMOS transistor. The sources of the first bias NMOS transistor, the second bias NMOS transistor, and the third bias NMOS transistor are all connected to the analog ground terminal. The drain of the first biased PMOS transistor is connected to the drain of the third biased NMOS transistor, its own gate, and the gate of the second biased PMOS transistor. The source of the first biased PMOS transistor and the source of the second biased PMOS transistor are both connected to the built-in power supply voltage. The drain of the second biased PMOS transistor is connected to the drain of the fourth biased NMOS transistor. The gate of the fourth bias NMOS transistor is connected to its own drain, the gate of the fifth bias NMOS transistor, and the gate of the sixth bias NMOS transistor. The drain of the fifth bias NMOS transistor is connected to the drain of the first common-source amplifier PMOS transistor, and the drain of the sixth bias NMOS transistor is connected to the drain of the second common-source amplifier PMOS transistor. The sources of the fourth, fifth, and sixth bias NMOS transistors are all connected to the analog ground terminal.

8. The current flow direction detection circuit according to claim 2, characterized in that, The first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all replaced with NPN transistors. The gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all replaced with the bases of NPN transistors. The drains of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all replaced with the collectors of NPN transistors. The sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all replaced with the emitters of NPN transistors.

9. The current flow direction detection circuit according to claim 7, characterized in that, If the power transistor is a PMOS transistor, then the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all replaced with NMOS transistors, and the source of the replaced NMOS transistor is connected to the analog ground terminal; the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all replaced with PMOS transistors, and the source of the PMOS transistor replacing the first NMOS transistor is connected to the source of the power transistor, and the source of the PMOS transistor replacing the second NMOS transistor and the third NMOS transistor is connected to the drain of the power transistor.

10. The current flow direction detection circuit according to claim 9, characterized in that, Both the first common-source PMOS transistor and the second common-source PMOS transistor are replaced with NMOS transistors, and the source of the replaced NMOS transistor is connected to the analog ground terminal; The first bias NMOS transistor, the second bias NMOS transistor, the third bias NMOS transistor, the fourth bias NMOS transistor, the fifth bias NMOS transistor, and the sixth bias NMOS transistor are all replaced with PMOS transistors, and the replaced PMOS transistors are connected to the power supply voltage; the first bias PMOS transistor and the second bias PMOS transistor are both replaced with NMOS transistors, and the source of the replaced NMOS transistors is connected to the analog ground terminal.

11. A circuit system, characterized in that, Includes the current flow direction detection circuit according to any one of claims 1 to 10.

12. An electronic device, characterized in that, Includes the circuit system described in claim 11.

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