Batch reading-based device data acquisition method and device

Abstract

The application provides a device data acquisition method and device based on batch reading, applied to a server in a data acquisition system, the data acquisition system further comprising a plurality of industrial devices; the method comprises: obtaining a register original address table and a historical access log of the plurality of industrial devices; determining a plurality of register heat maps and address distribution matrices based on the register original address table and the historical access log; inputting the register heat maps and the address distribution matrices into a preset dynamic block to obtain acquisition strategy information output by the dynamic block; encapsulating a byte length and address mapping table into a data acquisition instruction; issuing the data acquisition instruction to the plurality of industrial devices to obtain device data returned after the industrial devices perform a data acquisition operation. In this way, the server optimizes the acquisition strategy by limiting the byte length of the data acquisition and determining the address mapping table, so that the efficiency and practicability of the server in acquiring the industrial device data are improved, and the stability of the data acquisition system in operation is improved.

Description

Technical Field

[0001] This application relates to the field of data acquisition, and in particular to a device data acquisition method and apparatus based on batch reading. Background Technology

[0002] Currently, data acquisition systems for industrial equipment generally use batch reading methods to improve efficiency.

[0003] However, this batch strategy usually relies on manual pre-configuration of parameters. This method has obvious limitations. Its configuration is relatively coarse and fixed, and it cannot be dynamically optimized and adjusted according to the actual situation of the equipment. This leads to low efficiency of server data collection and increased communication risks, ultimately limiting the performance and reliability of the overall collection system. Summary of the Invention

[0004] This application proposes a device for acquiring equipment data based on batch reading, aiming to improve the efficiency of data acquisition for industrial equipment and the usability of equipment data by optimizing the acquisition strategy, while avoiding the problem of equipment overload in industrial equipment.

[0005] In a first aspect, embodiments of this application provide a device data acquisition method based on batch reading, applied to a server in a data acquisition system, the data acquisition system further including multiple industrial devices; the method includes: Obtain the original address table and historical access logs of the registers of multiple industrial devices; Based on the original address table of registers and historical access logs, multiple register heatmaps and address distribution matrices are determined, with each industrial device corresponding to one register heatmap and address distribution matrix; The register heatmap and address distribution matrix are input into a preset dynamic block to obtain the acquisition strategy information output by the dynamic block. The acquisition strategy information is used to indicate the byte length and address mapping table for data acquisition operations performed on multiple industrial devices. The byte length is used to indicate the upper limit of memory space occupied by device data acquired in a single acquisition. Encapsulate the byte length and address mapping table into a data acquisition instruction; Send data acquisition commands to multiple industrial devices to obtain the device data returned after the industrial devices perform data acquisition operations.

[0006] Secondly, embodiments of this application provide a device data acquisition method based on batch reading, applied to industrial equipment in a data acquisition system, the data acquisition system further including a server; the method includes: Receive data collection instructions from the server; Parse the data acquisition instructions to determine the byte length and address mapping table. The byte length is used to indicate the upper limit of memory space occupied by the device data in a single acquisition. Based on the byte length and address mapping table, perform data acquisition operations to obtain device data; Send device data to the server.

[0007] Thirdly, embodiments of this application also provide a device data acquisition apparatus based on batch reading, applied to a server in a data acquisition system, the data acquisition system further including multiple industrial devices; the apparatus includes: The information acquisition unit is used to acquire the original address table of registers and historical access logs of multiple industrial devices; The information determination unit is used to determine multiple register heatmaps and address distribution matrices based on the original register address table and historical access logs. Each industrial device corresponds to one register heatmap and address distribution matrix. The strategy acquisition unit is used to input the register heatmap and address distribution matrix into a preset dynamic block to obtain the acquisition strategy information output by the dynamic block. The acquisition strategy information is used to indicate the byte length and address mapping table for data acquisition operations performed on multiple industrial devices. The byte length is used to indicate the upper limit of memory space occupied by device data acquired in a single acquisition. The instruction generation unit is used to encapsulate byte length and address mapping table into data acquisition instructions; The instruction issuing unit is used to issue data acquisition instructions to multiple industrial devices in order to obtain the device data returned after the industrial devices perform data acquisition operations.

[0008] Fourthly, embodiments of this application also provide a device data acquisition apparatus based on batch reading, applied to industrial equipment in a data acquisition system, the data acquisition system further including a server; the apparatus includes: The instruction receiving unit is used to receive data acquisition instructions issued by the server. The instruction parsing unit is used to parse data acquisition instructions to determine the byte length and address mapping table. The byte length is used to indicate the upper limit of memory space occupied by device data in a single acquisition. The data acquisition unit is used to perform data acquisition operations based on the byte length and address mapping table to obtain device data; The data sending unit is used to send device data to the server.

[0009] Fifthly, embodiments of this application also provide a server, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described in the first aspect above.

[0010] In a sixth aspect, embodiments of this application also provide an industrial device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described in the second aspect above.

[0011] In a seventh aspect, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the methods in the first aspect or any of the methods in the second aspect described above.

[0012] Eighthly, embodiments of this application provide a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps described in the first or second aspects of embodiments of this application. The computer program product may be a software installation package.

[0013] As can be seen, in this embodiment, the server determines the register heatmap and address distribution matrix by obtaining the original address table of the registers and historical access logs of multiple industrial devices to be collected. It then converts this into collection strategy information to determine data collection instructions, and finally controls the industrial devices to transmit corresponding device data by issuing these instructions. In this way, the server optimizes the collection strategy based on the actual situation of the industrial devices, efficiently and stably executing data collection operations while avoiding device overload. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a data acquisition system provided in an embodiment of this application; Figure 2 This is a flowchart illustrating a device data acquisition method based on batch reading, as provided in an embodiment of this application. Figure 3 This is a flowchart illustrating another device data acquisition method based on batch reading provided in an embodiment of this application; Figure 4 This is a functional unit block diagram of a device data acquisition device based on batch reading provided in an embodiment of this application; Figure 5This is a functional unit block diagram of another device data acquisition device based on batch reading provided in this application embodiment; Figure 6 This is a functional unit block diagram of another device data acquisition device based on batch reading provided in this application embodiment; Figure 7 This is a structural block diagram of a server provided in an embodiment of this application; Figure 8 This is a structural block diagram of an industrial device provided in an embodiment of this application. Detailed Implementation

[0016] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0017] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a data acquisition system provided in an embodiment of this application. For example... Figure 1As shown, the data acquisition system 100 includes a server 110 and multiple industrial devices 120. The server 110 is communicatively connected to the multiple industrial devices 120. When preparing for data acquisition operations on the industrial devices 120, the server 110 first obtains the original register address table and historical access logs for each industrial device 120. Then, the server 110 converts this basic data into characteristic information corresponding to the industrial devices 120 that can guide efficient batch reading, and then determines optimized acquisition strategy information based on these characteristics. The acquisition strategy information is converted into specific instructions that the industrial devices 120 can understand and execute, i.e., data acquisition instructions. Finally, by issuing data acquisition instructions to the multiple industrial devices 120, the industrial devices 120 execute the optimized acquisition strategy and acquire device data, and then send the required device data back to the server 110. Each data acquisition system 100 is configured with one server 110, and each server 110 can interact with multiple industrial devices 120 to acquire device data from multiple industrial devices 120.

[0020] Based on this, the present application provides a device data acquisition method based on batch reading. The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0021] Please see Figure 2 , Figure 2 This is a flowchart illustrating a device data acquisition method based on batch reading, provided in an embodiment of this application. The method is applied to a server 110 in a data acquisition system 100, which also includes multiple industrial devices 120. The method includes: Step S201: Obtain the original address table of registers and historical access logs of multiple industrial devices.

[0022] Since servers typically host Manufacturing Execution Systems (MES), they need to collect equipment data from industrial equipment. A Manufacturing Execution System (MES) is a shop floor-level production information management system located between the enterprise planning layer (such as ERP) and the underlying industrial control layer. It bridges the information gap between the two through real-time data acquisition and optimized management. Its core functions include production scheduling, process monitoring, quality management, resource management, and data analysis. Production scheduling refers to refining and decomposing the ERP production plan to generate executable shop floor operation instructions; process monitoring refers to real-time collection of data such as equipment status, material flow, and quality inspection; quality management refers to monitoring product standard compliance, supporting statistical process control, and traceability of non-conforming products; resource management refers to coordinating the efficiency of personnel, equipment, and materials to reduce work-in-process costs; and data analysis refers to generating real-time reports (such as equipment utilization rate and defect rate) to support production decisions. The MES system hosted on the server can be any system commonly used in the market for controlling industrial automation equipment production; no specific limitations are specified here. Traditional MES systems employ a traditional polling mechanism-based communication protocol architecture for high-frequency, real-time data interaction with industrial equipment. This architecture suffers from two bottlenecks: significant timing delays at the data transmission level and excessive communication protocol processing load on the industrial equipment. These issues lead to poor real-time data acquisition efficiency and device response performance in the industrial IoT environment. To address this, this solution obtains the original address tables and historical access logs of multiple industrial equipment registers before collecting device data. Based on this fundamental data, the server optimizes the acquisition strategy, improves data acquisition efficiency, and reduces the load on the industrial equipment.

[0023] Furthermore, in order to acquire device data from multiple industrial devices required by the MES system, the server needs to first obtain the original register addresses and historical access logs of these devices in this step. The significance of this step lies in the fact that this data forms the foundation for the server to plan and execute dynamic acquisition strategies. The original register address table is like a "map" of the devices. It precisely lists which physical register addresses the server needs to read data from for each industrial device. These addresses represent the location of information such as device status, parameters, and measurements. The historical access log records the server's past behavior of actually reading these addresses. The historical access log reflects the following key information: the addresses read, the reading time, and the frequency of reading. This key information reflects the actual value and changing characteristics of the data, revealing at the data level which data is critical and frequent, and which is infrequent. Essentially, this step ensures that the data acquisition methods subsequently executed by the server in interaction with the industrial devices are based on the inherent characteristics of the industrial devices (the address layout corresponding to the original register address table) and the actual operating history (the access patterns corresponding to the historical access logs), providing a data foundation for optimizing the acquisition strategy.

[0024] Furthermore, this step is achieved through data interaction between the query optimizer on the server and the industrial equipment. The preceding step involves the MES system sending an optimal acquisition scheme request to the query optimizer. The query optimizer then responds to this request by requesting the raw register address table from the industrial equipment, or obtaining the raw register address table for each industrial equipment from the system configuration. This table records in detail the physical address range, data type, and basic attributes of all accessible registers for the corresponding device. Simultaneously, the server can retrieve the historical access logs of each device from the data storage unit. This log systematically records every read operation of the server on the device registers within a specific time period, including the specific address accessed, the access timestamp, and the success / failure status.

[0025] Step S202: Based on the original address table of the registers and the historical access log, determine the heatmap and address distribution matrix of multiple registers.

[0026] Each piece of industrial equipment corresponds to a register heatmap and address distribution matrix. The logical purpose of this step is to process the basic data obtained in step S201 into a feature profile that can guide efficient batch reading.

[0027] Furthermore, the query optimizer in the server processes each industrial device individually, calculating the corresponding register heatmap and address distribution matrix based on the original address table and historical access logs for that device. The register heatmap visually depicts the access heat (i.e., frequency or importance) of each register address. This is achieved by analyzing historical access logs to count the number of requests / frequency for each address. Addresses accessed more frequently are typically "hotter" in the heatmap or have higher numerical values, thus identifying hot data areas. The address distribution matrix quantitatively describes the layout of register addresses in the physical address space. This is achieved by analyzing the original register address table to calculate the distance, clustering, and adjacency relationships between different address segments. This identifies the spatial correlation characteristics of addresses (characterizing whether addresses are physically continuous or adjacent, or dispersed). This step transforms the raw low-level data (address list, access records) into high-level feature information (heatmap, distribution matrix) with high guiding value, thereby ensuring that the subsequent optimized collection strategy can improve the importance and real-time performance of the collected data (i.e., ensure hot data) while ensuring efficient batch reading.

[0028] In one possible embodiment, multiple register heatmaps and address distribution matrices are determined based on the register original address table and historical access logs, including: determining the access frequency and preset service parameters of the corresponding target register for the historical access logs of each industrial device; and determining the corresponding register heatmap based on the access frequency and preset service parameters of the target register; and parsing the corresponding register original address table for each industrial device to determine the corresponding address distribution matrix.

[0029] Among them, the preset business parameters are used to characterize the value priority of the device data associated with the target register in the business scenario.

[0030] The server determines the access frequency by statistically analyzing the frequency of each register address read within a unit of time in historical access logs and performing normalization. Preset business parameters, which can be pre-set by technical personnel and stored in a pre-set business parameter table on the server, can be understood as business weights, representing the value priority of the business scenario corresponding to the device data associated with the target register. For example, security registers have a weight coefficient of 0.8, production parameter registers 0.6, and log registers 0.3. The server performs a weighted calculation based on the access frequency and preset business parameters to determine the register heatmap. The register heatmap determined by the server based on weighted calculations avoids high-value registers being overlooked due to low-frequency access, ensuring that the heatmap accurately reflects business needs.

[0031] Furthermore, the specific implementation of the address distribution matrix can be to parse the original address table and extract the physical address continuity index, proximity (average distance between adjacent addresses) and functional area density (number of registers per KB). The continuity can be determined by the number of consecutive address segments and the total number of registers. The specific calculation formula is continuity = number of consecutive address segments / total number of registers.

[0032] As can be seen in this example, the server constructs a register heatmap by incorporating preset business parameters, ensuring that the heatmap not only reflects data density but also aligns with actual business scenario requirements. Furthermore, the server quantifies device memory layout characteristics using an address distribution matrix, providing a data foundation for address aggregation optimization. In this way, the server can effectively improve the accuracy and practicality of subsequent optimized data collection strategies, thereby increasing the efficiency of collecting equipment data from industrial equipment and enhancing the value of the acquired data.

[0033] Step S203: Input the register heatmap and address distribution matrix into the preset dynamic block to obtain the acquisition strategy information output by the dynamic block.

[0034] The acquisition strategy information is used to indicate the byte length and address mapping table for data acquisition operations on multiple industrial devices. The byte length indicates the upper limit of memory space occupied by device data acquired in a single session. The dynamic block is a core algorithm module that outputs acquisition strategy information as the register heatmap and address distribution matrix corresponding to different industrial devices. Specifically, the dynamic block combines access frequency information and address space distribution information, and makes intelligent decisions considering device communication characteristics (such as protocol limitations) and system resource constraints (such as server memory), thereby outputting the acquisition strategy information. Alternatively, this step can also be executed and completed by the query optimizer in the server.

[0035] The address mapping table defines one or more optimal data block grouping schemes. Dynamic blocks attempt to aggregate register addresses that are adjacent (determined by the address distribution matrix) and have similar access frequency (determined by the register heatmap) into efficient read blocks. These read blocks represent the specific address range sequence to be covered by a single batch read operation. The byte length parameter defines the maximum number of bytes of data that a single batch read instruction can read. Dynamic blocks comprehensively evaluate and constrain factors such as device communication capabilities, server memory buffer size, and expected data response time to ensure that a single request does not overload (leading to failure or timeout) while maximizing effective data throughput as much as possible. This step enables the server to collect device data by executing an optimized collection strategy. The server significantly reduces the number of communications and data redundancy (avoiding the reading of too much cold data) by aggregating physically adjacent addresses into blocks (using a distribution matrix) and prioritizing coverage of key hotspot areas (using a heatmap). Furthermore, by dynamically setting the upper limit of byte length, the server strictly ensures that the amount of data requested in a single request is within the safety threshold of the device and network channel, greatly reducing the risk of communication timeouts, data loss, or even device unresponsiveness caused by excessively large single requests, thereby improving the intelligence and operational stability of the data acquisition system.

[0036] In one possible embodiment, a register heatmap and an address distribution matrix are input to a preset dynamic block to obtain acquisition strategy information output by the dynamic block. This includes: selecting target registers whose corresponding reference weight values ​​exceed a preset threshold from the register heatmap to determine a set of key registers; and parsing the physical address characteristics of the address distribution matrix to determine discrete quantization values; determining the byte length based on the number of key registers contained in the key register set and their discrete quantization values; generating an address mapping table based on the physical address characteristics using a space filling curve; and determining the acquisition strategy information based on the address mapping table and the byte length.

[0037] Among them, the physical address feature is used to characterize the arrangement pattern of the physical addresses of the target register in the device memory space.

[0038] In this example, the server's execution steps include critical register filtering, discrete quantization calculation, dynamic byte length decision-making, and curve optimization. Critical register filtering involves setting a dynamic threshold to select high-value registers from the register heatmap whose reference weight values ​​exceed a preset threshold, thus forming a critical register set. The specific formula for discrete quantization calculation can be: Discrete quantization value = (Maximum address interval - Minimum address interval) / Average address interval × Continuity correction coefficient. The byte length calculation formula corresponding to dynamic byte length decision-making can be: Byte length = min(Protocol packet upper limit, Number of critical registers × Number of bytes per register × (1 - 0.5 × Discrete quantization value)). Finally, curve optimization refers to using the Hilbert curve algorithm to map physical addresses to continuous logical blocks. Based on its space-filling curve characteristics, the Hilbert curve can linearly traverse every discrete unit in two or higher dimensions, passing through only once and linearly sorting and encoding each discrete unit. This encoding serves as a unique identifier for that unit. Space-filling curves can map data that is not well ordered in a high-dimensional space to a one-dimensional space. With this encoding method, spatially adjacent objects will be stored together, which can reduce IO time and improve the efficiency of data processing in memory.

[0039] As can be seen, in this example, the server effectively solves the problem of batch acquisition efficiency bottleneck caused by fragmented address space in the polling mechanism used by traditional MES systems when interacting with industrial equipment by combining the number of key registers and dynamically setting the byte length with discrete quantized values, and by mapping scattered physical addresses to continuous logical blocks through space filling curves. This improves the throughput of single valid data, effectively reduces the number of acquisition instructions, and reduces the communication timeout rate when the server communicates with industrial equipment by limiting the byte length.

[0040] Step S204: Encapsulate the byte length and address mapping table into a data acquisition instruction.

[0041] This step involves the server converting the optimized acquisition strategy information generated by the dynamic block into instructions that the industrial equipment can receive. Specifically, the server encapsulates the byte length and address mapping table according to the communication protocol specifications supported by the corresponding industrial equipment, thereby constructing the corresponding data acquisition instructions that the industrial equipment can recognize and execute.

[0042] Step S205: Send data acquisition instructions to multiple industrial devices to obtain the device data returned by the industrial devices after performing the data acquisition operation.

[0043] In this step, the server sends the data acquisition command constructed in step S204 to the corresponding industrial equipment, and then waits for the industrial equipment to execute the corresponding data acquisition operation based on the data acquisition command to obtain the data required by the server and send it back to the server. Specifically, this step can be performed by the MES system mounted on the server, which obtains the data acquisition command generated by the query optimizer and then interacts with multiple industrial devices through communication connections. Therefore, the data acquisition command can be understood as an efficient structured query statement generated by the query optimizer in the server. The MES system uses the data acquisition command to instruct the industrial equipment to collect the corresponding equipment data and send it back.

[0044] Furthermore, the data transmitted back from industrial equipment is specifically sent to a parser on the server. The parser performs real-time verification, retransmission in case of verification failure, and data parsing on the transmitted equipment data. If the equipment data is successfully verified after parsing, the parser stores this data in the MES system so that the MES system can subsequently perform data analysis and decision-making operations based on this equipment data.

[0045] Furthermore, after parsing the device data, the parser performs a cyclic data type conversion operation. This operation includes automatic endianness identification, forced type conversion with overflow checking, and business logic verification. First, automatic endianness identification involves parsing the program startup code in the device registers to dynamically determine the byte order (big-endian / little-endian) of the current data, thus standardizing the endianness and eliminating cross-platform device data parsing errors. Forced type conversion with overflow checking converts the original byte stream to the target type based on the register data type definition, marking an overflow exception code when the value exceeds the target type's range to prevent data distortion caused by overflow. Business logic verification compares the data with the corresponding business logic code (from the original business data in the registers of the corresponding industrial equipment or a pre-set business rule base on the server) based on a preset business threshold range to verify data validity. Error flags are injected for data exceeding the limits to intercept invalid device data exceeding the corresponding business threshold range. This cyclic data type conversion operation ensures the accuracy of the acquired device data and improves the quality of structured data subsequently sent to the MES system, achieving uniformity in device data format, validity of values, and business compliance.

[0046] In one possible embodiment, the device data includes multiple data packets, each carrying a corresponding Cyclic Redundancy Check (CR) code. After issuing data acquisition commands to multiple industrial devices to obtain the device data returned by the industrial devices after performing data acquisition operations, the method further includes: performing the following preset data verification operations on each data packet to determine the corresponding first verification result and second verification result: recalculating the CR value corresponding to the currently processed data packet; comparing the CR value with the CR code corresponding to the currently processed data packet to determine the first verification result; obtaining the receiving timestamp corresponding to the currently processed data packet and the command issuance timestamp corresponding to the data acquisition command; and comparing the timestamp difference with a dynamic timeout threshold to determine the second verification result; if both the first verification result and the second verification result corresponding to multiple data packets are positive, then the multiple data packets are stored.

[0047] The first verification result is used to characterize whether the cyclic redundancy check value and the cyclic redundancy check code are the same. The timestamp difference is the difference between the receiving timestamp and the instruction sending timestamp. The dynamic timeout threshold is determined by the byte length, the current network bandwidth and the preset fixed delay base. The second verification result is used to characterize whether the timestamp difference is less than or equal to the dynamic timeout threshold.

[0048] In this example, after receiving the device data transmitted back from the industrial equipment, the server performs a data verification operation, which includes Cyclic Redundancy Check (CRC) verification and dynamic timeout verification. CRC is a commonly used error-checking code in the field of data communication, characterized by the fact that the lengths of the information field and the check field can be arbitrarily selected. Furthermore, CRC check refers to verifying transmission integrity by recalculating the CRC value and comparing it with the verification code embedded in the data packet; dynamic timeout check refers to calculating a dynamic threshold based on the current packet size (byte length), real-time bandwidth, and basic latency (the specific calculation formula can be: threshold = (byte length / network bandwidth) + fixed latency). The first and second check results are used to characterize the results of CRC check and dynamic timeout check, respectively. The server will only store the corresponding device data when both checks pass, ensuring the validity and timeliness of the collected data from the source.

[0049] As can be seen, in this example, the server establishes a dual-verification mechanism to detect both data integrity and transmission timeliness, effectively solving the data integrity and timeliness problems that may exist in traditional data transmission, improving the timeliness of device data, effectively reducing the rate of invalid retransmission and data pollution misjudgment, and improving the stability of the data acquisition system.

[0050] In one possible embodiment, after performing the following preset data verification operation for each data packet to determine the corresponding first verification result and second verification result, the method further includes: if there is a data packet whose first verification result and / or second verification result is negative, then determining the corresponding data packet as a failed data packet; determining the logical block address corresponding to the failed data packet according to the address mapping table; and issuing a data retransmission instruction for the corresponding continuous logical block to the industrial equipment according to the logical block address.

[0051] The targeted retransmission control process disclosed in this example includes failed data packet location and continuous block retransmission execution. A failed data packet refers to the logical block address corresponding to the failed data packet, which the server determines by parsing the address mapping table. Based on the logical block address, the server can determine the physical address range of the failed data packet. Continuous block retransmission execution means that the server controls the corresponding industrial equipment to retransmit failed data packets within that continuous address range based on the physical address range determined by the logical block address. This eliminates the need to retransmit all data packets, effectively reducing the amount of retransmitted data.

[0052] As can be seen in this example, the server accurately locates the range of data that needs to be retransmitted by using the continuous logical block addresses generated based on the address mapping table. Unlike traditional full retransmission, it only requests the continuous address segment data of the failed block, thereby achieving targeted retransmission control of failed data, improving the execution efficiency of data retransmission, compressing the amount of device data to be transmitted through targeted retransmission, reducing the network load rate, and thus improving the retransmission success rate and the operational stability of the data acquisition system.

[0053] As can be seen, in this embodiment, compared with the traditional polling mechanism communication protocol architecture used by the traditional MES system when interacting with industrial equipment, the server in this embodiment optimizes the data acquisition strategy to ensure the real-time performance of equipment data, effectively reduces the communication load rate during equipment interaction, and improves the stability of the data acquisition system and the efficiency of data acquisition.

[0054] Please see Figure 3 , Figure 3 This is a flowchart illustrating another device data acquisition method based on batch reading provided in this application embodiment. The method is applied to industrial equipment 120 in a data acquisition system 100, which also includes a server 110. The method includes: Step S301: Receive data acquisition instructions from the server.

[0055] In this system, multiple industrial devices communicate with the server, specifically by receiving encapsulation instructions, i.e. data acquisition instructions, issued by the server through industrial buses or Ethernet connections.

[0056] Step S302: Parse the data acquisition instruction to determine the byte length and address mapping table.

[0057] The byte length indicates the upper limit of memory space occupied by device data in a single acquisition.

[0058] Industrial equipment can use its built-in parsing engine to identify the instruction structure of data acquisition commands, and then identify the key parameters, namely the byte length and the address mapping table. The address mapping table is specifically used to indicate the address sequence of the logical blocks that the server needs the industrial equipment to collect.

[0059] Step S303: Perform a data acquisition operation based on the byte length and address mapping table to obtain device data.

[0060] In this process, industrial equipment uses the address mapping table and byte length constraints to trigger local registers to perform data acquisition operations. Then, it encapsulates the acquired data packets (containing device data) and sends them back to the server to complete the data acquisition process required by the data acquisition system.

[0061] In one possible embodiment, a data acquisition operation is performed to obtain device data based on the byte length and an address mapping table, including: dividing the registers to be acquired into multiple consecutive logical blocks according to the address mapping table; determining a maximum number of threads based on the smaller of the number of available CPU cores corresponding to the industrial device and the number of blocks corresponding to the multiple consecutive logical blocks; creating a thread pool with the same number of threads as the maximum number of threads, and controlling each thread in the thread pool to perform atomic operations in parallel to determine multiple acquisition results for the multiple consecutive logical blocks; and combining the multiple acquisition results according to the address order of the multiple consecutive logical blocks to determine the device data.

[0062] In this context, the memory space occupied by the device data corresponding to the registers contained in any consecutive logical block is less than the length of bytes, and each thread corresponds to one acquisition result.

[0063] This example discloses a dynamic parallel acquisition control process, including logical block segmentation, elastic thread pool construction, and parallel acquisition and data assembly. Logical block segmentation specifically refers to dividing the address to be read into consecutive logical blocks according to the address mapping table. The constraint of this step is that the data size of a single block is less than or equal to the length of bytes (to prevent single-threaded overload). Elastic thread pool construction specifically includes determining the number of available CPU cores in the computing device, the total number of computing logical blocks, the maximum number of threads, and creating a thread pool based on the maximum number of threads. Parallel acquisition and data assembly specifically includes each thread in the thread pool performing atomic operations to independently acquire data from a single block; the main thread assembles the data according to the block address order (e.g., block 1 data + block 2 data = complete device data).

[0064] As can be seen in this example, by adopting a dynamic thread pool based on the number of CPU cores and an ordered data assembly mechanism, the industrial equipment fully unleashes the parallel processing potential of multi-core devices, significantly reduces acquisition latency, eliminates the risk of memory overflow, and reduces the load rate during the operation of the industrial equipment.

[0065] In one possible embodiment, the atomic operation includes: converting the block address of the currently acquired consecutive logical blocks into a physical register range according to an address mapping table; initiating a single batch read request for the physical register range to obtain the block data of the currently acquired consecutive logical blocks; and performing a compression operation on the block data to determine the acquisition result of the current acquisition.

[0066] The atomic operations involve a triple-optimized process, specifically address space translation, single-batch reads, and real-time data compression. Address space translation maps logical block addresses to physical register ranges, which can be achieved by pre-setting an address translation table in industrial equipment, thereby reducing translation latency. Single-batch reads refer to initiating a single direct memory access read request (not multiple point reads) to the physical register range. Real-time data compression can employ a lightweight differential compression algorithm to reduce backhaul bandwidth usage and device memory consumption by compressing block data.

[0067] Furthermore, when the equipment data transmitted back from industrial equipment requires CRC verification by the server's parser, the data structure design for data compression and packaging can adopt a "header + body + CRC32" structure. The header refers to the information provided to help the receiver correctly parse subsequent data, typically containing basic information about the data, such as data length, type, and version number. The body is the main part of the data, containing the actual content to be transmitted or stored. The body content can be various types of data, such as text, images, and audio. CRC32 is a commonly used checksum algorithm used to detect whether errors have occurred during data transmission or storage. By calculating the checksum, CRC32 can verify the integrity of the data at the receiver.

[0068] As can be seen, in this example, the industrial equipment achieves extreme efficiency optimization for a single acquisition operation through a three-stage atomic operation pipeline of hardware-level address translation, batch register reading, and real-time data compression.

[0069] Step S304: Send device data to the server.

[0070] In the process of industrial equipment sending equipment data to the server, a data transmission method of "fragmentation numbering + flow control" can be adopted. Fragmentation numbering and flow control is a network traffic management mechanism used to ensure the efficiency and reliability of data transmission. During data transmission, data packets may be divided into multiple fragments, each with a unique number. The flow control mechanism uses these numbers to manage and control the data flow, ensuring that the receiver can correctly and orderly receive all fragments. This facilitates data integrity checks on the server side, effectively detects lost or duplicate data packets and requests retransmission, and also controls data transmission traffic, avoiding excessive communication load and improving system stability.

[0071] As can be seen, in this embodiment, the industrial equipment improves the real-time response to data acquisition commands issued by the server and the corresponding data acquisition efficiency by establishing an instruction parsing framework.

[0072] The following are embodiments of the apparatus of this application. These embodiments of the apparatus and the embodiments of the method of this application belong to the same concept and are used to execute the methods described in the embodiments of this application. For ease of explanation, only the parts related to the apparatus embodiments of this application are shown in the embodiments of this application. For specific technical details not disclosed, please refer to the description of the embodiments of the method of this application, which will not be repeated here.

[0073] This application provides a batch-read-based device data acquisition apparatus, applied to server 110 in a data acquisition system 100. Specifically, the batch-read-based device data acquisition apparatus is used to execute the steps performed by server 110 in the above-described batch-read-based device data acquisition method. The batch-read-based device data acquisition apparatus provided in this application may include modules corresponding to the respective steps.

[0074] This application embodiment can divide the device data acquisition device based on batch reading into functional modules according to the above method example. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. The module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0075] When dividing each function into modules according to its corresponding function. Figure 4 This is a functional unit block diagram of a device data acquisition device based on batch reading, provided in an embodiment of this application; the device data acquisition device based on batch reading is applied to... Figure 1The data acquisition system 100 shown includes a server 110. The batch-read-based device data acquisition apparatus 40 includes: an information acquisition unit 401, used to acquire the original address tables and historical access logs of multiple industrial devices; an information determination unit 402, used to determine multiple register heatmaps and address distribution matrices based on the original address tables and historical access logs, with each industrial device corresponding to one heatmap and address distribution matrix; a strategy acquisition unit 403, used to input the register heatmaps and address distribution matrices into a preset dynamic block to obtain acquisition strategy information output by the dynamic block, the acquisition strategy information indicating and constraining the byte length and address mapping table for data acquisition operations performed on multiple industrial devices, the byte length indicating the upper limit of memory space occupied by device data acquired in a single operation; an instruction generation unit 404, used to encapsulate the byte length and address mapping table into data acquisition instructions; and an instruction issuing unit 405, used to issue data acquisition instructions to multiple industrial devices to obtain the device data returned after the industrial devices perform data acquisition operations.

[0076] In one possible embodiment, regarding the determination of multiple register heatmaps and address distribution matrices based on the register original address table and historical access logs, the information determination unit 402 is specifically configured to: determine the access frequency and preset business parameters of the corresponding target register for each industrial device's historical access logs, wherein the preset business parameters are used to characterize the value priority of the device data associated with the target register in the business scenario; and determine the corresponding register heatmap based on the target register's access frequency and preset business parameters; and parse the corresponding register original address table for each industrial device to determine the corresponding address distribution matrix.

[0077] In one possible embodiment, in inputting the register heatmap and address distribution matrix into a preset dynamic block to obtain the acquisition strategy information output by the dynamic block, the strategy acquisition unit 403 is specifically used to: filter target registers whose corresponding reference weight values ​​exceed a preset threshold from the register heatmap to determine a set of key registers; and parse the physical address features of the address distribution matrix to determine discrete quantization values, wherein the physical address features are used to characterize the arrangement pattern of the physical addresses of the target registers in the device memory space; determine the byte length based on the number of key registers contained in the set of key registers and the discrete quantization values; generate an address mapping table based on the physical address features using a space filling curve; and determine the acquisition strategy information based on the address mapping table and the byte length.

[0078] In one possible embodiment, the device data includes multiple data packets, each carrying a corresponding Cyclic Redundancy Check (CRBC). After issuing data acquisition commands to multiple industrial devices to obtain the device data returned by the industrial devices after performing data acquisition operations, the command issuing unit 405 is further configured to: perform the following preset data verification operations for each data packet to determine the corresponding first verification result and second verification result: recalculate the CRBC value corresponding to the currently processed data packet; and compare the CRBC value with the CRBC corresponding to the currently processed data packet to determine the first verification result, wherein the first verification result is used to characterize whether the CRBC value and the CRBC are the same; obtain the receiving timestamp corresponding to the currently processed data packet and the command issuing timestamp corresponding to the data acquisition command; and compare the timestamp difference with the dynamic timeout threshold to determine the second verification result, wherein the timestamp difference is the difference between the receiving timestamp and the command issuing timestamp, the dynamic timeout threshold is determined by the byte length, the current network bandwidth, and the preset fixed delay base, and the second verification result is used to characterize whether the timestamp difference is less than or equal to the dynamic timeout threshold; if both the first verification result and the second verification result corresponding to multiple data packets are positive, then the multiple data packets are stored.

[0079] In one possible embodiment, after performing the following preset data verification operation for each data packet to determine the corresponding first verification result and second verification result, the instruction issuing unit 405 is further configured to: if there is a data packet whose first verification result and / or second verification result is negative, determine the corresponding data packet as a failed data packet; determine the logical block address corresponding to the failed data packet according to the address mapping table; and issue a data retransmission instruction for the corresponding continuous logical block to the industrial equipment according to the logical block address.

[0080] This application provides a batch-read-based device data acquisition apparatus, applied to industrial equipment 120 in a data acquisition system 100. Specifically, the batch-read-based device data acquisition apparatus is used to execute the steps performed by the industrial equipment 120 in the above-described batch-read-based device data acquisition method. The batch-read-based device data acquisition apparatus provided in this application may include modules corresponding to the respective steps.

[0081] This application embodiment can divide the device data acquisition device based on batch reading into functional modules according to the above method example. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. The module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0082] When dividing each function into modules according to its corresponding function. Figure 5 This is a functional unit block diagram of another device data acquisition device based on batch reading provided in this application embodiment; the device data acquisition device based on batch reading is applied to... Figure 1 The industrial equipment 120 in the data acquisition system 100 shown. The equipment data acquisition device 40 based on batch reading includes: an instruction receiving unit 501 for receiving data acquisition instructions from a server; an instruction parsing unit 502 for parsing the data acquisition instructions to determine the byte length and address mapping table, wherein the byte length is used to indicate the upper limit of memory space occupied by the equipment data acquired in a single acquisition; a data acquisition unit 503 for performing data acquisition operations according to the byte length and address mapping table to obtain equipment data; and a data sending unit 504 for sending equipment data to the server.

[0083] In one possible embodiment, in performing data acquisition operations based on byte length and an address mapping table to obtain device data, the data acquisition unit 503 is specifically configured to: divide the registers to be acquired into multiple consecutive logical blocks according to the address mapping table, wherein the memory space occupied by the device data corresponding to the registers contained in any consecutive logical block is less than the byte length; determine the maximum number of threads based on the smaller value between the number of available CPU cores corresponding to the industrial equipment and the number of blocks corresponding to the multiple consecutive logical blocks; create a thread pool with the same number of threads as the maximum number of threads, and control each thread in the thread pool to execute atomic operations in parallel to determine multiple acquisition results for the multiple consecutive logical blocks, with each thread corresponding to one acquisition result; and combine the multiple acquisition results according to the address order of the multiple consecutive logical blocks to determine the device data.

[0084] In one possible embodiment, the atomic operation includes: converting the block address of the currently acquired consecutive logical blocks into a physical register range according to an address mapping table; initiating a single batch read request for the physical register range to obtain the block data of the currently acquired consecutive logical blocks; and performing a compression operation on the block data to determine the acquisition result of the current acquisition.

[0085] When using integrated units, such as Figure 6 As shown, Figure 6 This is a functional unit block diagram of another device data acquisition device based on batch reading provided in an embodiment of this application. Figure 6In this document, the batch-read-based device data acquisition device 40 includes a processing module 602 and a communication module 601. The processing module 602 controls and manages the actions of the batch-read-based device data acquisition device 40, for example, the steps of the information acquisition unit 401, information determination unit 402, strategy acquisition unit 403, instruction generation unit 404, and instruction issuing unit 405, or the steps of the instruction receiving unit 501, instruction parsing unit 502, data acquisition unit 503, and data sending unit 504, and / or other processes for executing the techniques described herein. The communication module 601 supports interaction between the batch-read-based device data acquisition device and other devices. Figure 6 As shown, the device data acquisition device based on batch reading may include a storage module 603, which is used to store the program code and data of the device data acquisition device based on batch reading.

[0086] The processing module 602 can be a processor or server, such as a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an ASIC, an FPGA, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc. The communication module 601 can be a transceiver, RF circuitry, or a communication interface, etc. The storage module 603 can be a memory.

[0087] All relevant content in each scenario involved in the above method embodiments can be referenced from the functional descriptions of the corresponding functional modules, and will not be repeated here. The above-mentioned batch-read-based device data acquisition device 40 can all perform the above-mentioned... Figure 2 The device data acquisition method based on batch reading shown above or the above Figure 3 The method for acquiring device data based on batch reading is shown.

[0088] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions according to the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. A computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. Semiconductor media can be solid-state drives.

[0089] Figure 7 This is a structural block diagram of a server provided in an embodiment of this application. For example... Figure 7 As shown, server 110 may include one or more of the following components: processor 701, memory 702 coupled to processor 701, wherein memory 702 may store one or more computer programs 703, the one or more computer programs 703 being configured to implement the methods described in the above embodiments when executed by one or more processors 701.

[0090] Processor 701 may include one or more processing cores. Processor 701 connects to various parts of the server 110 using various interfaces and lines, and performs various functions and processes data of the server 110 by running or executing instructions, programs, code sets, or instruction sets stored in memory 702, and by calling data stored in memory 702. Optionally, processor 701 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). Processor 701 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the displayed content; and the modem handles wireless communication. It is understood that the modem may also not be integrated into processor 701 and may be implemented separately using a communication chip.

[0091] The memory 702 may include random access memory (RAM) or read-only memory (ROM). The memory 702 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 702 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as touch functionality, sound playback functionality, image playback functionality, etc.), and instructions for implementing the various method embodiments described above. The data storage area may also store data created by the server 110 during use.

[0092] Figure 8 This is a structural block diagram of an industrial device provided in an embodiment of this application. For example... Figure 8 As shown, industrial equipment 120 may include one or more of the following components: processor 801, memory 802 coupled to processor 801, wherein memory 802 may store one or more computer programs 803, the one or more computer programs 803 being configured to implement the methods described in the above embodiments when executed by one or more processors 801.

[0093] Processor 801 may include one or more processing cores. Processor 801 connects to various parts within the industrial equipment 120 using various interfaces and lines, and performs various functions and processes data of the industrial equipment 120 by running or executing instructions, programs, code sets, or instruction sets stored in memory 802, and by calling data stored in memory 802. Optionally, processor 801 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). Processor 801 may integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the displayed content; and the modem handles wireless communication. It is understood that the modem may also not be integrated into processor 801 and may be implemented separately using a communication chip.

[0094] The memory 802 may include random access memory (RAM) or read-only memory (ROM). The memory 802 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 802 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as touch functionality, sound playback functionality, image playback functionality, etc.), and instructions for implementing the various method embodiments described above. The data storage area may also store data created during the use of the industrial equipment 120.

[0095] It is understood that server 110 or industrial equipment 120 may include more or fewer structural elements than those shown in the above block diagram, and this is not limited thereto.

[0096] This application also provides a computer storage medium storing a computer program / instructions thereon, which, when executed by a processor, implements some or all of the steps of any of the methods described in the above method embodiments.

[0097] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments.

[0098] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0099] In the several embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, and systems can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and there may be other division methods in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0100] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0101] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can be physically comprised separately, or two or more units can be integrated into one unit. The integrated unit described above can be implemented in hardware or in the form of hardware plus software functional units.

[0102] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute partial steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes: a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, volatile memory, or non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM), etc., which are various media capable of storing program code.

[0103] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can easily conceive of variations or substitutions without departing from the spirit and scope of the present invention, and various modifications and alterations can be made, including combinations of the different functions and implementation steps described above, as well as software and hardware implementation methods, all of which are within the protection scope of the present invention.

Claims

1. A device data acquisition method based on batch reading, characterized in that, A server used in a data acquisition system, the data acquisition system also including multiple industrial devices; the method includes: Obtain the original address table and historical access log of the registers of the multiple industrial devices; Based on the original address table of the registers and the historical access log, multiple register heatmaps and address distribution matrices are determined, with each industrial device corresponding to one register heatmap and one address distribution matrix; The register heatmap and the address distribution matrix are input into a preset dynamic block to obtain the acquisition strategy information output by the dynamic block. The acquisition strategy information is used to indicate the byte length and address mapping table for data acquisition operations performed on the multiple industrial devices. The byte length is used to indicate the upper limit of memory space occupied by device data acquired in a single acquisition. The byte length and the address mapping table are encapsulated into a data acquisition instruction; The data acquisition command is sent to the plurality of industrial devices to obtain the device data returned by the industrial devices after performing the data acquisition operation.

2. The method according to claim 1, characterized in that, The process of determining multiple register heatmaps and address distribution matrices based on the original register address table and the historical access log includes: For each of the aforementioned industrial devices, the access frequency and preset service parameters of the corresponding target register are determined based on the historical access logs. These preset service parameters characterize the value priority of the device data associated with the target register within the business scenario. Based on the access frequency of the target register and the preset service parameters, determine the corresponding register heatmap; For each of the industrial devices, the corresponding register original address table is parsed to determine the corresponding address distribution matrix.

3. The method according to claim 2, characterized in that, The step of inputting the register heatmap and the address distribution matrix into a preset dynamic block to obtain the acquisition strategy information output by the dynamic block includes: The target registers whose corresponding reference weight values ​​exceed a preset threshold are selected from the register heatmap to determine the key register set; and the physical address features of the address distribution matrix are analyzed to determine discrete quantization values, wherein the physical address features are used to characterize the arrangement pattern of the physical addresses of the registers corresponding to the target registers in the device memory space. The byte length is determined based on the number of key registers contained in the key register set and the discrete quantization value; Based on the physical address characteristics, the address mapping table is generated using a space-filling curve; The acquisition strategy information is determined based on the address mapping table and the byte length.

4. The method according to any one of claims 1-3, characterized in that, The device data includes multiple data packets, each data packet carrying a corresponding cyclic redundancy check code; after issuing the data acquisition command to the multiple industrial devices to obtain the device data returned by the industrial devices after performing the data acquisition operation, the method further includes: For each data packet, the following preset data verification operation is performed to determine the corresponding first verification result and second verification result: Recalculate the cyclic redundancy check value corresponding to the currently processed data packet; and, The first verification result is determined by comparing the cyclic redundancy check value with the cyclic redundancy check code corresponding to the currently processed data packet, wherein the first verification result is used to characterize whether the cyclic redundancy check value and the cyclic redundancy check code are the same; Obtain the receiving timestamp of the currently processed data packet and the instruction issuance timestamp of the data acquisition instruction; and, The second verification result is determined by comparing the timestamp difference with the dynamic timeout threshold, wherein the timestamp difference is the difference between the received timestamp and the instruction sent timestamp, the dynamic timeout threshold is determined by the byte length, the current network bandwidth and the preset fixed delay base, and the second verification result is used to characterize whether the timestamp difference is less than or equal to the dynamic timeout threshold; If both the first verification result and the second verification result corresponding to the plurality of data packets are positive, then the plurality of data packets are stored.

5. The method according to claim 4, characterized in that, After performing the following preset data verification operation for each data packet to determine the corresponding first verification result and second verification result, the method further includes: If there is a data packet whose first verification result and / or second verification result indicates no, then the corresponding data packet is determined to be an invalid data packet; The logical block address corresponding to the failed data packet is determined according to the address mapping table; Based on the logical block address, a data retransmission instruction for the corresponding consecutive logical blocks is issued to the industrial equipment.

6. A device data acquisition method based on batch reading, characterized in that, An industrial device used in a data acquisition system, the data acquisition system further including a server; the method includes: Receive data collection instructions from the server; The data acquisition instruction is parsed to determine the byte length and address mapping table, wherein the byte length is used to indicate the upper limit of memory space occupied by device data in a single acquisition; According to the address mapping table, the registers to be collected are divided into multiple consecutive logical blocks, and the memory space occupied by the device data corresponding to the registers contained in any consecutive logical block is less than the length of bytes. The maximum number of threads is determined according to the smaller value between the number of available CPU cores corresponding to the industrial equipment and the number of blocks corresponding to the multiple consecutive logical blocks. A thread pool with the same number of threads as the maximum number of threads is created, and each thread in the thread pool is controlled to perform atomic operations in parallel to determine multiple collection results for the multiple consecutive logical blocks, with each thread corresponding to one collection result. The multiple collection results are combined according to the address order of the multiple consecutive logical blocks to determine the device data. Send the device data to the server.

7. The method according to claim 6, characterized in that, The atomic operations include: According to the address mapping table, the block address of the currently collected continuous logical block is converted into a physical register range; For the physical register range, initiate a single batch read request to obtain the block data of the currently collected continuous logical blocks; A compression process is performed on the block data to determine the current acquisition result.

8. A device data acquisition apparatus based on batch reading, characterized in that, A server used in a data acquisition system, the data acquisition system also including multiple industrial devices; the device includes: The information acquisition unit is used to acquire the original address table of the registers and the historical access log of the multiple industrial devices; The information determination unit is used to determine multiple register heatmaps and address distribution matrices based on the original address table of the registers and the historical access logs, with each industrial device corresponding to one register heatmap and one address distribution matrix; The strategy acquisition unit is used to input the register heatmap and the address distribution matrix into a preset dynamic block to obtain the acquisition strategy information output by the dynamic block. The acquisition strategy information is used to indicate the byte length and address mapping table for data acquisition operations performed on the multiple industrial devices. The byte length is used to indicate the upper limit of memory space occupied by device data acquired in a single acquisition. An instruction generation unit is used to encapsulate the byte length and the address mapping table into a data acquisition instruction; The instruction issuing unit is used to issue the data acquisition instruction to the plurality of industrial devices in order to obtain the device data returned by the industrial devices after performing the data acquisition operation.

9. A device data acquisition apparatus based on batch reading, characterized in that, An industrial device used in a data acquisition system, the data acquisition system further including a server; the device includes: The instruction receiving unit is used to receive data acquisition instructions issued by the server; The instruction parsing unit is used to parse the data acquisition instruction to determine the byte length and address mapping table. The byte length is used to indicate the upper limit of memory space occupied by the device data in a single acquisition. The data acquisition unit is configured to: divide the registers to be acquired into multiple consecutive logical blocks according to the address mapping table, wherein the memory space occupied by the device data corresponding to the registers contained in any consecutive logical block is less than the byte length; determine the maximum number of threads based on the smaller value between the number of available CPU cores corresponding to the industrial equipment and the number of blocks corresponding to the multiple consecutive logical blocks; create a thread pool with the same number of threads as the maximum number of threads; control each thread in the thread pool to execute atomic operations in parallel to determine multiple acquisition results for the multiple consecutive logical blocks, wherein each thread corresponds to one acquisition result; and combine the multiple acquisition results according to the address order of the multiple consecutive logical blocks to determine the device data. A data sending unit is used to send the device data to the server.

10. A server, characterized in that, It includes a processor, a memory, a communication interface, and one or more programs, said one or more programs being stored in the memory and configured to be executed by the processor, said programs including instructions for performing the steps of the method as claimed in any one of claims 1-5.

11. An industrial device, characterized in that, It includes a processor, a memory, a communication interface, and one or more programs, said one or more programs being stored in the memory and configured to be executed by the processor, said programs including instructions for performing the steps of the method as described in claim 6 or 7.

12. A computer-readable storage medium, characterized in that, A computer program for storing electronic data interchange is provided, wherein the computer program causes a computer to perform the method as described in any one of claims 1-5, 6, or 7.

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