A detectable bandgap reference voltage trimming circuit and bandgap reference circuit

Abstract

The application belongs to the technical field of integrated circuit testing, and particularly discloses a detectable band gap reference voltage trimming circuit and a band gap reference circuit. The circuit disclosed by the application comprises an enabling module, a control module, a counting module, a fusing module and an output module. The enabling module receives and responds to a first input signal, a second input signal and a third input signal, and is used for controlling the starting and working state of the whole circuit. The control module is used for controlling the counting module and the fusing module. The counting module counts the clock signal of the second input signal, and cooperates with the output signal of the fusing module. The fine interconnection wire corresponding to the trimming position in the fusing output module is used to realize the trimming of the reference voltage. The application realizes the high-precision adjustment of the band gap reference voltage through the combination of the fuse trimming and the digital trimming, and improves the precision and stability of the reference voltage. The application can be widely applied to the reference voltage adjustment of the band gap reference circuit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit testing technology, and specifically relates to a detectable bandgap reference voltage adjustment circuit and a bandgap reference circuit. Background Technology

[0002] Existing bandgap voltage reference circuits are used in analog integrated circuit design to provide high-precision, low-temperature-drift reference voltages, and are widely used in analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and power management chips. However, traditional bandgap reference circuits face the following technical challenges in practical applications: the reference output voltage is susceptible to process variations, temperature changes, and power supply voltage fluctuations, leading to a decrease in output accuracy. For example, when process parameters (such as transistor threshold voltage and resistor matching) deviate, the initial value of the reference voltage may deviate from the design target, requiring correction through calibration.

[0003] Existing calibration solutions are mainly divided into two categories: offline calibration and on-chip calibration. Offline calibration typically uses laser trimming technology or fuse burning methods to compensate for output voltage deviations by adjusting resistor arrays or transistor sizes. While these solutions offer high accuracy and mature technology, they suffer from the following drawbacks: 1) They require specialized equipment and complex processes, increasing production costs; 2) They cannot achieve online calibration after chip mass production; 3) Repeated calibration may damage the chip package, reducing long-term reliability. On-chip calibration solutions, on the other hand, achieve programmable calibration through digital control modules and embedded memory (such as EEPROM), dynamically adjusting the reference voltage in the reference circuit. For example, one solution introduces a programmable resistor array into the reference circuit, using digital signals to control a switch array to switch resistors of different values, thereby adjusting the reference current or voltage. However, this solution faces the following problems: 1) The matching accuracy of the resistor array is limited by the process, making it difficult to improve the calibration resolution to the sub-millivolt level; 2) A large number of switches and resistor units occupy a significant chip area, hindering integration; 3) Dynamically switching resistors may introduce transient noise, affecting the stability of the reference voltage.

[0004] Therefore, there is an urgent need for a bandgap reference circuit solution that can achieve high precision, online programmable adjustment, and also consider area, power consumption, and stability. This would address the shortcomings of existing technologies in terms of process adaptability, calibration flexibility, and system-level integration, and meet the stringent requirements of high-performance chips for reference voltage sources. Summary of the Invention

[0005] The purpose of this invention is to provide a detectable bandgap reference voltage adjustment circuit that achieves high-precision adjustment of the bandgap reference voltage by combining fuse adjustment and digital adjustment. It also has a built-in detection function, which improves the accuracy and stability of the reference voltage, enhances the reliability and long-term stability of the circuit, and reduces production costs while increasing integration.

[0006] The second objective of this invention is to provide a bandgap reference circuit that applies the above-described detectable bandgap reference voltage adjustment circuit.

[0007] To achieve the above objectives, the technical solution adopted by this invention is as follows:

[0008] A detectable bandgap reference voltage adjustment circuit includes an enable module, a counting module, a fuse module, and an output module, characterized in that it further includes a control module;

[0009] After receiving and responding to the first input signal, the second input signal, and the third input signal, the enabling module generates a first enabling signal, a second enabling signal, and a third enabling signal, and further generates a fourth enabling signal in response to its own third enabling signal.

[0010] The control module receives and responds to the first enable signal, the second enable signal, and the third enable signal, and generates the first control signal and the second control signal.

[0011] The fuse module receives and responds to a first enable signal, a second enable signal, and a first control signal to generate a first fuse signal; receives and responds to the first enable signal, the first control signal, and its own first fuse signal to generate a second fuse signal; and receives and responds to the first enable signal and a fourth enable signal to generate a third fuse signal.

[0012] The counting module receives and responds to the first fuse signal, the second fuse signal, the second enable signal, the fourth enable signal, and the first control signal, counts the second enable signal, and generates a counting signal.

[0013] The output module receives and responds to the second fuse signal, the third fuse signal, and the counting signal, fuses the fine interconnecting wires corresponding to the adjustment position, and outputs two sets of reference voltage control signals with opposite potential states after adjustment.

[0014] The enable module, control module, fuse module, counting module, and output module are all connected to a power supply terminal and a ground terminal.

[0015] As a limitation, a detection module is also included;

[0016] The detection module is used for the detection and determination of the adjustment position, receives and responds to the first enable signal, the second enable signal, and the second control signal, performs detection and determination on the reference voltage control signal, and outputs the detection result signal;

[0017] The detection module is connected to a power supply terminal and a ground terminal.

[0018] As a further limitation, when the counting module, the fuse module, and the output module are running, the detection module is not activated;

[0019] When the detection module is running, the counting module, the fuse module, and the output module are not enabled.

[0020] As a second limitation, the enabling module includes a first resistor, a second resistor, a third resistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a first diode, a second diode, a first capacitor, a second capacitor, a first Schmitt trigger, a second Schmitt trigger, a third Schmitt trigger, a fourth Schmitt trigger, a first buffer, a second buffer, a first RS flip-flop composed of two NOR gates, a first AND gate, and a second AND gate;

[0021] One end of the first resistor serves as the input terminal of the enable module and is connected to the first input signal, while the other end is connected to the source of the first PMOS transistor. The gate of the first PMOS transistor is connected to the power supply terminal, and the drain of the first PMOS transistor is connected to the input terminal of the first Schmitt trigger and the cathode of the first diode, respectively. The anode of the first diode is connected to one end of the first capacitor and grounded, while the other end of the first capacitor serves as the common terminal and is connected to the output terminal of the first Schmitt trigger and the input terminal of the first buffer, respectively.

[0022] The input terminal of the first inverter is connected to the third input signal as the input terminal of the enable module. The output terminal of the first inverter and the output terminal of the first buffer are respectively the set input terminal and the reset input terminal of the first RS flip-flop. The complementary terminal of the first RS flip-flop is connected to the input terminal of the second buffer.

[0023] One end of the second resistor serves as the input terminal of the enable module and is connected to the first input signal. The other end serves as the common terminal and is connected to the negative terminal of the second diode and the input terminal of the third Schmitt trigger, respectively. The positive terminal of the second diode is grounded.

[0024] The input of the second Schmitt trigger is connected to the second input signal as the input of the enable module. The output of the second Schmitt trigger and the output of the second buffer are respectively connected to the input of the first AND gate. The output of the first AND gate is the output of the enable module and outputs the second enable signal. The output of the third Schmitt trigger and the output of the second buffer are respectively connected to the input of the second AND gate. The output of the second AND gate is the output of the enable module and outputs the first enable signal.

[0025] The input terminal of the fourth Schmitt trigger is connected to the third input signal as the input terminal of the enable module; the output terminal of the fourth Schmitt trigger is connected to the common terminal as the third enable signal and is connected to the gates of the second PMOS transistor and the first NMOS transistor; the source of the second PMOS transistor is connected to the power supply terminal, the source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to one end of the third resistor, the other end of the third resistor is connected to the drain of the second PMOS transistor as the common terminal, and is connected to one end of the second capacitor, and is also connected to the output terminal of the enable module to output the fourth enable signal; the other end of the second capacitor is grounded.

[0026] As a third limitation, the control module includes a third AND gate, a first D flip-flop, a second D flip-flop, a fourth AND gate, and a fifth AND gate;

[0027] The two input terminals of the third AND gate are connected to the first enable signal and the second enable signal respectively as input terminals of the control module. The reset terminals of the first D flip-flop and the second D flip-flop are connected to the third enable signal.

[0028] The output of the third AND gate is connected to the clock input of the first D flip-flop. The output of the first D flip-flop is connected to the input of the fourth AND gate. The two's complement output of the first D flip-flop is connected as a common terminal to the data input of the first D flip-flop, the clock input of the second D flip-flop, and the input of the fifth AND gate. The output of the second D flip-flop is connected to the other input of the fifth AND gate. The two's complement output of the second D flip-flop is connected as a common terminal to the data input of the second D flip-flop and the other input of the fourth AND gate.

[0029] The output of the fourth AND gate serves as the output of the control module, outputting the second control signal, and the output of the fifth AND gate serves as the output of the control module, outputting the first control signal.

[0030] As a fourth limitation, the counting module includes a second to a fifth inverter, a third to a eighth D flip-flop, a sixth AND gate, a second RS flip-flop composed of two OR gates, a first NOR gate, and a decoder;

[0031] The input terminal of the second inverter is connected to the second enable signal as the input terminal of the counting module, the output terminal of the second inverter is connected to the input terminal of the sixth AND gate, and the other input terminal of the sixth AND gate is connected to the first control signal as the input terminal of the counting module.

[0032] The input of the third inverter is connected to the first fuse signal of the fuse module as the input of the counting module. The inputs of the fourth inverter and the fifth inverter are connected to the fourth enable signal as the inputs of the counting module. The outputs of the third inverter and the fourth inverter are respectively the reset input and set input of the second RS flip-flop. The outputs of the second RS flip-flop and the sixth AND gate are respectively connected to the inputs of the first NOR gate. The output of the first NOR gate is connected to the clock input of the third D flip-flop.

[0033] The reset terminals of the third to eighth D flip-flops are all connected to the output terminal of the fifth inverter; among the third to seventh D flip-flops, the two's complement output terminal of the current D flip-flop is connected to the data input terminal of the current D flip-flop and to the clock input terminal of the next D flip-flop, and the two's complement output terminal of the eighth D flip-flop is connected to the data input terminal of the eighth D flip-flop.

[0034] The outputs of the third to eighth D flip-flops are all connected to the input of the decoder. The two's complement outputs of the third to seventh D flip-flops are connected to the input of the decoder. The second fuse signal is connected to the input of the decoder.

[0035] As a further limitation, the decoder includes a sixth inverter and thirty-two decoder units;

[0036] The input terminal of the sixth inverter is connected to the second fuse signal of the fuse module as the input terminal of the decoder.

[0037] Each decoder unit includes a NAND gate and a NOR gate, with the output of the NAND gate connected to the input of the NOR gate; the output of the eighth D flip-flop and the output of the sixth inverter are both connected to the input of the NOR gate in each decoder unit.

[0038] The inputs of the 32 decoder units and NAND gates are connected in binary order to the outputs or two's complement outputs of the third to seventh D flip-flops.

[0039] The outputs of the thirty-two decoder units and their NOR gates output corresponding counting signals in binary order.

[0040] As a fifth limitation, the fuse module includes a seventh inverter, a third buffer, a first NAND gate, a second NOR gate, a first buffer delay unit, an eighth inverter, a seventh AND gate, a second NAND gate, a ninth inverter, a fourth buffer, a fifth buffer, a ninth D flip-flop, an eighth AND gate, and a trimming protection unit.

[0041] The adjustment and protection unit includes a third NAND gate, a tenth D flip-flop, an eleventh D flip-flop, a third RS flip-flop composed of two NOR gates, and a sixth buffer.

[0042] The input terminal of the seventh inverter is connected to the second enable signal as the input terminal of the fuse module, and the input terminal of the third buffer is connected to the first enable signal as the input terminal of the fuse module. The input terminal of the first NAND gate is connected to the output terminal of the seventh inverter, the output terminal of the third buffer, and the first control signal. The output terminal of the first NAND gate is connected to the input terminal of the second NOR gate. The other input terminal of the second NOR gate is connected to the complementary terminal of the third RS flip-flop. The output terminal of the second NOR gate is connected to the input terminal of the first buffer delay unit. The output terminal of the buffer delay unit is connected to the input terminal of the eighth inverter as a common terminal and outputs the first fuse signal. The output terminal of the eighth inverter and the first control signal are connected to the input terminal of the seventh AND gate.

[0043] The input of the second NAND gate is connected to the first control signal and the first enable signal. The output of the second NAND gate is connected as a common terminal to the input of the ninth inverter and the reset input of the third RS flip-flop. The output of the ninth inverter is connected to the input of the fourth buffer. The first control signal is connected to the input of the fifth buffer.

[0044] The outputs of the seventh AND gate, the fourth buffer, and the fifth buffer are connected in sequence to the data input, clock input, and reset input of the ninth D flip-flop. The output of the ninth D flip-flop and the first fuse signal are connected to the input of the eighth AND gate. The output of the eighth AND gate outputs the second fuse signal.

[0045] The fourth enable signal is connected to the reset terminals of the tenth D flip-flop and the eleventh D flip-flop. The clock input terminal of the tenth D flip-flop is connected to the output terminal of the third NAND gate. The two's complement output terminal of the tenth D flip-flop is connected to its own data input terminal and the clock input terminal of the eleventh D flip-flop, respectively. The data input terminal of the eleventh D flip-flop is connected to the power supply terminal. The output terminal of the eleventh D flip-flop outputs the third fuse signal. The two's complement output terminal of the eleventh D flip-flop serves as a common terminal and is connected to the set input terminal of the third RS flip-flop and the input terminal of the sixth buffer, respectively. The output terminal of the sixth buffer and the first enable signal are connected to the input terminal of the third NAND gate, respectively.

[0046] As a further limitation, the output module includes a bias circuit and an output drive circuit;

[0047] The bias circuit includes a tenth inverter, third to sixth resistors, third to fifth PMOS transistors, a second NMOS transistor, and a third NMOS transistor;

[0048] The input terminal of the tenth inverter and the gate of the fifth PMOS transistor are connected to the third fuse signal. The output terminal of the tenth inverter is connected to the gate of the sixth PMOS transistor. The source of the sixth PMOS transistor, one end of the fourth resistor, and one end of the fifth resistor are connected to the power supply terminal. The other end of the fourth resistor is connected to the source of the third PMOS transistor. The other end of the fifth resistor is connected to the source of the fourth PMOS transistor. The gate of the third PMOS transistor serves as a common terminal and is connected to the gate of the fourth PMOS transistor, the drain of the third PMOS transistor, the source of the fifth PMOS transistor, and the drain of the sixth PMOS transistor, and outputs the first bias voltage.

[0049] The drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the power supply terminal. The source of the second NMOS transistor is connected to one end of the sixth resistor. The other end of the sixth resistor and the source of the third NMOS transistor are connected to the power supply terminal. The gate of the third NMOS transistor serves as a common terminal and is connected to the drain of the fourth PMOS transistor and the drain of the third NMOS transistor respectively, and outputs the second bias voltage.

[0050] The output drive circuit includes thirty-two parallel output units, each of which includes a ninth AND gate, sixth to ninth resistors, a seventh PMOS transistor, an eighth PMOS transistor, fourth to sixth NMOS transistors, an eleventh inverter, a twelfth inverter, and a seventh buffer.

[0051] In each output unit, one end of the seventh resistor is grounded, and the other end is connected to the gate of the seventh PMOS transistor. The source of the seventh PMOS transistor is connected to the power supply terminal. The drain of the seventh PMOS transistor is connected to one end of the eighth resistor. The other end of the eighth resistor is connected to the drain of the fourth NMOS transistor and the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor is connected to the first bias voltage. The gate of the fourth NMOS transistor is connected to the output terminal of the ninth AND gate and one end of the ninth resistor. One input terminal of the ninth AND gate is connected to the second fuse signal. The other end of the ninth resistor is connected to the output terminal of the sixth NMOS transistor. The drain and gate, the source of the sixth NMOS transistor, the source of the fourth NMOS transistor, and the source of the fifth NMOS transistor are connected to the power supply terminal. The drain of the fifth NMOS transistor serves as a common terminal and is connected to the drain of the eighth PMOS transistor, the input of the twelfth inverter, the output of the eleventh inverter, and the input of the seventh buffer, respectively. The gate of the fifth NMOS transistor is connected to the second bias voltage. The output of the twelfth inverter is connected to the input of the eleventh inverter. The eleventh inverter is connected to the bias voltage of the third fuse signal. The seventh PMOS transistor and the eighth resistor are connected using fine interconnecting wires.

[0052] The other input terminal of the ninth AND gate of the thirty-two output units is connected in sequence to the output terminals of the thirty-two decoder units or NOT gates;

[0053] The output terminals of the twelfth inverter of the thirty-two output units sequentially output thirty-two reference voltage control signals, and the output terminals of the seventh buffer of the thirty-two output units sequentially output the inverse signals of the thirty-two reference voltage control signals.

[0054] As a further limitation, the resistance value of the eighth resistor in each of the output units is much smaller than that of the first resistor and the second resistor.

[0055] As a further definition, the detection module includes a detection counting unit, thirty-two detection decoding units, and a detection result signal output circuit;

[0056] The detection and counting unit includes: a thirteenth inverter, a fourteenth inverter, twelfth to sixteenth D flip-flops, and a fourth NAND gate;

[0057] The input terminal of the thirteenth inverter is connected to the first enable signal, the output terminal of the thirteenth inverter and the second control signal are connected to the input terminal of the fourth NAND gate, and the output terminal of the fourth NAND gate is connected to the clock input terminal of the twelfth D flip-flop.

[0058] The input terminal of the fourteenth inverter is connected to the fourth enable signal, and the output terminal of the fourteenth inverter is connected to the reset terminal of the twelfth to sixteenth D flip-flops.

[0059] In the twelfth to fifteenth D flip-flops, the two's complement output of the current D flip-flop is connected to the data input of the current D flip-flop and to the clock input of the next D flip-flop; the two's complement output of the sixteenth D flip-flop is connected to the data input of the sixteenth D flip-flop.

[0060] Each detection decoding unit includes an AND gate and an inverter. The output of the AND gate is connected to the bias voltage input of the inverter. The inputs of the AND gates of the thirty-two detection decoding units are connected to the outputs or two's complement outputs of the twelfth to sixteenth D flip-flops in binary order. The inputs of the inverters of the thirty-two detection decoding units are connected to thirty-two reference voltage control signals in sequence.

[0061] The output terminals of the inverters in the thirty-two detection and decoding units are all connected to the signal input terminals of the detection result signal output circuit.

[0062] The detection result signal output circuit includes a fifteenth inverter, a seventh NMOS transistor, an eighth buffer, a fifth NAND gate, a sixteenth inverter, a ninth buffer, an eighth NMOS transistor, and a ninth NMOS transistor;

[0063] The output terminals of the inverters in the thirty-two detection decoding units are connected to the input terminal of the eighth buffer and the drain of the seventh NMOS transistor, with the source of the seventh NMOS transistor grounded. The second control signal is connected to the input terminal of the fifteenth inverter, the input terminal of the fifth NAND gate, the bias voltage input terminal of the sixteenth inverter, and the input terminal of the ninth buffer, respectively. The output terminal of the fifteenth inverter is connected to the gate of the seventh NMOS transistor, the output terminal of the eighth buffer is connected to the input terminal of the fifth NAND gate, the output terminal of the fifth NAND gate is connected to the input terminal of the sixteenth inverter, the output terminal of the sixteenth inverter is connected to the gate of the eighth NMOS transistor, the output terminal of the ninth buffer is connected to the gate of the ninth NMOS transistor, the source of the ninth NMOS transistor is grounded, the drain of the ninth NMOS transistor is connected to the source of the eighth NMOS transistor, and the drain of the eighth NMOS transistor outputs the detection result signal.

[0064] A bandgap reference circuit includes the aforementioned detectable bandgap reference voltage adjustment circuit.

[0065] The present invention, by adopting the above-described technical solution, achieves the following technical advancements compared to existing technologies:

[0066] (1) The circuit of the present invention adopts a general process, is compatible with most bandgap references, and most PADs are compatible with the chip being tuned, thus reducing the area occupied by the tuning circuit.

[0067] (2) This invention incorporates a detection module that can simultaneously verify the 32-bit adjustment bits, ensuring the accuracy of the adjustment;

[0068] (3) The present invention has a function to prevent false triggering in the enable module. It requires a pulse signal with a certain pulse width and higher than the power supply voltage to be input when it is turned on, which reduces the static power consumption in normal mode.

[0069] (4) The present invention adds a trimming protection unit to the fuse module, and prevents false triggering through a dual-pulse verification mechanism. The trimming function will only be started after receiving at least two complete clock cycles of signals, thus avoiding trimming errors and improving the security of the present invention.

[0070] This invention belongs to the field of integrated circuit testing technology. By combining fuse adjustment and digital adjustment, it achieves high-precision adjustment of the bandgap reference voltage, thereby improving the accuracy and stability of the reference voltage. Attached Figure Description

[0071] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0072] In the attached diagram:

[0073] Figure 1 This is the overall circuit block diagram of Embodiment 1 of the present invention;

[0074] Figure 2 This is a schematic diagram showing the connection of all modules in Embodiment 1 of the present invention;

[0075] Figure 3 This is a circuit diagram of the enable module in Embodiment 1 of the present invention;

[0076] Figure 4 This is a circuit diagram of the control module in Embodiment 1 of the present invention;

[0077] Figure 5 This is a circuit diagram of the counting module without the decoder in Embodiment 1 of the present invention;

[0078] Figure 6 This is a circuit block diagram of the counting module decoder in Embodiment 1 of the present invention;

[0079] Figure 7 This is a circuit diagram of the sixth inverter in the decoder of the counting module in Embodiment 1 of the present invention;

[0080] Figure 8 This is a circuit diagram of the decoding unit in the counting module decoder of Embodiment 1 of the present invention;

[0081] Figure 9 This is a circuit diagram of the fuse module in Embodiment 1 of the present invention;

[0082] Figure 10 This is a circuit diagram of the output module bias circuit in Embodiment 1 of the present invention;

[0083] Figure 11 This is a circuit diagram of the output unit in the output module of Embodiment 1 of the present invention;

[0084] Figure 12 This is a circuit diagram of the detection counting unit in the detection module of Embodiment 1 of the present invention;

[0085] Figure 13 This is a circuit diagram of the detection decoding unit in the detection module of Embodiment 1 of the present invention;

[0086] Figure 14 This is a circuit diagram of the detection result signal output circuit in the detection module of Embodiment 1 of the present invention;

[0087] Figure 15 This is a waveform diagram of the adjustment in Embodiment 1 of the present invention;

[0088] Figure 16 This is a waveform diagram of the adjustment and positioning detection in Embodiment 1 of the present invention;

[0089] Figure 17 This is the overall circuit block diagram of Embodiment 2 of the present invention. Detailed Implementation

[0090] The preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the invention. Example 1

[0091] like Figures 1 to 14 As shown, this embodiment is a detectable bandgap reference voltage adjustment circuit, specifically an adjustment circuit integrated into a low dropout linear regulator (LDO) chip, including: an enable module, a control module, a counting module, a fuse module, an output module, and a detection module.

[0092] like Figure 2 As shown, the enable module receives and responds to the first input signal EF1, the second input signal EF2, and the third input signal EN, generating the first enable signal EF1P, the second enable signal EF2P, and the third enable signal ENP. In response to its own third enable signal ENP, it further generates the fourth enable signal ENPDELAY. The control module controls the counting module and the fuse module. It receives and responds to the first enable signal EF1P, the second enable signal EF2P, and the third enable signal ENP, generating the first control signal CTRL1 and the second control signal CTRL2. The fuse module receives and responds to the first enable signal EF1P, the second enable signal EF2P, and the first control signal CTRL1, generating the first fuse signal COUNT_CTRL; it receives and responds to the first enable signal EF1P, the first control signal CTRL1, and its own first fuse signal COUNT_CTRL, generating the second fuse signal EF_CTRL; and it receives and responds to the first enable signal EF1P and the fourth enable signal ENPDELAY, generating the third fuse signal BIAS_CTRL. The counting module receives and responds to the first fuse-breaking signal COUNT_CTRL, the second fuse-breaking signal EF_CTRL, the second enable signal EF2P, the fourth enable signal ENPDELAY, and the first control signal CTRL1. It counts the second enable signal EF2P and generates a count signal. The output module receives and responds to the second fuse-breaking signal EF_CTRL, the third fuse-breaking signal BIAS_CTRL, and the count signal. It fuses the corresponding fine interconnecting wire at the adjustment position and outputs two sets of reference voltage control signals with opposite potential states after adjustment. The detection module is used for detecting and determining the adjustment position. It receives and responds to the first enable signal EF1P, the second enable signal EF2P, and the second control signal CTRL2. It detects and determines the reference voltage control signal and outputs the detection result signal DET. The enable module, control module, fuse module, counting module, output module, and detection module are all connected to a power supply terminal VIN and a ground terminal (GND).

[0093] like Figure 3 As shown, the enable module includes a first resistor R1, a second resistor R2, a third resistor R3, a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, a first diode Diode1, a second diode Diode2, a first capacitor C1, a second capacitor C2, a first Schmitt trigger T1, a second Schmitt trigger T2, a third Schmitt trigger T3, a fourth Schmitt trigger T4, a first buffer, a second buffer, a first RS flip-flop composed of two NOR gates, a first AND gate, and a second AND gate.

[0094] One end of the first resistor R1 serves as the input terminal of the enable module and is connected to the first input signal EF1. The other end is connected to the source of the first PMOS transistor PM1. The gate of the first PMOS transistor PM1 is connected to the power supply terminal VIN. The drain of the first PMOS transistor PM1 is connected to the input terminal of the first Schmitt trigger T1 and the cathode of the first diode Diode1. The anode of the first diode Diode1 is connected to one end of the first capacitor C1 and grounded. The other end of the first capacitor C1 serves as a common terminal and is connected to the output terminal of the first Schmitt trigger T1 and the input terminal of the first buffer.

[0095] The input terminal of the first inverter is connected to the third input signal EN as the input terminal of the enable module. The output terminal of the first inverter and the output terminal of the first buffer are the set input terminal and the reset input terminal of the first RS flip-flop, respectively. The complementary terminal of the first RS flip-flop is connected to the input terminal of the second buffer.

[0096] One end of the second resistor R2 serves as the input terminal of the enable module and is connected to the first input signal EF1. The other end serves as the common terminal and is connected to the negative terminal of the second diode Diode2 and the input terminal of the third Schmitt trigger T3 respectively. The positive terminal of the second diode Diode2 is grounded.

[0097] The input of the second Schmitt trigger T2 is connected to the second input signal EF2 as the input of the enable module. The output of the second Schmitt trigger T2 and the output of the second buffer are respectively connected to the input of the first AND gate. The output of the first AND gate serves as the output of the enable module, outputting the second enable signal EF2P. The output of the third Schmitt trigger T3 and the output of the second buffer are respectively connected to the input of the second AND gate. The output of the second AND gate serves as the output of the enable module, outputting the first enable signal EF1P.

[0098] The input of the fourth Schmitt trigger T4 serves as the input of the enable module and is connected to the third input signal EN. The output of the fourth Schmitt trigger T4 serves as the common terminal, outputting the third enable signal ENP and connecting it to the gates of the second PMOS transistor PM2 and the first NMOS transistor NM1. The source of the second PMOS transistor PM2 is connected to the power supply terminal VIN, the source of the first NMOS transistor NM1 is grounded, and the drain of the first NMOS transistor NM1 is connected to one end of the third resistor R3. The other end of the third resistor R3 serves as the common terminal, connected to the drain of the second PMOS transistor PM2, and connected to one end of the second capacitor C2, which serves as the output of the enable module, outputting the fourth enable signal ENPDELAY. The other end of the second capacitor C2 is grounded.

[0099] like Figure 4 As shown, the control module includes a third AND gate, a first D flip-flop, a second D flip-flop, a fourth AND gate, and a fifth AND gate. The two inputs of the third AND gate serve as the inputs of the control module and are connected to the first enable signal EF1P and the second enable signal EF2P, respectively. The reset terminals of the first and second D flip-flops are connected to the third enable signal ENP.

[0100] The output of the third AND gate is connected to the clock input of the first D flip-flop. The output of the first D flip-flop is connected to the input of the fourth AND gate. The two's complement output of the first D flip-flop, as a common terminal, is connected to the data input of the first D flip-flop, the clock input of the second D flip-flop, and the input of the fifth AND gate. The output of the second D flip-flop is connected to the other input of the fifth AND gate. The two's complement output of the second D flip-flop, as a common terminal, is connected to the data input of the second D flip-flop and the other input of the fourth AND gate.

[0101] The output of the fourth AND gate is used as the output of the control module to output the second control signal CTRL2, and the output of the fifth AND gate is used as the output of the control module to output the first control signal CTRL1.

[0102] like Figures 5 to 8 As shown, the counting module includes second to fifth inverters, third to eighth D flip-flops, a sixth AND gate, a second RS flip-flop composed of two OR gates, a first NOR gate, and a decoder.

[0103] The input terminal of the second inverter is connected to the second enable signal EF2P as the input terminal of the counting module. The output terminal of the second inverter is connected to the input terminal of the sixth AND gate. The other input terminal of the sixth AND gate is connected to the first control signal CTRL1 as the input terminal of the counting module.

[0104] The input of the third inverter is connected to the first fuse signal COUNT_CTRL of the fuse module, serving as the input of the counting module. The inputs of the fourth and fifth inverters are connected to the fourth enable signal ENPDELAY, serving as the inputs of the counting module. The outputs of the third and fourth inverters are the reset and set inputs of the second RS flip-flop, respectively. The outputs of the second RS flip-flop and the sixth AND gate are connected to the inputs of the first NOR gate, and the output of the first NOR gate is connected to the clock input of the third D flip-flop.

[0105] The reset terminals of the third to eighth D flip-flops are all connected to the output terminal of the fifth inverter. In the third to seventh D flip-flops, the two's complement output terminal of the current D flip-flop is connected to the data input terminal of the current D flip-flop and to the clock input terminal of the next D flip-flop. The two's complement output terminal of the eighth D flip-flop is connected to the data input terminal of the eighth D flip-flop.

[0106] The outputs of the third to eighth D flip-flops are all connected to the input of the decoder. The two's complement outputs of the third to seventh D flip-flops are connected to the input of the decoder. The second fuse signal EF_CTRL is connected to the input of the decoder.

[0107] The decoder includes a sixth inverter and thirty-two decoder units. The input of the sixth inverter is connected to the second fuse signal EF_CTRL of the fuse module, serving as the input of the decoder.

[0108] Each decoder unit includes a NAND gate and a NOR gate, with the output of the NAND gate connected to the input of the NOR gate; the output of the eighth D flip-flop and the output of the sixth inverter are both connected to the input of the NOR gate in each decoder unit.

[0109] The inputs of the 32 decoder units and NAND gates are connected in binary order to the outputs or two's complement outputs of the third to seventh D flip-flops. The outputs of the 32 decoder units and NAND gates output the corresponding counting signals in binary order. The specific connections are as follows... Figure 8 As shown.

[0110] like Figure 9 As shown, the fuse module includes a seventh inverter, a third buffer, a first NAND gate, a second NOR gate, a first buffer delay unit KT1, an eighth inverter, a seventh AND gate, a second NAND gate, a ninth inverter, a fourth buffer, a fifth buffer, a ninth D flip-flop, an eighth AND gate, and a trimming protection unit.

[0111] The adjustment and protection unit includes a third NAND gate, a tenth D flip-flop, an eleventh D flip-flop, a third RS flip-flop composed of two NOR gates, and a sixth buffer.

[0112] The input of the seventh inverter is connected to the second enable signal EF2P as the input of the fuse module, and the input of the third buffer is connected to the first enable signal EF1P as the input of the fuse module. The input of the first NAND gate is connected to the output of the seventh inverter, the output of the third buffer, and the first control signal CTRL1. The output of the first NAND gate is connected to the input of the second NOR gate. The other input of the second NOR gate is connected to the complementary terminal of the third RS flip-flop, and the output of the second NOR gate is connected to the input of the first buffer delay unit KT1. The output of the buffer delay unit is connected as a common terminal to the input of the eighth inverter and outputs the first fuse signal COUNT_CTRL. The output of the eighth inverter and the first control signal CTRL1 are connected to the input of the seventh AND gate.

[0113] The input of the second NAND gate is connected to the first control signal CTRL1 and the first enable signal EF1P. The output of the second NAND gate serves as a common terminal and is connected to the input of the ninth inverter and the reset input of the third RS flip-flop. The output of the ninth inverter is connected to the input of the fourth buffer. The first control signal CTRL1 is connected to the input of the fifth buffer.

[0114] The outputs of the seventh AND gate, the fourth buffer, and the fifth buffer are connected in sequence to the data input, clock input, and reset input of the ninth D flip-flop. The output of the ninth D flip-flop and the first fuse signal COUNT_CTRL are connected to the input of the eighth AND gate. The output of the eighth AND gate outputs the second fuse signal EF_CTRL.

[0115] The fourth enable signal, ENPDELAY, is connected to the reset terminals of the 10th and 11th D flip-flops. The clock input of the 10th D flip-flop is connected to the output of the third NAND gate. The two's complement output of the 10th D flip-flop is connected to its own data input and the clock input of the 11th D flip-flop, respectively. The data input of the 11th D flip-flop is connected to the power supply terminal VIN. The output of the 11th D flip-flop outputs the third fuse signal, BIAS_CTRL. The two's complement output of the 11th D flip-flop serves as a common terminal and is connected to the set input of the third RS flip-flop and the input of the sixth buffer, respectively. The output of the sixth buffer and the first enable signal, EF1P, are connected to the input of the third NAND gate, respectively.

[0116] The output module includes a bias circuit and an output drive circuit.

[0117] like Figure 10 As shown, the bias circuit includes a tenth inverter, third to sixth resistors R3-R6, third to fifth PMOS transistors PM3-PM5, second NMOS transistor NM2, and third NMOS transistor NM3.

[0118] The input terminal of the tenth inverter and the gate of the fifth PMOS transistor PM5 are connected to the third fuse signal BIAS_CTRL. The output terminal of the tenth inverter is connected to the gate of the sixth PMOS transistor PM6. The source of the sixth PMOS transistor PM6, one end of the fourth resistor R4, and one end of the fifth resistor R5 are connected to the power supply terminal VIN. The other end of the fourth resistor R4 is connected to the source of the third PMOS transistor PM3. The other end of the fifth resistor R5 is connected to the source of the fourth PMOS transistor PM4. The gate of the third PMOS transistor PM3 serves as a common terminal and is connected to the gate of the fourth PMOS transistor PM4, the drain of the third PMOS transistor PM3, the source of the fifth PMOS transistor PM5, and the drain of the sixth PMOS transistor PM6, and outputs the first bias voltage BIAS1.

[0119] The drain of the fifth PMOS transistor PM5 is connected to the drain of the second NMOS transistor NM2. The gate of the second NMOS transistor NM2 is connected to the power supply terminal VIN. The source of the second NMOS transistor NM2 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 and the source of the third NMOS transistor NM3 are connected to the power supply terminal VIN. The gate of the third NMOS transistor NM3 serves as a common terminal and is connected to the drain of the fourth PMOS transistor PM4 and the drain of the third NMOS transistor NM3 respectively, and outputs the second bias voltage BIAS2.

[0120] like Figure 11 As shown, the output drive circuit includes thirty-two parallel output units. Each output unit includes a ninth AND gate, sixth to ninth resistors R6-R9, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, fourth to sixth NMOS transistors NM4-NM6, an eleventh inverter, a twelfth inverter, and a seventh buffer.

[0121] In each output unit, one end of the seventh resistor R7 is grounded, and the other end is connected to the gate of the seventh PMOS transistor PM7. The source of the seventh PMOS transistor PM7 is connected to the power supply terminal VIN. The drain of the seventh PMOS transistor PM7 is connected to one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to the drain of the fourth NMOS transistor NM4 and the source of the eighth PMOS transistor PM8. The gate of the eighth PMOS transistor PM8 is connected to the first bias voltage BIAS1. The gate of the fourth NMOS transistor NM4 is connected to the output terminal of the ninth AND gate and one end of the ninth resistor R9. One input terminal of the ninth AND gate is connected to the second fuse signal EF_CTRL. The other end of the ninth resistor R9 is connected to the sixth NMOS transistor. The drain and gate of NM6, the source of the sixth NMOS transistor NM6, the source of the fourth NMOS transistor NM4, and the source of the fifth NMOS transistor NM5 are connected to the power supply terminal VIN. The drain of the fifth NMOS transistor NM5 serves as a common terminal and is connected to the drain of the eighth PMOS transistor PM8, the input of the twelfth inverter, the output of the eleventh inverter, and the input of the seventh buffer. The gate of the fifth NMOS transistor NM5 is connected to the second bias voltage BIAS2. The output of the twelfth inverter is connected to the input of the eleventh inverter. The eleventh inverter is connected to the bias voltage of the third fuse signal BIAS_CTRL. The seventh PMOS transistor PM7 and the eighth resistor R8 are connected using fine interconnect wires.

[0122] The other input of the ninth AND gate of each of the thirty-two output units is connected in sequence to the output of the NOR gate of each of the thirty-two decoder units. The output of the twelfth inverter of each of the thirty-two output units outputs thirty-two reference voltage control signals FUSEN0-FUSEN31 in sequence, and the output of the seventh buffer of each of the thirty-two output units outputs the inverted signals FUSEP0-FUSEP31 of the thirty-two reference voltage control signals in sequence.

[0123] like Figures 12 to 14 As shown, the detection module includes a detection counting unit, thirty-two detection decoding units, and a detection result signal output circuit. The detection counting unit includes: a thirteenth inverter, a fourteenth inverter, twelve to sixteenth D flip-flops, and a fourth NAND gate.

[0124] The input of the thirteenth inverter is connected to the first enable signal EF1P. The output of the thirteenth inverter and the second control signal CTRL2 are connected to the input of the fourth NAND gate. The output of the fourth NAND gate is connected to the clock input of the twelfth D flip-flop.

[0125] The input of the fourteenth inverter is connected to the fourth enable signal ENPDELAY, and the output of the fourteenth inverter is connected to the reset terminals of the twelfth to sixteenth D flip-flops. In the twelfth to fifteenth D flip-flops, the two's complement output of the current D flip-flop is connected to the data input of the current D flip-flop and to the clock input of the next D flip-flop. The two's complement output of the sixteenth D flip-flop is connected to the data input of the sixteenth D flip-flop.

[0126] Each detection decoding unit includes an AND gate and an inverter. The output of the AND gate is connected to the bias voltage input of the inverter. The inputs of the AND gates in the thirty-two detection decoding units are connected in binary order to the outputs or two's complement outputs of the twelfth to sixteenth D flip-flops. The inputs of the inverters in the thirty-two detection decoding units are sequentially connected to thirty-two reference voltage control signals FUSEN0-FUSEN31.

[0127] The output terminals of the inverters in the thirty-two detection and decoding units are all connected to the signal input terminals of the detection result signal output circuit.

[0128] The detection result signal output circuit includes a fifteenth inverter, a seventh NMOS transistor NM7, an eighth buffer, a fifth NAND gate, a sixteenth inverter, a ninth buffer, an eighth NMOS transistor NM8, and a ninth NMOS transistor NM9.

[0129] The outputs of the inverters in the 32 detection and decoding units are connected to the input of the eighth buffer and the drain of the seventh NMOS transistor NM7, with the source of NM7 grounded. The second control signal CTRL2 is connected to the input of the 15th inverter, the input of the fifth NAND gate, the bias voltage input of the 16th inverter, and the input of the 9th buffer. The output of the 15th inverter is connected to the gate of the seventh NMOS transistor NM7. The output of the eighth buffer is connected to the input of the fifth NAND gate, the output of the fifth NAND gate is connected to the input of the 16th inverter, the output of the 16th inverter is connected to the gate of the eighth NMOS transistor NM8, and the output of the 9th buffer is connected to the gate of the 9th NMOS transistor NM9, with the source of NM9 grounded. The drain of NM9 is connected to the source of NM8, and the drain of NM8 outputs the detection result signal DET.

[0130] In this embodiment, during adjustment, the enable module, control module, counting module, fuse module, and output module are running, while the detection module is not enabled; during detection, the enable module, control module, and detection module are running, while the counting module, fuse module, and output module are not enabled.

[0131] In this embodiment, the enable module, through the combined action of the first resistor R1, the first PMOS transistor PM1, and the first diode Diode1, ensures that the first input signal EF1P and the second enable signal EF2P will synchronously respond to changes in the first input signal EF1 and the second input signal EF2 only when the first input signal EF1 exceeds the power supply terminal VIN by more than 1V. Otherwise, the first enable signal EF1P and the second enable signal EF2P will remain at a low level, thus avoiding false triggering during adjustment or detection. Simultaneously, based on voltage withstand design considerations, the first input signal EF1 only provides a voltage higher than the power supply terminal VIN during startup; subsequently, the voltage of the first input signal EF1 will not exceed the power supply terminal VIN. Thus, due to the action of the first RS flip-flop, the first enable signal EF1P and the second enable signal EF2P can accurately track changes in the first input signal EF1 and the second input signal EF2.

[0132] In this embodiment, the fuse module is equipped with a trimming protection unit. At least two complete clock cycles need to be input into the first enable signal EF1P of the trimming protection unit to change the two's complement output of the eleventh D flip-flop from high level to low level in order to change the state of the second fuse signal EF_CTRL constantly outputting a low level.

[0133] In the initial state of this embodiment, all modules are not activated. The ports of the first input signal EF1 and the second input signal EF2 in the enable module remain floating, and no power or enable signal is provided to the subsequent circuit. In the control module, the first control signal CTRL1 and the second control signal CTRL2 are both at low level. In the counting module, the third to the eighth D flip-flops are in the cleared state. In the fuse module, the ninth D flip-flop is in the cleared state. In the output module, since the resistance value of the eighth resistor R8 in each output unit is much smaller than that of the first resistor R1 and the second resistor R2, the output is an unadjusted reference voltage control signal. The thirty-two reference voltage control signals FUSEN0-FUSEN31 are kept at low level output, and the inverted signals FUSEP0-FUSEP31 of the thirty-two reference voltage control signals are kept at high level output.

[0134] In this embodiment, during adjustment, the third input signal EN in the enable module changes from low to high, causing the third enable signal ENP to change from low to high, and the fourth enable signal ENPDELAY to change from high to low. The state changes of the first enable signal EF1P and the second enable signal EF2P are synchronized with the first input signal EF1 and the second input signal EF2. Due to the presence of the adjustment protection unit in the fuse module, at least two complete clock cycles must be input to the first input signal EF1 to activate the fuse module.

[0135] The control module, based on the timing of the first input signal EF1 and the second input signal EF2, causes the first control signal CTRL1 and the second control signal CTRL2 to go high at specific times. If the first input signal EF1 is fixed at a high level, and the second input signal EF2 is a clock signal with a finite period, the second control signal CTRL2 rises from a low level to a high level when triggered by the first rising edge; when the second rising edge arrives, the first control signal CTRL1 changes from a low level to a high level, and at the same time, the second control signal CTRL2 is reset from a high level to a low level.

[0136] When the first control signal CTRL1 of the control module goes high, the counting module and the fuse module start up. The counting module begins counting the clock signal of the second input signal EF2, outputting the corresponding binary signals through the third to eighth D flip-flops, which then pass through the decoder, causing the decoder output to be high-level corresponding to the count. The second fuse signal EF_CTRL and the third fuse signal BIAS_CTRL of the fuse module also start outputting high-level signals. The third fuse signal BIAS_CTRL turns off the bias circuit and the eleventh inverter.

[0137] The high level of the counting module and the high level of the second fuse signal EF_CTRL turn on the fourth NMOS transistor NM4 in the output unit corresponding to the counting in the output module. This increases the current flowing between the seventh PMOS transistor PM7 and the eighth resistor R8, thereby melting the tiny interconnecting wire between the seventh PMOS transistor PM7 and the eighth resistor R8. This causes a change in the reference voltage control signal output in the current output unit, thus achieving precise control of the bandgap reference output voltage. After adjustment, the first input signal EF1 can be set to a low level, which locks the states of the first control signal CTRL1 and the second control signal CTRL2.

[0138] In this embodiment, the initial output value of the low-dropout linear regulator reference voltage is 1.221V, with a positive deviation of +21mV. It needs to be adjusted through two stages to achieve a voltage compensation of -20mV.

[0139] Based on the principles of circuit simplification and functional verification requirements, the second reference voltage control signal FUSEN1 and the third reference voltage control signal FUSEN2 were selected as the target adjustment bits. This selection is mainly based on the following design considerations: First, prioritizing the low-order registers can effectively reduce the number of clock signal inputs for the second input signal EF2; second, different combinations of sequence bit registers can fully verify the functional completeness of the counting circuit. Given the single-channel operation of the adjustment circuit, the adjustment process of the third reference voltage control signal FUSEN2 is demonstrated, and its test waveform is shown below. Figure 15 As shown.

[0140] Timing analysis shows that during the 50-100μs period, the first input signal EF1 receives a dual-cycle clock signal. The first cycle uses a 6V input voltage to activate the enable module, and the second cycle initializes and resets the fuse protection circuit. During the 150-250μs period, the clock signal of the second input signal EF2 initializes the control circuit configuration. During the 350-550μs period, the binary counting operation is completed using the clock pulse of the second input signal EF2. When the system reaches 600μs, the first input signal EF1 transitions to a high level, terminating the counting process and outputting a counting signal to the output module. This activates the third output unit to permanently adjust the third reference voltage control signal FUSEN2, achieving a step drop of approximately 10mV in the reference voltage.

[0141] The adjustment method for the second reference voltage control signal FUSEN1 is the same as that for the third reference voltage control signal FUSEN2; only the clock signal timing parameters need to be adjusted during the counting phase. After two stages of adjustment, the final output value of the reference voltage stabilizes at 1.201V, fully meeting the preset design specifications.

[0142] In this embodiment, the counting module, fuse module, and output module are not turned on during detection. At this time, the clock signal is input by the first input signal EF1. After counting by the twelfth to sixteenth D flip-flops, the corresponding binary signal is output, which in turn causes the corresponding detection decoding unit in the thirty-two detection decoding units to output the signal. The detection result signal DET is then output by the detection result signal output circuit.

[0143] The detection mode is jointly controlled by the first input signal EF1 and the second input signal EF2. Its control logic differs from the trimming mode: the second input signal EF2 controls the main mode switching, while the first input signal EF1 is responsible for the counting operation. For detailed trimming position detection results, please refer to... Figure 16 The waveform shown.

[0144] During the 100-110μs phase, the first input signal EF1 inputs a 6V voltage to activate the enable module. During the 150-300μs phase, the second input signal EF2 triggers the detection mode with a single-cycle square wave signal. At this time, the detection result signal DET outputs a count of 0, indicating that the first output unit is not blown. During the 300-500μs phase, the first input signal EF1 inputs a clock signal containing three rising edges, sequentially detecting the status of the second to fourth output units: a high-level output of the detection result signal DET indicates that the second and third output units are blown, and a level change in the detection result signal DET at the third rising edge confirms that the fourth output unit remains intact. The detection data perfectly matches the preset adjustment strategy.

[0145] In summary, this embodiment achieves high-precision adjustment of the bandgap reference voltage by combining fuse adjustment and digital adjustment, and has a built-in detection function, which improves the accuracy and stability of the reference voltage, enhances the reliability and long-term stability of the circuit, and reduces production costs while increasing integration. Example 2

[0146] This embodiment is a bandgap reference circuit including the detectable bandgap reference voltage adjustment circuit described in Embodiment 1. Specifically, the circuit connection is as follows: Figure 17 As shown, the reference voltage control signal of the bandgap reference voltage adjustment circuit is input to the bandgap reference module.

[0147] The bandgap reference voltage adjustment circuit is an indispensable back-end component for mass-produced high-performance reference sources. By fine-tuning the circuit parameters, it overcomes the inherent deviations and temperature drift introduced by the manufacturing process, ensuring that the output reference voltage is accurate, stable, and meets the design specifications, thereby providing a reliable reference for downstream circuits.

[0148] The core function of a bandgap reference circuit is to utilize the physical properties of silicon and circuit technology to overcome the effects of temperature, power supply voltage variations, and process deviations, generating a highly stable and accurate DC reference voltage. While a bandgap reference circuit can theoretically provide a stable reference, random deviations in the manufacturing process can cause the unadjusted actual circuit output voltage to deviate from the ideal value, and its temperature coefficient may also be imperfect. Therefore, in this embodiment, based on the bandgap reference voltage adjustment circuit of Example 1, a bandgap reference module is combined to achieve the high accuracy and high stability required for mass production. Those skilled in the art can select appropriate bandgap reference modules to form corresponding bandgap reference circuits to achieve their own purposes, and the hardware configuration of the bandgap reference module is not limited here.

[0149] In this embodiment, by configuring the first to sixteenth reference voltage control signals FUSEN0-FUSEN15 and the inverted signals FUSEP16-FUSEP31 of the seventeenth to thirty-second reference voltage control signals as a control signal group, and in conjunction with the NMOS switch array of the bandgap reference circuit, bidirectional voltage regulation can be achieved: when the level of the first to sixteenth reference voltage control signal group FUSEN0-FUSEN15 increases, the output voltage decreases; when the level of the inverted signals FUSEP16-FUSEP31 of the seventeenth to thirty-second reference voltage control signals decreases, the output voltage increases, and finally a 32-bit bidirectional programmable reference voltage output is achieved.

[0150] In this embodiment, the inverse signals FUSEP16-FUSEP31 of the first to sixteenth reference voltage control signals FUSEN0-FUSEN15 and the seventeenth to thirty-second reference voltage control signals FUSEN16-FUSEN31 and the inverse signals FUSEP0-FUSEP15 of the first to sixteenth reference voltage control signals can also be replaced with the inverse signals FUSEP0-FUSEP15 of the seventeenth to thirty-second reference voltage control signals FUSEN16-FUSEN31 and the first to sixteenth reference voltage control signals FUSEN0-FUSEP15.

Claims

1. A detectable bandgap reference voltage adjustment circuit, comprising an enable module, a counting module, a fuse module, and an output module, characterized in that, Also includes: Control module; After receiving and responding to the first input signal, the second input signal, and the third input signal, the enabling module generates a first enabling signal, a second enabling signal, and a third enabling signal, and further generates a fourth enabling signal in response to its own third enabling signal. The control module receives and responds to the first enable signal, the second enable signal, and the third enable signal, and generates the first control signal and the second control signal. The fuse module receives and responds to a first enable signal, a second enable signal, and a first control signal to generate a first fuse signal; receives and responds to the first enable signal, the first control signal, and its own first fuse signal to generate a second fuse signal; and receives and responds to the first enable signal and a fourth enable signal to generate a third fuse signal. The counting module receives and responds to the first fuse signal, the second fuse signal, the second enable signal, the fourth enable signal, and the first control signal, counts the second enable signal, and generates a counting signal. The output module receives and responds to the second fuse signal, the third fuse signal, and the counting signal, fuses the fine interconnecting wires corresponding to the adjustment position, and outputs two sets of reference voltage control signals with opposite potential states after adjustment. The enable module, control module, fuse module, counting module, and output module are all connected to a power supply terminal and a ground terminal.

2. The detectable bandgap reference voltage adjustment circuit according to claim 1, characterized in that, It also includes a detection module; The detection module is used for the detection and determination of the adjustment position, receives and responds to the first enable signal, the second enable signal, and the second control signal, performs detection and determination on the reference voltage control signal, and outputs the detection result signal; The detection module is connected to a power supply terminal and a ground terminal.

3. The detectable bandgap reference voltage adjustment circuit according to claim 2, characterized in that, When the counting module, fuse module, and output module are running, the detection module is not activated. When the detection module is running, the counting module, the fuse module, and the output module are not enabled.

4. A detectable bandgap reference voltage adjustment circuit according to any one of claims 1 to 3, characterized in that, The enabling module includes a first resistor, a second resistor, a third resistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a first diode, a second diode, a first capacitor, a second capacitor, a first Schmitt trigger, a second Schmitt trigger, a third Schmitt trigger, a fourth Schmitt trigger, a first buffer, a second buffer, a first RS flip-flop composed of two NOR gates, a first AND gate, and a second AND gate; One end of the first resistor serves as the input terminal of the enable module and is connected to the first input signal, while the other end is connected to the source of the first PMOS transistor. The gate of the first PMOS transistor is connected to the power supply terminal, and the drain of the first PMOS transistor is connected to the input terminal of the first Schmitt trigger and the cathode of the first diode, respectively. The anode of the first diode is connected to one end of the first capacitor and grounded, while the other end of the first capacitor serves as the common terminal and is connected to the output terminal of the first Schmitt trigger and the input terminal of the first buffer, respectively. The input terminal of the first inverter is connected to the third input signal as the input terminal of the enable module. The output terminal of the first inverter and the output terminal of the first buffer are respectively the set input terminal and the reset input terminal of the first RS flip-flop. The complementary terminal of the first RS flip-flop is connected to the input terminal of the second buffer. One end of the second resistor serves as the input terminal of the enable module and is connected to the first input signal. The other end serves as the common terminal and is connected to the negative terminal of the second diode and the input terminal of the third Schmitt trigger, respectively. The positive terminal of the second diode is grounded. The input of the second Schmitt trigger is connected to the second input signal as the input of the enable module. The output of the second Schmitt trigger and the output of the second buffer are respectively connected to the input of the first AND gate. The output of the first AND gate is the output of the enable module and outputs the second enable signal. The output of the third Schmitt trigger and the output of the second buffer are respectively connected to the input of the second AND gate. The output of the second AND gate is the output of the enable module and outputs the first enable signal. The input terminal of the fourth Schmitt trigger is connected to the third input signal as the input terminal of the enable module; the output terminal of the fourth Schmitt trigger is connected to the common terminal as the third enable signal and is connected to the gates of the second PMOS transistor and the first NMOS transistor; the source of the second PMOS transistor is connected to the power supply terminal, the source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to one end of the third resistor, the other end of the third resistor is connected to the drain of the second PMOS transistor as the common terminal, and is connected to one end of the second capacitor, and is also connected to the output terminal of the enable module to output the fourth enable signal; the other end of the second capacitor is grounded.

5. A detectable bandgap reference voltage adjustment circuit according to any one of claims 1 to 3, characterized in that, The control module includes a third AND gate, a first D flip-flop, a second D flip-flop, a fourth AND gate, and a fifth AND gate; The two input terminals of the third AND gate are connected to the first enable signal and the second enable signal respectively as input terminals of the control module. The reset terminals of the first D flip-flop and the second D flip-flop are connected to the third enable signal. The output of the third AND gate is connected to the clock input of the first D flip-flop. The output of the first D flip-flop is connected to the input of the fourth AND gate. The two's complement output of the first D flip-flop is connected as a common terminal to the data input of the first D flip-flop, the clock input of the second D flip-flop, and the input of the fifth AND gate. The output of the second D flip-flop is connected to the other input of the fifth AND gate. The two's complement output of the second D flip-flop is connected as a common terminal to the data input of the second D flip-flop and the other input of the fourth AND gate. The output of the fourth AND gate serves as the output of the control module, outputting the second control signal, and the output of the fifth AND gate serves as the output of the control module, outputting the first control signal.

6. A detectable bandgap reference voltage adjustment circuit according to claim 2 or 3, characterized in that, The counting module includes second to fifth inverters, third to eighth D flip-flops, a sixth AND gate, a second RS flip-flop composed of two OR gates, a first NOR gate, and a decoder; The input terminal of the second inverter is connected to the second enable signal as the input terminal of the counting module, the output terminal of the second inverter is connected to the input terminal of the sixth AND gate, and the other input terminal of the sixth AND gate is connected to the first control signal as the input terminal of the counting module. The input of the third inverter is connected to the first fuse signal of the fuse module as the input of the counting module. The inputs of the fourth inverter and the fifth inverter are connected to the fourth enable signal as the inputs of the counting module. The outputs of the third inverter and the fourth inverter are respectively the reset input and set input of the second RS flip-flop. The outputs of the second RS flip-flop and the sixth AND gate are respectively connected to the inputs of the first NOR gate. The output of the first NOR gate is connected to the clock input of the third D flip-flop. The reset terminals of the third to eighth D flip-flops are all connected to the output terminal of the fifth inverter; among the third to seventh D flip-flops, the two's complement output terminal of the current D flip-flop is connected to the data input terminal of the current D flip-flop and to the clock input terminal of the next D flip-flop, and the two's complement output terminal of the eighth D flip-flop is connected to the data input terminal of the eighth D flip-flop. The outputs of the third to eighth D flip-flops are all connected to the input of the decoder. The two's complement outputs of the third to seventh D flip-flops are connected to the input of the decoder. The second fuse signal is connected to the input of the decoder.

7. A detectable bandgap reference voltage adjustment circuit according to claim 6, characterized in that, The decoder includes a sixth inverter and thirty-two decoder units; The input terminal of the sixth inverter is connected to the second fuse signal of the fuse module as the input terminal of the decoder. Each decoder unit includes a NAND gate and a NOR gate, with the output of the NAND gate connected to the input of the NOR gate; the output of the eighth D flip-flop and the output of the sixth inverter are both connected to the input of the NOR gate in each decoder unit. The inputs of the 32 decoder units and NAND gates are connected in binary order to the outputs or two's complement outputs of the third to seventh D flip-flops. The outputs of the thirty-two decoder units and their NOR gates output corresponding counting signals in binary order.

8. A detectable bandgap reference voltage adjustment circuit according to any one of claims 1 to 3, characterized in that, The fuse module includes a seventh inverter, a third buffer, a first NAND gate, a second NOR gate, a first buffer delay unit, an eighth inverter, a seventh AND gate, a second NAND gate, a ninth inverter, a fourth buffer, a fifth buffer, a ninth D flip-flop, an eighth AND gate, and a trimming protection unit. The adjustment and protection unit includes a third NAND gate, a tenth D flip-flop, an eleventh D flip-flop, a third RS flip-flop composed of two NOR gates, and a sixth buffer. The input terminal of the seventh inverter is connected to the second enable signal as the input terminal of the fuse module, and the input terminal of the third buffer is connected to the first enable signal as the input terminal of the fuse module. The input terminal of the first NAND gate is connected to the output terminal of the seventh inverter, the output terminal of the third buffer, and the first control signal. The output terminal of the first NAND gate is connected to the input terminal of the second NOR gate. The other input terminal of the second NOR gate is connected to the complementary terminal of the third RS flip-flop. The output terminal of the second NOR gate is connected to the input terminal of the first buffer delay unit. The output terminal of the buffer delay unit is connected to the input terminal of the eighth inverter as a common terminal and outputs the first fuse signal. The output terminal of the eighth inverter and the first control signal are connected to the input terminal of the seventh AND gate. The input of the second NAND gate is connected to the first control signal and the first enable signal, and the output of the second NAND gate is connected as a common terminal to the input of the ninth inverter and the reset input of the third RS flip-flop. The output of the ninth inverter is connected to the input of the fourth buffer; the first control signal is connected to the input of the fifth buffer. The outputs of the seventh AND gate, the fourth buffer, and the fifth buffer are connected in sequence to the data input, clock input, and reset input of the ninth D flip-flop. The output of the ninth D flip-flop and the first fuse signal are connected to the input of the eighth AND gate. The output of the eighth AND gate outputs the second fuse signal. The fourth enable signal is connected to the reset terminals of the tenth D flip-flop and the eleventh D flip-flop. The clock input terminal of the tenth D flip-flop is connected to the output terminal of the third NAND gate. The two's complement output terminal of the tenth D flip-flop is connected to its own data input terminal and the clock input terminal of the eleventh D flip-flop, respectively. The data input terminal of the eleventh D flip-flop is connected to the power supply terminal. The output terminal of the eleventh D flip-flop outputs the third fuse signal. The two's complement output terminal of the eleventh D flip-flop serves as a common terminal and is connected to the set input terminal of the third RS flip-flop and the input terminal of the sixth buffer, respectively. The output terminal of the sixth buffer and the first enable signal are connected to the input terminal of the third NAND gate, respectively.

9. A detectable bandgap reference voltage adjustment circuit according to claim 7, characterized in that, The output module includes a bias circuit and an output drive circuit; The bias circuit includes a tenth inverter, third to sixth resistors, third to fifth PMOS transistors, a second NMOS transistor, and a third NMOS transistor; The input terminal of the tenth inverter and the gate of the fifth PMOS transistor are connected to the third fuse signal. The output terminal of the tenth inverter is connected to the gate of the sixth PMOS transistor. The source of the sixth PMOS transistor, one end of the fourth resistor, and one end of the fifth resistor are connected to the power supply terminal. The other end of the fourth resistor is connected to the source of the third PMOS transistor. The other end of the fifth resistor is connected to the source of the fourth PMOS transistor. The gate of the third PMOS transistor serves as a common terminal and is connected to the gate of the fourth PMOS transistor, the drain of the third PMOS transistor, the source of the fifth PMOS transistor, and the drain of the sixth PMOS transistor, and outputs the first bias voltage. The drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the power supply terminal. The source of the second NMOS transistor is connected to one end of the sixth resistor. The other end of the sixth resistor and the source of the third NMOS transistor are connected to the power supply terminal. The gate of the third NMOS transistor serves as a common terminal and is connected to the drain of the fourth PMOS transistor and the drain of the third NMOS transistor respectively, and outputs the second bias voltage. The output drive circuit includes thirty-two parallel output units, each of which includes a ninth AND gate, sixth to ninth resistors, a seventh PMOS transistor, an eighth PMOS transistor, fourth to sixth NMOS transistors, an eleventh inverter, a twelfth inverter, and a seventh buffer. In each output unit, one end of the seventh resistor is grounded, and the other end is connected to the gate of the seventh PMOS transistor. The source of the seventh PMOS transistor is connected to the power supply terminal. The drain of the seventh PMOS transistor is connected to one end of the eighth resistor. The other end of the eighth resistor is connected to the drain of the fourth NMOS transistor and the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor is connected to the first bias voltage. The gate of the fourth NMOS transistor is connected to the output terminal of the ninth AND gate and one end of the ninth resistor. One input terminal of the ninth AND gate is connected to the second fuse signal. The other end of the ninth resistor is connected to the output terminal of the sixth NMOS transistor. The drain and gate, the source of the sixth NMOS transistor, the source of the fourth NMOS transistor, and the source of the fifth NMOS transistor are connected to the power supply terminal. The drain of the fifth NMOS transistor serves as a common terminal and is connected to the drain of the eighth PMOS transistor, the input of the twelfth inverter, the output of the eleventh inverter, and the input of the seventh buffer, respectively. The gate of the fifth NMOS transistor is connected to the second bias voltage. The output of the twelfth inverter is connected to the input of the eleventh inverter. The eleventh inverter is connected to the bias voltage of the third fuse signal. The seventh PMOS transistor and the eighth resistor are connected using fine interconnecting wires. The other input terminal of the ninth AND gate of the thirty-two output units is connected in sequence to the output terminals of the thirty-two decoder units or NOT gates; The output terminals of the twelfth inverter of the thirty-two output units sequentially output thirty-two reference voltage control signals, and the output terminals of the seventh buffer of the thirty-two output units sequentially output the inverse signals of the thirty-two reference voltage control signals.

10. A detectable bandgap reference voltage adjustment circuit according to claim 9, characterized in that, The resistance value of the eighth resistor in each of the output units is much smaller than that of the first resistor and the second resistor.

11. A detectable bandgap reference voltage adjustment circuit according to claim 9 or 10, characterized in that, The detection module includes a detection counting unit, thirty-two detection decoding units, and a detection result signal output circuit. The detection and counting unit includes: a thirteenth inverter, a fourteenth inverter, twelfth to sixteenth D flip-flops, and a fourth NAND gate; The input terminal of the thirteenth inverter is connected to the first enable signal, the output terminal of the thirteenth inverter and the second control signal are connected to the input terminal of the fourth NAND gate, and the output terminal of the fourth NAND gate is connected to the clock input terminal of the twelfth D flip-flop. The input terminal of the fourteenth inverter is connected to the fourth enable signal, and the output terminal of the fourteenth inverter is connected to the reset terminal of the twelfth to sixteenth D flip-flops. In the twelfth to fifteenth D flip-flops, the two's complement output of the current D flip-flop is connected to the data input of the current D flip-flop and to the clock input of the next D flip-flop; the two's complement output of the sixteenth D flip-flop is connected to the data input of the sixteenth D flip-flop. Each detection decoding unit includes an AND gate and an inverter. The output of the AND gate is connected to the bias voltage input of the inverter. The inputs of the AND gates of the thirty-two detection decoding units are connected to the outputs or two's complement outputs of the twelfth to sixteenth D flip-flops in binary order. The inputs of the inverters of the thirty-two detection decoding units are connected to thirty-two reference voltage control signals in sequence. The output terminals of the inverters in the thirty-two detection and decoding units are all connected to the signal input terminals of the detection result signal output circuit. The detection result signal output circuit includes a fifteenth inverter, a seventh NMOS transistor, an eighth buffer, a fifth NAND gate, a sixteenth inverter, a ninth buffer, an eighth NMOS transistor, and a ninth NMOS transistor; The output terminals of the inverters in the thirty-two detection decoding units are connected to the input terminal of the eighth buffer and the drain of the seventh NMOS transistor, with the source of the seventh NMOS transistor grounded. The second control signal is connected to the input terminal of the fifteenth inverter, the input terminal of the fifth NAND gate, the bias voltage input terminal of the sixteenth inverter, and the input terminal of the ninth buffer, respectively. The output terminal of the fifteenth inverter is connected to the gate of the seventh NMOS transistor, the output terminal of the eighth buffer is connected to the input terminal of the fifth NAND gate, the output terminal of the fifth NAND gate is connected to the input terminal of the sixteenth inverter, the output terminal of the sixteenth inverter is connected to the gate of the eighth NMOS transistor, the output terminal of the ninth buffer is connected to the gate of the ninth NMOS transistor, the source of the ninth NMOS transistor is grounded, the drain of the ninth NMOS transistor is connected to the source of the eighth NMOS transistor, and the drain of the eighth NMOS transistor outputs the detection result signal.

12. A bandgap reference circuit, characterized in that, Includes a detectable bandgap reference voltage adjustment circuit as described in any one of claims 1 to 11.

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