A memory-compute integrated microcontroller and data processing method

Abstract

This application belongs to the field of computer architecture design, specifically disclosing a memory-based computing microcontroller and a data processing method. This application configures a separate functional circuit module for each processing unit, thereby ensuring that each processing unit can independently perform instruction addressing, decoding, and execution, increasing the parallelism of the computation process. The register module is defined at the processing unit level, and the system's memory hierarchy is clearly divided, ensuring that register operations are only performed within the processing unit during computation. Simultaneously, the data transmission chain is clearly defined as external memory – storage and management unit – data storage module – vector / scalar register module, making the microcontroller design more rational. The instruction set proposed in this application provides fine-grained in-memory computing instruction operations and designs a data processing scheme for this purpose, providing a basic operational specification for building general-purpose in-memory computing hardware.

Description

Technical Field

[0001] This application belongs to the field of computer architecture design technology, and more specifically, relates to a memory-based microcontroller and a data processing method. Background Technology

[0002] In-memory computing architecture has become a key solution for overcoming the von Neumann bottleneck. Resistive in-memory computing solutions implemented using novel non-volatile memory devices such as memristors and phase-change memories have achieved significant results in many applications, including machine learning and neural networks. However, with the rapid increase in data volume and model size, how to quickly deploy in-memory computing algorithms into in-memory computing hardware has become a new challenge. Unlike traditional computing hardware, in-memory computing systems exhibit higher parallelism, novel computing modes, and lower power consumption requirements, necessitating the design of entirely new in-memory computing microcontrollers to realize the control core implementation in in-memory computing application scenarios.

[0003] Furthermore, for in-memory computing microcontrollers, a novel instruction set framework needs to be developed to meet the data compilation and management requirements of in-memory computing applications. The open-source RISC-V instruction set architecture provides a rich set of basic computer instructions, laying the foundation for the implementation of in-memory computing microprocessors. Patent CN113010213B discloses a reduced instruction set in-memory computing neural network coprocessor based on a resistive-variable memristor; however, the instruction set design in this scheme is incompatible with the existing open-source RISC-V architecture, resulting in more complex instruction design and an inability to adapt to code compilation and data management processes with varying data computation precision in general scenarios. Moreover, this scheme offers coarser granularity control over in-memory computing units and a smaller compilation space. Therefore, based on the existing RISC-V open-source instruction set architecture, implementing multi-granularity in-memory computing instruction extensions that operate on different array sizes, and reducing the design difficulty of in-memory computing microcontrollers, is the only way to promote the application of in-memory computing technology.

[0004] The paper "Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing" discloses a memristor-based in-memory computing microcontroller and its instruction set. This in-memory computing microcontroller is abstracted into three levels: Tile, Processing Unit (PU), and Array. The Tile level integrates the system's control, interaction, and functional modules, while the Processing Unit only includes the array, shift register module, and registers. Based on this architecture, a separate instruction set was designed for the operation of the Processing Unit, including forward data read instructions, shift and column increment instructions at the Processing Unit level, and array programming instructions. However, in this architecture, because the controller only exists at the Tile level, different Processing Units cannot run instructions independently, reducing computational parallelism. Furthermore, the instruction design in this paper, such as the shift and increment instructions, does not conform to the basic instruction specifications of RISC-V, which will lead to more complex controller design. Moreover, the instruction design in this work is not perfect, lacking instructions corresponding to the reverse data operation mode in in-memory computing. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application aims to provide a memory computing microcontroller and data processing method, which solves the compatibility problem between existing in-memory computing architectures and RISC-V, and establishes general multi-granularity in-memory computing instructions on this basis to improve the in-memory computing system's ability to meet diverse computing needs.

[0006] To achieve the above objectives, in a first aspect, this application provides a memory computing microcontroller, which has a three-layer architecture of Tile-processing unit-array; The Tile includes multiple processing units and a storage and management unit, wherein each processing unit operates independently of the others; the storage and management unit is shared by all processing units, interacts with off-chip storage and external control, and is used to distribute data to or collect data from the processing units. Each processing unit is configured with a separate circuit and functional module for independently implementing instruction decoding and execution; each processing unit contains an array module, which includes multiple memory arrays, and the multiple memory arrays are uniformly addressed; The storage array is used to perform stored vector-matrix multiplication.

[0007] Preferably, the processing unit includes a control module, an instruction cache module, a vector / scalar register, an input / output conversion circuit, a shift-accumulator circuit, a data storage module, and an array module; wherein, The control module is connected to the instruction cache module and the vector / scalar register, and is used to independently implement the instruction execution and data calculation process of this unit. The calculation results are fed back to the storage and management unit through the data storage module. The instruction cache module is connected to the storage and management unit and the control module, and is used to store the running instructions converted from the user's code. The vector / scalar register is connected to the data storage module, input / output conversion circuit, and shift-accumulator circuit to support the data retrieval process during instruction execution. The vector register is used to perform operations on vector data, and the scalar register is used to perform operations on scalar data. The two registers are independently addressed and independently called. The input / output conversion circuit is connected to the array module and the vector / scalar register module, and is used to enable the interaction between the numerical data in the processing unit and the analog data required or obtained for array operation. The input conversion circuit is used to convert the input data from the vector / scalar register module into the corresponding voltage signal through a signal conversion device and apply it directly to the array module. The output conversion circuit is used to directly convert the analog voltage or analog current calculated by the array into a digital signal to realize the signal interaction process. The shift-accumulator circuit is connected to the vector / scalar register module and is used to implement the necessary shift and accumulation functions in in-memory computation. The data storage module is connected to the vector / scalar register module and the storage and management unit, and is used for temporary storage of non-register-level data to realize the data interaction process with Tile. The array module is connected to the input / output conversion circuit and is used to store matrix data defined by external control, while also cooperating with in-memory calculation instructions to perform specific in-memory calculation operations.

[0008] It should be noted that this application optimizes the functional circuit modules of the processing unit. Specifically, it is specially customized according to the actual computing needs of in-memory computing hardware, retaining only the functional circuits necessary for the implementation of in-memory computing, such as shift and accumulate circuits. Each processing unit contains all the necessary components for independent addressing, encoding, and execution of instructions, including control, cache, registers, and functional units, and therefore can operate independently. The array module is regarded as a special functional module with storage and computing capabilities.

[0009] Preferably, the hardware addressing scheme of the vector / scalar register is designed to be the same as that of the RISC-V architecture, and is compatible with the existing RISC-V basic instruction set architecture.

[0010] It should be noted that the hardware address design of the registers is the same as that of the RISC-V architecture, ensuring that the architecture is compatible with the RISC-V instruction set or its subsets, thus improving system compatibility.

[0011] Preferably, the input and output of the array are connected to the bus through a bidirectional gating circuit, and the array can realize bidirectional data path according to the control signal of the microcontroller.

[0012] Preferably, the instruction set of the in-memory computing microcontroller includes eight read instructions and two programming instructions, and the length and encoding rules of these ten instructions are the same as those of the RISC-V instruction set; The read instruction is used to support the control module in applying the data in the vector / scalar register to the input conversion circuit and in retrieving the result from the output conversion circuit and writing it back to the vector / scalar register. The programming instructions are used to support the control module in applying the data in the vector / scalar register to the input conversion circuit and writing it into the array module.

[0013] It should be noted that the length and encoding rules of the two types of ten instructions added in this application are the same as those of the RISC-V instruction set, and are compatible with the existing RISC-V vector instruction set. The atomic-level in-memory computation operation instruction set constructed in this application can serve as a supplement to the RISC-V vector instruction set, filling the gap in the implementation of RISC-V instructions in in-memory computing. The array addressing space defined by this instruction set is simpler, and there is no need to address again in the processing unit. On the one hand, this reduces the complexity of addressing in the processing unit, and on the other hand, it increases the addressing space of the array.

[0014] Preferably, the read instruction adopts a register-to-register operation mode, and its basic instruction format is "mnemonic result register address register input register". The mnemonic is used to determine the operation type during instruction decoding. The operation type includes forward point read, forward row read, forward column read, forward matrix read, reverse point read, reverse row read, reverse column read, and reverse matrix read. The result register is used to store the result of this calculation, the address register is used to decode and determine the memory location of this operation, and the input register is used to provide the data required for this operation. Among them, single-point operation refers to operating only a device at a fixed point in the array, including forward point read and reverse point read; single-row operation refers to operating a device in a row in the array, including forward row read and reverse row read; single-column operation refers to operating a device in a column in the array, including forward column read and reverse column read; array operation refers to operating a device in a region, including forward matrix read and reverse matrix read.

[0015] It should be noted that this application focuses only on the core instruction implementation of in-memory vector matrix multiplication, reducing unnecessary logic instructions, such as shift-accumulate instructions. This application can directly utilize the original shift-accumulate instructions in RISC-V by configuring a separate control module and registers in the processing unit. This application adds array reverse read operation instructions, resulting in a more complete instruction set design capable of handling more complex scenarios in in-memory computing applications. Based on this instruction architecture, it is possible to implement operation modes of memristor in-memory computing hardware with arbitrary precision and multiple control granularities. This application provides a bidirectional data operation path. Since in-memory computing applications, such as neural network accelerators, require transposing stored matrix operations during the gradient backpropagation process of weights, this operation can be achieved through the reverse data path, further ensuring the completeness of the microcontroller design.

[0016] Preferably, the programming instruction is determined by the memory access instruction format, and its basic operation format is "mnemonic address register input register input immediate value". The mnemonic is used to determine the operation type when decoding the instruction. The operation type includes point programming and column programming. The address register is used to decode the memory location of this operation. The input register is used to select the device location in the operation. The input immediate value is used to define the operation pulse voltage amplitude of this programming operation.

[0017] To achieve the above objectives, in a second aspect, this application provides a data processing method applied to the in-memory computing microcontroller described in the first aspect, the method comprising: The control module sequentially fetches execution instructions from the instruction cache module, generates corresponding vector / scalar registers based on the execution instructions, decodes them into corresponding control signals, and applies them to the data storage module, shift accumulator circuit, and array module. The control signals are used to implement memory access operations or computation operations, wherein... The memory access operation includes retrieving data from the storage and management unit and storing it in the data storage module and instruction cache module, or loading the corresponding vector / scalar data from the data storage module into the vector / scalar register according to the control signal, or storing data from the vector / scalar register into the data storage module; The computational operations include in-memory computation instruction operations and shift and shift accumulation operations under standard RISC-V instructions. The in-memory computation instructions include array point read, column read, row read, matrix read and their reverse operations, as well as point programming and column programming instruction operations. When the shift accumulation instruction is executed, the data stored in the vector / scalar register controlled by the instruction is received, and the calculation result is written back to the vector / scalar register.

[0018] It should be noted that the above method clarifies the logic of instruction control and decoding.

[0019] To achieve the above objectives, in a third aspect, this application provides a computer device in which the in-memory computing microcontroller described in the first aspect is deployed.

[0020] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0021] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: This application proposes a memory-computing microcontroller, which also has three levels: Tile-processing unit-array, but optimizes the Tile and processing unit. (1) This application configures a separate circuit and functional module for each processing unit, instead of defining a control module at the Tile level, thereby ensuring that each processing unit can independently perform instruction addressing, decoding and execution, increasing the parallelism in the operation process, and is not constrained by the Tile-level instruction execution, thus increasing the flexibility of the system. (2) This application defines the register module at the processing unit level and clearly divides the system's storage level, instead of having register and memory modules at both the Tile and PU levels, thereby simplifying the design of storage module management, so that the operation process of registers is only implemented in the processing unit during the operation process. At the same time, the data transmission chain is clearly defined as external memory-storage and management unit-data storage module-vector / scalar register module, making the design of the microcontroller more reasonable. Under this structure, the Tile-level hardware system can be more easily expanded. At this time, adding a processing unit only requires handling the data interaction between the storage and management unit and the processing unit, without modifying the hardware circuit structure. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a memory computing microcontroller structure provided in an embodiment of this application.

[0023] Figure 2A This is a schematic diagram of a resistive random access memory array used for forward vector-matrix multiplication, provided in an embodiment of this application.

[0024] Figure 2B This is a schematic diagram of vector matrix multiplication for reverse read operation of a resistive random access memory array provided in an embodiment of this application.

[0025] Figure 3A The basic structure of register-to-register operation instructions provided in the embodiments of this application.

[0026] Figure 3B The basic structure of memory access operation instructions provided in the embodiments of this application.

[0027] Figure 4 The basic structure of the addressing address of the operation unit in the in-memory computing unit provided in the embodiments of this application.

[0028] Figure 5 This is a basic operation module for a decoding circuit based on an operation address, provided in the embodiments of this application.

[0029] Figure 6 This is a schematic diagram of the basic structure of the controller implementing the memory operation instruction decoding process in the embodiments of this application.

[0030] Figure 7 The binary encoding scheme for the in-memory computing instruction set based on RISC-V provided in the embodiments of this application. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0032] The embodiments of this application are described below with reference to the accompanying drawings.

[0033] like Figure 1 As shown, this application provides a memory computing microcontroller, which has a three-layer architecture of Tile-processing unit-array; The Tile includes multiple processing units and a storage and management unit, wherein each processing unit operates independently of the others; the storage and management unit is shared by all processing units, interacts with off-chip storage and external control, and is used to distribute data to or collect data from the processing units. Each processing unit is configured with a separate circuit and functional module for independently implementing instruction decoding and execution; each processing unit contains an array module, which includes multiple memory arrays, and the multiple memory arrays are uniformly addressed; The storage array is used to perform stored vector-matrix multiplication.

[0034] The processing unit is the core functional module that includes an in-memory computing array. Its main functional modules include a control module, an instruction cache module, an input / output conversion circuit, a vector / scalar register, a shift and accumulate circuit, a data storage module, and an array module.

[0035] The control module, connected to the instruction cache module and vector / scalar registers, is used to implement the execution process of all operations in the processing unit. The control module sequentially obtains execution instructions from the instruction cache module, and based on these instructions, controls the corresponding vector / scalar registers to decode them into corresponding control signals, which are then applied to functional units such as the data storage module, shift / accumulate module, and array model. The control module can not only implement the instruction set for in-memory vector computation, but also execute instructions necessary for microcontroller operation, such as data loading, storage, shifting, accumulation, signal judgment, and jumps. These instructions are consistent with the existing open-source instruction architecture of RISC-V.

[0036] The instruction cache module is connected to the storage and management unit and the control module. The instruction cache module stores specific execution instructions derived from the user's code, including various types such as data loading, storage, and computation. The stored instructions in the instruction cache module are directly obtained through the storage and management unit and used by the control module for execution.

[0037] The vector / scalar registers are connected to the data storage module, input / output conversion circuit, shift / accumulate circuit, etc., to support the data retrieval process during instruction execution. The vector register is used to operate on vector data, and the scalar register is used to operate on scalar data; they are independently addressed and accessed. Under the RISC-V instruction architecture, both the element length and vector length of the vector register are programmable and consistent with the definitions in the RISC-V vector instruction extensions. The vector / scalar registers interact with the data storage module by executing load and store instructions. For computation instructions, the vector / scalar registers receive control signals from the control module, apply the stored data to the input conversion circuit, shift / accumulate circuit, etc., and receive the results written back from the output conversion circuit and shift / accumulate circuit.

[0038] The input / output conversion circuit, connected to the array module and the vector / scalar register module, is used to enable the interaction between the numerical data in the processing unit and the analog data required or obtained for array operations. Specifically, the input conversion circuit converts the input data from the vector / scalar register module into a corresponding voltage signal using a signal conversion device (represented by an analog-to-digital converter) and applies it directly to the array module. The output conversion circuit directly converts the analog voltage or analog current calculated by the array into a digital signal, enabling signal interaction with registers, memory, and other units.

[0039] The shift-accumulator circuit, connected to the vector / scalar register module, is used to implement the necessary shift and accumulation functions in in-memory computation and is a key module in data operation. When a shift-accumulator instruction is executed, it receives the data stored in the vector / scalar register controlled by the instruction and writes the calculation result back to the vector / scalar register.

[0040] The data storage module, connected to the vector / scalar register module and higher-level storage and management units, is used for temporary storage of non-register-level data. This module serves as a data intermediary for the storage and management unit, enabling data distribution and storage reclamation with the vector / scalar register module.

[0041] The array module, connected to the input / output conversion circuit, is used to store matrix data defined by external control and to perform specific in-memory calculation operations in conjunction with in-memory calculation instructions. The storage medium of the array module is a type of medium that uses resistive switching memory devices for data storage, including at least memristors, phase-change memory, magnetic memory, and ferroelectric memory. Each array in the array module can receive data signals from register units controlled by arithmetic instructions from both row and column directions. Based on the control signals provided by the control module, the bidirectional selection process and addressing process of the array are realized. Input and output data involved in the calculation process interact through the data bus and registers. The output conversion circuit is multiplexed in each array by introducing a sample-and-hold (S&H) circuit at the output terminal.

[0042] The processing unit interacts with Tile through a data storage module. Specifically, the data storage module receives and stores the computational data from the processing unit. The control module of the processing unit independently executes instructions and performs data calculations. The calculation results are fed back to the storage and management unit through the data storage module to achieve the integration of massive amounts of data.

[0043] The microcontroller instruction extension proposed in this application mainly involves adding data reading and data programming instructions to the array module. Specifically, the array module includes two data reading methods, such as... Figure 2A The demonstrated positive operating mode and Figure 2B The reverse operation mode is shown. These two modes operate on the array itself and its transpose, respectively. For the forward operation, the output current is the product of the input voltage and the corresponding column conductance, and this process satisfies Ohm's law and Kirchhoff's laws, i.e.

[0044] The reverse array readout process is similar, but because the direction of signal application changes, it actually calculates the transpose of the matrix. (Refer to...) Figure 2BMatrix programming does not distinguish between forward and reverse operations.

[0045] Considering the granularity of operations on devices in the array, data operations can be divided into single-point operations, single-row operations, single-column operations, and matrix operations. A single-point operation refers to operating only on a device at a fixed point in the array; single-row and single-column operations refer to operating on devices in a specific row or column of the array; and array operations refer to operating on devices across the entire matrix region. In array operations, the number of rows or columns that can be operated on at a time is fixed, which determines the size of the operational space for each of the four operation modes. The operational space (number of rows × number of columns) is a hyperparameter defined at the beginning of the system design. This space may differ from the actual space of the array, i.e., the number of array rows and columns. When defined, the number of rows (or columns) to be operated on is less than the number of array rows (or columns).

[0046] Based on the above operating mode Figure 3A and Figure 3B This paper demonstrates two basic instruction definition forms for register-to-register and memory access in a 32-bit computer under the RISC-V instruction framework. The opcode defines the basic instruction operation type, while fun3 and func7 define different implementation instructions for that type. rs1 and rs2 represent the addresses of two input registers, and rd represents the address of the output register. imm[4:0] and imm[11:5] together constitute a 12-bit immediate operand. The design and implementation of stored-store instructions are based on these two instruction forms.

[0047] The basic form of the in-memory computing instructions is defined as shown in Table 1. It mainly includes eight read instructions and two programming instructions. The read instructions support the control module in applying data from the vector / scalar register to the input conversion circuit and retrieving the result from the output conversion circuit back into the register. The programming instructions support the control module in applying data from the vector / scalar register to the input conversion circuit and writing it into the array module.

[0048] Table 1

[0049] The read instruction operates on a register-to-register basis, with a basic instruction format of "mnemonic result register address register input register". The mnemonic determines the operation type during instruction decoding, the result register stores the result of the current calculation, the address register decodes and determines the memory location for the current operation, and the input register provides the data needed for the current calculation. The result register, input register, and input register all refer to register indices within the processing unit; the actual data is stored in the registers. The address register is a scalar register, while the result register and input register can be either scalar registers or vector registers. The read instruction includes four read instruction formats: point read, row read, column read, and matrix read, as well as corresponding reverse read instruction formats. For example, the point read instruction in the first row of Table 1 is "vmmp rd, addr, rs", which means locating the corresponding point on the array based on the address defined by addr, then applying the scalar data stored in rs to the array through an input conversion circuit, and storing the array's calculation result in the scalar register rd through an output conversion circuit.

[0050] Programming instructions are determined by the memory access instruction format. The basic operation format is "mnemonic address register input register input immediate value". The mnemonic determines the operation type during instruction decoding, the address register decodes the memory location for this operation, the input register selects the device location in the operation, and the input immediate value defines the amplitude of the programming operation pulse voltage. During programming, the voltage pulse width is fixed. Programming instructions include two operation modes: point programming and column programming. In point programming, the input register is disabled and does not control the programming process. In column programming, the input register is a vector register used to control which devices in the column controlled by the address register need to be applied the programming operation voltage corresponding to the instruction. For example, the point programming instruction in row 5 of Table 1 is "progpaddr, -, #op_V", which means applying the voltage pulse corresponding to op_V to the device corresponding to the array point determined by addr, thus implementing the point programming process for the device.

[0051] Figure 4This demonstrates the encoding method of the address register data. In the 32-bit register, the lower 11 bits (bits 0-10) are used to control the column address in the array, bits 11-21 are used to control the row address in the array, and the remaining bits (bits 22-31) are used for array addressing. The highest bit of the column or row address is used to determine whether the array address is selected entirely or decoded to select a single column or row. For example, a full-selection mode can be defined with the highest bit set to "0". For instance, for "0000000001 00000000001 00000000010", the higher 10 bits (0000000001) determine the position of the array, i.e., the first array; the middle 11 bits (00000000001) represent the first row subspace in full-selection mode; and the last 11 bits (00000000010) represent the second column subspace in full-selection mode. The subspace refers to dividing the array into different operational regions based on the matrix size of each operation. For example, for an array with (rows, columns) = (512, 1024), the size of each operation is (64, 64), and the corresponding number of row and column subspaces is (8, 16). For "0000000001 10000000001 10000000010", it corresponds to the device in the first row and second column of the first array. This corresponds to different operation instructions.

[0052] Figure 5 The circuit block diagram for address register decoding is shown. IN 1-IN N represent the input data corresponding to the in-memory operation instructions. When the most significant bit of addr is 1, it is in single-select mode, selecting only one row (or column). The full-select driver is not activated; only the multiplexer (MUX) selection unit corresponding to one address is activated by enabling the decoder, and the corresponding input signal is applied to the array module. When the most significant bit is 0, it is in full-select mode. The decoder is not enabled, the full-select driver is activated, and all multiplexers (MUX) are selected through the output circuit, and all signals are applied to the corresponding operation positions.

[0053] Figure 6 The hardware module design required for decoding the aforementioned instructions is demonstrated. This includes operation decoding, immediate value decoding, register decoding, address decoding, operation voltage control, and word line and bit line gating modules. Operation decoding identifies the operation instruction mode based on the corresponding instruction code and determines the most basic decoding method. Immediate value decoding obtains the immediate value of the operation based on the binary code in the instruction, used in the device programming process. Register decoding decodes the corresponding register address based on the result of operation decoding, used to implement the calculation process. Address decoding... Figure 4The address encoding yields the memory's operating space. Operating voltage control determines the operating voltage based on the operation instruction, which further determines the instruction's operation mode on the array. For read operations, the read voltage is fixed; for programming operations, the operating voltage is determined by immediate values. The word line and bit line gating module connects the corresponding registers and interface circuits to the corresponding functional units according to the operation instruction.

[0054] Figure 7 This section demonstrates an example of an instruction set implemented based on the aforementioned instruction set definition. Here, opcode 0001000 is defined to represent a class of basic instructions used for store-and-click operations. Read and write instructions are distinguished by func3, with all read instructions having func3 as 000. Different read instructions are distinguished by func7, as shown in the figure. The func3 values ​​for dot programming and column programming are 001 and 100, respectively.

[0055] Based on the above, this application proposes a data processing method for a RISC-V compatible in-memory computing microcontroller, comprising: The control module sequentially fetches instructions from the instruction cache module, decodes them, and generates control signals based on the instructions; The control signals are used to implement memory access operations and computation operations.

[0056] The memory access operation includes retrieving data from the storage and management unit and storing it in the data storage module and the instruction cache module.

[0057] The memory access operation also includes loading the corresponding vector / scalar data from the data storage module into the vector / scalar register according to the control signal, or storing data from the vector / scalar register into the data storage module.

[0058] The computational operations include in-memory computation instructions and shift and accumulation operations under standard RISC-V instructions. The in-memory computation instructions include array point reads, column reads, row reads, matrix reads and their reverse operations, as well as point programming and column programming instructions.

[0059] Before executing the array read command, ensure that the array has been initialized and that valid data has been stored within it. Array initialization is achieved through point programming or column programming instructions. For example, for a (512, 1024) array, initialization via point programming requires applying point programming instructions to each of the 512 × 1024 devices individually to achieve the desired device state.

[0060] When the array performs a read operation, the control module applies a control signal to the register, decodes the corresponding register and applies voltage signal data to the input conversion circuit, and the array obtains the output current according to Ohm's law and Kirchhoff's law. The output conversion circuit converts the current into a digital signal and stores it in the register.

[0061] The read operation is performed on different granularities of the array according to the calculation instructions, so as to achieve a more flexible operation mode.

[0062] Furthermore, combining shift and accumulation modules allows for vector-matrix multiplication operations of varying precision. Specifically, during vector-matrix multiplication, the input data is loaded into the input buffer module in the form of a binary sequence. For example, corresponding to four fixed inputs, the input data 7 = 0111. （2） At this time, the four inputs are 1, 1, 1, and 0 respectively. The array address remains unchanged, so a vector-matrix multiplication operation requires four read instructions. The result of each operation is shifted and accumulated according to the input bias to obtain the final calculation result.

[0063] Furthermore, the computational precision of the input can be controlled by adjusting the number of inputs. For example, four inputs correspond to 4 bits of input precision, while eight inputs correspond to 8 bits of input precision. Increasing the number of inputs requires more computational instructions, which in turn increases time and power consumption.

[0064] Furthermore, for array-stored matrices, different arrays can be used to store different bits of a binary sequence. For example, for quantized data 7 = 0111 （2） When each array stores only 1 bit of data, 0, 1, 1, and 1 can be stored on four arrays respectively. For the same input data, when calculating on different arrays, the data needs to be shifted before accumulation. This scheme is similar to the input splitting scheme.

[0065] Furthermore, based on the above input and matrix splitting scheme, it is possible to realize the calculation process of vector-matrix multiplication with arbitrary precision.

[0066] In this application, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0067] In this application, the term "electrical connection" can refer to a direct circuit connection or a signal transmission via a communication protocol.

[0068] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0069] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0070] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0071] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0072] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. "Fixed connection" refers to a connection where the relative positional relationship remains unchanged after connection. "Rotary connection" refers to a connection where the components can rotate relative to each other after connection. "Sliding connection" refers to a connection where the components can slide relative to each other after connection. The directional terms mentioned in the embodiments of this application, such as "top," "bottom," "inner," "outer," "left," and "right," are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0073] Furthermore, the mathematical concepts mentioned in the embodiments of this application, such as symmetry, equality, parallelism, and perpendicularity, are limitations specific to the current technological level, rather than absolute and strict mathematical definitions. Slight deviations are permissible; approximations of symmetry, equality, parallelism, and perpendicularity are all acceptable. For example, "A and B are parallel" means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. "A and B are perpendicular" means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0074] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An in-memory microcontroller, comprising: The in-memory computing microcontroller has a three-layer architecture: Tile-processing unit-array. The Tile includes multiple processing units and a storage and management unit, wherein each processing unit operates independently of the others; the storage and management unit is shared by all processing units, interacts with off-chip storage and external control, and is used to distribute data to or collect data from the processing units. Each processing unit is configured with a separate circuit and functional module for independently implementing instruction decoding and execution; each processing unit contains an array module, which includes multiple memory arrays, and the multiple memory arrays are uniformly addressed; The storage array is used to implement stored vector-matrix multiplication; The processing unit includes a control module, an instruction cache module, a vector / scalar register, an input / output conversion circuit, a shift-accumulator circuit, a data storage module, and an array module; wherein... The control module is connected to the instruction cache module and the vector / scalar register, and is used to independently implement the instruction execution and data calculation process of this unit. The calculation results are fed back to the storage and management unit through the data storage module. The instruction cache module is connected to the storage and management unit and the control module, and is used to store the running instructions converted from the user's code. The vector / scalar register is connected to the data storage module, input / output conversion circuit, and shift-accumulator circuit to support the data retrieval process during instruction execution. The vector register is used to perform operations on vector data, and the scalar register is used to perform operations on scalar data. The two registers are independently addressed and independently called. The input / output conversion circuit is connected to the array module and the vector / scalar register module, and is used to enable the interaction between the numerical data in the processing unit and the analog data required or obtained for array operation. The input conversion circuit is used to convert the input data from the vector / scalar register module into the corresponding voltage signal through a signal conversion device and apply it directly to the array module. The output conversion circuit is used to directly convert the analog voltage or analog current calculated by the array into a digital signal to realize the signal interaction process. The shift-accumulator circuit is connected to the vector / scalar register module and is used to implement the necessary shift and accumulation functions in in-memory computation. The data storage module is connected to the vector / scalar register module and the storage and management unit, and is used for temporary storage of non-register-level data to realize the data interaction process with Tile. The array module is connected to the input / output conversion circuit and is used to store matrix data defined by external control, while also cooperating with in-memory calculation instructions to realize specific in-memory calculation operations. The hardware addressing scheme of the vector / scalar register is designed the same as that of the RISC-V architecture, and is compatible with the existing RISC-V basic instruction set architecture.

2. The in-memory computing microcontroller as described in claim 1, characterized in that, The array's input and output are connected to the bus via a bidirectional gating circuit, allowing the array to achieve bidirectional data paths based on the microcontroller's control signals.

3. The in-memory computing microcontroller as described in claim 1, characterized in that, The instruction set of the in-memory computing microcontroller includes eight read instructions and two programming instructions. The length and encoding rules of these ten instructions are the same as those of the RISC-V instruction set. The read instruction is used to support the control module in applying the data in the vector / scalar register to the input conversion circuit and in retrieving the result from the output conversion circuit and writing it back to the vector / scalar register. The programming instructions are used to support the control module in applying the data in the vector / scalar register to the input conversion circuit and writing it into the array module.

4. The in-memory computing microcontroller as described in claim 3, characterized in that, The read instruction employs a register-to-register operation, with the basic instruction format being "mnemonic result register address register input register". The mnemonic determines the operation type during instruction decoding, including forward point read, forward row read, forward column read, forward matrix read, reverse point read, reverse row read, reverse column read, and reverse matrix read. The result register stores the result of the current calculation, the address register decodes and determines the memory location for the current operation, and the input register provides the data required for the current operation. A single-point operation refers to operating only a device at a fixed point in the array, including forward point read and reverse point read; a single-row operation refers to operating devices in a row of the array, including forward row read and reverse row read; a single-column operation refers to operating devices in a column of the array, including forward column read and reverse column read; and an array operation refers to operating devices in an entire region, including forward matrix read and reverse matrix read.

5. The in-memory computing microcontroller as described in claim 3, characterized in that, The programming instructions are determined by the memory access instruction format. The basic operation format is "mnemonic address register input register input immediate value". The mnemonic is used to determine the operation type when decoding the instruction. The operation type includes point programming and column programming. The address register is used to decode the memory location of this operation. The input register is used to select the device location in the operation. The input immediate value is used to define the operation pulse voltage amplitude of this programming operation.

6. A data processing method, characterized in that, The method, applied to the in-memory computing microcontroller according to any one of claims 1 to 5, comprises: The control module sequentially fetches execution instructions from the instruction cache module, and controls the corresponding vector / scalar registers to decode the execution instructions into corresponding control signals, which are then applied to the data storage module, shift-accumulator circuit, and array module. The control signals are used to implement memory access operations or computation operations, wherein... The memory access operation includes retrieving data from the storage and management unit and storing it in the data storage module and instruction cache module, or loading the corresponding vector / scalar data from the data storage module into the vector / scalar register according to the control signal, or storing data from the vector / scalar register into the data storage module; The computational operations include in-memory computation instruction operations and shift and shift accumulation operations under standard RISC-V instructions. The in-memory computation instructions include array point read, column read, row read, matrix read and their reverse operations, as well as point programming and column programming instruction operations. When the shift accumulation instruction is executed, the data stored in the vector / scalar register controlled by the instruction is received, and the calculation result is written back to the vector / scalar register.

7. A computer device, characterized in that, The computer device is equipped with a memory-based microcontroller as described in any one of claims 1 to 5.

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