An integrated circuit simulation design method, platform and system

Abstract

The present application relates to the field of integrated circuit simulation design, in particular to an integrated circuit simulation design method, platform and system. The method first obtains the degradation effectiveness of each transistor type according to the distribution of the sensitivity of each stress parameter of each transistor of each transistor type under all aging parameters under any effect, obtains the reference degradation amount of the current simulation step according to the degradation amount of each transistor of each transistor type of the integrated circuit in the current simulation step and the degradation effectiveness of each transistor type, determines the length of the next simulation step, performs iterative transient simulation on the integrated circuit under each effect based on the length of the next simulation step, obtains the stability index of the integrated circuit under the current aging test, and further evaluates the stability of the integrated circuit under the current aging test. The present application can accurately evaluate the stability performance of the aging test of the integrated circuit and optimize the design of the integrated circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit simulation design, and specifically to an integrated circuit simulation design method, platform, and system. Background Technology

[0002] With the rapid development of information technology and the continuous advancement of the trends of intelligentization, miniaturization, and high performance in electronic products, integrated circuits, as the core of electronic systems, are facing increasingly complex designs and higher integration levels. This places stringent demands on design accuracy and verification efficiency. Against this backdrop, electronic circuit simulation technology, as an indispensable key technology in the integrated circuit design process, establishes accurate mathematical models to simulate the operating state and physical behavior of actual circuits in a virtual environment. This enables precise analysis and optimization of key circuit parameters (such as timing, power consumption, and signal integrity) without relying on physical prototypes, significantly improving the accuracy, reliability, and development efficiency of the design.

[0003] In related technologies, the aging response of transistors in integrated circuits is typically modeled using simulation, and the circuit is simulated and analyzed using integrated circuit simulation tools. This maps the aging of the device to the degradation of the entire integrated circuit, allowing designers to make optimizations by analyzing the performance changes of the integrated circuit. However, in the process of simulating and modeling integrated circuits, existing methods usually perform simulation processing within a pre-set fixed step size, and the aging model usually only considers the hot carrier injection (HCI) effect or the bias temperature instability (BTI) effect separately. In the actual aging process of integrated circuits, the HCI and BTI effects of transistors occur simultaneously and influence each other, making it impossible for existing methods to accurately evaluate the stability performance of integrated circuit aging tests. Summary of the Invention

[0004] To address the technical problem that existing methods cannot accurately assess the stability performance of integrated circuit aging tests, the present invention aims to provide an integrated circuit simulation design method, platform, and system. The specific technical solution adopted is as follows:

[0005] This invention proposes an integrated circuit simulation design method, the method comprising:

[0006] Obtain the degradation of each transistor of each transistor type under two different effects at the current simulation step, and the sensitivity of each transistor to each stress parameter under each aging parameter.

[0007] Under any effect, taking any transistor type as the target transistor type, the circuit influence degree of each transistor is obtained based on the distribution of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters; the degradation effectiveness of the target transistor type is obtained based on the distribution of the circuit influence degree of all transistors of the target transistor type; the reference degradation amount of the current simulation step is obtained based on the degradation amount of each transistor of each transistor type in the current simulation step and the degradation effectiveness of each transistor type; the length of the current simulation step is adjusted based on the difference between the reference degradation amount between the current simulation step and the previous simulation step to obtain the length of the next simulation step.

[0008] Based on the length of the next simulation step, iterative transient simulations are performed on the integrated circuit under each effect to obtain the performance stability and coupling performance stability of the integrated circuit under each effect. Based on the difference in the coupling performance stability of the integrated circuit between the current aging test and the historical aging test, as well as the performance stability and coupling performance stability of the integrated circuit under each effect under the current aging test, the stability index of the integrated circuit under the current aging test is obtained.

[0009] Based on the aforementioned stability metrics, the stability of the integrated circuit under the current aging test is evaluated.

[0010] Furthermore, obtaining the circuit influence of each transistor includes:

[0011] The average value of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters is taken as the overall sensitivity of each stress parameter of each transistor of the target transistor type.

[0012] After analyzing the dispersion of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters and performing negative correlation mapping, the consistency of the sensitivity of each stress parameter of each transistor of the target transistor type is obtained.

[0013] By combining the overall sensitivity and the degree of consistency of the sensitivity, an initial influence coefficient for each stress parameter of each transistor of the target transistor type is obtained;

[0014] The average value of the initial influence coefficients of all stress parameters for each transistor of the target transistor type is taken as the circuit influence degree of each transistor of the target transistor type.

[0015] Furthermore, the degradation effectiveness of obtaining the target transistor type includes:

[0016] The average value of the circuit influence of all transistors of the target transistor type is taken as the overall circuit influence of the target transistor type.

[0017] The dispersion of the circuit influence of all transistors of the target transistor type is analyzed to obtain the dispersion of the circuit influence of the target transistor type.

[0018] After synthesizing and normalizing the overall circuit influence degree and the circuit influence dispersion, the degradation effectiveness of the target transistor type is obtained, wherein the sum of the degradation effectiveness of all transistor types is equal to the value 1.

[0019] Furthermore, the reference degradation amount for obtaining the current simulation step size includes:

[0020] The average of the degradation of all transistors of each transistor type in the integrated circuit at the current simulation step is taken as the overall degradation of the integrated circuit for each transistor type at the current simulation step.

[0021] By utilizing the degradation effectiveness of each transistor type, the overall degradation of the integrated circuit at the current simulation step is weighted and summed to obtain the reference degradation at the current simulation step.

[0022] Furthermore, the length for obtaining the next simulation step includes:

[0023] The difference between the reference degradation amount of the previous simulation step and the reference degradation amount of the current simulation step is normalized to obtain the step size adjustment weight of the next simulation step.

[0024] The product of the step size adjustment weight for the next simulation step and the length of the current simulation step is used as the length adjustment amount for the next simulation step.

[0025] The sum of the current simulation step length and the length adjustment amount of the next simulation step is used as the length of the next simulation step.

[0026] Furthermore, obtaining the performance stability of the integrated circuit under each effect and the coupling performance stability of the integrated circuit includes:

[0027] The length of the next simulation step is used as the length of the new current simulation step. Within the new current simulation step, transient simulations are performed on the integrated circuit under each effect until the cumulative length of all simulation steps equals the preset stress duration. This allows us to obtain the performance stability of the integrated circuit under each effect and the coupling performance stability of the integrated circuit.

[0028] Furthermore, the stability indicators of the integrated circuit under the current aging test include:

[0029] The average value of the coupling performance stability of all historically tested integrated circuits is used as the reference coupling performance stability of the integrated circuit currently undergoing aging tests.

[0030] The difference between the coupling performance stability of the integrated circuit under the current aging test and the reference coupling performance stability is normalized by negative correlation to obtain the reference weight of the coupling performance stability of the current aging test.

[0031] Based on the calculation formula for the stability index, the stability index of the integrated circuit under the current aging test is obtained. The calculation formula for the stability index is as follows:

[0032]

[0033] in, This indicates the stability of the integrated circuit under the current aging test. The reference weights represent the stability of the coupling performance in the current aging test; This indicates the stability of the coupling performance of the integrated circuit currently undergoing aging tests; This indicates the performance stability of the integrated circuit under the first effect; This indicates the performance stability of the integrated circuit under the second effect; This represents the hyperbolic tangent function, used for normalization.

[0034] Furthermore, the evaluation of the stability of the integrated circuit under the current aging test includes:

[0035] If the stability index of the integrated circuit under the current aging test is greater than the preset stability threshold, then the stability performance of the integrated circuit in the current aging test meets the standard; otherwise, the stability performance of the integrated circuit in the current aging test does not meet the standard.

[0036] This invention also proposes an integrated circuit simulation design platform, the platform comprising:

[0037] The data acquisition module is used to acquire the degradation of each transistor of each transistor type under two different effects at the current simulation step, and the sensitivity of each transistor to each stress parameter under each aging parameter.

[0038] The step size adjustment module is used to, under any effect, take any transistor type as the target transistor type, obtain the circuit influence degree of each transistor based on the distribution of sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters; obtain the degradation effectiveness of the target transistor type based on the distribution of the circuit influence degree of all transistors of the target transistor type; obtain the reference degradation amount of the current simulation step size based on the degradation amount of each transistor of each transistor type of the integrated circuit at the current simulation step size and the degradation effectiveness of each transistor type; and adjust the length of the current simulation step size based on the difference between the reference degradation amount and the previous simulation step size to obtain the length of the next simulation step size.

[0039] The stability analysis module is used to perform iterative transient simulations of the integrated circuit under each effect based on the length of the next simulation step, to obtain the performance stability and coupling performance stability of the integrated circuit under each effect; based on the difference in the coupling performance stability of the integrated circuit between the current aging test and the historical aging test, and the performance stability and coupling performance stability of the integrated circuit under each effect under the current aging test, the stability index of the integrated circuit under the current aging test is obtained.

[0040] An evaluation module is used to evaluate the stability of the integrated circuit under the current aging test based on the stability index.

[0041] The present invention also proposes an integrated circuit simulation design system, the system comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement any of the steps of an integrated circuit simulation design method.

[0042] The present invention has the following beneficial effects:

[0043] This invention analyzes the impact of each stress parameter of each transistor on the integrated circuit to obtain the validity of the degradation amount of each type of transistor in the integrated circuit simulation model. Then, by analyzing the difference between the reference degradation amount of the transistor under the current simulation step size and the previous simulation step size, the length of the next simulation step size is determined, thereby achieving adaptive control of the simulation step size. This avoids simulation processing under a fixed simulation step size, improves the accuracy of integrated circuit simulation processing, and optimizes the overall aging test results. Furthermore, by analyzing the degree of influence of the coupling effect between the HCI effect and the BTI effect on the stability of the integrated circuit, the stability index of the integrated circuit model is determined, which improves the accuracy of stability performance evaluation in integrated circuit aging tests, thereby helping designers to design better integrated circuits. Attached Figure Description

[0044] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a flowchart of an integrated circuit simulation design method provided in one embodiment of the present invention. Detailed Implementation

[0046] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of an integrated circuit simulation design method, platform, and system proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0048] The following description, in conjunction with the accompanying drawings, details the specific solution of the integrated circuit simulation design method, platform, and system provided by this invention.

[0049] Please see Figure 1 The diagram illustrates a flowchart of an integrated circuit simulation design method according to an embodiment of the present invention, the method comprising:

[0050] Step S1: Obtain the degradation of each transistor of each transistor type under the current simulation step size for the integrated circuit under two different effects, and the sensitivity of each transistor to each stress parameter under each aging parameter.

[0051] The integrated circuit simulation tool used in this embodiment of the invention is the Relxpert circuit reliability simulation tool, which allows users to add custom aging models and can also model each aging effect separately. First, the required aging model is determined. In this embodiment, the aging model refers to an aging model based on the HCI effect and an aging model based on the BTI effect. Then, the aging model object and model parameters are initialized. After the model is established, the Relxpert tool is used to import the model into the circuit netlist. Aging parameters and stress parameters are core variables describing the device aging process. Aging parameters are imported in the form of parameter files, and the aging parameters differ for different types of transistors. Stress parameters are captured from the transient simulation waveform of the circuit using the Relxpert tool. Aging parameters include threshold voltage drift, saturation drain current degradation, and linear region transconductance degradation, while stress parameters include real-time fluctuation values ​​of voltage stress, temperature stress, time stress, and duty cycle.

[0052] In existing technologies, a preset stress duration (i.e., the cumulative exposure time of a transistor under specific electrical stress conditions) is typically divided into multiple equal-length steps, and a transient simulation is performed within each fixed-length step. Stress parameters are then captured in each transient simulation, and the degradation of the transistor is determined by analyzing the changes in these parameters. However, because the sensitivity of integrated circuit performance to aging effects varies within each step, this method suffers from unreasonable step size design. Therefore, this embodiment of the invention first presets the lengths of the first two simulation steps, setting both to 500 milliseconds. The lengths of the first two simulation steps can also be set by the implementer according to the specific implementation scenario, and are not limited here. Since subsequent steps require merging the current simulation step with the previous simulation step... The true step size parameters are compared and analyzed. To ensure that there are other simulation step sizes before the current simulation step size, this embodiment of the invention starts the analysis from the second simulation step size, takes the second simulation step size as the current simulation step size, and adaptively adjusts the length of the third simulation step size in subsequent steps. Under the current simulation step size, transient analysis of the integrated circuit is performed using an aging model based on the HCI effect and an aging model based on the BTI effect, respectively. The degradation amount of each transistor of each transistor type under the two different effects at the current simulation step size is obtained, as well as the sensitivity of each stress parameter of each transistor under each aging parameter. The methods for obtaining the degradation amount and sensitivity are well known to those skilled in the art and will not be elaborated here. For example, the sensitivity of voltage stress is obtained by the small current injection saturation voltage drop method.

[0053] Step S2: Under any effect, take any transistor type as the target transistor type. Based on the distribution of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters, obtain the circuit influence of each transistor. Based on the distribution of the circuit influence of all transistors of the target transistor type, obtain the degradation effectiveness of the target transistor type. Based on the degradation amount of each transistor of each transistor type in the current simulation step and the degradation effectiveness of each transistor type, obtain the reference degradation amount of the current simulation step. Based on the difference between the reference degradation amount between the current simulation step and the previous simulation step, adjust the length of the current simulation step to obtain the length of the next simulation step.

[0054] The embodiments of this invention first perform analysis under any effect. For example, taking the aging model of the HCI effect as an example, since the parameter degradation of different transistors in the integrated circuit has different effects on the circuit, its impact on circuit performance is different in the transient simulation process of the current simulation step size. Therefore, the embodiments of this invention first take any transistor type as the target transistor type, and analyze the distribution of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters. The obtained circuit influence degree reflects the degree of influence of each transistor in the target transistor type on the stability of integrated circuit performance.

[0055] Preferably, in one embodiment of the present invention, the method for obtaining the circuit influence of each transistor of the target transistor type specifically includes:

[0056] The average sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters is taken as the overall sensitivity of each stress parameter of each transistor of the target transistor type.

[0057] After analyzing the dispersion of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters and performing negative correlation mapping, the consistency of the sensitivity of each stress parameter of each transistor of the target transistor type is obtained.

[0058] In embodiments of the present invention, the dispersion of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters can be analyzed by calculating the standard deviation or variance of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters, and the same method can be used to analyze the dispersion of the data in subsequent steps.

[0059] The greater the overall level of sensitivity of each stress parameter of each transistor under all aging parameters, and the higher the similarity of sensitivity under all aging parameters, the greater the influence of each stress parameter of each transistor on the performance of the integrated circuit. Therefore, the overall sensitivity and the degree of sensitivity consistency can be combined to obtain the initial influence coefficient of each stress parameter of each transistor of the target transistor type, and the average value of the initial influence coefficients of all stress parameters of each transistor of the target transistor type is taken as the circuit influence degree of each transistor of the target transistor type.

[0060] In embodiments of the present invention, the sum or product of the overall sensitivity and the degree of sensitivity consistency can be used as the initial influence coefficient of each stress parameter of each transistor of the target transistor type to achieve the integration of the two. This is not limited here. Furthermore, the integration processing of two or more data in subsequent steps can also be achieved using the same method.

[0061] As an example, in one embodiment of the present invention, the expression for the circuit influence of each transistor of the target transistor type can be specifically, for example, as follows:

[0062]

[0063]

[0064] in, The first one representing the target transistor type The circuit influence of each transistor; The first one representing the target transistor type The first transistor The initial influence coefficient of the stress parameter; Indicates the number of stress parameters; The first one representing the target transistor type The first transistor The standard deviation of the sensitivity of a stress parameter to all aging parameters; The first one representing the target transistor type The first transistor The degree of consistency in the sensitivity of various stress parameters; Represented by natural constant An exponential function with base 0 is used for negative correlation mapping. The first one representing the target transistor type The first transistor The stress parameter in the first Sensitivity under various aging parameters; The first one representing the target transistor type The first transistor The overall sensitivity of stress parameters; This indicates the number of aging parameters.

[0065] It should be noted that negative correlation mapping can also be achieved through other basic mathematical operations in other embodiments of the present invention, which will not be elaborated here.

[0066] Since transistors of the same type have the same structure, under the same simulation conditions, the degree of influence of transistors of the same type on integrated circuits is similar. Therefore, the degradation effectiveness of the target transistor type can be obtained based on the distribution of the circuit influence of all transistors of the target transistor type. The larger the degradation effectiveness, the more realistic the degradation exhibited by the transistors of the target transistor type. Subsequently, based on the degradation of transistors of each crystal crown type and combined with the degradation effectiveness of each transistor type, the aging and degradation exhibited by the integrated circuit under the current simulation step size can be accurately analyzed.

[0067] Preferably, in one embodiment of the present invention, the method for obtaining the degradation effectiveness of the target transistor type specifically includes:

[0068] The greater the overall level of the circuit influence of all transistors of the target transistor type, and the worse the consistency of the circuit influence of all transistors of the target transistor type, the more realistic the degradation exhibited by the transistors of the target transistor type. Therefore, the average value of the circuit influence of all transistors of the target transistor type can be used as the overall circuit influence of the target transistor type. The dispersion of the circuit influence of all transistors of the target transistor type can be analyzed to obtain the circuit influence dispersion of the target transistor type.

[0069] Then, the overall circuit influence degree and the circuit influence dispersion are combined and normalized to limit the calculation results to within a certain range. Within the range, the degradation effectiveness of the target transistor type is obtained, where the sum of the degradation effectiveness of all transistor types is equal to the value 1.

[0070] As an example, in one embodiment of the present invention, the expression for the degradation effectiveness of the target transistor type can be specifically, for example, as follows:

[0071]

[0072] in, Indicates the degradation effectiveness of the target transistor type; This indicates the overall circuit impact of the target transistor type; The standard deviation of the circuit influence of all transistors of the target transistor type represents the dispersion of the circuit influence of the target transistor type. Indicates the first The overall circuit impact of each transistor type; Indicates the first The type of transistor in the circuit affects the dispersion; Indicates the number of transistor types.

[0073] The degradation efficiency for each transistor type can be obtained using the same method described above, where, Used for Normalization is performed so that the sum of the degradation effectiveness of all transistor types equals 1, which facilitates subsequent calculations and analysis.

[0074] Then, based on the degradation amount of each transistor of each transistor type in the integrated circuit at the current simulation step, and the degradation effectiveness of each transistor type, a reference degradation amount for the current simulation step can be obtained. The reference degradation amount reflects the degree of degradation and aging exhibited by the integrated circuit at the current simulation step. Subsequently, the difference between the reference degradation amount between the current simulation step and the previous simulation step can be analyzed to determine the length of the next simulation step, thereby achieving adaptive control of the simulation step, avoiding simulation processing at a fixed simulation step, improving the accuracy of integrated circuit simulation processing, and thus optimizing the overall aging test results.

[0075] Preferably, in one embodiment of the present invention, the method for obtaining the reference degradation amount of the current simulation step size specifically includes:

[0076] The average degradation of all transistors of each transistor type in the current simulation step is taken as the overall degradation of the integrated circuit in the current simulation step for each transistor type. Using the degradation effectiveness of each transistor type, the overall degradation of the integrated circuit in the current simulation step for each transistor type is weighted and summed to obtain the reference degradation of the current simulation step.

[0077] As an example, in one embodiment of the present invention, the expression for the reference degradation amount of the current simulation step size can be specifically as follows:

[0078]

[0079] in, This represents the reference degradation amount for the current simulation step size; Indicates the first Degradation efficiency of various transistor types; This indicates the integrated circuit at the current simulation step number. Overall degradation of each transistor type; Indicates the number of transistor types.

[0080] If the reference degradation of the previous simulation step is less than that of the current simulation step, the length of the next simulation step needs to be appropriately reduced. Conversely, if the reference degradation of the previous simulation step is greater than that of the current simulation step, the length of the next simulation step needs to be appropriately increased to ensure the accuracy of the integrated circuit simulation processing and thus optimize the overall aging test results. Therefore, the length of the current simulation step can be adjusted according to the difference in reference degradation between the current simulation step and the previous simulation step to obtain the length of the next simulation step.

[0081] Preferably, in one embodiment of the present invention, the method for obtaining the length of the next simulation step specifically includes:

[0082] The difference between the reference degradation value of the previous simulation step and the reference degradation value of the current simulation step is normalized, and the calculation result is limited to... Within the range, the step size adjustment weight for the next simulation step size is obtained. It should be noted that the same calculation method as the reference degradation amount of the current simulation step size can be used to calculate the reference degradation amount of the previous simulation step size. In other words, the reference degradation amount of each simulation step size is analyzed in real time, and the corresponding reference degradation amount can be calculated for each simulation step size according to the above method.

[0083] In one embodiment of the present invention, normalization can be achieved using, for example, the hyperbolic tangent function, without limitation.

[0084] When the step size adjustment weight is less than 0 and smaller, the length of the next simulation step size needs to be reduced to a greater extent. When the step size adjustment weight is greater than 0 and larger, the length of the next simulation step size needs to be increased to a greater extent. Therefore, the product of the step size adjustment weight of the next simulation step size and the length of the current simulation step size can be used as the length adjustment amount of the next simulation step size, and the sum of the length of the current simulation step size and the length adjustment amount of the next simulation step size can be used as the length of the next simulation step size.

[0085] As an example, in one embodiment of the present invention, the expression for the length of the next simulation step can be specifically as follows:

[0086]

[0087] in, Indicates the length of the next simulation step; This indicates the length of the current simulation step. Indicates the length of the previous simulation step; This indicates the step size adjustment weight for the next simulation step. This indicates the length adjustment amount for the next simulation step. This represents the hyperbolic tangent function, used for normalization.

[0088] Step S3: Based on the length of the next simulation step, perform iterative transient simulations of the integrated circuit under each effect to obtain the performance stability and coupling performance stability of the integrated circuit under each effect; based on the difference in coupling performance stability between the current aging test and the historical aging test, and the performance stability and coupling performance stability of the integrated circuit under each effect in the current aging test, obtain the stability index of the integrated circuit under the current aging test.

[0089] Once the length of the next simulation step is determined, iterative transient simulations of the integrated circuit under each effect can be performed based on the length of the next simulation step. This allows us to obtain the performance stability and coupling stability of the integrated circuit under each effect. Subsequently, based on the performance stability and coupling stability of the integrated circuit under each effect, we can calculate and analyze the stability indicators of the integrated circuit under the current aging test. This avoids considering only the single HCI effect or BTI effect without taking into account the impact of the coupling effect between these two effects on the performance analysis of the integrated circuit, thereby improving the accuracy of subsequent performance stability assessments of the integrated circuit.

[0090] Preferably, in one embodiment of the present invention, the method for obtaining the performance stability of the integrated circuit under each effect and the coupling performance stability of the integrated circuit specifically includes:

[0091] The length of the next simulation step is taken as the length of the new current simulation step. Within the new current simulation step, transient simulations are performed on the integrated circuit under each effect. This process is repeated until the cumulative length of all simulation steps equals the preset stress duration. This allows us to obtain the performance stability of the integrated circuit under each effect and the coupling performance stability of the integrated circuit. In one embodiment of the present invention, the preset stress duration is set to 10 minutes. The specific value of the preset stress duration can also be set by the implementer according to the specific implementation scenario, and is not limited here.

[0092] It should be noted that the methods for obtaining the performance stability of integrated circuits under each effect and the coupling performance stability of integrated circuits are well known to those skilled in the art and will not be elaborated here. The performance stability of integrated circuits under a single effect, such as the performance stability of integrated circuits under the HCI effect, refers to the performance stability exhibited by integrated circuits under the influence of the HCI effect, while the coupling performance stability of integrated circuits refers to the performance stability exhibited by integrated circuits under the combined influence of the HCI effect and the BTI effect.

[0093] In the simulation design process of integrated circuits, it is necessary to conduct multiple aging tests on the integrated circuit to optimize its performance. Furthermore, in the simulation design process, not only do individual effects affect the performance of the integrated circuit, but the coupling effect between HCI and BTI effects can also influence its performance. The degree of influence of a single HCI or BTI effect on the integrated circuit performance differs from the degree of influence of their coupling effect. Therefore, by considering the difference in the stability of the integrated circuit's coupling performance between the current aging test and historical aging tests, as well as the performance stability of the integrated circuit under each effect and the stability of its coupling performance under the current aging test, a stability index of the integrated circuit under the current aging test can be obtained. This stability index reflects the performance stability of the integrated circuit during the current aging test process.

[0094] Preferably, in one embodiment of the present invention, the method for obtaining the stability index of the integrated circuit under the current aging test specifically includes:

[0095] The average coupling performance stability of all historically tested integrated circuits is used as the reference coupling performance stability for the current tested integrated circuit.

[0096] The difference between the coupling performance stability of the current aging test integrated circuit and the reference coupling performance stability is normalized by applying a negative correlation, and the calculation result is limited to... Within this range, a reference weight for the coupling performance stability of the current aging test is obtained. The larger the reference weight, the stronger the reference value of the coupling performance stability of the integrated circuit in the current aging test in the subsequent calculation of stability indicators.

[0097] It should be noted that the coupling performance stability of the integrated circuits currently undergoing aging tests, as well as the coupling performance stability of integrated circuits undergoing various historical aging tests, can be obtained using the same method described above.

[0098] As an example, in one embodiment of the present invention, the expression for the reference weight of the coupling performance stability of the current aging test can be specifically as follows:

[0099]

[0100] in, The reference weights represent the stability of the coupling performance in the current aging test; This indicates the stability of the coupling performance of the integrated circuit under current aging test; This represents the average coupling performance stability of the integrated circuits tested throughout history, which is the reference coupling performance stability of the integrated circuits currently undergoing aging tests. This represents the activation function used for normalization. Used for normalization of negative correlations.

[0101] in, The smaller the negative value, the lower the overall level of coupling performance stability of the integrated circuit in the current aging test relative to the coupling performance stability of integrated circuits in historical aging tests. This indicates a greater degree of influence from the coupling effect between the two effects in the current aging test. When the value is positive and larger, it indicates that the overall level of coupling performance stability of the integrated circuit in the current aging test is greater than that of the integrated circuit in the historical aging test, and the influence of the coupling effect between the two effects in the current aging test is smaller.

[0102] Then, based on the formula for calculating the stability index, the stability index of the integrated circuit under the current aging test is obtained. The formula for calculating the stability index is:

[0103]

[0104] in, This indicates the stability of the integrated circuit under the current aging test. The reference weights represent the stability of the coupling performance in the current aging test; This indicates the stability of the coupling performance of the integrated circuit under current aging test; This indicates the performance stability of the integrated circuit under the first effect; This indicates the performance stability of the integrated circuit under the second effect; This represents the hyperbolic tangent function, used for normalization.

[0105] Step S4: Evaluate the stability of the integrated circuit under the current aging test based on stability indicators.

[0106] The higher the stability index of an integrated circuit under the current aging test, the more stable its performance under the current aging test. Therefore, the stability index can be used to evaluate the stability of an integrated circuit under the current aging test, thereby improving the accuracy of the stability performance evaluation of the aging test of integrated circuits.

[0107] Preferably, in one embodiment of the present invention, the method for evaluating the stability of an integrated circuit under current aging tests specifically includes:

[0108] If the stability index of the integrated circuit under the current aging test is greater than the preset stability threshold, then the stability performance of the integrated circuit in the current aging test meets the standard. Otherwise, the stability performance of the integrated circuit in the current aging test does not meet the standard. If the stability performance of the integrated circuit does not meet the standard, it is necessary to adjust the wiring layout or transistor layout to optimize the integrated circuit. After optimizing the design, the designer should conduct stability testing on the integrated circuit using the same method as above until the stability performance of the integrated circuit meets the standard. The preset stability threshold value range is [insert range here]. In one embodiment of the present invention, the preset stability threshold is set to 0.7. The specific value of the preset stability threshold can also be set by the implementer according to the specific implementation scenario, and is not limited here.

[0109] One embodiment of the present invention provides an integrated circuit simulation design platform, the platform comprising:

[0110] The data acquisition module is used to acquire the degradation of each transistor of each transistor type under two different effects at the current simulation step, as well as the sensitivity of each transistor to each stress parameter under each aging parameter.

[0111] The step size adjustment module is used to select any transistor type as the target transistor type under any effect, and obtain the circuit influence degree of each transistor based on the distribution of sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters; obtain the degradation effectiveness of the target transistor type based on the distribution of the circuit influence degree of all transistors of the target transistor type; obtain the reference degradation amount of the current simulation step size based on the degradation amount of each transistor of each transistor type of the integrated circuit at the current simulation step size, and the degradation effectiveness of each transistor type; and adjust the length of the current simulation step size based on the difference between the reference degradation amount between the current simulation step size and the previous simulation step size to obtain the length of the next simulation step size.

[0112] The stability analysis module is used to perform iterative transient simulations of the integrated circuit under each effect based on the length of the next simulation step, to obtain the performance stability and coupling performance stability of the integrated circuit under each effect. Based on the difference in coupling performance stability between the current aging test and the historical aging test, as well as the performance stability and coupling performance stability of the integrated circuit under each effect in the current aging test, the stability index of the integrated circuit under the current aging test is obtained.

[0113] The evaluation module is used to assess the stability of integrated circuits under current aging tests based on stability metrics.

[0114] One embodiment of the present invention provides an integrated circuit simulation design system, which includes a memory, a processor, and a computer program. The memory is used to store the corresponding computer program, and the processor is used to run the corresponding computer program. When the computer program runs in the processor, it can implement the methods described in steps S1 to S4.

[0115] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0116] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

Claims

1. An integrated circuit simulation design method, characterized in that, The method includes: Obtain the degradation of each transistor of each transistor type under two different effects at the current simulation step, and the sensitivity of each transistor to each stress parameter under each aging parameter. Under any effect, any transistor type is taken as the target transistor type. Based on the distribution of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters, the circuit influence of each transistor is obtained, including: taking the average value of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters as the overall sensitivity of each stress parameter of each transistor of the target transistor type. After analyzing the dispersion of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters and performing negative correlation mapping, the consistency of the sensitivity of each stress parameter of each transistor of the target transistor type is obtained. By combining the overall sensitivity and the degree of sensitivity consistency, the initial influence coefficient of each stress parameter for each transistor of the target transistor type is obtained; The average value of the initial influence coefficients of all stress parameters of each transistor of the target transistor type is used as the circuit influence degree of each transistor of the target transistor type; the degradation effectiveness of the target transistor type is obtained according to the distribution of the circuit influence degree of all transistors of the target transistor type, including: the average value of the circuit influence degree of all transistors of the target transistor type is used as the overall circuit influence degree of the target transistor type. The dispersion of the circuit influence of all transistors of the target transistor type is analyzed to obtain the dispersion of the circuit influence of the target transistor type. After synthesizing and normalizing the overall circuit impact degree and circuit impact dispersion, the degradation effectiveness of the target transistor type is obtained, where the sum of the degradation effectiveness of all transistor types equals the value 1. Based on the degradation amount of each transistor of each transistor type in the current simulation step and the degradation effectiveness of each transistor type, the reference degradation amount of the current simulation step is obtained. Based on the difference between the reference degradation amount of the current simulation step and the previous simulation step, the length of the current simulation step is adjusted to obtain the length of the next simulation step, including: normalizing the difference between the reference degradation amount of the previous simulation step and the reference degradation amount of the current simulation step to obtain the step size adjustment weight of the next simulation step. The product of the step size adjustment weight of the next simulation step and the length of the current simulation step is used as the length adjustment amount of the next simulation step. The sum of the current simulation step length and the adjustment amount of the next simulation step length is used as the length of the next simulation step. Based on the length of the next simulation step, iterative transient simulations are performed on the integrated circuit under each effect to obtain the performance stability and coupling performance stability of the integrated circuit under each effect. Based on the difference in coupling performance stability between the current aging test and the historical aging test, as well as the performance stability and coupling performance stability of the integrated circuit under each effect in the current aging test, the stability index of the integrated circuit under the current aging test is obtained. Based on stability metrics, the stability of integrated circuits under current aging tests is evaluated.

2. The integrated circuit simulation design method according to claim 1, characterized in that, The reference degradation value for obtaining the current simulation step size includes: The average of the degradation of all transistors of each transistor type in the integrated circuit at the current simulation step is taken as the overall degradation of the integrated circuit for each transistor type at the current simulation step. By utilizing the degradation effectiveness of each transistor type, the overall degradation of the integrated circuit at the current simulation step is weighted and summed to obtain the reference degradation at the current simulation step.

3. The integrated circuit simulation design method according to claim 1, characterized in that, The process of obtaining the performance stability of the integrated circuit under each effect and the coupling performance stability of the integrated circuit includes: The length of the next simulation step is used as the length of the new current simulation step. Within the new current simulation step, transient simulations are performed on the integrated circuit under each effect until the cumulative length of all simulation steps equals the preset stress duration. This allows us to obtain the performance stability of the integrated circuit under each effect and the coupling performance stability of the integrated circuit.

4. The integrated circuit simulation design method according to claim 1, characterized in that, The stability indicators of the integrated circuit under the current aging test include: The average value of the coupling performance stability of all historically tested integrated circuits is used as the reference coupling performance stability of the integrated circuit currently undergoing aging tests. The difference between the coupling performance stability of the integrated circuit under the current aging test and the reference coupling performance stability is normalized by negative correlation to obtain the reference weight of the coupling performance stability of the current aging test. Based on the calculation formula for the stability index, the stability index of the integrated circuit under the current aging test is obtained. The calculation formula for the stability index is as follows: in, This indicates the stability of the integrated circuit under the current aging test. The reference weights represent the stability of the coupling performance in the current aging test; This indicates the stability of the coupling performance of the integrated circuit currently undergoing aging tests; This indicates the performance stability of the integrated circuit under the first effect; This indicates the performance stability of the integrated circuit under the second effect; This represents the hyperbolic tangent function, used for normalization.

5. The integrated circuit simulation design method according to claim 1, characterized in that, The evaluation of the stability of the integrated circuit under the current aging test includes: If the stability index of the integrated circuit under the current aging test is greater than the preset stability threshold, then the stability performance of the integrated circuit in the current aging test meets the standard; otherwise, the stability performance of the integrated circuit in the current aging test does not meet the standard.

6. An integrated circuit simulation design platform, characterized in that, The platform includes: The data acquisition module is used to acquire the degradation of each transistor of each transistor type under two different effects at the current simulation step, and the sensitivity of each transistor to each stress parameter under each aging parameter. The step size adjustment module is used to, under any effect, take any transistor type as the target transistor type, obtain the circuit influence degree of each transistor based on the distribution of sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters; obtain the degradation effectiveness of the target transistor type based on the distribution of the circuit influence degree of all transistors of the target transistor type; obtain the reference degradation amount of the current simulation step size based on the degradation amount of each transistor of each transistor type of the integrated circuit at the current simulation step size and the degradation effectiveness of each transistor type; and adjust the length of the current simulation step size based on the difference between the reference degradation amount and the previous simulation step size to obtain the length of the next simulation step size. The step size adjustment module is specifically used to take the average value of the circuit influence of all transistors of the target transistor type as the overall circuit influence of the target transistor type. The dispersion of the circuit influence of all transistors of the target transistor type is analyzed to obtain the dispersion of the circuit influence of the target transistor type. After synthesizing and normalizing the overall circuit influence degree and circuit influence dispersion, the degradation effectiveness of the target transistor type is obtained, where the sum of the degradation effectiveness of all transistor types is equal to the value 1. The difference between the reference degradation amount of the previous simulation step and the reference degradation amount of the current simulation step is normalized to obtain the step size adjustment weight of the next simulation step. The product of the step size adjustment weight of the next simulation step and the length of the current simulation step is used as the length adjustment amount of the next simulation step. The sum of the current simulation step length and the adjustment amount of the next simulation step length is used as the length of the next simulation step. The stability analysis module is used to perform iterative transient simulations of the integrated circuit under each effect based on the length of the next simulation step, to obtain the performance stability and coupling performance stability of the integrated circuit under each effect; based on the difference in the coupling performance stability of the integrated circuit between the current aging test and the historical aging test, and the performance stability and coupling performance stability of the integrated circuit under each effect under the current aging test, the stability index of the integrated circuit under the current aging test is obtained. An evaluation module is used to evaluate the stability of the integrated circuit under the current aging test based on the stability index. The step size adjustment module is also used to take the average of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters as the overall sensitivity of each stress parameter of each transistor of the target transistor type. After analyzing the dispersion of the sensitivity of each stress parameter of each transistor of the target transistor type under all aging parameters and performing negative correlation mapping, the consistency of the sensitivity of each stress parameter of each transistor of the target transistor type is obtained. By combining the overall sensitivity and the degree of consistency of the sensitivity, an initial influence coefficient for each stress parameter of each transistor of the target transistor type is obtained; The average value of the initial influence coefficients of all stress parameters for each transistor of the target transistor type is taken as the circuit influence degree of each transistor of the target transistor type.

7. An integrated circuit simulation design system, the system comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 5.

Images