Chip layout photolithography hotspot detection method and system based on asynchronous meta-learning

Abstract

The application belongs to the technical field of industrial vision detection, and specifically discloses a chip layout photolithography hotspot detection method and system based on asynchronous meta-learning. The method comprises the following steps: slicing a new chip layout to be detected to obtain a plurality of chip layout slices to be detected corresponding to the new chip layout; inputting the plurality of chip layout slices to be detected into a chip layout photolithography hotspot detection model to obtain a photolithography hotspot detection result of the new chip layout output by the chip layout photolithography hotspot detection model; the chip layout photolithography hotspot detection model is obtained by performing single-sample training on a meta-initialization model by using the new chip layout; and the meta-initialization model is obtained by performing meta-training according to an old chip layout sample and a classification label set corresponding to the old chip layout sample. Through the application, the generalization performance of the chip layout photolithography hotspot detection model can be greatly improved, and effective detection of photolithography hotspots of cross-chip design layout is realized under the condition of only single training sample.

Description

Technical Field

[0001] This application belongs to the field of industrial vision inspection technology, and more specifically, relates to a chip layout lithography hotspot detection method and system based on asynchronous meta-learning. Background Technology

[0002] As the feature size of application-specific integrated circuits (ASICs) continues to shrink, the sensitivity of chip layouts to optical diffraction effects has increased significantly, leading to defects such as short circuits or open circuits (known as lithography hotspots) during manufacturing. Detecting and correcting such hotspots during the chip design and visual inspection stages has become a critical step in ensuring chip manufacturing yield.

[0003] However, existing detection methods are mainly divided into four categories: lithography simulation-based methods, pattern matching methods, traditional machine learning methods, and deep learning methods. Among them, lithography simulation methods simulate manufacturing results based on physical models, achieving high accuracy but incurring huge computational costs, making it difficult to meet the timeliness requirements of large-scale layouts; pattern matching methods achieve rapid detection by comparing known hotspot patterns, but cannot identify novel hotspot structures that have not been recorded; traditional machine learning methods have a certain generalization ability, but they heavily rely on manually designed features (such as density and geometric parameters), easily losing key topological information, resulting in low accuracy and high false alarm rates; deep learning methods automatically extract features through end-to-end training, which can improve accuracy and generalization ability to a certain extent, but has serious limitations, namely, the model may overfit the layout style distribution of the training data rather than learning the real lithography physical principles (such as optical proximity effect). This bias causes the model to only have high detection performance on the same layout as the training data, while its generalization ability on new chip design layouts is poor, resulting in unsatisfactory detection accuracy and false alarm rates.

[0004] Therefore, how to better detect lithographic hotspots on chip layouts has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this application is to better realize the detection of lithography hot spots on chip layout, and to solve the problem that the detection accuracy and false alarm rate are not ideal due to the poor generalization of cross-chip design layout lithography hot spot identification in the prior art.

[0006] To achieve the above objectives, in a first aspect, this application provides a chip layout lithography hotspot detection method based on asynchronous meta-learning, comprising: The new chip layout to be tested is sliced ​​to obtain multiple layout slices corresponding to the new chip layout; The multiple slices of the layout to be detected are input into the chip layout lithography hot spot detection model to obtain the lithography hot spot detection result of the new chip layout output by the chip layout lithography hot spot detection model; The chip layout lithography hotspot detection model is obtained by training the meta-initialization model with a single sample using the new chip layout; the meta-initialization model is obtained by meta-training based on the old chip layout samples and their corresponding classification label sets.

[0007] Optionally, before inputting the plurality of lithography hotspot slices to be detected into the chip layout lithography hotspot detection model to obtain the lithography hotspot detection result of the new chip layout output by the chip layout lithography hotspot detection model, the method further includes: Each of the old chip layout samples and its corresponding classification label set is divided into a support set and a query set; An asynchronous update strategy is adopted, and the basic detection model is iteratively trained using the support set and query set corresponding to each old chip layout sample to obtain a trained basic detection model, and the trained basic detection model is used as the meta-initialization model. The meta-initialization model is trained using the new chip layout with a single sample to obtain the chip layout lithography hotspot detection model.

[0008] Optionally, the basic detection model includes a feature extractor and a classifier; the asynchronous update strategy, using the support set and query set corresponding to each old chip layout sample to iteratively train the basic detection model, to obtain a trained basic detection model, includes: The model parameters of the basic detection model are initialized to obtain the initialized model; For each of the old chip layout samples, the initialization model is iteratively trained using its respective support set to obtain its corresponding intermediate model. The intermediate model is then iteratively trained using its respective query set. During the process, the network parameters of the initialization model are updated by calculating the loss gradient until the initialization model after training is obtained. The initial model after training is used as the trained base detection model; During model training using the support set, the network parameters of the feature extractor are updated with a first learning rate, and the network parameters of the classifier are updated with a second learning rate; the first learning rate is less than the second learning rate.

[0009] Optionally, the feature extractor includes multiple feature extraction modules connected in sequence, each feature extraction module including an Inception module and a CBAM attention module connected in sequence; the classifier includes a fully connected layer.

[0010] Optionally, the step of using the new chip layout to perform single-sample training on the meta-initialization model to obtain the chip layout lithography hotspot detection model includes: Based on the new chip layout, slices and feature extraction are performed to obtain a single sample corresponding to the new chip layout; Photolithographic simulation is performed on the single sample to determine the classification label corresponding to the single sample; The meta-initialization model is trained using the single sample and its corresponding classification label, and the trained meta-initialization model is used as the chip layout lithography hotspot detection model.

[0011] Optionally, the step of slicing and extracting features based on the new chip layout to obtain a single sample corresponding to the new chip layout includes: The new chip layout is sliced ​​to obtain multiple layout slices corresponding to the new chip layout; Each of the aforementioned map slices is encoded to determine a first topological feature vector corresponding to each of the aforementioned map slices; Principal component analysis is performed on the first topological feature vectors corresponding to all slices to obtain the second topological feature vectors corresponding to each slice. Cluster analysis is performed based on the second topological feature vector corresponding to each slice to obtain a single sample corresponding to the new chip layout.

[0012] Optionally, encoding each of the layout slices to determine the first topological feature vector corresponding to each layout slice includes: According to a preset size, each of the layout slices is evenly divided into multiple grid units, so that each grid unit contains at most one metal layer wiring; Determine the width and spacing of the metal layer wiring in each of the aforementioned grid cells; The encoding results of each grid cell in each of the layout slices are obtained by encoding the metal layer wiring width as a positive value and the spacing size as a negative value. The encoding results of each grid cell in each of the layout slices are combined according to the topological structure to obtain the first topological feature vector corresponding to each layout slice.

[0013] Secondly, this application provides a chip layout lithography hotspot detection system based on asynchronous meta-learning, comprising: The slicing module is used to slice the new chip layout to be tested, thereby obtaining multiple slices of the new chip layout to be tested. The detection module is used to input the multiple slices of the layout to be detected into the chip layout lithography hot spot detection model, and obtain the lithography hot spot detection result of the new chip layout output by the chip layout lithography hot spot detection model; The chip layout lithography hotspot detection model is obtained by training the meta-initialization model with a single sample using the new chip layout; the meta-initialization model is obtained by meta-training based on the old chip layout samples and their corresponding classification label sets.

[0014] Thirdly, this application provides an electronic device, comprising: at least one memory for storing a program; and at least one processor for executing the program stored in the memory, wherein when the program stored in the memory is executed, the processor is configured to execute the method described in the first aspect or any possible implementation thereof.

[0015] Fourthly, this application provides a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to perform the method described in the first aspect or any possible implementation thereof.

[0016] Fifthly, this application provides a computer program product that, when run on a processor, causes the processor to perform the method described in the first aspect or any possible implementation thereof.

[0017] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0018] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: This application provides a chip layout lithography hotspot detection method and system based on asynchronous meta-learning. By employing a meta-initialization model trained on old chip layout samples and a single-sample sampling strategy for new chip layout topology, the meta-initialization model trained on old chip layout samples is generalized on a single sample of the selected new chip layout to be detected. This significantly improves the generalization performance of the chip layout lithography hotspot detection model. It achieves effective detection of lithography hotspots across chip design layouts with only a single training sample, improving the accuracy of cross-chip design layout lithography hotspot detection, reducing false alarm rates, and effectively overcoming the generalization failure problem caused by differences in chip layout design in existing methods. Attached Figure Description

[0019] Figure 1 This is a schematic flowchart of the chip layout lithography hotspot detection method based on asynchronous meta-learning provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the chip layout lithography hotspot detection model provided in the embodiments of this application; Figure 3 This is a flowchart illustrating the asynchronous meta-learning training method provided in an embodiment of this application; Figure 4 This is a flowchart illustrating the topology-based encoding method provided in an embodiment of this application; Figure 5 (a) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application under the first chip layout test with other existing methods; (b) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application under the second chip layout test with other existing methods; (c) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application under the third chip layout test with other existing methods; and (d) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application under the fourth chip layout test with other existing methods. Figure 6 (a) is a schematic diagram of the hotspot detection performance confusion matrix of the lithography hotspot detection model provided in the embodiment of this application under the first type of chip layout test; (b) is a schematic diagram of the hotspot detection performance confusion matrix of the lithography hotspot detection model provided in the embodiment of this application under the second type of chip layout test; (c) is a schematic diagram of the hotspot detection performance confusion matrix of the lithography hotspot detection model provided in the embodiment of this application under the third type of chip layout test; and (d) is a schematic diagram of the hotspot detection performance confusion matrix of the lithography hotspot detection model provided in the embodiment of this application under the fourth type of chip layout test. Figure 7 This is a schematic diagram of the chip layout lithography hotspot detection system based on asynchronous meta-learning provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first learning rate" and "second learning rate," etc., are used to distinguish different learning rates, not to describe a specific order of learning rates.

[0022] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0023] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0024] Currently, deep learning-based lithography hotspot detection technology exhibits severe generalization defects in industrial deployments. While existing convolutional neural network (CNN)-based detectors demonstrate high accuracy on chip design layouts corresponding to the training data, their performance deteriorates catastrophically when applied to other design layouts. This phenomenon reveals a fundamental problem: existing models have not learned universal lithography physics principles but rather overfit the apparent features of specific design styles. This design style bias prevents the model from stably supporting chip design iterations in practical applications. This is because each new design requires re-annotating massive amounts of data to train the model, and the high computational cost of lithography simulation makes the annotation process unbearable.

[0025] To address these shortcomings, this application provides a chip layout lithography hotspot detection method based on asynchronous meta-learning.

[0026] The embodiments of this application are described below with reference to the accompanying drawings.

[0027] Figure 1 This is a flowchart illustrating the chip layout lithography hotspot detection method based on asynchronous meta-learning provided in this application embodiment, as follows: Figure 1 As shown, it includes: Step S1: Slice the new chip layout to be tested to obtain multiple slices of the new chip layout to be tested. Step S2: Input multiple slices of the layout to be detected into the chip layout lithography hotspot detection model to obtain the lithography hotspot detection result of the new chip layout output by the chip layout lithography hotspot detection model; the chip layout lithography hotspot detection model is obtained by training the meta-initialization model with a single sample using the new chip layout; the meta-initialization model is obtained by meta-training based on the old chip layout samples and their corresponding classification label sets.

[0028] Specifically, the meta-initialization model described in this application refers to the model obtained by meta-training the basic detection model using old chip layout samples and their corresponding classification label sets. The old chip layout samples refer to samples composed of existing completed chip layouts collected from the database. The basic detection model can be a lithography hotspot detection model built based on a deep learning network.

[0029] It is understood that the new chip layout refers to the latest designed chip layout, which is also the chip layout to be detected in this application embodiment that requires photolithography hotspot detection.

[0030] The chip layout lithography hotspot detection model described in this application refers to a hotspot detection model obtained by training a meta-initialization model with a single sample using a new chip layout. It is used to capture the common patterns of lithography processes and can quickly adapt to and identify lithography hotspots in a new chip layout with only a very small number of samples (such as a single sample) of a newly designed chip layout.

[0031] In the embodiments of this application, in step S1, the new chip layout to be tested is sliced ​​to obtain multiple slices of the new chip layout to be tested. Here, the slicing window for slicing the new chip layout to be tested can be calculated according to the Bessel function, based on the wavelength of the process library used in the chip design, to determine the size of the slicing region that has no diffraction effect on the central region of size 230nm*230nm. This process can be represented as follows: ; In the formula, The angular distribution function representing the intensity of diffracted light; Indicates the center point of the diffraction pattern ( The light intensity of the incident light is a constant, determined by the incident light intensity and the aperture size. Represents the first-order Bessel function; Indicates the wavelength of the incident light used in photolithography; This indicates the angle of deviation of a point on the photomask from the incident optical axis.

[0032] Considering the energy loss that occurs as the range increases, we can take the sixth positive solution of the above equation. At this point, the energy retention rate Within acceptable limits. Because... It is a first-order Bessel function, therefore it can be solved. .

[0033] therefore, , NA The numerical aperture of the photolithography system.

[0034] For the 28nm process node used , Therefore, minimum resolution distance Thus, in the embodiments of this application, the detection window can be set to 230nm*230nm, while the segmentation window can be set to 690nm*690nm, so as to ensure that the distance between the segmentation boundary and the center detection window boundary is greater than 233.36nm.

[0035] In the embodiments of this application, in step S2, meta-training is first performed based on old chip layout samples and their corresponding classification label sets. Specifically, old chip layout samples are obtained based on collected completed chip design layouts. Then, the old chip layout samples are segmented according to the aforementioned segmentation window to obtain defect location markers after the complete chip design layout is segmented. Image conversion and binarization preprocessing are then performed. The classification labels of the corresponding slice layouts are obtained according to the detection window. This allows the determination of the classification label set corresponding to each old chip layout sample, and independent datasets can be constructed for each old chip layout sample using the "layout-classification label" format. Next, a basic detection model is built. This model can be a hotspot detection model built based on a deep learning network. The model is then asynchronously updated and meta-trained using various datasets. This yields a trained basic detection model and a meta-initialized model.

[0036] Understandably, category tags can include both "hot" and "non-hot" tags.

[0037] In the embodiments of this application, an unsupervised clustering sampling strategy based on topological coding can be adopted. The new chip layout to be detected is topologically image encoded to obtain feature representation, and the cluster centers are sampled based on the unsupervised clustering method. The most representative feature samples are selected to form a single sample, and the meta-initialization model obtained by the above training is generalized and trained on the single sample to obtain the generalized hot spot detection model, which is the chip layout lithography hot spot detection model.

[0038] Furthermore, in step S2, the multiple lithography hotspot slices obtained in step S1 can be input into the chip layout lithography hotspot detection model. By learning the design style and data distribution of the new chip layout through the chip layout lithography hotspot detection model, lithography hotspot identification and detection are performed on the lithography hotspot slices obtained by dividing the new chip layout, and the lithography hotspot detection results of the new chip layout are output.

[0039] The asynchronous meta-learning-based chip layout lithography hotspot detection method of this application adopts a strategy of training a meta-initialized model on old chip layout samples and sampling a single sample from the topology of the new chip layout. By using the meta-initialized model trained on old chip layout samples to perform generalization training on a single sample of the selected new chip layout to be detected, the generalization performance of the chip layout lithography hotspot detection model can be greatly improved. It achieves effective detection of lithography hotspots across chip design layouts with only a single training sample, improves the accuracy of cross-chip design layout lithography hotspot detection, reduces the false alarm rate, and effectively overcomes the generalization failure problem caused by differences in chip layout design in existing methods.

[0040] Based on the above embodiments, as an optional embodiment, before step S2, in which multiple lithography hotspot slices to be detected are input into the chip layout lithography hotspot detection model to obtain the lithography hotspot detection result of the new chip layout output by the chip layout lithography hotspot detection model, the method further includes: Each old chip layout sample and its corresponding set of classification labels are divided into a support set and a query set; An asynchronous update strategy is adopted, and the basic detection model is iteratively trained using the support set and query set corresponding to each old chip layout sample to obtain a trained basic detection model, which is then used as the meta-initialization model. A single-sample training of the meta-initialization model was performed using the new chip layout to obtain a chip layout lithography hotspot detection model.

[0041] Specifically, in the embodiments of this application, before performing lithography hotspot detection on the new chip layout in step S2, it is also necessary to train the chip layout lithography hotspot detection model.

[0042] In the embodiments of this application, completed chip design layouts are first collected to obtain old chip layout samples, which in turn yield each old chip layout sample and its corresponding set of classification labels. Each old chip layout sample is divided into multiple slices, and the classification label corresponding to each slice sample is determined based on the corresponding set of classification labels. Multiple sets consisting of a small number of slice samples and their corresponding classification labels are randomly selected from the divided slices as support sets, and multiple sets consisting of a large number of slice samples and their corresponding classification labels are randomly selected from the divided slices as query sets. Thus, each old chip layout sample can be divided into corresponding support sets and query sets.

[0043] Furthermore, in the embodiments of this application, an asynchronous update strategy can be adopted to perform meta-training on the basic detection model using the support set and query set corresponding to each old chip layout sample, thereby obtaining a trained basic detection model, which can then be used as a meta-initialization model.

[0044] Based on the above embodiments, as an optional embodiment, the basic detection model includes a feature extractor and a classifier; employing an asynchronous update strategy, the basic detection model is iteratively trained using the support set and query set corresponding to each old chip layout sample to obtain a trained basic detection model, including: The model parameters of the basic detection model are initialized to obtain the initialized model; For each old chip layout sample, the initialization model is iteratively trained using its respective support set to obtain its corresponding intermediate model. The intermediate model is then iteratively trained using its respective query set. During the process, the network parameters of the initialization model are updated by calculating the loss gradient until the initialization model after training is obtained. Use the initial model after training as the base detection model after training; In the process of training the model using the support set, the network parameters of the feature extractor are updated with a first learning rate, and the network parameters of the classifier are updated with a second learning rate; the first learning rate is less than the second learning rate.

[0045] Specifically, the first learning rate described in the embodiments of this application refers to the learning rate used by the feature extractor to update network parameters.

[0046] The second learning rate described in the embodiments of this application refers to the learning rate used by the classifier to update network parameters.

[0047] In the embodiments of this application, the basic detection model includes a feature extractor and a classifier, wherein the feature extractor is used to capture the common patterns of photolithography processes, while the classifier is used to maintain the model's rapid adaptability.

[0048] Based on the above embodiments, as an optional embodiment, the feature extractor includes multiple feature extraction modules connected in sequence, each feature extraction module including an Inception module and a CBAM attention module connected in sequence; the classifier includes a fully connected layer.

[0049] Specifically, in the embodiments of this application, the feature extractor may include multiple feature extraction modules connected in sequence. Each feature extraction module is composed of an Inception module and a CBAM attention module connected in sequence, and the classifier adopts a fully connected layer.

[0050] like Figure 2As shown, in a specific embodiment of this application, the feature extractor may include five feature extraction modules connected in sequence. The basic detection model is specifically composed of a first Inception module, a first CBAM attention module, a second Inception module, a second CBAM attention module, a third Inception module, a third CBAM attention module, a fourth Inception module, a fourth CBAM attention module, a fifth Inception module, a fifth CBAM attention module, a flattening layer, a first fully connected layer, a metric layer, a second fully connected layer, and a prediction layer.

[0051] The first Inception module comprises four parallel branches: the first branch consists of a max pooling layer and a 1×1 convolutional layer; the second branch consists of a 1×1 convolutional layer and a max pooling layer; the third branch consists of a 1×1 convolutional layer, a 3×3 convolutional layer, and a max pooling layer; and the fourth branch consists of a 1×1 convolutional layer, a 5×5 convolutional layer, and a max pooling layer. The first CBAM attention module consists of a channel attention mechanism and a spatial attention mechanism. The channel attention mechanism includes a global average pooling layer, a global max pooling layer, a shared multilayer perceptron, and a sigmoid activation function. The spatial attention mechanism includes a channel-level max pooling layer, a channel-level average pooling layer, a convolutional layer, and a sigmoid activation function.

[0052] The second, third, fourth, and fifth Inception modules have the same structure as the first Inception module, but different channel parameters. Similarly, the second, third, fourth, and fifth CBAM attention modules have the same structure as the first CBAM attention module, but different numbers of channels. The flattening layer converts multidimensional features into one-dimensional vectors. The first fully connected layer has 1024 neurons and uses the ReLU activation function. The metric layer performs L2 normalization on the features. The second fully connected layer has 250 neurons and uses the ReLU activation function. The prediction layer has 2 neurons and uses the Softmax activation function.

[0053] The method in this application embodiment builds a feature extractor for a basic detection model by using multiple Inception modules and multiple CBAM attention modules. It uses multi-scale convolution of the Inception module to achieve feature extraction, and combines CBAM's cascaded channel attention and spatial attention mechanisms to optimize feature weight allocation, forming complementary advantages, improving the richness of feature expression, and enhancing the model's ability to capture key information. This allows for better capture of the common regularities of lithography processes in chip layout, which is beneficial for improving the generalization performance of the basic detection model.

[0054] Furthermore, in the embodiments of this application, the basic detection model is first initialized with model parameters to obtain an initialized model.

[0055] For each old chip layout sample, the initialized model of the basic detection model after parameter initialization is iteratively trained using its respective support set to obtain its corresponding intermediate model. Then, the corresponding intermediate model is iteratively trained using its respective query set. Here, in each iteration of training, the network parameters of the aforementioned initialized model are updated by calculating the loss gradient each time, until the initialized model after training is obtained, which is the trained basic detection model.

[0056] It should be noted that during model training using the support set, the network parameters of the feature extractor are updated with a first learning rate, and the network parameters of the classifier are updated with a second learning rate.

[0057] Here, the first learning rate is smaller than the second learning rate. During model training using the support set, by setting the feature extractor of the basic detection model to slowly update parameters with a smaller learning rate, overfitting to a single chip design style can be effectively suppressed. At the same time, the classifier updates parameters quickly with a larger learning rate, which can enhance the discriminative ability of the current design. This differentiated update is achieved by setting the two independent learning rates mentioned above.

[0058] More specifically, such as Figure 3 As shown in the embodiments of this application, the asynchronous update meta-training process includes: At the start of training, the model parameters of the base detection model are initialized to obtain the initialized model. This is done using samples from each old chip layout, including the layout data. Figure 1 ,version Figure 2 The layout N performs meta-training on the initialization model.

[0059] For each design training task, the inner loop adaptation process involves training the model using the support set data for each layout. During this process, the model network parameters are updated asynchronously. Specifically, the feature extractor of the base detection model updates its parameters slowly with a small first learning rate, while the classifier updates its parameters quickly with a larger second learning rate. After the inner loop update, temporary model parameters are obtained for each layout. The lithographic hotspot detection model under these temporary parameters becomes the intermediate model.

[0060] Next, the corresponding outer loop optimization phase begins: intermediate models for all training tasks calculate their loss gradients on their respective query sets, sum and average these gradients, and then update the network parameters of the initial model with a uniform learning rate. This aggregated update forces the model to learn universal lithography principles across designs.

[0061] The entire training process alternates between inner loop task adaptation and outer loop parameter update, ultimately yielding the initialized model after training, which is the trained basic detection model. This results in a meta-initialized model with strong generalization ability. The feature extractor of this model can effectively capture the common patterns of photolithography processes, while the classifier maintains rapid adaptability, enabling it to quickly identify objects with only a very small number of newly designed samples (such as a single sample).

[0062] The method in this application embodiment trains a basic detection model using an asynchronous meta-learning framework and asynchronously updates the network parameters of the feature extraction module (learning rate α) and the classification module (learning rate β) using a differentiated learning rate. This can effectively suppress the overfitting of the model to a single chip design style, enhance the discrimination ability of the current design, and improve the generalization ability of the hotspot detection model.

[0063] Furthermore, in the embodiments of this application, by using the new chip layout to perform single-sample training on the obtained meta-initialization model, a chip layout lithography hotspot detection model can be obtained.

[0064] The method in this application embodiment, by combining the meta-initialization model obtained from meta-training with a single-sample training strategy to perform multi-stage model training, can obtain a chip layout lithography hotspot detection model with strong generalization performance, and can achieve effective detection and identification of lithography hotspots with only a single training sample.

[0065] Based on the above embodiments, as an optional embodiment, a single-sample training of the meta-initialization model is performed using the new chip layout to obtain a chip layout lithography hotspot detection model, including: Based on the new chip layout, slices and feature extraction are performed to obtain single samples corresponding to the new chip layout; Photolithographic simulation is performed on a single sample to determine the classification label corresponding to the single sample; The meta-initialization model was trained to generalize using single samples and their corresponding classification labels, and the trained meta-initialization model was used as a chip layout lithography hotspot detection model.

[0066] Specifically, in the embodiments of this application, after obtaining the meta-initialized model by meta-training using old chip layout samples and their corresponding classification label sets, a single-sample training method is further adopted to train the meta-initialized model using the new chip layout to obtain the chip layout lithography hotspot detection model.

[0067] In the embodiments of this application, the new chip layout is first sliced, and the sliced ​​layout slices are feature-encoded by a topology-based encoding method. Then, feature sampling is performed based on an unsupervised clustering method to obtain the most representative feature samples, which are the single samples corresponding to the new chip layout.

[0068] Based on the above embodiments, as an optional embodiment, slicing and feature extraction are performed according to the new chip layout to obtain a single sample corresponding to the new chip layout, including: Slice the new chip layout to obtain multiple layout slices corresponding to the new chip layout; Encode each map slice to determine the first topological feature vector corresponding to each map slice; Principal component analysis is performed on the first topological feature vectors corresponding to all slices to obtain the second topological feature vectors corresponding to each slice. Cluster analysis is performed based on the second topological feature vector corresponding to each slice to obtain a single sample corresponding to the new chip layout.

[0069] Specifically, in the embodiments of this application, the new chip layout is sliced ​​to obtain multiple layout slices corresponding to the new chip layout, and then a topology-based encoding method is used to encode each layout slice to determine the first topological feature vector corresponding to each layout slice.

[0070] Based on the above embodiments, as an optional embodiment, each map slice is encoded to determine the first topological feature vector corresponding to each map slice, including: According to the preset size, each layout slice is evenly divided into multiple grid units so that each grid unit contains at most one metal layer wiring; Determine the width and spacing of the metal layer wiring in each grid cell; The encoding results of each grid cell in each layout slice are obtained by encoding the metal layer wiring width as a positive value and the spacing size as a negative value. The encoding results of each grid cell in each plot slice are combined according to the topological structure to obtain the first topological feature vector corresponding to each plot slice.

[0071] Specifically, in the embodiments of this application, after the new chip layout is sliced ​​into multiple layout slices (size R×R, half-pitch P), as follows: Figure 4As shown, the input layout slices are cut to a preset size (each unit size is represented as...). w × w The image is uniformly divided into Z×Z grid cells, where Z must satisfy the constraint: Z>R / P, to ensure that each grid contains at most one metal layer wiring. In semiconductor manufacturing, half-pitch refers to half the smallest feature size in the photoresist pattern and is an important indicator of chip manufacturing process precision.

[0072] Subsequently, the width and spacing of the metal layer wiring in each grid cell are determined. Specifically, within each grid cell, center scan lines can be set horizontally from left to right and vertically from top to bottom to capture the geometric dimensions of the metal width and spacing within the grid. Further, the metal layer wiring width is encoded as a positive value, and the spacing dimension as a negative value, to obtain the encoding results for each grid cell. For example... Figure 4 As shown, the exemplary grid, after being encoded, is encoded horizontally as (0.2). w -0.8 w ), encoded as (-) in the vertical direction w Finally, the horizontal and vertical scan encoding results of each grid can be sequentially combined topologically to form a fixed-length one-dimensional topological feature vector, thus obtaining the first topological feature vector corresponding to each plot slice.

[0073] The method in this application embodiment, through a topology-based encoding method, can obtain a topology feature vector that fully preserves key topology information such as metal distribution and line width / spacing dimensions of the layout, providing dimensionally consistent input for subsequent unsupervised clustering.

[0074] Furthermore, in the embodiments of this application, an unsupervised clustering method is adopted. First, principal component analysis (PCA) is performed on the first topological feature vectors corresponding to all slices to reduce the data dimensionality, thereby obtaining the second topological feature vector corresponding to each slice. Then, the K-Means clustering method is used to perform cluster analysis on the second topological feature vectors corresponding to each slice, and the sample closest to the cluster center is selected, thereby obtaining the single sample corresponding to the new chip layout.

[0075] The method in this application combines a topology-based encoding method and an unsupervised clustering method to slice and extract features from a new chip layout, thereby obtaining single-sample data for training a meta-initialization model. This effectively ensures the representativeness of the features of the obtained single samples and provides reliable training sample data for the subsequent generalization training of the meta-initialization model.

[0076] Furthermore, in the embodiments of this application, photolithographic simulation can be performed on a single sample, and the defect location markers in the single sample can be determined through the photolithographic simulation results, that is, the corresponding classification labels can be obtained.

[0077] Finally, the single samples and corresponding classification labels obtained above can be used to perform generalization training on the meta-initialization model, and the trained meta-initialization model can be used as the chip layout lithography hotspot detection model.

[0078] The method in this application embodiment obtains the most representative feature samples by slicing and extracting features from the new chip layout, and obtains the corresponding classification labels through photolithography simulation to perform generalization training on the meta-initialization model. This improves the generalization performance of the photolithography hotspot detection model under the condition of only requiring a single training sample, and improves the accuracy of photolithography hotspot recognition across chip design layouts.

[0079] Figure 5 (a) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application embodiment with other existing methods under the first benchmark test ("ICCAD2012 Benchmark2"). (b) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application embodiment with other existing methods under the second benchmark test ("ICCAD2012 Benchmark3"). (c) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application embodiment with other existing methods under the third benchmark test ("ICCAD2012 Benchmark4"). (d) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application embodiment with other existing methods under the fourth benchmark test ("ICCAD2012Benchmark5").

[0080] Figure 5 (a) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application embodiment with other existing methods under the first chip layout test ("ICCAD2012 Benchmark2"). (b) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application embodiment with other existing methods under the second chip layout test ("ICCAD2012 Benchmark3"). (c) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application embodiment with other existing methods under the third chip layout test ("ICCAD2012 Benchmark4"). (d) is a schematic diagram comparing the detection results of the lithography hotspot detection model provided in this application embodiment with other existing methods under the fourth chip layout test ("ICCAD2012 Benchmark5").

[0081] Figure 5 In this document, RT represents the retraining method; TL represents the transfer learning method; ADP represents the ADAPT model method; Ours represents the method provided in the embodiments of this application; STD represents the standard deviation; and Mean represents the average value of the experimental results.

[0082] like Figure 5 As shown, the lithographic hotspot detection model provided in this application only uses a single sample for generalization training to obtain its generalization performance. Regardless of the sampling ratio, its generalization efficiency and detection accuracy are better than other existing methods that use more data.

[0083] Figure 6 (a) is a schematic diagram of the hotspot detection performance confusion matrix of the lithography hotspot detection model provided in the embodiments of this application under the first chip layout test ("ICCAD2012 Benchmark2"); (b) is a schematic diagram of the hotspot detection performance confusion matrix of the lithography hotspot detection model provided in the embodiments of this application under the second chip layout test ("ICCAD2012 Benchmark3"); (c) is a schematic diagram of the hotspot detection performance confusion matrix of the lithography hotspot detection model provided in the embodiments of this application under the third chip layout test ("ICCAD2012 Benchmark4"); and (d) is a schematic diagram of the hotspot detection performance confusion matrix of the lithography hotspot detection model provided in the embodiments of this application under the fourth chip layout test ("ICCAD2012 Benchmark5").

[0084] from Figure 6 As can be seen, the lithography hotspot detection model in this application demonstrates good generalization performance across chip layouts, maintaining high detection accuracy for lithography hotspots and low false alarm rate for non-hotspots on different chip layouts. For example, Figure 6 In (a), the confusion matrix is ​​shown after the model training test results. The vertical axis represents the true class of the data, and the horizontal axis represents the predicted class of the model. The experimental results show that the model proposed in this application achieves a detection accuracy of 99% for all hotspot maps and a detection accuracy of 96% for all non-hotspot maps. Figure 6 In (b), the experimental results show that the model proposed in this application achieves a detection accuracy of 95% for all hotspot maps and 98% for all non-hotspot maps, etc.

[0085] The chip layout lithography hotspot detection system based on asynchronous meta-learning provided in this application is described below. The chip layout lithography hotspot detection system based on asynchronous meta-learning described below can be referred to in correspondence with the chip layout lithography hotspot detection method based on asynchronous meta-learning described above.

[0086] Figure 7 This is a schematic diagram of the structure of the chip layout lithography hotspot detection system based on asynchronous meta-learning provided in the embodiments of this application, as shown below. Figure 7 As shown, the system includes: The slicing module 10 is used to slice the new chip layout to be tested, and obtain multiple slices of the new chip layout to be tested. The detection module 20 is used to input multiple slices of the layout to be detected into the chip layout lithography hot spot detection model, and obtain the lithography hot spot detection result of the new chip layout output by the chip layout lithography hot spot detection model; The chip layout lithography hotspot detection model is obtained by training the meta-initialization model with a single sample using the new chip layout; the meta-initialization model is obtained by meta-training based on the old chip layout samples and their corresponding classification label sets.

[0087] It is understood that the detailed functional implementation of each of the above units / modules can be found in the description in the aforementioned method embodiments, and will not be repeated here.

[0088] It should be understood that the above system is used to execute the methods in the above embodiments. The corresponding program modules in the system are similar in implementation principle and technical effect to those described in the above methods. The working process of the system can be referred to the corresponding process in the above methods, and will not be repeated here.

[0089] The chip layout lithography hotspot detection system based on asynchronous meta-learning in this application adopts a strategy of using a meta-initialized model trained on old chip layout samples and a single-sample sampling of new chip layout topology. By using the meta-initialized model trained on old chip layout samples for generalization training on a single sample of the selected new chip layout to be detected, the system can greatly improve the generalization performance of the chip layout lithography hotspot detection model. It achieves effective detection of lithography hotspots across chip design layouts with only a single training sample, improves the accuracy of cross-chip design layout lithography hotspot detection, reduces the false alarm rate, and effectively overcomes the generalization failure problem caused by differences in chip layout design in existing methods.

[0090] Based on the methods in the above embodiments, this application provides an electronic device, such as... Figure 8 As shown, the electronic device may include a processor 810, a communications interface 820, a memory 830, and a communication bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other via the communication bus 840. The processor 810 can call logical instructions in the memory 830 to execute the methods in the above embodiments.

[0091] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0092] Based on the methods in the above embodiments, this application provides a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0093] Based on the methods in the above embodiments, this application provides a computer program product that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0094] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0095] The method steps in this application embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0096] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0097] It is understood that the various numerical designations used in the embodiments of this application are merely for the convenience of description and are not intended to limit the scope of the embodiments of this application.

[0098] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip layout lithography hotspot detection method based on asynchronous meta-learning, characterized in that, include: The new chip layout to be tested is sliced ​​to obtain multiple layout slices corresponding to the new chip layout; The multiple slices of the layout to be detected are input into the chip layout lithography hot spot detection model to obtain the lithography hot spot detection result of the new chip layout output by the chip layout lithography hot spot detection model; The chip layout lithography hotspot detection model is obtained by training the meta-initialization model with a single sample using the new chip layout; the meta-initialization model is obtained by meta-training based on old chip layout samples and their corresponding classification label sets; the single sample is the most representative feature sample extracted from the new chip layout through topological coding, principal component analysis and cluster sampling. The method further includes, prior to inputting the plurality of lithography hotspot slices to be detected into the chip layout lithography hotspot detection model and obtaining the lithography hotspot detection result of the new chip layout output by the chip layout lithography hotspot detection model: Each of the old chip layout samples and its corresponding classification label set is divided into a support set and a query set; An asynchronous update strategy is adopted, and the basic detection model is iteratively trained using the support set and query set corresponding to each old chip layout sample to obtain a trained basic detection model, and the trained basic detection model is used as the meta-initialization model. The meta-initialization model is trained using the new chip layout with a single sample to obtain the chip layout lithography hotspot detection model. The basic detection model includes a feature extractor and a classifier; during model training using the support set, the network parameters of the feature extractor are updated with a first learning rate, and the network parameters of the classifier are updated with a second learning rate; the first learning rate is less than the second learning rate. The method for obtaining a single sample is as follows: The new chip layout is sliced ​​to obtain multiple layout slices corresponding to the new chip layout; Each of the aforementioned map slices is encoded to determine a first topological feature vector corresponding to each of the aforementioned map slices; Principal component analysis is performed on the first topological feature vectors corresponding to all slices to obtain the second topological feature vectors corresponding to each slice. Cluster analysis is performed based on the second topological feature vector corresponding to each slice to obtain a single sample corresponding to the new chip layout.

2. The chip layout lithography hotspot detection method according to claim 1, characterized in that, The asynchronous update strategy is adopted, and the basic detection model is iteratively trained using the support set and query set corresponding to each old chip layout sample to obtain a trained basic detection model, including: The model parameters of the basic detection model are initialized to obtain the initialized model; For each of the old chip layout samples, the initialization model is iteratively trained using its respective support set to obtain its corresponding intermediate model. The intermediate model is then iteratively trained using its respective query set. During the process, the network parameters of the initialization model are updated by calculating the loss gradient until the initialization model after training is obtained. The initial model after training is used as the trained base detection model.

3. The chip layout lithography hotspot detection method according to claim 2, characterized in that, The feature extractor includes multiple feature extraction modules connected in sequence, and each feature extraction module includes an Inception module and a CBAM attention module connected in sequence; the classifier includes a fully connected layer.

4. The chip layout lithography hotspot detection method according to claim 1, characterized in that, The step of using the new chip layout to perform single-sample training on the meta-initialization model to obtain the chip layout lithography hotspot detection model includes: Based on the new chip layout, slices and feature extraction are performed to obtain a single sample corresponding to the new chip layout; Photolithographic simulation is performed on the single sample to determine the classification label corresponding to the single sample; The meta-initialization model is trained using the single sample and its corresponding classification label, and the trained meta-initialization model is used as the chip layout lithography hotspot detection model.

5. The chip layout lithography hotspot detection method according to claim 1, characterized in that, The step of encoding each of the layout slices to determine the first topological feature vector corresponding to each layout slice includes: According to a preset size, each of the layout slices is evenly divided into multiple grid units, so that each grid unit contains at most one metal layer wiring; Determine the width and spacing of the metal layer wiring in each of the aforementioned grid cells; The encoding results of each grid cell in each of the layout slices are obtained by encoding the metal layer wiring width as a positive value and the spacing size as a negative value. The encoding results of each grid cell in each of the layout slices are combined according to the topological structure to obtain the first topological feature vector corresponding to each layout slice.

6. A chip layout lithography hotspot detection system based on asynchronous meta-learning, characterized in that, include: The slicing module is used to slice the new chip layout to be tested, thereby obtaining multiple slices of the new chip layout to be tested. The detection module is used to input the multiple slices of the layout to be detected into the chip layout lithography hot spot detection model, and obtain the lithography hot spot detection result of the new chip layout output by the chip layout lithography hot spot detection model; The chip layout lithography hotspot detection model is obtained by training the meta-initialization model with a single sample using the new chip layout; the meta-initialization model is obtained by meta-training based on old chip layout samples and their corresponding classification label sets; the single sample is the most representative feature sample extracted from the new chip layout through topological coding, principal component analysis and cluster sampling. The method further includes, before inputting the plurality of lithography hotspot slices to be detected into the chip layout lithography hotspot detection model and obtaining the lithography hotspot detection result of the new chip layout output by the chip layout lithography hotspot detection model: Each of the old chip layout samples and its corresponding classification label set is divided into a support set and a query set; An asynchronous update strategy is adopted, and the basic detection model is iteratively trained using the support set and query set corresponding to each old chip layout sample to obtain a trained basic detection model, and the trained basic detection model is used as the meta-initialization model. The meta-initialization model is trained using the new chip layout with a single sample to obtain the chip layout lithography hotspot detection model. The basic detection model includes a feature extractor and a classifier; during model training using the support set, the network parameters of the feature extractor are updated with a first learning rate, and the network parameters of the classifier are updated with a second learning rate; the first learning rate is less than the second learning rate. The method for obtaining a single sample is as follows: The new chip layout is sliced ​​to obtain multiple layout slices corresponding to the new chip layout; Each of the aforementioned map slices is encoded to determine a first topological feature vector corresponding to each of the aforementioned map slices; Principal component analysis is performed on the first topological feature vectors corresponding to all slices to obtain the second topological feature vectors corresponding to each slice. Cluster analysis is performed based on the second topological feature vector corresponding to each slice to obtain a single sample corresponding to the new chip layout.

7. An electronic device, characterized in that, include: At least one memory for storing computer programs; At least one processor is configured to execute a program stored in the memory, wherein when the program stored in the memory is executed, the processor is configured to perform the method as described in any one of claims 1-5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is run on the processor, it causes the processor to perform the method as described in any one of claims 1-5.

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