Display device

Abstract

The invention discloses a display device. The display device comprises a gate driving circuit (GOA), a driving chip and a display panel, the gate driving circuit is composed of a plurality of gate driving sub-circuits, and each gate driving sub-circuit comprises a first control switch and a plurality of cascaded gate driving units. The first control switch is connected between the input end of the first-stage gate driving unit in the plurality of gate driving units and a frame starting line for transmitting a frame starting signal, so that the input end of the first-stage gate driving unit is electrically connected or disconnected with the frame starting line through the control of the first control signal. And the tail-stage gate driving unit of the plurality of gate driving units connected in series is connected with the driving chip. For each gate driving sub-circuit, the driving chip detects whether a level transmission link of the gate driving sub-circuit is abnormal or not according to whether a tail-level gate driving unit feeds back a return signal or not. The GOA is divided into a plurality of groups, and the group with the abnormal level transmission link can be judged according to whether the return signal is fed back or not.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display device. Background Technology

[0002] As automobiles become increasingly intelligent, displays are playing a more crucial role in vehicle operation, serving functions such as information display and vehicle control. Currently, some displays employ a gate-driven array (GOA) architecture. Based on this architecture, in extreme situations, such as impacts or the end of its lifespan, if any stage of the GOA fails, subsequent displays may fail, or certain important information display areas may become fixed. Damage to a single stage can result in incomplete display, preventing the display of crucial information and impairing some vehicle functions. For example, it may prevent the display of current speed, thus failing to alert the driver to vehicle speed, increasing the risk of speeding, and potentially even leading to serious accidents. Summary of the Invention

[0003] This application provides a display device that divides the GOA into multiple groups, each group working independently, and can also determine whether the cascading link in each group of GOA is abnormal based on whether the driver chip included in the display device receives a feedback signal.

[0004] The display device provided in this application includes: a gate driving circuit, a driving chip, and a display panel, wherein: the gate driving circuit includes a plurality of gate driving sub-circuits; the gate driving sub-circuit includes: a first control switch and a plurality of cascaded gate driving units; wherein, the first control switch is connected between the input terminal of the first-stage gate driving unit in the plurality of cascaded gate driving units and a frame start line for transmitting a frame start signal, so as to connect or disconnect the electrical connection between the input terminal of the first-stage gate driving unit and the frame start line according to a first control signal; the tail-stage gate driving unit in the plurality of cascaded gate driving units is connected to the driving chip; each gate driving unit is connected to a pixel unit in the display panel through a gate line, for transmitting a scan signal to the pixel unit through the gate line to turn on the pixel unit; for each gate driving sub-circuit, the driving chip detects whether the cascade link of the gate driving sub-circuit is abnormal according to whether the tail-stage gate driving unit feeds back a feedback signal.

[0005] This application provides a display device by dividing a gate driving circuit into multiple gate driving sub-circuits. Each gate driving sub-circuit includes a first control switch and multiple cascaded gate driving units. The first control switch is connected between the input terminal of the first-stage gate driving unit of the cascaded gate driving units and the frame start transmission line, and the electrical connection between the input terminal of the first-stage gate driving unit and the frame start line is connected or disconnected according to a first control signal. The tail-stage gate driving unit of the cascaded gate driving units is connected to a driver chip. In the display device provided by this application, for each gate driving sub-circuit, the driver chip detects whether the cascaded link of the gate driving sub-circuit is abnormal based on whether the tail-stage gate driving unit of the corresponding gate driving sub-circuit feeds back a feedback signal. This allows the display panel to continue displaying normally even after a portion of it is damaged, and also enables rapid location of the damaged area. Attached Figure Description

[0006] The present application will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for explaining some embodiments of the present application. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0007] Figure 1 This is an exemplary schematic diagram of a damaged display panel in a display device in the related art.

[0008] Figure 2 This is an exemplary block diagram of a display device provided in an embodiment of this application.

[0009] Figure 3 This is an exemplary block diagram of the gate driving sub-circuit provided in an embodiment of this application.

[0010] Figure 4 This is a schematic diagram showing the connection relationship between the display panel, the gate driving circuit, and the driving chip in the display device provided in the embodiments of this application.

[0011] Figure 5 Provided for the embodiments of this application Figure 4 Exemplary timing diagrams of each signal Figure 1 .

[0012] Figure 6 Provided for the embodiments of this application Figure 4 Exemplary timing diagrams of various signals Figure 2 .

[0013] Figure 7 This is a schematic diagram of an exemplary circuit structure for detecting abnormal data transmission paths provided in an embodiment of this application.

[0014] Figure 8 This is a schematic diagram showing the available display area and the damaged display area provided in the embodiments of this application.

[0015] Figure 9 An exemplary schematic diagram showing image data displayed in the original display area for embodiments of this application.

[0016] Figure 10 An exemplary schematic diagram showing image data provided in an embodiment of this application displayed in an available display area. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to these processes, methods, products, or devices.

[0019] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0020] The display device provided in this application may include, but is not limited to, the following embodiments and combinations thereof.

[0021] See Figure 1The display device 100 shown includes a driver chip, a gate driving circuit, and a display panel containing a display area. The gate driving circuit may include gate driving circuit 1 and gate driving circuit 2 forming a dual-sided driving architecture, with a step-by-step transmission architecture. Under this transmission architecture, if the display panel suffers damage (becoming a damaged display area) to the display area corresponding to a certain stage of the gate driving unit in gate driving circuit 1 and gate driving circuit 2 due to an impact, the display areas corresponding to subsequent stage gate driving units will also be unable to display. For example, as... Figure 1 As shown, from top to bottom, if the original display area of ​​the display panel is damaged, the display area near the driver chip within that original display area will also fail to display. Therefore, if the display device installed in a car experiences this problem, it will result in the inability to obtain important information, leading to impaired vehicle functionality. For example, if critical driving information such as navigation information cannot be displayed, the driver will be unable to obtain route guidance when driving on unfamiliar roads, potentially leading to getting lost or experiencing delays. Furthermore, the inability to display the current vehicle speed affects the driver's control of the vehicle's speed, increasing the risk of speeding. Another example is the malfunction of warning lights, such as the brake system warning light not illuminating, causing the driver to overlook potential mechanical problems, increasing driving risks.

[0022] Based on this, this application provides a display device that divides the GOA (Graphical Object Assemblies) into multiple groups. Each group of GOAs can operate independently through control. Furthermore, it can determine whether the cascading link in each group of GOAs is abnormal based on whether the driver chip receives a feedback signal, allowing for rapid identification of which group of GOAs is malfunctioning. Further, by combining the subsequent determination of abnormal data transmission paths, the damaged display area and the usable display area in the original display area of ​​the display panel are obtained. Image data is displayed in the usable display area to ensure normal operation even after the display area is damaged.

[0023] Specifically, see Figure 2 and Figure 3 As shown, Figure 2 As shown, the display device 200 may include a gate driving circuit 201, a driving chip 202, and a display panel 203. The gate driving circuit 201 may include multiple gate driving sub-circuits 2011. Each gate driving sub-circuit 2011 has a gate driving unit connected to a pixel unit in the display panel 203 via a gate line, used to transmit a scan signal to the pixel unit through the gate line to activate the pixel unit. The driving chip 202 may be connected to each of the multiple gate driving sub-circuits 2011 in the gate driving circuit 201. The driving chip 202 may also be connected to the pixel unit in the display panel 203 via a data line, used to provide data voltage to the pixel unit through the data line. The display panel 203 may include, but is not limited to, a liquid crystal display panel or a self-emissive display panel.

[0024] Among them, such as Figure 3 As shown, the gate driving sub-circuit 2011 may include: a first control switch 301 and a plurality of cascaded gate driving units 302-1 to 302-n; wherein, the first control switch 301 is connected between the input terminal of the first-stage gate driving unit 302-1 among the cascaded gate driving units 302-1 to 302-n and the frame start line for transmitting the frame start signal STV, so as to connect or disconnect the electrical connection between the input terminal of the first-stage gate driving unit 302-1 and the frame start line according to a first control signal. In one exemplary implementation, the first control switch 301 may connect the electrical connection between the input terminal of the first-stage gate driving unit and the frame start line in response to a first level of the first control signal, and disconnect the electrical connection between the input terminal of the first-stage gate driving unit and the frame start line in response to a second level of the first control signal.

[0025] In one optional implementation, the first control switch 301 is an N-type transistor, and the first voltage level is high. Under the control of the high voltage level, the first control switch 301 is turned on to connect the electrical connection between the input terminal of the first-stage gate driving unit 302-1 and the frame start line. Correspondingly, the second voltage level is low. Under the control of the low voltage level, the first control switch 301 is turned off to disconnect the electrical connection between the input terminal of the first-stage gate driving unit 302-1 and the frame start line.

[0026] In another alternative implementation, the first control switch 301 is a P-type transistor, and the first level is low. Under the control of the low level, the first control switch 301 is turned on to connect the electrical connection between the input terminal of the first-stage gate driving unit 302-1 and the frame start line. Correspondingly, the second level is high, and under the control of the high level, the first control switch 301 is turned off to disconnect the electrical connection between the input terminal of the first-stage gate driving unit 302-1 and the frame start line.

[0027] In this embodiment, GOAs are grouped to form multiple GOA groups (i.e., multiple gate driver sub-circuits). A frame start line is set in each GOA group, and a first control switch is set at the input terminal of the first-stage gate driver unit in the corresponding GOA group. This first control signal controls the connection and disconnection between the frame start line and the first-stage gate driver unit. With this design, the driver chip can achieve zoned control of the display panel by controlling the timing of the first control signals corresponding to each GOA group. Furthermore, the input terminals of the first-stage gate driver units of multiple GOA groups are connected to the frame start signal. When the first control switch is on, the activation control signal for each GOA group is the frame start signal, allowing the GOAs to operate independently. This ensures that if any one GOA group fails, the remaining GOA groups can still function normally.

[0028] See back Figure 3 As shown, the tail-stage gate driving unit 302-n of the cascaded gate driving units 302-1 to 302-n is connected to the driving chip 202, and as described above, each gate driving unit is connected to a pixel unit in the display panel 203 via a gate line, for transmitting a scan signal to the pixel unit through the gate line to activate the pixel unit. In some embodiments, such as Figure 3 As shown, the gate driving sub-circuit 2011 may further include a second control switch 303. The second control switch 303 is connected between the tail-stage gate driving unit 302-n and the driving chip 202 to connect or disconnect the electrical connection between the tail-stage gate driving unit 302-n and the driving chip 202 according to a second control signal. That is, the aforementioned tail-stage gate driving unit 302-n and the driving chip 202 can be directly connected or indirectly connected through the second control switch 303.

[0029] In the case where the aforementioned tail-stage gate driving unit 302-n is connected to the driving chip 202 via a second control switch 303, the second control switch 303 can be a transistor of the same type as the first control switch 301, or a transistor of a different type. If the second control switch 303 and the first control switch 301 are transistors of the same type, then the second control switch responds to the first level of the second control signal to connect the electrical connection between the tail-stage gate driving unit and the driving chip, and responds to the second level of the second control signal to disconnect the electrical connection between the tail-stage gate driving unit and the driving chip. The first level here can also be a low level or a high level, and correspondingly, the second level can also be a high level or a low level; this can be referred to the previous understanding and will not be repeated here.

[0030] Based on the foregoing, such as Figure 3 As shown, in the display device 200, for each gate driving sub-circuit 2011, the driving chip 202 can detect whether the cascading link of the gate driving sub-circuit is abnormal based on whether the tail-stage gate driving unit 302-n sends back a feedback signal. Specifically, if the electrical connection between the input terminal of the first-stage gate driving unit 302-1 and the frame start line is connected, and the electrical connection between the tail-stage gate driving unit 302-n and the driving chip 202 is connected, and the driving chip 202 does not receive the feedback signal from the tail-stage gate driving unit 302-n, then the cascading link of the gate driving sub-circuit 2011 is abnormal. If the driving chip 202 receives the feedback signal from the tail-stage driving unit 302-n, then the cascading link of the gate driving sub-circuit 2011 is in normal working condition. In some embodiments, the feedback signal can be a cascading signal output by the tail-stage gate driving unit or a scan signal output by the tail-stage gate driving unit.

[0031] In this embodiment, by setting a second control switch between the tail gate drive unit and the drive chip in each group of GOAs, the drive chip can determine whether the cascading link of that group of GOAs is abnormal by monitoring in real time whether a feedback signal is received. Specifically, when both the first and second control switches are closed (or turned on), if the drive chip receives a feedback signal, it determines that the cascading link of that group of GOAs is in normal working condition; if the drive chip does not receive a feedback signal, it determines that the cascading link of that group of GOAs is abnormal. With this design, the drive chip can quickly locate which group of GOAs has an abnormal cascading link by controlling the timing of the second control signals corresponding to each group of GOAs and determining when a feedback signal is not received.

[0032] To understand the above scheme, for example, as follows: Figure 4 The diagram illustrates an exemplary connection relationship between the driver chip, gate drive circuit, and display panel in a display device provided in this embodiment. Figure 4 In this diagram, SW1 is the first control signal. STV is the frame start signal. CK is the clock signal. SW2 is the second control signal. GOA1 to GOAn are N gate drive sub-circuits, respectively. VT1 to VTn are the feedback signals corresponding to the N gate drive sub-circuits, respectively. line11 to linen1 are the n gate lines in GOA1, and so on, with line1n to linenn being the n gate lines in GOAn. VTx is one of VT1 to VTn. This example uses N-type transistors as both the first and second control switches.

[0033] It should be noted that, Figure 4The diagram shows a separate arrangement of the gate driving circuit 201 and the display panel 203, but this embodiment does not limit the specific structure or composition of the display panel. In other embodiments, the gate driving circuit 201 may also be integrated into the display panel 203, and this embodiment does not specifically limit this.

[0034] Based on this, when SW1 and STV are both high, the first control switch is turned on, and the first-stage gate drive unit of the GOA in this group can receive STV. Therefore, the GOA cascading is enabled, meaning the GOA in this group starts working. If SW2 is high, the second control switch is turned on. If the driver chip 202 receives a feedback signal VTx, then the GOA cascading link in this group is normal. If the driver chip 202 does not receive the feedback signal VTx, then the GOA cascading link in this group is abnormal.

[0035] For example, such as Figure 5 and Figure 6 As shown, where, Figure 5 When all cascade links of each GOA group are normal. Figure 4 The timing sequence of each signal in the process. Figure 6 This indicates that there is an anomaly in the cascade link of GOA2 in each group of GOAs. Figure 4 The timing sequence of each signal in the sequence. Assume... Figure 4 The gate driver sub-circuits shown are turned on sequentially from top to bottom. Therefore, as follows... Figure 5 As shown, STV, SW1, and SW2 corresponding to GOA1 to GOAn are applied sequentially. In this case, as... Figure 5 As shown, if the driver chip can receive the feedback signal from each group of GOAs, it indicates that the cascading link of each group of GOAs is in normal condition. Figure 6 As shown, if the driver chip does not receive the feedback signal from GOA2 (VT2, represented by the dashed line, is not received), it indicates that there is an abnormality in the GOA2 cascade link.

[0036] In practical applications, a display panel may include a pixel array, wherein the pixel array comprises multiple pixel units PX arranged in rows and columns, forming multiple pixel rows arranged along the row direction and multiple pixel columns arranged along the column direction. Each pixel row and each pixel column includes multiple pixel units. For ease of description, the pixel rows and pixel columns may also be simply referred to as "rows" and "columns" thereafter. In this application, the first direction can be, exemplarily, the row direction or column direction mentioned herein; correspondingly, the second direction can be, exemplarily, the column direction or the row direction. This application takes the first direction as the column direction and the second direction as the row direction as an example. That is, the gate line is connected to each pixel unit in at least one pixel row, and the data line is connected to each pixel unit in at least one pixel column. Based on this, the aforementioned gate line arranged along the first direction is, exemplarily, arranged along the column direction. The aforementioned data line arranged along the second direction is, exemplarily, arranged along the row direction, wherein the first direction and the second direction are perpendicular.

[0037] Based on this, in order to locate the damaged display area and the usable display area of ​​the display panel, the driver chip also needs to perform the following operations. First, the aforementioned driver chip can also be used to detect the charging time of the data line voltage to the data voltage, and when the charging time is not within the preset charging time range, it is determined that the data transmission path between the driver chip and the pixel unit is abnormal; the data transmission path is the transmission path through which the driver chip provides data voltage to the pixel unit.

[0038] As an optional implementation, the driver chip may include a comparator circuit and a controller. The comparator circuit may include a first input terminal connected to the data line, a second input terminal for connecting a reference voltage, and an output terminal connected to the controller; the reference voltage is equal to the data voltage. The controller may sample the output signal of the comparator circuit and determine the charging time based on the sampling result; and determine whether the data transmission path between the driver chip and the pixel unit is abnormal based on the charging time and the preset charging time range.

[0039] It should be noted that in the display field, the driver chip can be a general term for the control chips that drive the display panel in a display device. These chips can include source driver chips (Source ICs), timing control chips (TCONs), and power management chips (PMICs), among other modules. The data transmission path described above is essentially the path through which the Source IC provides data voltage to the pixel units via data lines. Here, the charging time refers to the time required for the voltage on the data line to reach the data voltage provided by the Source IC. In practical applications, if an open circuit occurs in the data transmission path (e.g., a broken line or a cold solder joint), the effective load capacitance (C) decreases significantly, leading to a faster charging speed and a shorter charging time than when the data transmission path is normal. If a short circuit occurs in the data transmission path, most of the current is diverted by the short circuit, resulting in a smaller current in the circuit. It takes a very long time for the voltage to rise to the required data voltage, or even longer, than when the data transmission path is normal. The comparison circuit can be a comparator.

[0040] Based on this, the above determination process can be understood in the following logical order:

[0041] First, one input terminal of the comparator is connected to the data line, the other input terminal is connected to the reference voltage, and the output terminal outputs the comparison result between the voltage of the data line and the reference voltage.

[0042] Secondly, the controller samples the comparison result and calculates the time in the comparator's output signal between the jump from digit 1 to digit 0 and between the jump from digit 0 to digit 1, which is the charging time; or, the controller calculates the time in the output signal between the jump from digit 0 to digit 1 and between the jump from digit 1 to digit 0, which is the charging time.

[0043] Next, after obtaining the charging time, it is determined whether the charging time is within a preset charging time range. If the detected charging time is not within the preset charging time range, it is determined that the data transmission path between the driver chip and the pixel unit is abnormal. If the charging time is within the preset charging time range, it is determined that the data transmission path between the driver chip and the pixel unit is normal. The preset charging time range can be calculated based on empirical values.

[0044] For example, such as Figure 7 The diagram illustrates an exemplary circuit connection diagram for determining whether a data transmission path is abnormal, provided in an embodiment of this application. Figure 7 This refers to the detection of the data transmission path between a pixel unit in the liquid crystal display panel and the driver chip 202. REF The data voltage. The voltage connected to the comparator on the data line and V.REF And based on the voltage of the data line and V REF The difference between the two values ​​outputs either a digit 1 or a digit 0. The controller acquires the comparator's output signal and determines the charging time based on the acquisition result. One calculation method is to assume the comparator's initial output is digit 0, and then calculate the charging time as the time between the transition from digit 0 to digit 1 and then back to digit 0 in the output signal. Another optional calculation method is to assume the comparator's initial output is digit 1, and then calculate the charging time as the time between the transition from digit 1 to digit 0 and then back to digit 1 in the output signal. After this, the controller determines whether the data transmission path between the driver chip and the pixel unit is abnormal based on the charging time and the preset charging time range. The specific determination process has been shown and described previously and will not be repeated here.

[0045] Secondly, the driving chip 202 can also be used to determine the damaged display area and the usable display area of ​​the display panel 203 based on the abnormal gate driving sub-circuit and abnormal data transmission path of the cascade link, and display the image data through the usable display area.

[0046] It should be noted that both the damaged display area and the usable display area of ​​the display panel are part of the original display area of ​​the display panel. Specifically, the driver chip 202 can also be used to: determine the first damage coordinates of the display panel in the first direction based on the abnormal gate driver sub-circuit, and determine the second damage coordinates of the display panel in the second direction based on the abnormal data transmission path; determine the damaged display area based on the first damage coordinates and the second damage coordinates; and determine the usable display area based on the damaged display area.

[0047] It should be noted that, based on the foregoing, the gate driving sub-circuit includes multiple cascaded gate driving units, each gate driving unit being connected to at least one pixel row. Therefore, the first damage coordinates can include the row coordinates of the multiple pixel rows connected to at least one gate driving sub-circuit. Similarly, since the data line connects to at least one pixel column, the second damage coordinates can include the column coordinates of the pixel column connected to at least one data transmission path by the data line. After obtaining the row and column coordinates, a geometric range is obtained based on these coordinates, and the display area corresponding to this geometric range is the damaged display area. Then, the usable display area is obtained based on the original display area of ​​the display panel and the calculated damaged display area. This usable display area can be all or part of the remaining display area in the original display area of ​​the display panel, excluding the damaged display area. For example, the usable display area can be the largest display area among the remaining display areas.

[0048] For example, such as Figure 8 As shown, assume that 1, 2, 3, 4, ..., m are m data lines, and 1, 2, 3, 4, ..., n are n gate lines. Figure 8 The small grid shown represents one pixel unit. Figure 8 The original display area of ​​the shown display panel contains m*n pixel units. Assuming the first damaged coordinate of the damaged display area includes row coordinates 2 and 3, and the second damaged coordinate includes column coordinates 2 and 3, then the geometric range formed by combining the row and column coordinates is a rectangular area with vertices (2, 2), (2, 3), (3, 2), and (3, 3). The display area corresponding to this rectangular area is the damaged display area. Then, within the original display area of ​​the display panel, a rectangular area with vertices (4, 4), (4, n), (m, 4), and (m, n) is calculated. The display area corresponding to this rectangular area is the usable display area.

[0049] It should be noted that, Figure 8 This example only illustrates one way to determine the available display area. In actual gate drive circuits, a gate drive sub-circuit may contain more than two gate drive units, and there may be more than one abnormal gate drive unit. Therefore, there may be more than two row coordinates involved in calculating the damaged display area, but the calculation method is similar, and will not be illustrated here.

[0050] After obtaining the available display area of ​​the display panel, the driver chip 202 can display image data through the available display area. Specifically, the driver chip can also be used to obtain a first adjustment ratio in the first direction and a second adjustment ratio in the second direction based on the first resolution of the display panel and the second resolution of the available display area; and to display the image data through the available display area based on the first adjustment ratio and the second adjustment ratio.

[0051] It should be noted that the first resolution can refer to the resolution of the original display area of ​​the display panel, such as the one mentioned above. Figure 8 The m*n figure shows a second resolution, which can be the product of the number of pixel units in a pixel row and the number of pixels in a pixel column of the available display area. This resolution characterizes the number of pixels within the available display area, for example, as mentioned above. Figure 8The figure shows (m-4)*(n-4). The first adjustment ratio can be the ratio between (m-4) corresponding to the available display area and m corresponding to the original display area of ​​the display panel. The second adjustment ratio can be the ratio between (n-4) corresponding to the available display area and n corresponding to the original display area of ​​the display panel. Then, combining the first and second adjustment ratios, the image data to be displayed in the original display area is scaled according to the first and second adjustment ratios before being displayed in the available display area. This ensures that the adjusted image is correctly distributed to each pixel position in the available display area, guaranteeing the consistency and accuracy of the display effect. For example, as shown... Figure 9 and Figure 10 As shown. Figure 9 An exemplary schematic diagram showing image data displayed in the original display area for embodiments of this application. Figure 10 An exemplary schematic diagram showing image data provided in an embodiment of this application displayed in an available display area. Figure 9 The large pentagram shown is the image displayed in the original display area based on the image data. Figure 10 The small five-pointed star shown is the image displayed in the available display area based on the image data.

[0052] The display device provided in this application provides a way to easily locate which group of GOAs has an abnormal transmission link by grouping GOAs and setting a first control switch and a second control switch in each group of GOAs. Furthermore, the abnormal data transmission path is quickly located using a comparison circuit and a controller. Then, based on the row coordinates of the pixel units connected to the abnormal GOA and the column coordinates of the pixel units connected to the data lines in the abnormal data transmission path, the damaged display area and the usable display area in the display panel are obtained. Finally, the image data is displayed in the usable display area. With this design, even if one group of GOAs is damaged, the remaining groups of GOAs can still function normally. The damaged GOA can report to the driver chip via a feedback signal. Combined with the driver chip's detection settings for the data transmission path, the damaged display area of ​​the screen can be identified, and the image data to be displayed can be transferred to the normally usable display area, thus enabling the screen to continue displaying normally even after damage. The display device provided in this application reduces the risk of the entire device being scrapped due to partial failures through dynamic adjustment and optimization, and ensures that image quality and display effect remain optimal under various display conditions.

[0053] The display device provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device, characterized in that, include: Gate driving circuit, driving chip, and display panel, wherein; The gate driving circuit includes multiple gate driving sub-circuits; The gate driving sub-circuit includes: a first control switch and a plurality of cascaded gate driving units; wherein, the first control switch is connected between the input terminal of the first-stage gate driving unit in the plurality of cascaded gate driving units and a frame start line for transmitting a frame start signal, so as to connect or disconnect the electrical connection between the input terminal of the first-stage gate driving unit and the frame start line according to the first control signal. The tail gate driving unit in the cascaded plurality of gate driving units is connected to the driving chip; each gate driving unit is connected to a pixel unit in the display panel through a gate line, for transmitting a scan signal to the pixel unit through the gate line to turn on the pixel unit; For each gate driver sub-circuit, the driver chip detects whether the cascade link of the gate driver sub-circuit is abnormal based on whether the tail-stage gate driver unit feeds back a feedback signal.

2. The display device according to claim 1, characterized in that, The gate driving sub-circuit further includes: a second control switch, which is connected between the tail gate driving unit and the driving chip to connect or disconnect the electrical connection between the tail gate driving unit and the driving chip according to a second control signal; Wherein, if the electrical connection between the input terminal of the first-stage gate driving unit and the frame start line is connected, and the electrical connection between the tail-stage gate driving unit and the driving chip is connected, and the driving chip does not receive the feedback signal from the tail-stage gate driving unit, then the cascading link of the gate driving sub-circuit is abnormal.

3. The display device according to claim 2, characterized in that, The first control switch connects the electrical connection between the input terminal of the first gate driving unit and the frame start line in response to a first level of the first control signal, and disconnects the electrical connection between the input terminal of the first gate driving unit and the frame start line in response to a second level of the first control signal. The second control switch connects the electrical connection between the tail gate driving unit and the driving chip in response to the first level of the second control signal, and disconnects the electrical connection between the tail gate driving unit and the driving chip in response to the second level of the second control signal.

4. The display device according to claim 1 or 2, characterized in that, The feedback signal is the stage transmission signal or scan signal output by the tail stage gate drive unit.

5. The display device according to claim 1 or 2, characterized in that, The driver chip is connected to the pixel unit via a data line and is used to provide data voltage to the pixel unit through the data line. The driver chip is also used to detect the charging time from the voltage of the data line to the data voltage, and when the charging time is not within a preset charging time range, it is determined that the data transmission path between the driver chip and the pixel unit is abnormal. The data transmission path is the transmission path through which the driver chip provides data voltage to the pixel unit.

6. The display device according to claim 5, characterized in that, The driver chip includes: a comparator circuit and a controller; wherein... The comparator circuit includes a first input terminal connected to the data line, a second input terminal for receiving a reference voltage, and an output terminal connected to the controller; the voltage value of the reference voltage is equal to the voltage value of the data voltage. The controller is used to sample the output signal of the output terminal of the comparison circuit and determine the charging time based on the sampling result; and to determine whether the data transmission path between the driver chip and the pixel unit is abnormal based on the charging time and the preset charging time range.

7. The display device according to claim 5, characterized in that, The driving chip is also used to determine the damaged display area and the usable display area of ​​the display panel based on the abnormal gate driving sub-circuit and abnormal data transmission path of the cascade link, and to display the image data through the usable display area.

8. The display device according to claim 7, characterized in that, The display device includes a plurality of gate lines arranged along a first direction and a plurality of data lines arranged along a second direction, wherein the first direction is perpendicular to the second direction; wherein, The driver chip is also used for: The first damage coordinate of the display panel in the first direction is determined based on the abnormal gate driving sub-circuit, and the second damage coordinate of the display panel in the second direction is determined based on the abnormal data transmission path. The damage display area is determined based on the first damage coordinate and the second damage coordinate; and The available display area is determined based on the damaged display area.

9. The display device according to claim 8, characterized in that, The driver chip is also used for: A first adjustment ratio in the first direction and a second adjustment ratio in the second direction are obtained based on the first resolution of the display panel and the second resolution of the available display area; as well as The image data is displayed through the available display area according to the first adjustment ratio and the second adjustment ratio.

10. The display device according to claim 7, characterized in that, The display panel includes a liquid crystal display panel or a self-emissive display panel.

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