Dual-process memory cell and method of making same, array of dual-process memory cells, dual-process memory, and chip

Abstract

The present disclosure relates to the technical field of storage, and particularly relates to a dual-process storage unit, a preparation method of the dual-process storage unit, a dual-process storage unit array, a dual-process memory and a chip. The dual-process storage unit comprises a first storage unit and a second storage unit based on two different processes. The anti-magnetic interference capability of the first storage unit is less than that of the second storage unit, and the anti-erase-write capability of the first storage unit is greater than that of the second storage unit. When the first storage unit is in a data read-write active state and external magnetic field interference satisfies a first switching condition, the data read-write operation is switched to the second storage unit, and the data in the first storage unit is written into the second storage unit; when the second storage unit is in a data read-write active state and external magnetic field interference satisfies a second switching condition, the data read-write operation is switched back to the first storage unit, and the data in the second storage unit is written into the first storage unit. Thus, the limitation of a single storage technology is solved, external magnetic field interference is resisted, and high durability demand is met.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, specifically to a dual-process storage cell and its fabrication method, a dual-process storage cell array, a dual-process memory, and a chip. Background Technology

[0002] With the rapid development of information technology, the demand for data storage is growing exponentially, and the performance requirements for memory are also increasing. Traditional memory technologies, such as magnetoresistive random access memory (MRAM) and flash memory, although they dominate the market, have certain limitations in terms of durability, read / write speed, and anti-interference capabilities.

[0003] Among them, magnetoresistive random access memory (MRAM), as a novel type of memory combining the high-speed read / write capability of static random access memory (SRAM) and the high density and non-volatility of dynamic random access memory (DRAM), has received widespread attention and research. MRAM memory cells are mainly composed of magnetic tunnel junctions (MTJs). The MTJ has a unique structure; its core consists of two layers of ferromagnetic material (a "free" ferromagnetic layer and a "pinned" ferromagnetic layer) sandwiching an extremely thin insulating shielding layer (such as magnesium oxide or aluminum oxide). This structure gives the MTJ a bistable tunnel magnetoresistance (TMR) effect. That is, when the spin magnetic states of the "free" ferromagnetic layer and the "pinned" ferromagnetic layer are "parallel" or "antiparallel," the MTJ exhibits two stable states: low resistance and high resistance. These two states can be used to represent logic data "0" and "1," respectively. Although MRAM theoretically has near-infinite write cycles and excellent non-volatility, it still faces some challenges in practical applications. In particular, since MRAM data storage depends on the magnetization state inside the MTJ, this magnetization state is highly susceptible to interference from strong external magnetic fields. When a strong interfering magnetic field exists, the "free" ferromagnetic layer in the MTJ may be affected, causing its magnetization direction to change, which in turn leads to erroneous flipping of stored data. This severely affects the read / write accuracy and data reliability of MRAM, limiting its application in strong magnetic field environments.

[0004] Flash memory (Flash EEPROM Memory) is one of the most widely used non-volatile memories. The most basic unit of Flash memory is a floating-gate field-effect transistor (FET). By applying different voltages to the floating gate, the state of electrons within it is changed, thus representing binary data "0" or "1". Specifically, applying a high voltage injects electrons into the floating gate, changing the state of the memory cell; another high voltage removes the electrons, restoring the cell to its initial state; by reading the voltage state of the floating gate, the value of the memory cell can be determined as "0" or "1". Flash memory offers high storage density and low cost, but its erase / write cycles are limited, typically around 100,000, which restricts its application in scenarios requiring frequent erase / write operations. Furthermore, Flash memory has relatively slow read / write speeds, which cannot meet the demands of high-performance computing.

[0005] As shown above, Flash memory has a limited number of erase / write cycles, which cannot meet the requirements for high durability. While MRAM offers high durability and high-speed read / write capabilities, it is susceptible to interference from external magnetic fields, affecting data reliability. Therefore, existing memory technologies struggle to achieve an ideal balance between performance, durability, and cost, failing to meet the ever-increasing demand for data storage.

[0006] Therefore, developing a new storage technology that can effectively resist external magnetic field interference and meet the requirements of high durability has become an important issue that urgently needs to be addressed in the current storage technology field. Summary of the Invention

[0007] To address the problems in related technologies, this disclosure provides a dual-process memory cell and its fabrication method, a dual-process memory cell array, a dual-process memory, and a chip.

[0008] In a first aspect, this disclosure provides a dual-process memory cell, comprising: a first memory cell fabricated using a first process and a second memory cell fabricated using a second process, wherein the first memory cell has a lower resistance to magnetic field interference than the second memory cell, and the first memory cell has a higher resistance to erasure and write operation than the second memory cell, and the first memory cell and the second memory cell are respectively connected to a data read / write circuit so as to realize data read / write operations on the dual-process memory cell based on the first memory cell or the second memory cell;

[0009] Specifically, when the first storage unit of the dual-process storage unit is in a data read / write active state and the second storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the first switching condition, the data read / write circuit controls the data read / write operation of the dual-process storage unit to switch from the first storage unit to the second storage unit of the dual-process storage unit through the control logic module. The current data in the first storage unit of the dual-process storage unit is written to the second storage unit of the dual-process storage unit, so that the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state.

[0010] When the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the second switching condition, the data read / write circuit controls the data read / write operation of the dual-process storage unit to switch from the second storage unit to the first storage unit of the dual-process storage unit through the control logic module. The current data in the second storage unit of the dual-process storage unit is written to the first storage unit of the dual-process storage unit, so that the first storage unit of the dual-process storage unit is in a data read / write active state and the second storage unit of the dual-process storage unit is in a data read / write standby state.

[0011] According to embodiments of this disclosure, the first storage unit and the second storage unit are respectively connected to a data read / write circuit, including: the first storage unit and the second storage unit are respectively directly connected to the data read / write circuit, or the first storage unit and the second storage unit are respectively connected to the data read / write circuit through a signal selector, wherein the signal selector includes a multiplexer or a multiplexer switch.

[0012] According to an embodiment of this disclosure, the first memory cell includes: an MRAM memory cell, the MRAM memory cell including: a MOS transistor, a magnetic tunnel junction, a first metal layer and a second metal layer, the magnetic tunnel junction including a free layer, a non-magnetic tunneling layer and a fixed layer disposed sequentially, the free layer of the magnetic tunnel junction being electrically contacted with the first metal layer, and the fixed layer of the magnetic tunnel junction being electrically contacted with the second metal layer; the second memory cell includes: a Flash memory cell, the Flash memory cell including: a floating gate field-effect transistor.

[0013] According to embodiments of this disclosure, the first storage unit and the second storage unit are directly connected to the data read / write circuit and the control logic module, respectively, including:

[0014] The second metal layer of the MRAM memory cell is connected to the bit line, the gate of the MOS transistor of the MRAM memory cell is connected to the word line, the source of the MOS transistor of the MRAM memory cell is connected to the source line, and the drain of the MOS transistor of the MRAM memory cell is connected to the first metal layer.

[0015] The gate of the floating gate field-effect transistor is connected to the word line, the source of the floating gate field-effect transistor is connected to the source line, and the drain of the floating gate field-effect transistor is connected to the bit line.

[0016] The word line, the bit line, and the source line are respectively connected to the data read / write circuit.

[0017] According to embodiments of this disclosure, the first storage unit and the second storage unit are respectively connected to the data read / write circuit via signal selectors, including:

[0018] The second metal layer of the MRAM memory cell is connected to the first input port of the signal selector, the gate of the MOS transistor of the MRAM memory cell is connected to the second input port of the signal selector, the source of the MOS transistor of the MRAM memory cell is connected to the third input port of the signal selector, and the drain of the MOS transistor of the MRAM memory cell is connected to the first metal layer.

[0019] The gate of the floating gate field-effect transistor is connected to the fourth input port of the signal selector, the source of the floating gate field-effect transistor is connected to the fifth input port of the signal selector, and the drain of the floating gate field-effect transistor is connected to the sixth input port of the signal selector.

[0020] The bit line output port of the signal selector is connected to the bit line, the word line output port of the signal selector is connected to the word line, and the source line output port of the signal selector is connected to the source line.

[0021] The word line, the bit line, and the source line are respectively connected to the data read / write circuit.

[0022] According to embodiments of this disclosure, the current external magnetic field interference satisfies a first switching condition, including:

[0023] By comparing the magnetic field strength of the current external magnetic field with the upper limit threshold of the dynamic magnetic field interference, it is determined whether the current external magnetic field interference meets the first switching condition. If the magnetic field strength of the current external magnetic field exceeds the upper limit threshold of the dynamic magnetic field interference, the first switching condition is met.

[0024] The condition that the current external magnetic field interference meets the second switching condition includes: determining whether the current external magnetic field interference meets the second switching condition by comparing the magnetic field strength of the current external magnetic field with the lower limit threshold of the dynamic magnetic field interference; if the magnetic field strength of the current external magnetic field is lower than the lower limit threshold of the dynamic magnetic field interference, the second switching condition is met.

[0025] According to embodiments of this disclosure, the upper limit threshold and the lower limit threshold of dynamic magnetic field interference are set based on the magnetic field interference resistance parameter of the first storage unit, the historical magnetic field strength of the external magnetic field, and the external environment change parameter.

[0026] According to embodiments of this disclosure, the external environment change parameters include: external ambient temperature and external magnetic field fluctuation frequency; the magnetic field interference resistance parameters include: coercivity and reversal magnetic field; and the dynamic magnetic field interference upper limit threshold and the dynamic magnetic field interference lower limit threshold are set based on the magnetic field interference resistance parameters of the first storage unit, the historical magnetic field strength of the external magnetic field, and the external environment change parameters in the following manner:

[0027] The initial values ​​of the upper limit threshold and the lower limit threshold of dynamic magnetic field interference are set according to the magnetic field interference resistance parameter of the first storage unit and the external ambient temperature, including:

[0028] The initial value of the upper limit threshold for dynamic magnetic field interference, Th_high, is calculated using the following formula. init :

[0029] Th_high init =(Hsw-k1)·(1-α·(TT) ref ));

[0030] The initial value of the lower limit threshold for dynamic magnetic field interference, Th_low, is calculated using the following formula. init :

[0031] Th_low init =(Hc+k2)·(1-β·(TT) ref ));

[0032] Where Hsw represents the flip magnetic field of the first memory cell, Hc represents the coercivity of the first memory cell, k1 is the first safety margin, k2 is the second safety margin, α is the first temperature coefficient, β is the second temperature coefficient, and T ref The reference temperature is T, where T is the ambient temperature.

[0033] The current values ​​of the upper and lower limits of dynamic magnetic field interference are dynamically adjusted based on the historical magnetic field strength and fluctuation frequency of the external magnetic field, including:

[0034] The current value of the dynamic magnetic field interference upper limit threshold, Th_high, is dynamically adjusted using the following formula:

[0035] Th_high=μ+k·σ·(1+γ·f);

[0036] The current value of the dynamic magnetic field interference lower limit threshold, Th_low, is dynamically adjusted using the following formula:

[0037] Th_low=μ-k·σ·(1+γ·f);

[0038] Where μ represents the average value of the historical magnetic field strength, σ represents the standard deviation of the historical magnetic field strength, k represents the adjustment coefficient, f represents the external magnetic field fluctuation frequency, and γ represents the fluctuation frequency coefficient.

[0039] Secondly, this disclosure provides a dual-process memory cell array, comprising: M×N dual-process memory cells arranged in an array as described in any one of claims 1 to 8, where M is the number of rows and N is the number of columns, and both M and N are integers greater than 1, wherein:

[0040] The dual-process memory cell array has N dual-process memory cells in each column sharing a bit line and a source line, and M dual-process memory cells in each row sharing a word line.

[0041] Thirdly, this disclosure provides a dual-process memory, comprising: an external magnetic field detection module, a control logic module, a data read / write circuit, and a dual-process memory cell array cluster, wherein the dual-process memory cell array cluster comprises one or more of the dual-process memory cell arrays as described in claim 9, wherein:

[0042] The external magnetic field detection module is connected to the control logic module and is configured to acquire external magnetic field parameters and send the external magnetic field parameters to the control logic module.

[0043] The control logic module is connected to the data read / write circuit and is configured to receive the external magnetic field parameters, determine whether the current external magnetic field interference meets the switching conditions based on the external magnetic field parameters, generate a switching signal based on the determination result, and send the switching signal to the data read / write circuit.

[0044] The data read / write circuit is connected to an external I / O port and configured to receive write data from the I / O port and output read data to the I / O port, and to receive the switching signal from the control logic module. Based on the switching signal, it controls the data read / write operation of the dual-process memory cells in the dual-process memory cell array to switch between the first memory cell and the second memory cell of the dual-process memory cell array, and performs data read / write operations on the dual-process memory cells in the dual-process memory cell array. The switching operation includes: if the switching signal is a first switching signal, the data read / write operation of the dual-process memory cell is switched from the first memory cell to the second memory cell, and the current data in the first memory cell of the dual-process memory cell is written to the second memory cell of the dual-process memory cell; if the switching signal is a second switching signal, the data read / write operation of the dual-process memory cell is switched from the second memory cell to the first memory cell, and the current data in the second memory cell of the dual-process memory cell is written to the first memory cell of the dual-process memory cell.

[0045] Fourthly, this disclosure provides a method for fabricating a dual-process memory cell, the dual-process memory cell comprising: a first memory cell and a second memory cell, wherein the first memory cell has a lower resistance to magnetic field interference than the second memory cell, and the first memory cell has a higher write resistance than the second memory cell, the fabrication method comprising:

[0046] The first storage unit is fabricated using the first process;

[0047] The second storage cell is fabricated using the second process;

[0048] The first storage unit and the second storage unit are respectively connected to the data read / write circuit so as to realize data read / write operations on the dual-process storage unit based on the first storage unit or the second storage unit;

[0049] When the first storage unit of the dual-process storage unit is in a data read / write active state and the second storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the first switching condition, the data read / write circuit controls the data read / write operation of the dual-process storage unit to switch from the first storage unit to the second storage unit of the dual-process storage unit through the control logic module. The current data in the first storage unit of the dual-process storage unit is written to the second storage unit of the dual-process storage unit, so that the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state.

[0050] When the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the second switching condition, the data read / write circuit controls the data read / write operation of the dual-process storage unit to switch from the second storage unit to the first storage unit of the dual-process storage unit through the control logic module. The current data in the second storage unit of the dual-process storage unit is written to the first storage unit of the dual-process storage unit, so that the first storage unit of the dual-process storage unit is in a data read / write active state and the second storage unit of the dual-process storage unit is in a data read / write standby state.

[0051] According to embodiments of this disclosure, the first storage unit includes an MRAM storage unit, and the second storage unit includes a Flash storage unit, wherein the Flash storage unit includes a floating gate field-effect transistor.

[0052] The fabrication of the first memory cell based on the first process includes:

[0053] Forming a MOS transistor on the substrate;

[0054] A first metal layer is formed above the drain of the MOS transistor, and a magnetic tunnel junction is formed above the first metal layer. The magnetic tunnel junction includes a free layer, a non-magnetic tunneling layer and a fixed layer arranged sequentially. The free layer is in electrical contact with the first metal layer.

[0055] A second metal layer is formed above the fixing layer of the magnetic tunnel junction, so that the fixing layer and the second metal layer are in electrical contact;

[0056] In this configuration, the second metal layer of the MRAM memory cell is connected to the bit line, the gate of the MOS transistor is connected to the word line, the source of the MOS transistor is connected to the source line, and the drain of the MOS transistor is connected to the second metal layer.

[0057] The fabrication of the second memory cell based on the second process includes:

[0058] The floating gate field-effect transistor is formed on the substrate, wherein the gate of the floating gate field-effect transistor is connected to the word line, the source of the floating gate field-effect transistor is connected to the source line, and the drain of the floating gate field-effect transistor is connected to the bit line.

[0059] Fifthly, this disclosure provides a dual-process memory cell, which is prepared according to the preparation method described in any one of the fourth aspects.

[0060] Sixthly, this disclosure provides a chip, characterized in that it includes a dual-process memory cell as described in any one of the first aspects.

[0061] According to the technical solution provided in the embodiments of this disclosure, an innovative dual-process storage unit is proposed. The dual-process storage unit combines two storage units with different processes (a first storage unit and a second storage unit) and a dynamic switching mechanism, and utilizes their respective advantages (the first storage unit has high durability and the second storage unit has high resistance to magnetic field interference) to solve the limitations of single storage technology in terms of resistance to magnetic field interference and durability.

[0062] Specifically, the dual-process storage unit includes a first storage unit fabricated using a first process and a second storage unit fabricated using a second process. The first storage unit has lower resistance to magnetic field interference than the second storage unit, but higher resistance to erasure and rewrite. The first and second storage units are respectively connected to a data read / write circuit to realize data read / write operations based on either the first or second storage unit. When the first storage unit is in a data read / write active state and external magnetic field interference meets a first switching condition, the data read / write circuit switches the data read / write operation to the second storage unit through a control logic module, writing the data from the first storage unit to the second storage unit. When the second storage unit is in a data read / write active state and external magnetic field interference meets a second switching condition, the data read / write circuit switches the data read / write operation back to the first storage unit through a control logic module, writing the data from the second storage unit to the first storage unit. This solves the limitations of single-process storage technology in terms of resistance to magnetic field interference and durability, providing a novel storage solution that can effectively resist external magnetic field interference while meeting high durability requirements.

[0063] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0064] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0065] Figure 1 This diagram illustrates the structure of a dual-process memory cell according to an embodiment of the present disclosure.

[0066] Figure 2 This diagram illustrates the structure of another dual-process memory cell according to an embodiment of the present disclosure;

[0067] Figure 3 This diagram illustrates the connection between a dual-process memory cell and a data read / write circuit in a specific example of this disclosure.

[0068] Figure 4 This diagram illustrates the connection between a dual-process memory cell and a data read / write circuit in another specific example of this disclosure.

[0069] Figure 5 This diagram illustrates the structure of a dual-process memory cell array in a specific example of this disclosure.

[0070] Figure 6 This diagram illustrates the structure of a dual-process memory according to an embodiment of the present disclosure.

[0071] Figure 7 A flowchart illustrating a method for fabricating a dual-process memory cell according to an embodiment of the present disclosure is shown. Detailed Implementation

[0072] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of exemplary embodiments have been omitted from the drawings.

[0073] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0074] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0075] As mentioned above, Flash memory has a limited number of erase / write cycles, which cannot meet the requirements for high durability. While MRAM offers high durability and high-speed read / write capabilities, it is susceptible to interference from external magnetic fields, affecting data reliability. Therefore, existing memory technologies struggle to achieve an ideal balance between performance, durability, and cost, failing to meet the ever-increasing demand for data storage.

[0076] How can we overcome the limitations of single-process storage technology in terms of resistance to magnetic field interference and durability, so that the memory can effectively resist external magnetic field interference and meet the requirements of high durability? After repeated demonstrations and careful consideration, the inventors of this disclosure have innovatively proposed the concept of dual-process memory cell, and then developed a dual-process memory with this dual-process memory cell as the basic memory cell. Specifically, the dual-process memory unit includes: a first memory unit (e.g., an MRAM memory unit) fabricated using a first process and a second memory unit (e.g., a Flash memory unit) fabricated using a second process. The first memory unit has a lower resistance to magnetic field interference than the second memory unit, and its write resistance is greater than that of the second memory unit. The first and second memory units are respectively connected to a data read / write circuit and a control logic module to enable data read / write operations on the dual-process memory unit based on either the first or the second memory unit. When the first memory unit of the dual-process memory unit is in a data read / write active state and the second memory unit is in a data read / write standby state, if the current external magnetic field interference meets a first switching condition, the control logic module controls the data read / write operation of the dual-process memory unit to switch from the first memory unit to the second memory unit. The data read / write circuit controls the current data in the first storage unit of the dual-process storage unit to be written to the second storage unit of the dual-process storage unit, so that the second storage unit of the dual-process storage unit is in a data read / write active state, and the first storage unit of the dual-process storage unit is in a data read / write standby state. When the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the second switching condition, the control logic module controls the data read / write operation of the dual-process storage unit to switch from the second storage unit to the first storage unit of the dual-process storage unit, and the data read / write circuit controls the current data in the second storage unit of the dual-process storage unit to be written to the first storage unit of the dual-process storage unit, so that the first storage unit of the dual-process storage unit is in a data read / write active state, and the second storage unit of the dual-process storage unit is in a data read / write standby state.

[0077] The dual-process memory cell disclosed herein employs a dual-process memory cell design. The first memory cell (e.g., MRAM) offers high durability but has weak resistance to magnetic field interference, while the second memory cell (e.g., Flash) offers high resistance to magnetic field interference but lower durability. Furthermore, an intelligent switching mechanism is utilized. Through control logic modules and data read / write circuits, the first or second memory cell is dynamically switched based on external magnetic field interference. Simultaneously, during the switching process, data in the current memory cell is ensured to be written to the target memory cell, guaranteeing data integrity and consistency. Thus, based on the physical implementation of dual processes, and through intelligent switching and data synchronization mechanisms, this dual-process memory cell fully leverages the advantages of two different memory cell processes while ensuring data consistency and reliability. In strong magnetic field environments, the more interference-resistant Flash memory cell is used to store data, while in weak magnetic field environments, the MRAM memory cell is used. This overcomes the limitations of single-process memory technologies in terms of magnetic field interference resistance and durability, providing a novel storage solution that effectively resists external magnetic field interference while meeting high durability requirements.

[0078] Figure 1 A schematic diagram of a dual-process memory cell according to an embodiment of the present disclosure is shown. Figure 1 As shown, the dual-process memory cell includes: a first memory cell fabricated using a first process and a second memory cell fabricated using a second process. The first memory cell has a lower resistance to magnetic field interference than the second memory cell, and the first memory cell has a higher write resistance than the second memory cell. The first memory cell and the second memory cell are respectively connected to a data read / write circuit. (For clarity,) Figure 1 The diagram also shows a control logic module connected to the data read / write circuit, and an external magnetic field detection module connected to the control logic module, so as to realize data read / write operations on the dual-process memory unit based on the first memory unit or the second memory unit.

[0079] In this disclosure, the first process and the second process are two different manufacturing processes. The first process is a specific manufacturing method or technical process for manufacturing the first storage cell in the dual-process storage cell of this disclosure, and the second process is a specific manufacturing method or technical process for manufacturing the second storage cell in the dual-process storage cell of this disclosure. Due to the different manufacturing processes, the first storage cell and the second storage cell have different characteristics, specifically in terms of resistance to magnetic field interference and resistance to erasure and rewrite. The first storage cell manufactured based on the first process has stronger resistance to erasure and rewrite than the second storage cell manufactured based on the second process, while the second storage cell manufactured based on the second process has stronger resistance to magnetic field interference than the first storage cell manufactured based on the first process. In this disclosure, the first storage cell and the second storage cell are complementary in terms of their resistance to magnetic field interference and resistance to erasure and rewrite. Thus, this complementary relationship can be utilized to read and write data using the first storage cell and the second storage cell respectively under different magnetic field interference conditions.

[0080] Based on the above limitations regarding the magnetic field interference resistance and erase / write resistance of the first and second storage units, in one specific embodiment, the first storage unit includes, but is not limited to, an MRAM storage unit, and the second storage unit includes, but is not limited to, a Flash storage unit. Therefore, the first process is specifically a process for fabricating an MRAM storage unit, and the second process is specifically a process for fabricating a Flash storage unit, wherein the Flash storage unit can be a NAND Flash storage unit or a NOR Flash storage unit.

[0081] Furthermore, the first and second storage units are not limited to a combination of MRAM and Flash storage units; they can also be other types of storage units. Specifically, the first and second storage units can be flexibly selected and combined using different storage technologies according to actual application requirements. For example, the first storage unit can be DRAM (Dynamic Random Access Memory), and the second storage unit can be FRAM (Ferroelectric Random Access Memory).

[0082] According to embodiments of this disclosure, the first storage unit and the second storage unit are respectively connected to a data read / write circuit, including the following two methods:

[0083] Method 1: The first storage unit and the second storage unit are directly connected to the data read / write circuit (e.g., Figure 1 (As shown).

[0084] Method 2: The first storage unit and the second storage unit are respectively connected to the data read / write circuit through signal selectors (e.g., Figure 2 As shown, for the sake of clarity, Figure 2 The diagram also shows a control logic module connected to the data read / write circuit, and an external magnetic field detection module connected to the control logic module.

[0085] The signal selector includes, but is not limited to, a multiplexer or a multiplexer switch.

[0086] In one specific embodiment, when the first storage unit is an MRAM storage unit and the second storage unit is a Flash storage unit, the MRAM storage unit includes: a MOS transistor, a magnetic tunnel junction, a first metal layer, and a second metal layer. The magnetic tunnel junction includes a free layer, a non-magnetic tunneling layer, and a fixed layer sequentially disposed thereon. The free layer of the magnetic tunnel junction is electrically contacted with the first metal layer, and the fixed layer of the magnetic tunnel junction is electrically contacted with the second metal layer. The Flash storage unit includes: a floating gate field-effect transistor. In this specific embodiment, when the first storage unit and the second storage unit are respectively connected to a data read / write circuit, methods 1 and 2 are specifically manifested as follows:

[0087] Method 1: When the first storage unit and the second storage unit are directly connected to the data read / write circuit, such as... Figure 3 As shown, the second metal layer of the MRAM memory cell is connected to the bit line, the gate of the MOS transistor of the MRAM memory cell is connected to the word line, the source of the MOS transistor of the MRAM memory cell is connected to the source line, and the drain of the MOS transistor of the MRAM memory cell is connected to the first metal layer; the gate of the floating gate field-effect transistor is connected to the word line, the source of the floating gate field-effect transistor is connected to the source line, and the drain of the floating gate field-effect transistor is connected to the bit line; the word line, the bit line, and the source line are respectively connected to the data read / write circuit.

[0088] Method 2: When the first storage unit and the second storage unit are respectively connected to the data read / write circuit through signal selectors, such as... Figure 4As shown, the second metal layer of the MRAM memory cell is connected to the first input port 1 of the signal selector; the gate of the MOS transistor of the MRAM memory cell is connected to the second input port 2 of the signal selector; the source of the MOS transistor of the MRAM memory cell is connected to the third input port 3 of the signal selector; and the drain of the MOS transistor of the MRAM memory cell is connected to the first metal layer. The gate of the floating gate field-effect transistor is connected to the fourth input port 4 of the signal selector; the source of the floating gate field-effect transistor is connected to the fifth input port 5 of the signal selector; and the drain of the floating gate field-effect transistor is connected to the sixth input port 6 of the signal selector. The bit line output port 7 of the signal selector is connected to the bit line; the word line output port 8 of the signal selector is connected to the word line; and the source line output port 9 of the signal selector is connected to the source line. The word line, the bit line, and the source line are respectively connected to the data read / write circuit.

[0089] Although the first and second storage units are logically integrated into a single, unified dual-process storage unit, they are physically independent. Data read / write operations can switch between the first and second storage units depending on external conditions (such as magnetic field interference) or internal needs. This means that at one time, data read / write operations may rely on the first storage unit, while at another time they may rely on the second storage unit. The control logic module and the data read / write circuitry function as follows: the control logic module monitors external conditions (such as magnetic field interference) and determines when to switch between the first and second storage units. The data read / write circuitry is responsible for actually performing data read / write operations based on the switching signals from the control logic module, including transferring data from the first storage unit to the second storage unit or vice versa when a switch occurs.

[0090] According to embodiments of this disclosure, when data read / write operations on the dual-process memory unit are implemented based on the first memory unit or the second memory unit, the specific limitations are as follows:

[0091] When the first storage unit of the dual-process storage unit is in a data read / write active state and the second storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the first switching condition, the data read / write circuit controls the data read / write operation of the dual-process storage unit to switch from the first storage unit to the second storage unit of the dual-process storage unit through the control logic module. The current data in the first storage unit of the dual-process storage unit is written to the second storage unit of the dual-process storage unit, so that the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state.

[0092] When the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the second switching condition, the data read / write circuit controls the data read / write operation of the dual-process storage unit to switch from the second storage unit to the first storage unit of the dual-process storage unit through the control logic module. The current data in the second storage unit of the dual-process storage unit is written to the first storage unit of the dual-process storage unit, so that the first storage unit of the dual-process storage unit is in a data read / write active state and the second storage unit of the dual-process storage unit is in a data read / write standby state.

[0093] Specifically, "data read / write active state" and "data read / write standby state" describe the working state of the storage unit. The data read / write active state indicates that the storage unit is currently performing data read / write operations or is ready to perform data read / write operations; that is, the storage unit is in a working state and can respond to data read / write requests. The data read / write standby state indicates that the storage unit is not currently performing data read / write operations and is in a low-power waiting state; that is, the storage unit does not respond to data read / write requests, the data read / write circuitry and control logic module do not interact directly with it, the storage unit still retains data, but it needs to switch to the active state before read / write operations can be performed. In a dual-process storage unit, when a storage unit is in the data read / write active state, data read / write operations are performed based on that storage unit; when a storage unit is in the data read / write standby state, that storage unit exists as a backup unit, ready to be switched to the data read / write active state for data read / write operations when needed.

[0094] According to embodiments of this disclosure, the data read / write circuit further includes a pre-charge module connected to the bit line. Before performing a data read / write operation, the pre-charge module pre-charges the bit line to a corresponding voltage level based on the type of the current storage unit (first storage unit or second storage unit) and the operation mode (write or read). For example, when performing a write operation on the first storage unit, the pre-charge module pre-charges the bit line to a first preset voltage value (this voltage value is set to a specific value that can accelerate the write speed) to speed up the write operation; when performing a read operation on the second storage unit, the pre-charge module pre-charges the bit line to a second preset voltage value (this voltage value is set to a specific value that can reduce read errors) to reduce read errors. The introduction of the pre-charge module can improve the efficiency and accuracy of the data read / write circuit.

[0095] In addition, the data read / write circuit also includes an adaptive voltage regulation module. This module dynamically adjusts the power supply voltage of the data read / write circuit based on the intensity of external magnetic field interference and the operating state of the dual-process memory cell. When the intensity of external magnetic field interference exceeds a preset first interference threshold, the adaptive voltage regulation module increases the power supply voltage to a first adjustment voltage value (set to a specific value that enhances the memory cell's anti-interference capability) to improve its anti-interference ability. When the intensity of external magnetic field interference is lower than a preset second interference threshold, the power supply voltage decreases to a second adjustment voltage value (set to a specific value that reduces power consumption) to reduce power consumption. Furthermore, depending on whether the dual-process memory cell is in a data read / write active state or a standby state, the adaptive voltage regulation module can also perform different voltage adjustments to further optimize the performance of the data read / write circuit.

[0096] According to embodiments of this disclosure, the control logic module includes a learning algorithm unit. This unit records historical data on external magnetic field interference, the switching history of dual-process storage units, and the success rate of data read / write operations. By learning and analyzing this historical data, the learning algorithm unit can predict the changing trends of external magnetic field interference and the performance changes of the storage units, thereby adjusting the thresholds of the switching conditions (first switching condition and second switching condition) in advance. For example, if the learning algorithm unit detects an upward trend in external magnetic field interference within a specific time period, it will adjust the dynamic magnetic field interference upper limit threshold to a preset first adjustment threshold (this first adjustment threshold is a pre-set value used to ensure safe data switching under an upward trend in external magnetic field interference), switching the data from the first storage unit to the second storage unit in advance to avoid data loss.

[0097] According to embodiments of this disclosure, the current external magnetic field interference satisfies a first switching condition, including:

[0098] By comparing the current external magnetic field strength with the dynamic magnetic field interference upper limit threshold, it is determined whether the current external magnetic field interference meets the first switching condition. If the current external magnetic field strength exceeds the dynamic magnetic field interference upper limit threshold, the first switching condition is met.

[0099] According to an embodiment of this disclosure, the current external magnetic field interference satisfying the second switching condition includes: determining whether the current external magnetic field interference satisfies the second switching condition by comparing the magnetic field strength of the current external magnetic field with the dynamic magnetic field interference lower limit threshold; if the magnetic field strength of the current external magnetic field is lower than the dynamic magnetic field interference lower limit threshold, the second switching condition is satisfied.

[0100] Specifically, the external environmental change parameters include, but are not limited to, external environmental temperature and external magnetic field fluctuation frequency. The magnetic field interference resistance parameters include, but are not limited to, coercivity and reversal magnetic field. The upper limit threshold and the lower limit threshold of dynamic magnetic field interference are set according to the magnetic field interference resistance parameters of the first storage unit, the historical magnetic field strength of the external magnetic field, and the external environmental change parameters in the following manner:

[0101] The initial values ​​of the upper limit threshold and the lower limit threshold of dynamic magnetic field interference are set according to the magnetic field interference resistance parameter of the first storage unit and the external ambient temperature, including:

[0102] The initial value of the upper limit threshold for dynamic magnetic field interference, Th_high, is calculated using the following formula. init :

[0103] Th_high init =(Hsw-k1)·(1-α·(TT) ref ));

[0104] The initial value of the lower limit threshold for dynamic magnetic field interference, Th_low, is calculated using the following formula. init :

[0105] Th_low init =(Hc+k2)·(1-β·(TT) ref ));

[0106] Where Hsw represents the flip magnetic field of the first memory cell, Hc represents the coercivity of the first memory cell, k1 is the first safety margin, k2 is the second safety margin, α is the first temperature coefficient, β is the second temperature coefficient, and T ref T is the reference temperature, and T is the external ambient temperature.

[0107] The current values ​​of the upper and lower limits of dynamic magnetic field interference are dynamically adjusted based on the historical magnetic field strength and fluctuation frequency of the external magnetic field, including:

[0108] The current value of the dynamic magnetic field interference upper limit threshold, Th_high, is dynamically adjusted using the following formula:

[0109] Th_high=μ+k·σ·(1+γ·f);

[0110] The current value of the dynamic magnetic field interference lower limit threshold, Th_low, is dynamically adjusted using the following formula:

[0111] Th_low=μ-k·σ·(1+γ·f);

[0112] Where μ represents the average value of the historical magnetic field strength, σ represents the standard deviation of the historical magnetic field strength, k represents the adjustment coefficient, f represents the external magnetic field fluctuation frequency, and γ represents the fluctuation frequency coefficient.

[0113] In this disclosure, the upper and lower threshold values ​​for dynamic magnetic field interference are set based on the magnetic field interference resistance parameters of the first storage unit, the historical magnetic field strength of the external magnetic field, and external environmental change parameters. That is, the settings of the upper and lower threshold values ​​for dynamic magnetic field interference are related to the characteristics of the storage unit itself and the external environment (e.g., magnetic field environment, temperature environment), and are dynamically adjusted as the external environment changes. Thus, when determining whether the current external magnetic field interference meets the switching conditions based on the upper and lower threshold values ​​for dynamic magnetic field interference, compared to using a preset fixed magnetic field interference threshold, it has the following beneficial technical effects:

[0114] 1. Enhanced adaptability. Specifically, the dynamic threshold can be adjusted in real time according to changes in external magnetic field strength and environment, adapting to different application scenarios; in addition, by combining historical magnetic field strength, the dynamic threshold can more accurately reflect the current level of magnetic field interference.

[0115] 2. Improve the reliability of storage units. Specifically, the dynamic threshold is based on the magnetic field interference resistance parameters of the first storage unit (such as coercivity and flipping magnetic field) to ensure that the storage unit is switched before the magnetic field interference reaches the critical value, thus avoiding data corruption. At the same time, parameters such as external ambient temperature are considered so that the dynamic threshold can adapt to the impact of temperature changes on the interference resistance of the storage unit.

[0116] 3. Extend storage unit lifespan. Specifically, dynamic thresholds can more accurately determine the switching timing, avoiding frequent switching caused by overly conservative or aggressive fixed thresholds, thus extending the lifespan of storage units. At the same time, it reduces unnecessary switching, lowers energy consumption, and extends device usage time.

[0117] 4. Improve system performance. Specifically, dynamic thresholds can respond to changes in the external magnetic field in real time, ensuring that the system quickly switches storage units when magnetic field interference changes, thus improving system performance. Furthermore, by combining historical data and environmental parameters, dynamic thresholds can reduce misjudgments caused by magnetic field fluctuations, improving system stability.

[0118] 5. Enhanced security. Specifically, a safety margin is introduced into the dynamic threshold calculation to ensure that storage units are switched before magnetic field interference reaches a critical value, thereby enhancing data security.

[0119] 6. Fluctuation frequency consideration: By combining the fluctuation frequency of the external magnetic field, the dynamic threshold can more accurately determine the persistence of magnetic field interference and avoid false switching caused by short-term fluctuations.

[0120] In summary, compared to fixed thresholds, the method based on dynamic magnetic field interference upper and lower thresholds offers greater adaptability, higher reliability, longer storage cell lifespan, better system performance, and stronger security. This dynamic adjustment mechanism can more effectively cope with complex and ever-changing magnetic field interference environments, ensuring that storage cells operate in optimal condition.

[0121] In this disclosure, in addition to comparing the current external magnetic field strength with the upper and lower limits of dynamic magnetic field interference, a judgment on the duration of external magnetic field interference is also added. The first switching condition is met only when the external magnetic field strength exceeds the upper limit of dynamic magnetic field interference and the duration exceeds a preset time threshold; similarly, the second switching condition is met only when the external magnetic field strength is below the lower limit of dynamic magnetic field interference and the duration exceeds the preset time threshold. This avoids frequent memory unit switching due to brief magnetic field interference, improving system stability and reliability.

[0122] Furthermore, in this disclosure, the switching conditions are determined by comprehensively considering the workload of the storage units. When the first storage unit is under high load (e.g., frequent read / write operations), the upper limit threshold of the dynamic magnetic field interference is adjusted to a preset first specific threshold (this first specific threshold is determined through prior experiments and evaluations, and is a specific value that can reduce unnecessary switching and fully utilize the strong anti-erasure and write capability advantage of the first storage unit when it is under high load), reducing the frequency of switching to the second storage unit to fully utilize the strong anti-erasure and write capability advantage of the first storage unit; when the second storage unit is under high load, the lower limit threshold of the dynamic magnetic field interference is adjusted to a preset second specific threshold (this second specific threshold is determined through prior experiments and evaluations, and is a specific value that can increase the chance of switching to the first storage unit and improve the overall system performance when the second storage unit is under high load), increasing the chance of switching to the first storage unit to improve the overall system performance.

[0123] Figure 5 This diagram illustrates a structural schematic of a dual-process memory cell array according to a specific example of this disclosure. In this specific example, the dual-process memory cell array includes four such... Figure 1 or Figure 2 Taking the dual-process memory cell shown as an example, the structure of the dual-process memory cell array will be described.

[0124] like Figure 5 As shown, the dual-process memory cell array includes: four cells arranged in an array as shown in the diagram. Figure 1 or Figure 2The dual-process memory cells shown are a first dual-process memory cell, a second dual-process memory cell, a third dual-process memory cell, and a fourth dual-process memory cell, with 2 rows and 2 columns. The two dual-process memory cells in each column of the dual-process memory cell array (the first column contains the first and third dual-process memory cells, and the second column contains the second and fourth dual-process memory cells) share one bit line and one source line, namely the first bit line and the first source line. The two dual-process memory cells in each row (the first row contains the first and second dual-process memory cells, and the second row contains the third and fourth dual-process memory cells) share one word line, namely the first word line and the second word line.

[0125] Figure 6 A schematic diagram of a dual-process memory according to an embodiment of the present disclosure is shown. Figure 6 As shown, the dual-process memory includes: an external magnetic field detection module, a control logic module, a data read / write circuit, and a dual-process memory cell array cluster; the dual-process memory cell array cluster includes one or more dual-process memory cell arrays as described above. For clarity, Figure 6 The diagram also shows an address decoder that is not included in the dual-process memory.

[0126] The external magnetic field detection module is connected to the control logic module and is configured to acquire external magnetic field parameters and send the external magnetic field parameters to the control logic module.

[0127] The control logic module is connected to the data read / write circuit and is configured to receive the external magnetic field parameters, determine whether the current external magnetic field interference meets the switching conditions based on the external magnetic field parameters, generate a switching signal based on the determination result, and send the switching signal to the data read / write circuit.

[0128] In a specific example, the external magnetic field detection module includes a magnetic field sensor (such as a Hall effect sensor, magnetoresistive sensor, etc.) and a corresponding signal processing circuit. The magnetic field sensor detects external magnetic field parameters, and the signal processing circuit amplifies, filters, and digitizes the signal output by the sensor to obtain accurate external magnetic field parameters. These external magnetic field parameters can be: magnetic field strength, magnetic field direction, magnetic field rate of change, and magnetic field frequency, etc.

[0129] The data read / write circuit is connected to an external I / O port and configured to receive write data from the I / O port and output read data to the I / O port, and to receive the switching signal from the control logic module. Based on the switching signal, it controls the data read / write operation of the dual-process memory cells in the dual-process memory cell array to switch between the first memory cell and the second memory cell of the dual-process memory cell array, and performs data read / write operations on the dual-process memory cells in the dual-process memory cell array. The switching operation includes: if the switching signal is a first switching signal, the data read / write operation of the dual-process memory cell is switched from the first memory cell to the second memory cell, and the current data in the first memory cell of the dual-process memory cell is written to the second memory cell of the dual-process memory cell; if the switching signal is a second switching signal, the data read / write operation of the dual-process memory cell is switched from the second memory cell to the first memory cell, and the current data in the second memory cell of the dual-process memory cell is written to the first memory cell of the dual-process memory cell.

[0130] The basic memory cell provided in this disclosure is a dual-process memory cell as described above. When external magnetic field interference requires switching from MRAM memory mode to Flash memory mode, or from Flash memory mode to MRAM memory mode, the switching is performed between MRAM memory cells and Flash memory cells in each dual-process memory cell. Compared to integrating separate MRAM memory and Flash memory (i.e., hybrid memory) in the chip in the prior art, the switching between MRAM memory and Flash memory when a switch is required has the following beneficial technical effects:

[0131] 1. Higher switching efficiency. Since the MRAM and Flash memory cells of the dual-process memory cell are located in the same memory cell, data transfer only needs to be performed within the same cell during switching, reducing data transfer paths and latency, and improving switching speed. In contrast, for a separate memory, data needs to be transferred between independent MRAM and Flash memory during switching, resulting in longer paths, greater latency, and lower efficiency.

[0132] 2. Lower power consumption. Because data is switched within the same cell in dual-process memory units, the power consumption for data transfer is reduced. In contrast, for standalone memory, data is transferred between independent memory units, resulting in higher power consumption.

[0133] 3. Higher data reliability. Because data in dual-process memory cells can be quickly backed up and restored between MRAM and Flash, the risk of data loss is reduced. In contrast, single-process memory offers slower data backup and recovery speeds and lower reliability.

[0134] 4. Reduced design complexity. Since the MRAM and Flash memory cells of the dual-process memory are integrated in the same cell, the circuit design is simplified and the complexity is reduced. For separate memory, independent design and integration are required, which is more complex.

[0135] 5. Higher area utilization. Because the MRAM and Flash memory cells in dual-process memory share some circuitry, the chip area footprint is reduced. In contrast, separate memory designs require more area.

[0136] In summary, integrating dual-process memory cells into a memory module outperforms hybrid memory modules that integrate MRAM and Flash memory separately in terms of switching efficiency, power consumption, interference immunity, data reliability, design complexity, and area utilization.

[0137] Figure 7 A flowchart illustrating a method for fabricating a dual-process memory cell according to an embodiment of the present disclosure is shown. The dual-process memory cell includes: a first memory cell and a second memory cell, wherein the first memory cell has a lower resistance to magnetic field interference than the second memory cell, and the first memory cell has a higher write resistance than the second memory cell. Figure 7 As shown, the preparation method includes the following steps S710 to S720:

[0138] In step S710, the first memory cell is fabricated based on the first process.

[0139] According to embodiments of this disclosure, the fabrication of the first memory cell based on a first process includes:

[0140] First, a MOSFET is formed on the substrate. Specifically, a suitable substrate material, such as silicon (Si) or silicon-on-insulator (SOI), is selected, and the substrate is cleaned and pretreated to remove surface contaminants and oxide layers.

[0141] In one specific embodiment, a MOSFET is formed on a substrate using standard CMOS processes. This includes steps such as growing a gate oxide, depositing and patterning a polysilicon gate, and doping the source and drain regions. The gate oxide serves as an insulating layer between the gate and channel of the MOSFET. The polysilicon gate serves as the gate electrode of the MOSFET. The source and drain regions are doped using ion implantation or diffusion processes to form conductive regions.

[0142] Then, a first metal layer is formed above the drain of the MOS transistor, and a magnetic tunnel junction is formed above the first metal layer. The magnetic tunnel junction includes a free layer, a non-magnetic tunneling layer and a fixed layer arranged sequentially, and the free layer is in electrical contact with the first metal layer.

[0143] Finally, a second metal layer is formed above the fixing layer of the magnetic tunnel junction, so that the fixing layer and the second metal layer are in electrical contact.

[0144] In this configuration, the second metal layer of the MRAM memory cell is connected to the bit line, the gate of the MOS transistor is connected to the word line, the source of the MOS transistor is connected to the source line, and the drain of the MOS transistor is connected to the second metal layer.

[0145] When forming source and drain regions on both sides of the gate using ion implantation, if the resulting MOS transistor is a PMOS transistor, the source and drain need to be N-type doped to form N-type regions. Electrons in these regions will be repelled into the channel, leaving holes as conductive charge carriers. Then, N-type impurities (such as phosphorus P or arsenic As) are implanted into the active regions on both sides of the gate using ion implantation to form source and drain regions. If the resulting MOS transistor is an NMOS transistor, the source and drain need to be P-type doped to form P-type regions. Holes in these regions will be repelled into the channel, leaving electrons as conductive charge carriers. Then, P-type impurities (such as boron B or indium In) are implanted into the active regions on both sides of the gate using ion implantation to form source and drain regions.

[0146] In step S720, the second memory cell is fabricated based on the second process.

[0147] The fabrication of the second memory cell based on the second process includes:

[0148] The floating gate field-effect transistor is formed on the substrate, wherein the gate of the floating gate field-effect transistor is connected to the word line, the source of the floating gate field-effect transistor is connected to the source line, and the drain of the floating gate field-effect transistor is connected to the bit line.

[0149] Specifically, a suitable substrate material is selected and cleaned and pretreated. Then, the channel region and source / drain regions of the field-effect transistor (FET) are formed on the substrate using standard CMOS processes. A gate oxide is formed above the channel region as an insulating layer between the FET's gate and channel. A floating gate material, such as polysilicon or metal nitride, is deposited and patterned above the gate oxide. The floating gate serves as the region for storing charge. Another insulating layer (called a control gate oxide) is formed above the floating gate, and then a control gate electrode material is deposited and patterned. The control gate electrode is used to control the charge state on the floating gate.

[0150] It should be noted that throughout the entire preparation process, temperature, pressure, and atmosphere are strictly controlled to avoid material contamination and performance degradation.

[0151] This disclosure also provides a dual-process memory cell, which is prepared according to any of the preparation methods described in this disclosure.

[0152] This disclosure also provides a chip including the dual-process memory cell array described in the embodiments of this disclosure.

[0153] According to the technical solution provided in the embodiments of this disclosure, an innovative dual-process storage unit is proposed. The dual-process storage unit combines two storage units with different processes (a first storage unit and a second storage unit) and a dynamic switching mechanism, and utilizes their respective advantages (the first storage unit has high durability and the second storage unit has high resistance to magnetic field interference) to solve the limitations of single storage technology in terms of resistance to magnetic field interference and durability.

[0154] Specifically, the dual-process storage unit includes a first storage unit fabricated using a first process and a second storage unit fabricated using a second process. The first storage unit has lower resistance to magnetic field interference than the second storage unit, but higher resistance to erasure and rewrite. The first and second storage units are respectively connected to a data read / write circuit to realize data read / write operations based on either the first or second storage unit. When the first storage unit is in a data read / write active state and external magnetic field interference meets a first switching condition, the data read / write circuit switches the data read / write operation to the second storage unit through a control logic module, writing the data from the first storage unit to the second storage unit. When the second storage unit is in a data read / write active state and external magnetic field interference meets a second switching condition, the data read / write circuit switches the data read / write operation back to the first storage unit through a control logic module, writing the data from the second storage unit to the first storage unit. This solves the limitations of single-process storage technology in terms of resistance to magnetic field interference and durability, providing a novel storage solution that can effectively resist external magnetic field interference while meeting high durability requirements.

[0155] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A dual-process memory cell, characterized in that, The dual-process memory cell includes: a first memory cell fabricated based on a first process and a second memory cell fabricated based on a second process. The first memory cell has a lower resistance to magnetic field interference than the second memory cell, and the first memory cell has a higher resistance to erasure and write than the second memory cell. The first memory cell and the second memory cell are respectively connected to a data read / write circuit so that data read / write operations on the dual-process memory cell can be performed based on the first memory cell or the second memory cell. Specifically, when the first storage unit of the dual-process storage unit is in a data read / write active state and the second storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the first switching condition, the data read / write circuit controls the data read / write operation of the dual-process storage unit to switch from the first storage unit to the second storage unit of the dual-process storage unit through the control logic module. The current data in the first storage unit of the dual-process storage unit is written to the second storage unit of the dual-process storage unit, so that the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state. When the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the second switching condition, the data read / write circuit controls the data read / write operation of the dual-process storage unit to switch from the second storage unit to the first storage unit of the dual-process storage unit through the control logic module. The current data in the second storage unit of the dual-process storage unit is written to the first storage unit of the dual-process storage unit, so that the first storage unit of the dual-process storage unit is in a data read / write active state and the second storage unit of the dual-process storage unit is in a data read / write standby state.

2. The dual-process memory cell according to claim 1, characterized in that, The first storage unit and the second storage unit are respectively connected to the data read / write circuit, including: the first storage unit and the second storage unit are respectively directly connected to the data read / write circuit, or the first storage unit and the second storage unit are respectively connected to the data read / write circuit through a signal selector, wherein the signal selector includes a multiplexer or a multiplexer switch.

3. The dual-process memory cell according to claim 2, characterized in that, The first memory cell includes an MRAM memory cell, which includes a MOS transistor, a magnetic tunnel junction, a first metal layer, and a second metal layer. The magnetic tunnel junction includes a free layer, a non-magnetic tunneling layer, and a fixed layer disposed sequentially. The free layer of the magnetic tunnel junction is electrically in contact with the first metal layer, and the fixed layer of the magnetic tunnel junction is electrically in contact with the second metal layer. The second memory cell includes a Flash memory cell, which includes a floating gate field-effect transistor.

4. The dual-process memory cell according to claim 3, characterized in that, The first storage unit and the second storage unit are directly connected to the data read / write circuit and the control logic module, respectively, including: The second metal layer of the MRAM memory cell is connected to the bit line, the gate of the MOS transistor of the MRAM memory cell is connected to the word line, the source of the MOS transistor of the MRAM memory cell is connected to the source line, and the drain of the MOS transistor of the MRAM memory cell is connected to the first metal layer. The gate of the floating gate field-effect transistor is connected to the word line, the source of the floating gate field-effect transistor is connected to the source line, and the drain of the floating gate field-effect transistor is connected to the bit line. The word line, the bit line, and the source line are respectively connected to the data read / write circuit.

5. The dual-process memory cell according to claim 3, characterized in that, The first storage unit and the second storage unit are respectively connected to the data read / write circuit via signal selectors, including: The second metal layer of the MRAM memory cell is connected to the first input port of the signal selector, the gate of the MOS transistor of the MRAM memory cell is connected to the second input port of the signal selector, the source of the MOS transistor of the MRAM memory cell is connected to the third input port of the signal selector, and the drain of the MOS transistor of the MRAM memory cell is connected to the first metal layer. The gate of the floating gate field-effect transistor is connected to the fourth input port of the signal selector, the source of the floating gate field-effect transistor is connected to the fifth input port of the signal selector, and the drain of the floating gate field-effect transistor is connected to the sixth input port of the signal selector. The bit line output port of the signal selector is connected to the bit line, the word line output port of the signal selector is connected to the word line, and the source line output port of the signal selector is connected to the source line. The word line, the bit line, and the source line are respectively connected to the data read / write circuit.

6. The dual-process memory cell according to claim 1, characterized in that, The current external magnetic field interference satisfies the first switching condition, including: By comparing the magnetic field strength of the current external magnetic field with the upper limit threshold of the dynamic magnetic field interference, it is determined whether the current external magnetic field interference meets the first switching condition. If the magnetic field strength of the current external magnetic field exceeds the upper limit threshold of the dynamic magnetic field interference, the first switching condition is met. The condition that the current external magnetic field interference meets the second switching condition includes: determining whether the current external magnetic field interference meets the second switching condition by comparing the magnetic field strength of the current external magnetic field with the lower limit threshold of the dynamic magnetic field interference; if the magnetic field strength of the current external magnetic field is lower than the lower limit threshold of the dynamic magnetic field interference, the second switching condition is met.

7. The dual-process memory cell according to claim 6, characterized in that, in, The upper limit threshold and the lower limit threshold of dynamic magnetic field interference are set based on the magnetic field interference resistance parameter of the first storage unit, the historical magnetic field strength of the external magnetic field, and the external environment change parameter.

8. The dual-process memory cell according to claim 7, characterized in that, in, The external environment change parameters include: external ambient temperature and external magnetic field fluctuation frequency. The magnetic field interference resistance parameters include: coercivity and reversal magnetic field. The upper limit threshold and the lower limit threshold of dynamic magnetic field interference are set according to the magnetic field interference resistance parameters of the first storage unit, the historical magnetic field strength of the external magnetic field, and the external environment change parameters in the following manner: The initial values ​​of the upper limit threshold and the lower limit threshold of dynamic magnetic field interference are set according to the magnetic field interference resistance parameter of the first storage unit and the external ambient temperature, including: The initial value of the upper limit threshold for dynamic magnetic field interference, Th_high, is calculated using the following formula. init : Th_high init =(Hsw-k1)·(1-α·(T-T ref )); The initial value of the lower limit threshold for dynamic magnetic field interference, Th_low, is calculated using the following formula. init : Th_low init =(Hc+k2)·(1-β·(T-T ref )); Where Hsw represents the flip magnetic field of the first memory cell, Hc represents the coercivity of the first memory cell, k1 is the first safety margin, k2 is the second safety margin, α is the first temperature coefficient, β is the second temperature coefficient, and T ref The reference temperature is T, where T is the ambient temperature. The current values ​​of the upper and lower limits of dynamic magnetic field interference are dynamically adjusted based on the historical magnetic field strength and fluctuation frequency of the external magnetic field, including: The current value of the dynamic magnetic field interference upper limit threshold, Th_high, is dynamically adjusted using the following formula: Th_high=μ+k·σ·(1+γ·f); The current value of the dynamic magnetic field interference lower limit threshold, Th_low, is dynamically adjusted using the following formula: Th_low=μ-k·σ·(1+γ·f); Where μ represents the average value of the historical magnetic field strength, σ represents the standard deviation of the historical magnetic field strength, k represents the adjustment coefficient, f represents the external magnetic field fluctuation frequency, and γ represents the fluctuation frequency coefficient.

9. A dual-process memory cell array, characterized in that, include: M×N dual-process memory cells as described in any one of claims 1 to 8, arranged in an array, where M is the number of rows and N is the number of columns, and both M and N are integers greater than 1, wherein: The dual-process memory cell array has N dual-process memory cells in each column sharing a bit line and a source line, and M dual-process memory cells in each row sharing a word line.

10. A dual-process memory, characterized in that, include: The system comprises an external magnetic field detection module, a control logic module, a data read / write circuit, and a dual-process memory cell array cluster, wherein the dual-process memory cell array cluster includes one or more of the dual-process memory cell arrays as described in claim 9, wherein: The external magnetic field detection module is connected to the control logic module and is configured to acquire external magnetic field parameters and send the external magnetic field parameters to the control logic module. The control logic module is connected to the data read / write circuit and is configured to receive the external magnetic field parameters, determine whether the current external magnetic field interference meets the switching conditions based on the external magnetic field parameters, generate a switching signal based on the determination result, and send the switching signal to the data read / write circuit. The data read / write circuit is connected to an external I / O port and configured to receive write data from the I / O port and output read data to the I / O port, and to receive the switching signal from the control logic module. Based on the switching signal, it controls the data read / write operation of the dual-process memory cells in the dual-process memory cell array to switch between the first memory cell and the second memory cell of the dual-process memory cell array, and performs data read / write operations on the dual-process memory cells in the dual-process memory cell array. The switching operation includes: if the switching signal is a first switching signal, the data read / write operation of the dual-process memory cell is switched from the first memory cell to the second memory cell, and the current data in the first memory cell of the dual-process memory cell is written to the second memory cell of the dual-process memory cell; if the switching signal is a second switching signal, the data read / write operation of the dual-process memory cell is switched from the second memory cell to the first memory cell, and the current data in the second memory cell of the dual-process memory cell is written to the first memory cell of the dual-process memory cell.

11. A method for fabricating a dual-process memory cell, characterized in that, The dual-process memory cell includes: a first memory cell and a second memory cell. The first memory cell has a lower resistance to magnetic field interference than the second memory cell, and the first memory cell has a higher write resistance than the second memory cell. The fabrication method includes: The first storage unit is fabricated using the first process; The second memory cell is fabricated using the second process; The first storage unit and the second storage unit are respectively connected to the data read / write circuit so as to realize data read / write operations on the dual-process storage unit based on the first storage unit or the second storage unit; When the first storage unit of the dual-process storage unit is in a data read / write active state and the second storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the first switching condition, the data read / write circuit controls the data read / write operation of the dual-process storage unit to switch from the first storage unit to the second storage unit of the dual-process storage unit through the control logic module. The current data in the first storage unit of the dual-process storage unit is written to the second storage unit of the dual-process storage unit, so that the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state. When the second storage unit of the dual-process storage unit is in a data read / write active state and the first storage unit of the dual-process storage unit is in a data read / write standby state, if the current external magnetic field interference meets the second switching condition, the data read / write circuit controls the data read / write operation of the dual-process storage unit to switch from the second storage unit to the first storage unit of the dual-process storage unit through the control logic module. The current data in the second storage unit of the dual-process storage unit is written to the first storage unit of the dual-process storage unit, so that the first storage unit of the dual-process storage unit is in a data read / write active state and the second storage unit of the dual-process storage unit is in a data read / write standby state.

12. The preparation method according to claim 11, characterized in that, The first storage unit includes an MRAM storage unit, and the second storage unit includes a Flash storage unit, wherein the Flash storage unit includes a floating gate field-effect transistor. The fabrication of the first memory cell based on the first process includes: Forming a MOS transistor on the substrate; A first metal layer is formed above the drain of the MOS transistor, and a magnetic tunnel junction is formed above the first metal layer. The magnetic tunnel junction includes a free layer, a non-magnetic tunneling layer and a fixed layer arranged sequentially. The free layer is in electrical contact with the first metal layer. A second metal layer is formed above the fixing layer of the magnetic tunnel junction, so that the fixing layer and the second metal layer are in electrical contact; In this configuration, the second metal layer of the MRAM memory cell is connected to the bit line, the gate of the MOS transistor is connected to the word line, the source of the MOS transistor is connected to the source line, and the drain of the MOS transistor is connected to the second metal layer. The fabrication of the second memory cell based on the second process includes: The floating gate field-effect transistor is formed on the substrate, wherein the gate of the floating gate field-effect transistor is connected to the word line, the source of the floating gate field-effect transistor is connected to the source line, and the drain of the floating gate field-effect transistor is connected to the bit line.

13. A dual-process memory cell, characterized in that, The dual-process memory cell is prepared by the preparation method according to any one of claims 11 to 12.

14. A chip, characterized in that, Includes the dual-process memory cell as described in any one of claims 1 to 8.

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