Method, circuit, and system for data drift detection during operation of a storage array

Abstract

The present invention relates to a method, circuit and system for detecting data drift during operation of a memory array. An input node is coupled to a line under test in the memory array, and first and second output nodes are used to generate a relative voltage drop. An input stage transistor is provided between the first and second output nodes and the input node for regulating current flow. A pre-stage shunt unit is connected in parallel with the input stage transistor and shunts current flow from the input stage transistor. If the level of data transmitted on the line under test causes the relative voltage drop between the first and second output nodes to be outside a predetermined range, it is determined that the level of data has drifted, thereby providing a discrimination mechanism for determining whether the data has been corrupted.

Description

Technical Field

[0001] This invention mainly relates to the technical field of data storage, and more specifically, to a method, circuit, and system for detecting data drift during data operations in a memory, which can capture errors in various stages such as data writing, reading, or transmission in a timely manner during data storage or processing. Background Technology

[0002] In electronic products, control terminals, such as main control chips (CPUs or GPUs), increasingly utilize high-speed data exchange channels in data processing, such as the progressively upgraded NVLink, PCIe, and optical communication. The faster the communication speed of these protocols, the weaker the error monitoring capability for data exchange becomes. This is because the data width of each bit becomes narrower with increasing protocol speed, or the duration of a single bit decreases. Identifying whether a single bit of data has erred during the exchange becomes extremely difficult. Data streams consist of multiple bits that continuously emerge in the data channel within a very short time; monitoring requirements cannot create waiting slots for the bits. Furthermore, normal data transmission and reception must not be negatively affected, otherwise it would violate the established protocol specifications of the data communication mode. The sources of data errors are very complex and are the result of a combination of multiple factors. Under mechanical or thermal stress, semiconductors may experience minor deformations or stress accumulation in their internal components, potentially leading to structural failures. Irreversible or reversible changes in circuit performance parameters over time or under varying operating conditions can cause deviations or degradation in circuit operating characteristics, speed, power consumption, or other critical indicators. Overvoltage or overcurrent in the operating circuitry can affect its withstand capability. When memory is exposed to ambient radiation or radioactive particles, collisions with memory components can cause transient changes in the data bits stored in the device, resulting in errors. These are just some of the reasons why detecting data errors in storage applications is a crucial prerequisite for ensuring data accuracy, especially in demanding fields such as aerospace. Summary of the Invention

[0003] This application relates to a data drift detection circuit for a storage array during data operations, comprising:

[0004] An input node of the line under test coupled to the memory array, and first and second output nodes for generating relative voltage drops;

[0005] An input stage transistor that regulates current between a first and a second output node and an input node, wherein the first output node is coupled to the collector of the input stage transistor via a resistor, the second output node is coupled to the base of the input stage transistor via a resistor, and one or more resistors are provided between the first and second output nodes.

[0006] At least one pre-stage shunt unit is connected in parallel with the input stage transistor and shunts the input stage transistor. The voltage divider portion of the pre-stage shunt unit is connected to the collector of the input stage transistor. The voltage divider value provided by the voltage divider portion is applied to the base of a branch transistor of the pre-stage shunt unit. The collector of the branch transistor is connected to a second output node. The emitters of the branch transistor and the input stage transistor have the same reference ground.

[0007] When the level of the data transmitted on the line under test causes the relative voltage drop between the first and second output nodes to be outside the preset range, it is determined that the level of the data has drifted.

[0008] The above-mentioned data drift detection circuit for a storage array during data operations:

[0009] The circuit under test in each physical block of the storage array includes parallel bit lines under the same physical block, and any bit line under test under the same physical block is coupled to a single input node through an isolation capacitor.

[0010] The above-mentioned data drift detection circuit for a storage array during data operations:

[0011] A voltage source with a voltage value greater than the stated level is set between the reference ground and the input node to superimpose the level of the data transmitted on the line under test onto the voltage source, thereby improving the resolution of the data.

[0012] The above-mentioned data drift detection circuit for a storage array during data operations:

[0013] The system is equipped with a microprocessor for converting the analog voltage values ​​of the first and second output nodes into digital voltage values, and for calculating the relative voltage drop represented by the voltage values ​​between the first and second output nodes.

[0014] The above-mentioned data drift detection circuit for a storage array during data operations:

[0015] The microprocessor is also used to perform data operations on the storage array, including at least data read, data write, and data erase.

[0016] The above-mentioned data drift detection circuit for a storage array during data operations:

[0017] When using a subsequent shunt unit, it is connected in parallel with the preceding shunt unit, and it shunts the preceding shunt unit. The voltage divider portion of the subsequent shunt unit is coupled to the first output node, and the voltage divided by the voltage divider portion of the subsequent shunt unit is applied to the base of a branch transistor of the subsequent shunt unit; and

[0018] The collector of the branch transistor of the subsequent shunt unit is coupled to the second output node. The emitters of the branch transistor of the subsequent shunt unit and the input stage transistor have the same reference ground. One or more resistors are provided between the voltage divider portion of the subsequent shunt unit and the collector of the branch transistor of the subsequent shunt unit, between the first and second output nodes.

[0019] The above-mentioned data drift detection circuit for a storage array during data operations:

[0020] Under the premise of using the subsequent shunt unit, it is connected in parallel with the previous shunt unit, and it shunts the previous shunt unit. One or more resistors are provided between the first output node and an intermediate node, and one or more resistors are provided between the second output node and the intermediate node. The collector of the branch transistor of the previous shunt unit is indirectly coupled to the second output node through the resistor between the second output node and the intermediate node.

[0021] The voltage divider portion of the subsequent shunt unit is indirectly coupled to the first output node through a resistor between the first output node and the intermediate stage node. The voltage divided value provided by the voltage divider portion of the subsequent shunt unit is applied to the base of a branch transistor of the subsequent shunt unit. The collector of the branch transistor of the subsequent shunt unit is coupled to the second output node. The emitters of the branch transistor of the subsequent shunt unit and the input stage transistor have the same reference ground.

[0022] The above-mentioned data drift detection circuit for a storage array during data operations:

[0023] One or more capacitors are arranged between the first output node and the reference ground, and the level of the data transmitted on the line under test is used to compensate the current at the first output node in a positive or negative direction when the level changes.

[0024] One or more capacitors are arranged between the second output node and the reference ground, and the level of the data transmitted on the line under test is used to compensate the current at the second output node in a positive or negative direction when the level changes.

[0025] One or more capacitors are arranged between the base of the input stage transistor and the reference ground, which are used to compensate the current at the base of the input stage transistor in either the forward or reverse direction when the level of the data transmitted on the line under test changes.

[0026] This application relates to a method for detecting data drift during data operations in a storage array, characterized in that:

[0027] For a line under test in a storage array, an input node is coupled to the line under test, and a relative voltage drop is generated at the first and second output nodes;

[0028] An input stage transistor is provided to regulate the current between the first and second output nodes and the input node, and the first output node is configured to be coupled to the collector of the input stage transistor through a resistor, and the second output node is coupled to the base of the input stage transistor through a resistor, and one or more resistors are arranged between the first and second output nodes.

[0029] A pre-amplifier shunt unit is provided, which is configured to be connected in parallel with the input stage transistor and is used to shunt the input stage transistor. The voltage divider portion of the pre-amplifier shunt unit is connected to the collector of the input stage transistor, and the voltage divider value provided by the voltage divider portion is applied to the base of a branch transistor of the pre-amplifier shunt unit. The collector of the branch transistor is connected to a second output node, and the emitters of the branch transistor and the input stage transistor have the same reference ground.

[0030] Monitor the fluctuations in the relative voltage drop between the first and second output nodes:

[0031] When the voltage level of the data transmitted on the line under test causes the relative voltage drop between the first and second output nodes to be outside the preset range, it is determined that the voltage level of the transmitted data has drifted.

[0032] The above method involves placing one or more capacitors between the first output node and the reference ground, which are used to positively or negatively compensate the current at the first output node when the level of the data transmitted on the line under test changes.

[0033] One or more capacitors are arranged between the second output node and the reference ground, which are used to positively or negatively compensate the current at the second output node when the level of the data transmitted on the line under test changes.

[0034] One or more capacitors are arranged between the base of the input stage transistor and the reference ground, which are used to compensate the current at the base of the input stage transistor in either the forward or reverse direction when the level of the data transmitted on the line under test changes.

[0035] The above method: The line under test of each physical block in the storage array includes parallel bit lines under the same physical block, and any bit line under test under the same physical block is coupled to a single input node through an isolation capacitor.

[0036] The above method involves setting a voltage source with a voltage value greater than the level between the reference ground and the input node, superimposing the voltage source on the level of the data transmitted on the line under test, thereby increasing the resolution of the data.

[0037] The above method is equipped with a microprocessor to convert the analog voltage values ​​of the first and second output nodes into digital voltage values ​​and to calculate the relative voltage drop between the first and second output nodes.

[0038] The above method also includes microprocessors performing data operations on the storage array, including at least data read, data write, and data erase.

[0039] The above method, under the premise of using a subsequent shunt unit, is connected in parallel with the preceding shunt unit, and it shunts the preceding shunt unit; the voltage divider portion of the subsequent shunt unit is coupled to the first output node; and the voltage divided value provided by the voltage divider portion of the subsequent shunt unit is applied to the base of a branch transistor of the subsequent shunt unit; and

[0040] The collector of the branch transistor of the subsequent shunt unit is coupled to the second output node. The emitters of the branch transistor of the subsequent shunt unit and the input stage transistor have the same reference ground. One or more resistors are provided between the voltage divider portion of the subsequent shunt unit and the collector of the branch transistor of the subsequent shunt unit, between the first and second output nodes.

[0041] The above method: under the premise of using the subsequent shunt unit, it is connected in parallel with the previous shunt unit and it shunts the previous shunt unit. One or more resistors are provided between the first output node and an intermediate node, and one or more resistors are provided between the second output node and the intermediate node. The collector of the branch transistor of the previous shunt unit is indirectly coupled to the second output node through the resistor between the second output node and the intermediate node.

[0042] The voltage divider portion of the subsequent shunt unit is indirectly coupled to the first output node through a resistor between the first output node and the intermediate stage node. The voltage divided value provided by the voltage divider portion of the subsequent shunt unit is applied to the base of a branch transistor of the subsequent shunt unit. The collector of the branch transistor of the subsequent shunt unit is coupled to the second output node. The emitters of the branch transistor of the subsequent shunt unit and the input stage transistor have the same reference ground.

[0043] The above method: One or more capacitors are arranged between the first output node and the reference ground, and the level of the data transmitted on the line under test is used to compensate the current at the first output node in a positive or negative direction when the level changes.

[0044] One or more capacitors are arranged between the second output node and the reference ground, and the level of the data transmitted on the line under test is used to compensate the current at the second output node in a positive or negative direction when the level changes.

[0045] One or more capacitors are arranged between the base of the input stage transistor and the reference ground, which are used to compensate the current at the base of the input stage transistor in either the forward or reverse direction when the level of the data transmitted on the line under test changes.

[0046] This application relates to a data drift detection system for a storage array during data operations, comprising:

[0047] A microprocessor that performs data operations on the storage array;

[0048] An input node of the circuit under test is coupled to the storage array, and first and second output nodes are used to generate relative voltage drops, with the voltage values ​​of the first and second output nodes respectively output to the microprocessor;

[0049] An input stage transistor that regulates current between a first and a second output node and an input node, wherein the first output node is coupled to the collector of the input stage transistor via a resistor, the second output node is coupled to the base of the input stage transistor via a resistor, and one or more resistors are provided between the first and second output nodes.

[0050] A pre-shunting unit is connected in parallel with the input stage transistor and shunts the input stage transistor. The voltage divider portion of the pre-shunting unit is connected to the collector of the input stage transistor. The voltage divider value provided by the voltage divider portion is applied to the base of a branch transistor of the pre-shunting unit. The collector of the branch transistor is connected to a second output node, and the emitters of the branch transistor and the input stage transistor have the same reference ground.

[0051] When the microprocessor determines that the level of the data transmitted on the line under test causes the relative voltage drop between the first and second output nodes to be outside the preset range, it determines that the level of the data has drifted.

[0052] The above-mentioned data drift detection system for a storage array during data operations:

[0053] The circuit under test in each physical block of the storage array includes parallel bit lines under the same physical block, and any bit line under test under the same physical block is coupled to a single input node through an isolation capacitor.

[0054] The above-mentioned data drift detection system for a storage array during data operations:

[0055] A voltage source with a voltage value greater than the stated level is set between the reference ground and the input node to superimpose the level of the data transmitted on the line under test onto the voltage source, thereby improving the resolution of the data.

[0056] The above-mentioned data drift detection system for a storage array during data operations:

[0057] The equipped microprocessor is used to convert the analog voltage values ​​of the first and second output nodes into digital voltage values, and to calculate the relative voltage drop between the first and second output nodes.

[0058] The above-mentioned data drift detection system for a storage array during data operations:

[0059] The microprocessor is also used to perform data operations on the storage array, including at least data read, data write, and data erase.

[0060] The above-mentioned data drift detection system for a storage array during data operations:

[0061] When using a subsequent shunt unit, it is connected in parallel with the preceding shunt unit, and it shunts the preceding shunt unit. The voltage divider portion of the subsequent shunt unit is coupled to the first output node, and the voltage divided by the voltage divider portion of the subsequent shunt unit is applied to the base of a branch transistor of the subsequent shunt unit; and

[0062] The collector of the branch transistor of the subsequent shunt unit is coupled to the second output node. The emitters of the branch transistor of the subsequent shunt unit and the input stage transistor have the same reference ground. One or more resistors are provided between the voltage divider portion of the subsequent shunt unit and the collector of the branch transistor of the subsequent shunt unit, between the first and second output nodes.

[0063] The above-mentioned data drift detection system for a storage array during data operations:

[0064] Under the premise of using the subsequent shunt unit, it is connected in parallel with the previous shunt unit, and it shunts the previous shunt unit. One or more resistors are provided between the first output node and an intermediate node, and one or more resistors are provided between the second output node and the intermediate node. The collector of the branch transistor of the previous shunt unit is indirectly coupled to the second output node through the resistor between the second output node and the intermediate node.

[0065] The voltage divider portion of the subsequent shunt unit is indirectly coupled to the first output node through a resistor between the first output node and the intermediate stage node. The voltage divided value provided by the voltage divider portion of the subsequent shunt unit is applied to the base of a branch transistor of the subsequent shunt unit. The collector of the branch transistor of the subsequent shunt unit is coupled to the second output node. The emitters of the branch transistor of the subsequent shunt unit and the input stage transistor have the same reference ground.

[0066] The above-mentioned data drift detection system for a storage array during data operations:

[0067] One or more capacitors are arranged between the first output node and the reference ground, and the level of the data transmitted on the line under test is used to compensate the current at the first output node in a positive or negative direction when the level changes.

[0068] One or more capacitors are arranged between the second output node and the reference ground, and the level of the data transmitted on the line under test is used to compensate the current at the second output node in a positive or negative direction when the level changes.

[0069] One or more capacitors are arranged between the base of the input stage transistor and the reference ground, which are used to compensate the current at the base of the input stage transistor in either the forward or reverse direction when the level of the data transmitted on the line under test changes. Attached Figure Description

[0070] To make the objectives, features, and advantages described above more easily understood, the following detailed description of specific embodiments is provided in conjunction with the accompanying drawings. After reading the following description and referring to the accompanying drawings, the features and advantages of this application will become apparent.

[0071] Figure 1 It refers to the data information of different physical blocks within the memory being processed at different frequencies.

[0072] Figure 2 This is an optional example of a data drift detection circuit for a storage array during data operations.

[0073] Figure 3 A digital signal processor is used to replace a microcontroller as the main control chip for managing memory.

[0074] Figure 4 It is a simulation segment used to generate the relative voltage drop between the first and second output nodes.

[0075] Figure 5 It is a technology in which front-end splitter units and back-end splitter units can coexist in parallel splitting.

[0076] Figure 6 It is the parallel bit lines of the physical blocks that make up the memory array inside the memory coupled to the input node. Detailed Implementation

[0077] The technical solutions disclosed in this application will be clearly and completely described below with reference to specific embodiments. However, the described embodiments are only the embodiments used for description and illustration in this application and not all the embodiments. Based on these embodiments, those skilled in the art should recognize that any solution obtained without creative effort is within the protection scope of this application.

[0078] See Figure 1In terms of physical structure, memory typically consists of numerous physical blocks, and each physical block contains a large number of data pages. A typical example is the memory array inside flash memory. For ease of understanding, the diagram shows data pages BMA0 and BMA1 separately. Data page BMA0 contains numerous memory arrays sharing a word line, while a physical block contains numerous data pages controlled by different word lines. This is existing technology and will not be elaborated further.

[0079] See Figure 1 Data information Data_S1 to Data_S3 is recorded in data page BMA0. Erasing Data_S1 by selecting the memory cell string and its bit line is denoted as Era; writing Data_S2 by selecting the memory cell string and its bit line is denoted as Wrt; and reading Data_S3 by selecting the memory cell string and its bit line is denoted as Rea. Note that any specified data operation here can be replaced with different data operations of different types in alternative embodiments. Note that polymorphic content-addressable memory and content search operations are also applicable to the scheme of this application.

[0080] See Figure 1Let's assume the key characteristics of data operation Era (frequency, rate, or bandwidth) are pro1, data operation Wrt (frequency, rate, or bandwidth) are pro2, and data operation Rea (frequency, rate, or bandwidth) are pro3. Under different data transmission or operation characteristics, the probability of data error varies. Generally, high-speed scenarios like pro3 have a much higher error probability than pro1 and pro2, but mainstream data processing increasingly tends to use high-speed data interaction channels. A typical example is the generational upgrade of PCIe. It's important to note that one source of data error is crosstalk between parallel data bit lines. Because the cell strings within the same physical block often share the same semiconductor substrate, operations on a single memory cell string inevitably affect other neighboring memory cell strings. For example, consider reading from a memory array. When reading a page, voltage is applied to the word lines of other pages located on the same physical block but not selected. This ensures that the unselected pages and their memory transistors are conducting, allowing data to be read smoothly. However, applying high-frequency voltage to the gate control terminals of the memory transistors can cause them to be programmed—that is, electrons are attracted into the floating gate. This leads to bit flips and interference in these unintendedly programmed transistors. A further consequence is that the bitlines of a memory cell string may experience voltage deviations due to the presence of irregularly programmed transistors within them. This significantly increases the probability of bit errors during data operations on the memory cell strings containing this bitline and adjacent bitlines. This is one of the most significant negative impacts of crosstalk between parallel data bitlines. Typically, after an error is captured, it can be partially repaired using limited means or measures (such as erasing and rewriting). This application considers that local bit lines share the same common semiconductor substrate, which at least eliminates common perturbation factors. For example, applying a voltage to the common semiconductor substrate will result in approximately similar voltage or current perturbations on the bit lines and adjacent bit lines of a memory cell string, without significant differences. This is beneficial for data drift detection. However, specific circuits and schemes still need to be designed to determine whether the voltage level characterizing the logic data has actually caused a so-called drift. This is crucial for locating memory defects and error correction. Write operations can also induce bit flips. Irregular bit flips within a memory cell string can easily cause undesirable dark currents generated during data operations to affect itself and adjacent strings within the common substrate, potentially causing slight oscillations in the bit line data of itself and adjacent strings.

[0081] See Figure 2The data drift detection circuit for the memory array during data operations is designed to include an input node NX coupled to each line under test, such as a bit line, in the memory array, and a first output node N2 and a second output node N3 for generating a relative voltage drop. The bit line interface I / O is located at node N1, and the data stream is temporarily represented by the data Data_S at the bit line. The memory cells of the memory array are typically read page by page, and the internal storage information can be extracted from the numerous parallel bit lines.

[0082] See Figure 2 The data drift detection circuit includes an input stage transistor Q1 that regulates the current between the first output node N2, the second output node N3, and the aforementioned input node NX. The current regulation function of the input stage transistor Q1 will be further explained below: the current between nodes N2 and N3 and node NX is not fixed; it requires precise identification of the relative voltage drop between the first output node N2 (denoted as V1) and the second output node N3 (denoted as V2), for example, V2 / V1 (or V1 / V2). One key factor is whether the current regulation function and effect between nodes N2 and N3 and node NX can follow the high-speed data operation of node N1 rhythmically or frequently. As shown in the figure, the first output node N2 is coupled to the collector of the input stage transistor Q1 through resistor R2, and simultaneously, as shown in the figure, the second output node N3 is coupled to the base of the input stage transistor Q1 through resistor R4. In addition, as shown in the figure, one or more resistors, such as R3, are provided between the first output node N2 and the second output node N3.

[0083] See Figure 2The data drift detection circuit includes at least one pre-stage shunt unit, which mainly comprises a voltage divider section (such as series resistors R5 and R6) and a branch transistor Q2. This pre-stage shunt unit is connected in parallel with the input stage transistor Q1 and shunts the input stage transistor Q1. The voltage divider section of the pre-stage shunt unit is connected to the collector of the input stage transistor Q1; for example, the series resistors R5 and R6 of the voltage divider section are connected to the collector of the input stage transistor Q1, and the voltage divider section is connected between the collector of the input stage transistor Q1 and NG. The voltage divider section can divide and sample the voltage at the collector of the input stage transistor Q1. The voltage divided value provided by the voltage divider section is applied to the base of one branch transistor Q2 of the pre-stage shunt unit. The voltage divided value provided by the voltage divider section, such as the interconnection node of the series resistors R5 and R6 (i.e., the node where R5 and R6 are interconnected), is applied to the base of the branch transistor Q2 of the pre-stage shunt unit, thereby driving the branch transistor Q2 to conduct. Furthermore, the magnitude of the voltage divider value determines the magnitude of the drive current and the conduction current of transistor Q2. As shown in the figure, the collector of branch transistor Q2 is connected to the second output node N3, and the emitters of branch transistor Q2 and the input stage transistor Q1 share the same reference ground, NG. Optionally, branch transistor Q2 can be connected to the second output node N3 via one or more resistors R7. Optionally, a capacitor C4 is connected between the base of branch transistor Q2 and NG, and in a small-signal model, the charge of capacitor C4 and the voltage divider value together drive branch transistor Q2.

[0084] See Figure 2 Regarding the data drift detection circuit: If the level of the data transmitted on the line under test (e.g., a bit line) causes the relative voltage drop V2 / V1 or V1 / V2 between the first output node N2 and the second output node N3 to be outside the preset range, it is determined that the data represented by that level has drifted. The data level is often based on the logic values ​​of high and low levels to identify zero and one. The superposition of various unexpected noises on the data level often leads to unpredictable characteristics. Since noise has no specific pattern, it is necessary to distinguish whether the level is caused by a specific factor. This application focuses on crosstalk between different bit lines of a storage array, which is a specific factor in the storage field. In other words, although crosstalk between bit lines on the same physical block exhibits some random noise fluctuations in timing, these fluctuations are related to the logic zero or one processing of data storage. Therefore, it is necessary to implement signal feature extraction and noise processing through nonlinear methods. Thus, a data drift detection circuit is proposed.

[0085] See Figure 6In a memory array, the test line for each physical block comprises parallel bit lines within the same physical block. Examples include bit lines containing memory cell strings M11-M20, M21-M30, and M31-M30. The diagram shows a limited number of bit lines, and others not shown belong to the same physical block. In an optional example, any bit line under test within the same physical block of the memory array or memory can be coupled to a single input node NX location via an isolation capacitor C5. If each bit line is paired with a separate data drift detection circuit, the number of data drift detection circuits matches the number of bit lines. If all bit lines share the same data drift detection circuit, different bit lines can be time-divisionally coupled to the data drift detection circuit. Alternatively, several data drift detection circuits can be provided, and all bit lines can be divided into different bit line clusters, with each cluster sharing the same data drift detection circuit. In NAND flash memory, some cells are inherently unstable, and this instability increases with continued use. Typically, users employ ECC protection to correct for bit flipping during reads. For such physical blocks, data drift detection circuitry can enhance monitoring and management. The diagram shows the data flow (Data_S) of the bit line under test, such as the bit line I / O (coupled at N1). Node N1 is coupled to NX via C5.

[0086] See Figure 2One noteworthy concern is that in data drift detection circuits, considering that the high and low levels representing logic one or logic zero are typically based on minute voltages, especially in embedded electronic applications, the recognition rate can be low when errors such as inter-bit line crosstalk occur. A regulated voltage source is used between the reference ground NG and the input node NX, and its voltage value can theoretically be either larger or smaller than the level representing the data logic value (logic one or zero). However, in the optional embodiment shown, the voltage source Vbat is larger than the data level; in other words, the voltage source is larger than the absolute value of the high or low level of the data transmitted on the line under test. Regardless of whether the data transmitted on the line under test is high or low, it can be adaptively boosted and elevated: thus, the level of the data transmitted on the line under test can be superimposed on the voltage source Vbat to improve data resolution. When the voltage level of the data transmitted on the line under test (e.g., a bit line) causes the relative voltage drop V2 / V1 or V1 / V2 of the first output node N2 and the second output node N3 to fall outside the preset specified range, it is determined that the voltage level of the transmitted data has drifted or shifted. If the voltage level of the data has drifted, the data is highly likely to contain bit errors. In addition to triggering error correction measures, this system also provides a screening mechanism for error-prone pages and blocks, thereby locating locations prone to bit flips, charge leakage, or process defects such as electron tunneling.

[0087] See Figure 2 The negative terminal of the voltage source Vbat is coupled to the reference ground NG, while the positive terminal is directly coupled to the input node NX, or the positive terminal of Vbat is coupled to the input node NX through resistor R1. The illustrated voltage source embodiments include conventional batteries, linear regulated power sources, and various DC power supplies; switching power supplies are preferred. If a switching power supply cannot effectively suppress its ripple, the disadvantage of using a switching power supply for the voltage source Vbat is the introduction of switching noise superimposed on the transmitted data. This noise is likely to mix with bit line noise. Note that in this scenario, the voltage source Vbat can withstand high and low level surges under normal conditions. In fact, a capacitor can be used instead, as this application allows charging the capacitor using high and low levels, and a parallel discharge branch can also be provided for the capacitor-type voltage source.

[0088] See Figure 2The data drift detection circuit is equipped with a microprocessor. As shown in the figure, the microprocessor converts the analog voltage values ​​(V1 and V2) of the first output node N2 and the second output node N3 into their respective easily processed digital voltage values. The analog voltage value V1 of the first output node N2 is converted into the corresponding digital voltage value V1_digital by the microprocessor, and the analog voltage value V2 of the second output node N3 is converted into the corresponding digital voltage value V2_digital by the microprocessor. This process is an analog-to-digital converter (ADC), and the microprocessor usually has the function of converting analog signals into digital signals. The microprocessor can then calculate the relative voltage drop represented by the voltage values ​​between the first and second output nodes: the relative voltage drop is V1 / V2 or vice versa (V2 / V1). Using digital voltage values, the relative voltage drop is V1_digital / V2_digital or vice versa (V2_digital / V1_digital). The ratio of the voltage value (analog or digital) of the first output node to the voltage value (analog or digital) of the second output node is also considered. The voltage count (analog or digital) of the second output node is greater than the voltage count (analog or digital) of the first output node.

[0089] See Figure 2 In an optional embodiment, the data drift detection circuit is a discrete circuit that can serve as an external circuit for the microprocessor. The data drift detection circuit can be fabricated as an integrated chip, or it can be configured as a separate electronic component mounted on a circuit board.

[0090] See Figure 2 In an optional embodiment, the data drift detection circuit is a functional module that can serve as an internal circuit of the microprocessor. The data drift detection circuit is thus fabricated and integrated as a sub-circuit of the microprocessor chip, and is pre-fabricated within the microprocessor during the wafer fabrication process.

[0091] See Figure 3 In alternative embodiments, a microprocessor using a single-chip microcomputer (MCU) is employed, but there are numerous alternatives, such as a digital signal processor (DSP). Field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), and application-specific integrated circuits (ASICs) are all alternative embodiments of MCUs. If an ASIC is designed, the data drift detection circuitry can be integrated internally as a sub-module; however, it is difficult to directly integrate data drift detection circuitry into commercially available MCUs, FPGAs, and DSPs when using standardized commercial microprocessors.

[0092] See Figure 3In optional embodiments, the microprocessor, in addition to cooperating with the data drift detection circuit to extract and capture the analog and digital voltage values ​​of the first output node N2 and the second output node N3, and further calculating the relative voltage drop between the first output node N2 and the second output node N3, and determining whether the level of the data transmitted on the line under test has caused the relative voltage drop between the first output node N2 and the second output node N3 to be outside the preset specified range, can also be used to perform conventional data operations on the memory array, including at least data read, data write, or data erase. The microprocessor plays many roles in this application, but its most important and crucial function is determining whether the level of the data transmitted on the line under test has drifted. The aforementioned preset specified range can be programmed into the microprocessor's internal or external memory.

[0093] See Figure 4 In an optional embodiment, the above figure shows the analog signal extracted from the first output node N2 of the data drift detection circuit in a simulation. The horizontal axis represents time (e.g., milliseconds, ms), and the vertical axis represents the approximate waveform of the analog voltage number V1. The microprocessor needs to digitize the analog signal. Microprocessors typically have a built-in high-speed analog-to-digital converter (ADC) sampling module. In optional application scenarios, an ADC chip can be used to sample the analog voltage number V1 separately and transmit it to the microprocessor. Finally, the analog voltage number V1 of the first output node N2 is converted into the corresponding digital voltage number V1_digital by the microprocessor.

[0094] See Figure 4 In an optional embodiment, the figure below shows the analog signal extracted from the second output node N3 of the data drift detection circuit in a simulation. The horizontal axis represents time (e.g., milliseconds, ms), and the vertical axis represents the approximate waveform of the analog voltage V2. The microprocessor needs to digitize the analog signal. Microprocessors typically have a built-in high-speed analog-to-digital converter (ADC) sampling module. In optional application scenarios, an ADC chip can be used to sample the analog voltage V2 separately and transmit it to the microprocessor. Finally, the analog voltage V2 of the second output node N3 is converted into the corresponding digital voltage V2_digital by the microprocessor.

[0095] See Figure 5In the embodiments described above, a pre-stage shunt unit is used: the pre-stage shunt unit is connected in parallel with the input stage transistor Q1, and the pre-stage shunt unit mainly shunts the input stage transistor Q1. The voltage divider portion of the pre-stage shunt unit (e.g., including R5 and R6) is connected to the collector of the input stage transistor Q1. The voltage divided by the voltage divider portion is applied to the base of a branch transistor Q2 in the pre-stage shunt unit. The collector of the branch transistor Q2 is connected to the second output node N3, and the emitter of the branch transistor Q2 and the emitter of the input stage transistor Q1 both have the same reference ground NG potential. The embodiments described above use a single-stage shunt scheme.

[0096] See Figure 5 In the embodiment illustrated, a multi-stage shunt unit is used: when using a subsequent shunt unit, the subsequent shunt unit and the preceding shunt unit are connected in parallel, and the subsequent shunt unit shunts the current from the preceding shunt unit. In this embodiment, the voltage divider portion of the subsequent shunt unit (e.g., a voltage divider including resistors R8 and R9) is coupled to the first output node N2. The voltage division value provided by the voltage divider portion of the subsequent shunt unit (e.g., including resistors R8 and R9) is applied to the base of a branch transistor Q3 of the subsequent shunt unit.

[0097] See Figure 5 The voltage divider portion of the subsequent shunt unit is coupled to the first output node N2. For example, the series resistors R8 and R9 of the voltage divider portion are connected to the first output node N2 through another resistor R3. As shown in the figure, the voltage divider portion is coupled between the first output node N2 and the reference ground NG. The voltage divider portion, such as the series resistors R8 and R9, provides a voltage divider value at their interconnection node, i.e., at the node where R8 and R9 are interconnected. This voltage divider value is applied to the base of the branch transistor Q3 in the subsequent shunt unit, thereby driving the branch transistor Q3 to conduct. The magnitude of the voltage divider value determines the magnitude of the drive current and the conduction current of transistor Q3. As shown in the figure, the collector of the branch transistor Q3 is connected to the second output node N3, and the emitters of the branch transistor Q3 and the input stage transistor Q1 have the same reference ground, i.e., NG. Optionally, the branch transistor Q3 can be connected to the second output node N3 through one or more resistors R10. Optionally, a capacitor C6 can be connected between the base of the branch transistor Q3 and NG, and in the small-signal model, the charge of the capacitor C6 and the voltage division value of the voltage divider portion can drive the branch transistor Q3 together.

[0098] See Figure 5In the embodiment illustrated, a multi-stage shunt unit is used: the collector of the branch transistor Q3 in the subsequent shunt unit is coupled to the second output node N3, and the emitters of the branch transistor Q3 and the input stage transistor Q1 have the same reference ground NG potential. In addition, as shown in the figure, one or more resistors R3, R11, etc., are provided between the first output node N2 and the second output node N3. The voltage divider portion of the subsequent shunt unit can be indirectly coupled to the first output node N2 through a resistor such as R3 between the first output node N2 and the second output node N3. Furthermore, considering that one or more resistors R3 are already provided between the first output node N2 and the second output node N3, the voltage divider portion of the subsequent shunt unit is coupled to the first output node N2: the voltage divider portion of the subsequent shunt unit is indirectly coupled to the first output node N2 through a resistor R3 between the first output node N2 and the second output node N3. Here, R3 can be called the preceding stage resistor, and R11 can be called the following stage resistor.

[0099] See Figure 5 In the embodiment illustrated in this paper, a multi-stage shunt unit is used. Note that in this case, one or more resistors R11 are provided between the voltage divider portion of the subsequent shunt unit (such as those containing resistors R8 and R9) and the collector of the branch transistor Q3 of the subsequent shunt unit, between the first output node N2 and the second output node N3. Another term for the voltage divider portion in this application is a voltage divider. Voltage dividers typically include transistor voltage dividers, resistor voltage dividers, and even capacitor voltage dividers, etc., but this application uses a resistor voltage divider for description and explanation.

[0100] See Figure 5 In the embodiment illustrated, a multi-stage shunt unit is used: at least one front-stage shunt unit connected in parallel with the input stage transistor Q1. The front-stage shunt unit still shunts the input stage transistor Q1. The voltage divider portion of the front-stage shunt unit (e.g., including resistors R5 and R6) is connected to the collector of the input stage transistor. The voltage divided by the voltage divider portion (resistors R5 and R6) is applied to the base of a branch transistor of the front-stage shunt unit, namely Q2. In this example, the collector of branch transistor Q2 is indirectly coupled or connected to the second output node N3 through another resistor R11 between the first output node N2 and the second output node N3. The emitters of branch transistor Q2 and input stage transistor Q1 in the figure have the same reference ground NG. In an alternative example, resistors R7 and R10 can be ignored; note that R7 and R10 are not between N2 and N3.

[0101] See Figure 2In an optional, albeit not mandatory, example, one or more capacitors C1, as shown in the figure, are arranged between the first output node N2 and the reference ground NG. Capacitor C1 is positioned between node N2 and node NM. When the level of the data transmitted on the line under test changes, one of the functions of capacitor C1 is to compensate for the current at the first output node N2 in either the forward or reverse direction. Node NM is connected to the reference ground NG. The current of the input stage transistor Q1 changes drastically with the level of the data transmitted on the line under test. The pre-stage shunt unit is connected in parallel with the input stage transistor and shunts the current of the input stage transistor Q1. When the current of the input stage transistor Q1 changes drastically, the pre-stage shunt unit may not be able to maintain a high-speed response to the high-frequency change. Capacitor C1, however, has excellent high-frequency response characteristics and can quickly compensate for the current change at the first output node N2 in either the forward or reverse direction when the current of the input stage transistor Q1 changes drastically. For example, capacitor C1 flows forward from node N2 to node NM to compensate for current changes at the first output node N2. Alternatively, capacitor C1 flows backward from node NM to node N2 to compensate for current changes at the first output node N2. Here, capacitor C1 and its impedance characteristics play a crucial role in maintaining current balance at the first output node and in ensuring relatively high resolution of the relative voltage drop between the first output node N2 and the second output node N3 during synchronization. This application configures one or more capacitors between the first output node and reference ground. The level of the data transmitted on the line under test is used to compensate for current changes at the first output node in either the forward or reverse direction. This is an optional embodiment.

[0102] See Figure 2In an optional, albeit not mandatory, example, one or more capacitors C2, as shown in the figure, are arranged between the second output node N3 and the reference ground NG. Capacitor C2 is positioned between node N3 and node NM. When the data level transmitted on the line under test changes, one of the functions of capacitor C2 is to compensate for the current at the second output node N3 in either the forward or reverse direction. Node NM is connected to the reference ground NG. The current of the input stage transistor Q1 changes drastically with the data level changes transmitted on the line under test. The pre-stage shunt unit is connected in parallel with the input stage transistor and shunts the current of the input stage transistor Q1. When the current of the input stage transistor Q1 changes drastically, the pre-stage shunt unit may not be able to maintain a high-speed response to the high-frequency change. Capacitor C2, however, has excellent high-frequency response characteristics and can quickly compensate for the current change at the second output node N3 in either the forward or reverse direction when the current of the input stage transistor Q1 changes drastically. For example, capacitor C2 flows forward from node N3 to node NM to compensate for current changes at the second output node N3. Alternatively, capacitor C2 flows backward from node NM to node N3 to compensate for current changes at the second output node N3. Here, capacitor C2 and its impedance characteristics play a crucial role in maintaining current balance at the second output node and in ensuring relatively high resolution of the relative voltage drop between the first output node N2 and the second output node N3 during synchronization. This application configures one or more capacitors between the second output node and reference ground. The level of the data transmitted on the line under test is used to compensate for current changes at the second output node in either the forward or reverse direction. This is an optional embodiment.

[0103] See Figure 2In an optional, albeit not mandatory, example, one or more capacitors C3 are arranged between the base of the input stage transistor Q1 and the reference ground NG, as shown in the figure. Capacitor C3 is positioned between the base of Q1 and node NM. When the data level transmitted on the circuit under test changes, one of the functions of capacitor C3 is to compensate for the current at the base of the input stage transistor Q1 in either the forward or reverse direction. Node NM is connected to the reference ground NG. The current of the input stage transistor Q1 changes drastically with the level of the data transmitted on the circuit under test. The pre-stage shunt unit is connected in parallel with the input stage transistor and shunts the current of the input stage transistor Q1. When the current of the input stage transistor Q1 changes drastically, the pre-stage shunt unit may not be able to maintain a high-speed response to the high-frequency change. Capacitor C3, however, has excellent high-frequency response characteristics and can quickly compensate for the current change at the base of the input stage transistor Q1 in either the forward or reverse direction when the current changes drastically. For example, capacitor C3 flows forward from the base of Q1 to node NM to compensate for current changes at the base of the input stage transistor. Alternatively, capacitor C3 flows backward from node NM to the base of Q1 to compensate for current changes at the base of the input stage transistor. Here, capacitor C3 and its impedance characteristics play a crucial role in maintaining current balance at the base of the input stage transistor and in ensuring relatively high resolution of the relative voltage drop between the first output node N2 and the second output node N3 during synchronization. This application configures one or more capacitors between the base of the input stage transistor and reference ground. The level of the data transmitted on the circuit under test is used to compensate for the current at the base of the input stage transistor in either the forward or reverse direction during transitions. This is an optional embodiment.

[0104] See Figure 2 In an optional, albeit not mandatory, first output node N2 is coupled to the collector of input stage transistor Q1 via resistor R2. Additionally, as shown in the figure, second output node N3 is coupled to the base of input stage transistor Q1 via resistor R4. Further, as shown in the figure, one or more resistors, such as R3 and / or R11, are provided between first output node N2 and second output node N3. Capacitor C1 is connected between first output node N2 and the reference ground NG, capacitor C2 is connected between second output node N3 and the reference ground NG, and capacitor C3, as shown in the figure, is connected between the base of input stage transistor Q1 and the reference ground NG.

[0105] See Figure 2 This application also relates to a data drift detection method for a storage array during data operations. The data drift detection method mainly includes: for a line under test, such as a bit line, in the storage array, an input node NX can be coupled to the line under test, generating a relative voltage drop at the first and second output nodes N2 and N3.

[0106] See Figure 2 An input stage transistor Q1 is provided to regulate the current between a first output node N2, a second output node N3 and an input node NX. The first output node N2 is coupled to the collector of the input stage transistor Q1 through a resistor such as R2, the second output node N3 is coupled to the base of the input stage transistor Q1 through a resistor such as R4, and one or more resistors (such as R3 and / or R11) are arranged between the first and second output nodes N2 and N3.

[0107] See Figure 2 A pre-amplifier shunt unit is provided, which is connected in parallel with the input stage transistor Q1. The pre-amplifier shunt unit is used to shunt the input stage transistor Q1. The voltage divider portion of the pre-amplifier shunt unit, such as a voltage divider including resistors R5 and R6, is connected to the collector of the input stage transistor Q1. The voltage divider value provided by the voltage divider portion, such as the voltage divider value provided at the interconnection node of resistors R5 and R6, is applied to the base of the branch transistor Q2 of the pre-amplifier shunt unit. The collector of the branch transistor Q2 is connected to the second output node N3, and the emitter of the branch transistor Q2 and the emitter of the input stage transistor Q1 are also configured to have the same reference ground NG potential. Regarding the data drift detection method, it further includes: monitoring the fluctuation of the relative voltage drop between the first output node N2 and the second output node N3: when the line under test (e.g., Figure 6 If the voltage level of the data transmitted on the bit line of the storage array causes the relative voltage drop between the first output node N2 and the second output node N3 to be outside the pre-defined range, then the voltage level of the transmitted data is determined to have drifted (e.g., a point of error).

[0108] See Figure 2 Regarding the data drift detection method, one or more capacitors C1 as shown in the figure are arranged between the first output node N2 and the reference ground NG. When the level of the data transmitted on the line under test (such as a bit line) changes, the capacitor C1 is used to compensate the current at the first output node N2 in either the forward or reverse direction.

[0109] See Figure 2 Regarding the data drift detection method, one or more capacitors C2, as shown in the figure, are arranged between the second output node N3 and the reference ground NG. When the level of the data transmitted on the line under test (such as a bit line) changes, the capacitor C2 is used to compensate the current at the second output node N3 in either the forward or reverse direction.

[0110] See Figure 2Regarding the data drift detection method, one or more capacitors C3 as shown in the figure are arranged between the base of the input stage transistor Q1 and the reference ground NG. When the level of the data transmitted on the line under test (such as a bit line) changes, the capacitor C3 is used to compensate the current at the base of the input stage transistor Q1 in either the forward or reverse direction.

[0111] See Figure 2 This application also relates to a data drift detection system for a storage array during data operations. The data drift detection system mainly includes: a microprocessor (such as a microcontroller, digital signal processor, programmable logic device, or application-specific integrated circuit) that performs data operations on the storage array; an input node NX coupled to each line under test (such as a bit line) in the storage array; and a first output node N2 and a second output node N3 for generating a relative voltage drop. The voltage values ​​of the first output node N2 and the second output node N3 are respectively output to the aforementioned microprocessor. In the figure, the microprocessor is an MCU as an example.

[0112] See Figure 2 This application also relates to a data drift detection system for a storage array during data operations. The data drift detection system further includes: an input stage transistor Q1 that regulates the current between the first output node N2, the second output node N3, and the input node NX; the first output node N2 is coupled to the collector of the input stage transistor Q1 via a resistor R2; and the second output node N3 is coupled to the base of the input stage transistor Q1 via a resistor R4. The circuit is also designed to have one or more resistors R3 (or resistor R11) positioned between the first output node N2 and the second output node N3. A microprocessor extracts the voltage information of nodes N2 and N3.

[0113] See Figure 2 This application also relates to a data drift detection system for a memory array during data operations. The data drift detection system further includes: a pre-shunting unit connected in parallel with the input stage transistor Q1, and the pre-shunting unit shunting the input stage transistor Q1. A voltage divider portion of the pre-shunting unit, such as a resistor divider (R5 / R6), is connected to the collector of the input stage transistor Q1. The voltage divider value provided by the voltage divider portion, such as the voltage divider value (provided at the interconnection node of R5 / R6), is applied to the base of a branch transistor Q2 illustrated in the pre-shunting unit. The collector of the branch transistor Q2 is connected to a second output node N3, and the emitter of the branch transistor Q2 in the pre-shunting unit and the emitter of the input stage transistor Q1 have the same reference ground NG.

[0114] See Figure 2This application also relates to a data drift detection system for storage arrays during data operations. Regarding the data drift detection system: when a microprocessor (MCU, DSP, FPGA, SOC, ASIC, etc.) determines that the voltage level of the data transmitted on the line under test causes the relative voltage drop between the first output node N2 and the second output node N3 to be outside a preset specified range, the microprocessor determines that the voltage level representing the data has drifted. Drift often leads to bit errors in the data information. See also... Figure 6 The microprocessor is also used to perform data operations on the memory array, including at least data reading, data writing, or data erasure. In other words, the microprocessor originally performs data operations on the memory array. Examples of memory arrays in the figure are memory cell strings containing memory transistors M11-M20, memory cell strings containing memory transistors M21-M30, and memory cell strings containing memory transistors M31-M30.

[0115] See Figure 2 Regarding the detection circuit, corresponding methods, and system: As shown in the figure, the input node NX is coupled to the circuit under test in the memory array (see...). Figure 6 A series of bit lines with I / O ports are provided, including a first output node N2 and a second output node N3 for generating a relative voltage drop. An input stage transistor Q1 is provided to regulate the current between the first output node N2, the second output node N3, and the input node NX. The first output node N2 is coupled to the collector of the input stage transistor Q1 via a resistor, and the second output node N3 is coupled to the base of the input stage transistor Q1 via a resistor. One or more resistors are provided between the first output node N2 and the second output node N3. Additionally, a pre-shunting unit is included, connected in parallel with the input stage transistor Q1. The pre-shunting unit shunts current to the input stage transistor Q1. A voltage divider portion (such as a voltage divider) of the pre-shunting unit is connected to the collector of the input stage transistor Q1. The voltage division value provided by the voltage divider portion (such as the voltage divided by the voltage divider) is applied to the base of the branch transistor Q2 of the pre-shunting unit. The collector of the branch transistor Q2 is connected to the second output node N3, and the emitters of the branch transistor Q2 and the input stage transistor Q1 have the same reference ground NG potential. In an optional embodiment, refer to... Figure 6Referring to the bit lines containing the memory cell strings of storage transistors M11-M20, and the bit lines containing the memory cell strings of storage transistors M21-M30 and M31-M30, etc., assuming they belong to the same physical block. As mentioned earlier, for a memory cell string in the memory array with bit flips, if the test line (e.g., bit line) of an adjacent memory cell string located in the same physical block experiences voltage oscillation deviation during data operation due to its bit flip event, causing the voltage level of the data transmitted on the test line to cause the relative voltage drop between the first output node N2 and the second output node N3 to be outside the preset specified range, then it is determined that the voltage level of the data has drifted. Based on this, it can be inferred that the test line itself or its nearby memory cell strings with drifted voltage levels are suspected to be sources of error. Note that the read and write operations of the memory cell string containing the drifted test line and its nearby memory cell strings are performed on a page-by-page basis. Therefore, in an optional embodiment: the test line of each physical block in the storage array includes parallel bit lines under the same physical block; for a storage cell string in the storage array with bit flipping, the test line such as the bit line of the adjacent storage cell string located in the same physical block has a voltage deviation during data operation due to the bit flipping, so that the level of the data transmitted on the test line such as the bit line causes the relative voltage drop between the first output node and the second output node to be outside the preset specified range, then it is determined that the level of the data has drifted.

[0116] See Figure 6 When using a downstream shunt unit, the downstream shunt unit and the upstream shunt unit are connected in parallel, and the downstream shunt unit shunts the upstream shunt unit. One or more resistors, such as R3, are provided between the first output node N2 and the intermediate node NY, and one or more resistors, such as R11, are provided between the second output node N3 and the intermediate node NY. The collector of the branch transistor Q2 inside the upstream shunt unit is indirectly coupled to the second output node N3 through a resistor, such as R11, between the second output node N3 and the intermediate node NY. If the collector of the branch transistor Q2 uses resistor R7, the collector of transistor Q2 is first indirectly coupled to the second output node N3 via resistor R7 and then through a resistor, such as R11, between the second output node N3 and the intermediate node NY.

[0117] See Figure 6When using a subsequent shunt unit, the subsequent shunt unit has a voltage divider section, for example, a resistor divider (including resistors R8 and R9). The voltage divider section is indirectly coupled to the first output node N2 via a resistor such as R3 between the first output node N2 and the aforementioned intermediate stage node NY. The voltage divider section of the subsequent shunt unit provides a divided voltage value (between resistors R8 and R9) applied to the base of the branch transistor Q3 of the subsequent shunt unit, and the collector of the branch transistor Q3 of the subsequent shunt unit is coupled to the second output node N3. The emitter of the branch transistor Q3 of the subsequent shunt unit and the emitter of the input stage transistor Q1 have the same reference ground NG potential. If the collector of the branch transistor Q3 of the subsequent shunt unit uses resistor R10, the collector of transistor Q3 is indirectly coupled to the second output node N3 via resistor R10. This is an example of using a subsequent shunt unit and a preceding shunt unit.

[0118] The foregoing description and accompanying drawings have provided typical embodiments of specific structures for specific implementations. The above-described invention presents preferred embodiments, but these are not intended to be limiting. Various changes and modifications will undoubtedly be apparent to those skilled in the art after reading the foregoing description. Therefore, the appended claims should be considered to cover all changes and modifications that encompass the true intent and scope of the invention. Any and all equivalent scope and content within the scope of the claims should be considered to still fall within the intent and scope of the invention.

Claims

1. A data drift detection circuit for a storage array during data operations, characterized in that, include: An input node of the line under test coupled to the memory array, and first and second output nodes for generating relative voltage drops; The circuit under test in each physical block of the storage array includes parallel bit lines under the same physical block, and any bit line under test under the same physical block is coupled to a single input node through an isolation capacitor; An input-level transistor that regulates current between a first and a second output node and an input node, wherein the first output node is coupled to the collector of the input-level transistor via a resistor, the second output node is coupled to the base of the input-level transistor via a resistor, and one or more resistors are provided between the first and second output nodes; wherein the input node is connected to the collector of the input-level transistor. At least one pre-stage shunt unit is connected in parallel with the input stage transistor and shunts the input stage transistor. The voltage divider portion of the pre-stage shunt unit is connected to the collector of the input stage transistor. The voltage divider value provided by the voltage divider portion is applied to the base of a branch transistor of the pre-stage shunt unit. The collector of the branch transistor is connected to a second output node. The emitters of the branch transistor and the input stage transistor have the same reference ground. When the level of the data transmitted on the line under test causes the relative voltage drop between the first and second output nodes to be outside the preset range, it is determined that the level of the data has drifted.

2. The data drift detection circuit for a storage array during data operations according to claim 1, characterized in that: A voltage source with a voltage value greater than the level is set between the reference ground and the input node to superimpose the level of the data transmitted on the line under test onto the voltage source, thereby improving the resolution of the data.

3. The data drift detection circuit for a storage array during data operations according to claim 1, characterized in that: It is equipped with a microprocessor for converting the analog voltage values ​​of the first and second output nodes into digital voltage values ​​and calculating the relative voltage drop between the first and second output nodes.

4. The data drift detection circuit for a storage array during data operations according to claim 3, characterized in that: The microprocessor is also used to perform data operations on the storage array, including at least data read, data write, and data erase.

5. The data drift detection circuit for a storage array during data operations according to claim 1, characterized in that: When using a subsequent shunt unit, it is connected in parallel with the preceding shunt unit, and it shunts the preceding shunt unit. The voltage divider part of the subsequent shunt unit is coupled to the first output node, and the voltage divider value provided by the voltage divider part of the subsequent shunt unit is applied to the base of a branch transistor of the subsequent shunt unit. as well as The collector of the branch transistor of the subsequent shunt unit is coupled to the second output node. The emitters of the branch transistor of the subsequent shunt unit and the input stage transistor have the same reference ground. One or more resistors are provided between the voltage divider portion of the subsequent shunt unit and the collector of the branch transistor of the subsequent shunt unit, between the first and second output nodes.

6. The data drift detection circuit for a storage array during data operations according to claim 1, characterized in that: One or more capacitors are arranged between the first output node and the reference ground, which are used to positively or negatively compensate the current at the first output node when the level of the data transmitted on the line under test changes. One or more capacitors are arranged between the second output node and the reference ground, which are used to positively or negatively compensate the current at the second output node when the level of the data transmitted on the line under test changes. One or more capacitors are arranged between the base of the input stage transistor and the reference ground, which are used to positively or negatively compensate the current at the base of the input stage transistor when the level of the data transmitted on the line under test changes.

7. A method for detecting data drift during data operations in a storage array, characterized in that: For a circuit under test in a memory array, an input node is coupled to the circuit under test, and a relative voltage drop is generated at the first and second output nodes; the circuit under test of each physical block in the memory array includes parallel bit lines under the same physical block, and any bit line under test under the same physical block is coupled to a single input node through an isolation capacitor; An input-level transistor is provided for current regulation between a first and a second output node and an input node. The first output node is configured to be coupled to the collector of the input-level transistor via a resistor, and the second output node is coupled to the base of the input-level transistor via a resistor. One or more resistors are arranged between the first and second output nodes. The input node is connected to the collector of the input-level transistor. A pre-amplifier shunt unit is provided, which is configured to be connected in parallel with the input stage transistor and is used to shunt the input stage transistor. The voltage divider portion of the pre-amplifier shunt unit is connected to the collector of the input stage transistor, and the voltage divider value provided by the voltage divider portion is applied to the base of a branch transistor of the pre-amplifier shunt unit. The collector of the branch transistor is connected to a second output node, and the emitters of the branch transistor and the input stage transistor have the same reference ground. Monitor the fluctuations in the relative voltage drop between the first and second output nodes: When the voltage level of the data transmitted on the line under test causes the relative voltage drop between the first and second output nodes to be outside the preset range, it is determined that the voltage level of the transmitted data has drifted.

8. The method according to claim 7, characterized in that: One or more capacitors are arranged between the first output node and the reference ground to compensate the current at the first output node in either the forward or reverse direction when the level of the data transmitted on the line under test changes. One or more capacitors are arranged between the second output node and the reference ground to compensate the current at the second output node in either the forward or reverse direction when the level of the data transmitted on the line under test changes. One or more capacitors are arranged between the base of the input stage transistor and the reference ground, which are used to positively or negatively compensate the current at the base of the input stage transistor when the level of the data transmitted on the line under test changes.

9. A data drift detection system for a storage array during data operations, characterized in that, include: A microprocessor that performs data operations on the storage array; An input node of the circuit under test is coupled to the storage array, and first and second output nodes are used to generate a relative voltage drop, with the voltage numbers of the first and second output nodes respectively output to the microprocessor; the circuit under test of each physical block in the storage array includes parallel bit lines under the same physical block, and any bit line under test under the same physical block is coupled to a single input node through an isolation capacitor; An input-level transistor that regulates current between a first and a second output node and an input node, wherein the first output node is coupled to the collector of the input-level transistor via a resistor, the second output node is coupled to the base of the input-level transistor via a resistor, and one or more resistors are provided between the first and second output nodes; wherein the input node is connected to the collector of the input-level transistor. A pre-shunting unit is connected in parallel with the input stage transistor and shunts the input stage transistor. The voltage divider portion of the pre-shunting unit is connected to the collector of the input stage transistor. The voltage divider value provided by the voltage divider portion is applied to the base of a branch transistor of the pre-shunting unit. The collector of the branch transistor is connected to a second output node, and the emitters of the branch transistor and the input stage transistor have the same reference ground. When the microprocessor determines that the level of the data transmitted on the line under test causes the relative voltage drop between the first and second output nodes to be outside the preset range, it determines that the level of the data has drifted.

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