Preparation method of through hole and semiconductor device

Abstract

The invention provides a preparation method of a through hole and a semiconductor device, and belongs to the field of semiconductors. The preparation method of the through hole comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises an etching stop layer; coating a first photoresist on the surface of the semiconductor structure, and performing first PRB baking on the first photoresist to obtain a first photoresist layer; the surface of the first photoresist layer is coated with second photoresist, second PRB baking is carried out on the second photoresist to obtain a second photoresist layer, and the electrostatic sensitivity of the second photoresist layer is lower than that of the first photoresist layer; exposing the first photoresist layer and the second photoresist layer; developing the first photoresist layer and the second photoresist layer to form a through hole preparation region so as to expose the semiconductor structure at the bottom of the through hole preparation region; and etching the semiconductor structure at the bottom of the through hole preparation region until the etching stop layer is etched to form a through hole. According to the method, development residues caused by static electricity of the photoresist can be avoided, and the morphology of the through hole is ensured.

Description

Technical Field

[0001] This application belongs to the field of semiconductors, and in particular relates to a method for fabricating a through-hole and a semiconductor device. Background Technology

[0002] Semiconductor devices are structurally composed of stacked film layers, including semiconductor layers and metal layers. To ensure that signals can be transmitted between these film layers, vias are typically formed using photolithography and etching processes.

[0003] In existing via fabrication processes, a photoresist layer (such as a photoresist layer) is typically formed first on the surface of a semiconductor layer. The photoresist layer is then exposed and developed to create a pattern (i.e., a pattern corresponding to the via). Under the obstruction of the patterned photoresist layer, the semiconductor layer is etched, and the photoresist layer is removed, resulting in the via formed in the semiconductor layer.

[0004] However, due to limitations in photolithography processes, the photoresist layer used for through-holes is generally a photoresist layer prone to static electricity. The core performance requirements of the photoresist layer are generally related to its insulation properties (static susceptibility). Because the size of through-holes is extremely small (typically nanometer-scale), this necessitates a photoresist with extremely high resolution. High-resolution photoresist layers typically require low molecular weight / narrow molecular weight distribution and a high-sensitivity chemical structure. These characteristics essentially require high-purity organic polymers, i.e., excellent insulators. Furthermore, the photoresist layer used in through-hole fabrication requires further requirements on its etching resistance (to prevent the photoresist layer from being simultaneously etched during the through-hole etching process). This further necessitates a high cross-linking density in the photoresist layer used in through-hole fabrication. A highly cross-linked, dense structure further hinders charge migration and exacerbates insulation problems. All these characteristics indicate that the photoresist layer used for through-holes requires strong insulation properties.

[0005] The stronger the insulating properties of the photoresist layer, the stronger its ability to impede charge movement. This leads to the accumulation of charge in the photoresist layer during via fabrication, thus forming an electrostatic field (i.e., stronger insulation makes it easier to generate static electricity). Furthermore, because the photoresist layer used in via fabrication has a low aperture ratio and a large specific surface area, the photoresist layer is highly susceptible to static electricity during development. Simultaneously, the photoresist layer is affected by the development process, resulting in a pH shock effect and the formation of development residues (i.e., some photoresist layer is not completely removed during development). Additionally, the static electricity generated in the photoresist layer during development inevitably causes development residues to adhere to the semiconductor layer in the via fabrication area. These development residues result in poor-quality vias or, due to their obstruction, prevent the etching process from etching the semiconductor layer to form a via. Summary of the Invention

[0006] In view of this, this application provides a method for fabricating a through-hole and a semiconductor device, which aims to create a through-hole with good morphology and improve the performance and reliability of the semiconductor device including the through-hole by creating a through-hole with good morphology.

[0007] In a first aspect, this application provides a method for preparing a through hole, comprising: A semiconductor structure is provided, the semiconductor structure including an etch stop layer; A first photoresist is coated on the surface of a semiconductor structure, and the first photoresist is baked with a first PRB to obtain a first photoresist layer. A second photoresist is coated on the surface of the first photoresist layer, and the second photoresist is baked with a second PRB to obtain a second photoresist layer. The electrostatic sensitivity of the second photoresist layer is lower than that of the first photoresist layer. The first and second photoresist layers are exposed. The first and second photoresist layers are developed to form a via fabrication region to expose the semiconductor structure at the bottom of the via fabrication region; The semiconductor structure at the bottom of the via fabrication area is etched until the etching stop layer is reached to form the via.

[0008] Optionally, the PRB sensitivity of the second photoresist is higher than that of the first photoresist.

[0009] Optionally, the second photoresist includes any one of I-line photoresist, krF photoresist, and ArF photoresist.

[0010] Optionally, the PRB baking temperature of the second photoresist is lower than that of the first photoresist.

[0011] Optionally, the ratio of the PRB baking temperature of the second photoresist to the PRB baking temperature of the first photoresist is 8:9 to 10:11.

[0012] Optionally, the PRB baking time of the second photoresist is shorter than that of the first photoresist.

[0013] Optionally, the ratio of the PRB baking time of the second photoresist to the PRB baking time of the first photoresist is 1:2 to 3:4.

[0014] Optionally, the opening width of the second photoresist layer in the via fabrication area is smaller than the opening width of the first photoresist layer in the via fabrication area.

[0015] Optionally, the thickness of the first photoresist layer is greater than the thickness of the etch stop layer.

[0016] Optionally, the thickness of the first photoresist layer is 1.2 to 1.8 times the thickness of the etch stop layer.

[0017] Optionally, the step of developing the first photoresist layer and the second photoresist layer includes: Development step: The first photoresist layer and the second photoresist layer are developed using a developing solution; Deionized water cleaning step: Clean the first and second photoresist layers after development with deionized water; Nitrogen purging step: Nitrogen gas is used to purge the first and second photoresist layers; The first and second photoresist layers are periodically cleaned with deionized water and purged with nitrogen gas before development is completed.

[0018] Optionally, the step of etching the semiconductor structure in the via fabrication region includes: The semiconductor structure at the bottom of the via fabrication area is etched, and the second photoresist layer is etched simultaneously. After the second photoresist layer is removed, the semiconductor structure at the bottom of the via fabrication area continues to be etched under the blocking effect of the first photoresist layer until the etching stop layer is reached, forming a via.

[0019] Optionally, plasma etching is used in an environment with a temperature of 20℃~90℃ and a pressure of 5Pa~10Pa, with an etching power of 100W~500W, and fluorine-based gas is used as the etching gas for etching.

[0020] Secondly, this application provides a method for fabricating a semiconductor device, the method comprising the method described in any of the preceding claims.

[0021] The unexpected technical effects of the technical solution provided in this application include at least the following: This application involves fabricating a second photoresist layer on the surface of a first photoresist layer. The second photoresist layer has lower insulation than the first photoresist layer and covers the first photoresist layer. An unexpected technical advantage is that by covering the first photoresist layer with a second photoresist layer that has lower electrostatic sensitivity, charge accumulation in the first photoresist layer can be avoided during development. Furthermore, the second photoresist layer, with its lower electrostatic sensitivity, has better charge migration capabilities than the first photoresist layer. The second photoresist layer itself does not accumulate charge and facilitates the release of accumulated charge in the first photoresist layer. This prevents the generation of an electrostatic field due to charge accumulation, thus avoiding the adhesion of development residues to the via fabrication area after development, ensuring a superior via fabrication result. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating a method for preparing a through-hole according to an embodiment of this application.

[0024] Figure 2 This is a schematic diagram of the substrate structure provided during the fabrication process of a semiconductor structure according to an embodiment of this application.

[0025] Figure 3 This is a schematic diagram of the formation of a first photoresist layer during the fabrication process of a semiconductor structure provided in an embodiment of this application.

[0026] Figure 4 This is a schematic diagram of the formation of a second photoresist layer during the fabrication process of a semiconductor structure provided in an embodiment of this application.

[0027] Figure 5 This is a schematic diagram of the semiconductor structure provided in an embodiment of this application being exposed during the fabrication process.

[0028] Figure 6 This is a schematic diagram showing the formation of an exposure area during the fabrication process of a semiconductor structure provided in an embodiment of this application.

[0029] Figure 7 This is a schematic diagram of the through-hole fabrication region formed after development during the fabrication process of a semiconductor structure provided in an embodiment of this application.

[0030] Figure 8This is a schematic diagram of the hard baking process after development of a semiconductor structure provided in an embodiment of this application.

[0031] Figure 9 This is a schematic diagram showing the etching of the semiconductor structure at the bottom of the via fabrication region during the fabrication process of a semiconductor structure provided in an embodiment of this application.

[0032] Figure 10 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application after the photoresist sacrificial layer has been removed during the fabrication process.

[0033] Figure 11 This is a schematic diagram showing the etching of a semiconductor structure to the etch barrier layer during the fabrication process, according to an embodiment of this application.

[0034] Figure 12 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application, showing the formation of a via by removing the photoresist layer during fabrication.

[0035] Figure 13 This is a schematic diagram of a developing process provided in an embodiment of this application.

[0036] Figure 14 A comparative image of a developed wafer provided in this application.

[0037] The attached figures are labeled as follows: 10: Substrate; 100: Etching barrier layer; 11: First photoresist layer; 12: Second photoresist layer; 13: Mask; 14: Exposure area; 15: Via fabrication area; 16: Photoresist layer; 17: Photoresist sacrificial layer; 18: Via. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0039] Figure 1 This is a flowchart illustrating a method for preparing a through-hole according to an embodiment of this application. See also... Figure 1 The method includes the following steps: S101. A semiconductor structure is provided, wherein the semiconductor structure includes an etch stop layer.

[0040] In one example, the semiconductor structure can be any structure used in the fabrication process of a semiconductor device that requires the fabrication of through-holes, and this application does not impose any limitations on it.

[0041] For ease of understanding, this application uses a semiconductor structure as a substrate for illustration.

[0042] See Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application, wherein the semiconductor structure includes a substrate 10 and an etch barrier layer 100 is provided inside the substrate 10.

[0043] S102. Coat the semiconductor structure surface with a first photoresist and bake the first photoresist with a first PRB to obtain a first photoresist layer.

[0044] In one example, step S102 includes: The first step is to spin-coat the first photoresist onto the surface of the semiconductor structure.

[0045] The first photoresist layer is a photoresist layer with superior insulating properties to ensure good etching resistance during the fabrication of vias. This ensures the resolution and fidelity of the photoresist pattern, thereby guaranteeing the morphology of the fabricated vias. Furthermore, more precise pattern transfer also helps improve the electrical performance and reliability of semiconductor devices.

[0046] As an example, the first photoresist layer can be EUV photoresist.

[0047] The second step is to bake the first photoresist at the first target temperature to form the first photoresist layer.

[0048] PRB (Post-Apply Bake) refers to the baking step performed after photoresist has been coated onto the wafer surface and spin-coated evenly, but before exposure. Its main purpose is to remove residual solvents, improve adhesion and stability, stabilize photoresist film thickness, improve uniformity, and enhance exposure control.

[0049] In one example, the first target temperature is 90℃~110℃.

[0050] For example, the first target temperature is 100°C.

[0051] In one example, the baking time for the first photoresist layer is 60s to 120s.

[0052] For example, the baking time for the first photoresist layer is 80 seconds.

[0053] In one example, the thickness of the first photoresist layer is greater than the thickness of the etch stop layer.

[0054] In one example, the thickness of the first photoresist layer is 1.2 to 1.8 times the thickness of the etch stop layer.

[0055] For example, the thickness of the first photoresist layer is 1.5 times the thickness of the etch stop layer.

[0056] The first photoresist layer is used to protect the non-etched areas during the via etching process, while the etching barrier layer is used to ensure that the depth of each via is reached during the via etching process, and that over-etching does not occur.

[0057] The phrase "each via is etched to the required depth" means that the depth of multiple vias obtained through etching in the semiconductor structure meets or is equal to the target depth.

[0058] Over-etching refers to situations where the depth of multiple vias obtained through etching in a semiconductor structure exceeds the target depth, or where the etched vias not only exceed the target depth but also penetrate the semiconductor structure, causing damage to the semiconductor structure or connecting semiconductor layers that should not be connected.

[0059] Because semiconductor structures require the simultaneous etching of multiple vias, it's impossible to ensure that the etching efficiency of each via is uniform. This results in some areas of vias reaching the target depth faster than others. By setting an etch stop layer, once the faster-etched vias reach the target depth, the etch stop layer prevents them from extending further, thus stopping the depth increase. Etching continues until the slower-etched vias reach their target depth, ensuring that all vias formed in the semiconductor structure reach the target depth.

[0060] See Figure 3 Specifically, the first photoresist layer 11 formed on the surface of the substrate 10 is shown.

[0061] S103. A second photoresist is coated on the surface of the first photoresist layer, and the second photoresist is subjected to a second PRB baking to obtain a second photoresist layer. The electrostatic sensitivity of the second photoresist layer is lower than that of the first photoresist layer.

[0062] In one example, step S103 includes: The first step is to coat the surface of the first photoresist layer with a second photoresist.

[0063] In one example, the PRB sensitivity of the second photoresist layer is higher than that of the first photoresist layer.

[0064] It should be noted that PRB sensitivity (Post-Apply Bake Sensitivity) refers to the degree to which the final performance of the photoresist (especially the critical dimensions of the pattern it forms) is sensitive to changes in PRB (post-apply bake / pre-bake / soft bake) process parameters (mainly temperature and time).

[0065] In simpler terms, it measures how much the critical dimensions of the final developed photoresist pattern will deviate if the PRB baking temperature is slightly too high or too low, or the baking time is slightly longer or shorter; and to what extent small fluctuations in PRB baking parameters will "amplify" or affect the final pattern accuracy.

[0066] In one example, the solvent content of the second photoresist is 1.3 to 1.8 times that of the first photoresist.

[0067] For example, the solvent content of the second photoresist is 1.5 times that of the first photoresist.

[0068] In one example, the second photoresist includes any one of I-line photoresist, krF photoresist, and ArF photoresist.

[0069] It should be noted that the types of second photoresists mentioned above are only some examples provided in this application. Any photoresist that meets the above-mentioned PRB sensitivity and subsequent electrostatic sensitivity can be used as the second photoresist in this application.

[0070] The second step involves baking the second photoresist with a second PRB at a second target temperature to obtain a second photoresist layer. The electrostatic sensitivity of the second photoresist layer is lower than that of the first photoresist layer.

[0071] It should be noted that electrostatic sensitivity is used to characterize whether a photoresist layer is prone to generating static electricity. High electrostatic sensitivity indicates that the photoresist layer is prone to generating static electricity (or that the charge migration ability in the photoresist layer is poor). Low electrostatic sensitivity indicates that the photoresist layer is difficult to generate static electricity or has a low probability of generating static electricity (or that the charge migration ability in the photoresist layer is relatively superior).

[0072] In one example, the PRB baking temperature of the second photoresist is lower than that of the first photoresist.

[0073] In one example, the ratio of the PRB baking temperature of the second photoresist to the PRB baking temperature of the first photoresist is 8 to 10:11, more preferably 8:9 to 10:11.

[0074] For example, the ratio of the PRB baking temperature of the second photoresist to the PRB baking temperature of the first photoresist is 8.5:9.5.

[0075] In one example, the second target temperature is 80℃~100℃.

[0076] In one example, the PRB baking time for the second photoresist is shorter than the baking time for the first photoresist.

[0077] In one example, the ratio of the PRB baking time of the second photoresist to the PRB baking time of the first photoresist is 1:2 to 3:4.

[0078] For example, the ratio of the PRB baking time of the second photoresist to the PRB baking time of the first photoresist is 2:3.

[0079] In one example, the PRB baking time for the second photoresist is 30s to 90s.

[0080] By using a first photoresist and a second photoresist with different properties, and by baking the first photoresist and the second photoresist differently, a first photoresist layer and a second photoresist layer are formed, so that the areas of the first photoresist layer and the second photoresist layer that are developed away after exposure and development steps are different.

[0081] In this process, the area of ​​the first photoresist layer that is developed is larger than that of the second photoresist layer, meaning that the opening width of the first photoresist layer is larger than that of the second photoresist layer. This ensures that the second photoresist layer can better cover the first photoresist layer, thus ensuring that the first photoresist layer is less likely to generate static electricity.

[0082] See Figure 4 Specifically, a second photoresist layer 12 formed on the surface of the first photoresist layer 11 is shown.

[0083] S104. Expose the first photoresist layer 11 and the second photoresist layer 12.

[0084] In this process, the first photoresist layer 11 and the second photoresist layer 12 are exposed under the blocking effect of the mask plate 13.

[0085] In one example, after exposure is completed, the first photoresist layer 11 and the second photoresist layer 12 are post-exposure baked (PEB) at a third target temperature.

[0086] In one example, the third target temperature is 90°C to 120°C.

[0087] See Figure 5 Under the cover of the photomask 13, the first photoresist layer 11 and the second photoresist layer 12 are exposed.

[0088] See Figure 6After the first photoresist layer 11 and the second photoresist layer 12 are exposed, an exposure area 14 is formed. The exposure area 14 is the area formed after the first photoresist layer 11 and the second photoresist layer 12 react with light after light passes through the mask plate 13 and irradiates the first photoresist layer 11 and the second photoresist layer 12.

[0089] In one example, the exposure area 14 includes a first photoresist layer 11 and a second photoresist layer 12 that react with light. The exposure area 14 is convex, indicating that the area of ​​the second photoresist layer 12 that reacts with light is smaller than the area of ​​the first photoresist layer 11 that reacts with light.

[0090] S105. Develop the first photoresist layer and the second photoresist layer to form a via fabrication area to expose the semiconductor structure at the bottom of the via fabrication area.

[0091] In one example, step S105 includes: Step 1, Development Step: The first and second photoresist layers are developed using a developer.

[0092] As an example, the developer is an alkaline developer that includes a 2.38% TMAH solution.

[0093] For example, the pH value of the developer can be 11.8.

[0094] In other examples, the developer may be an acidic solution, which is not limited in this application. Those skilled in the art can choose the type of developer as needed.

[0095] In one example, the area of ​​the second photoresist layer that is developed away in the via fabrication area is smaller than the area of ​​the first photoresist layer that is developed away in the via fabrication area, thereby ensuring that the second photoresist layer can better cover the first photoresist layer.

[0096] See Figure 7 Specifically, the via fabrication area 15 is shown. The first photoresist layer 11 and the second photoresist layer 12 at the exposure area 14 are removed to form the via fabrication area 15. The opening width of the second photoresist layer at the via fabrication area is smaller than the opening width of the first photoresist layer at the via fabrication area, so that the remaining first photoresist layer 11 and the second photoresist layer 12 have a T-shaped cross section.

[0097] Step 2, Deionized Water Cleaning: Clean the first and second photoresist layers after development with deionized water.

[0098] The pH value of the deionized water is 7.

[0099] The purpose of rinsing with deionized water is to remove the developing solution remaining in the first photoresist layer, the second photoresist layer, and the via preparation area, so as to avoid over-development.

[0100] Step 3, Nitrogen purging step: Nitrogen gas is used to purge the first and second photoresist layers.

[0101] Nitrogen purging refers to using nitrogen gas to purge residual developer, deionized water, and other liquids from the first photoresist layer, the second photoresist layer, and the via preparation area.

[0102] Step 4: Periodically perform deionized water cleaning and nitrogen purging steps on the first and second photoresist layers to complete the development process.

[0103] In one example, the rinsing time with deionized water is 10s to 30s per cycle.

[0104] The rinsing time with deionized water should not be too long, otherwise the pH value of the developer in the through-hole preparation area will drop too quickly, causing a pH shock effect. If the rinsing time with deionized water is too short, the rinsing efficiency of the developer in the through-hole preparation area will be low.

[0105] During the process of cleaning the developer with deionized water, especially when cleaning the developer in the via preparation area, a pH shock effect is likely to occur. This is because the developer in the via preparation area has a high pH and is difficult to remove (because the via cross-sectional size is small and the via is deep). During the process of cleaning the developer in the via preparation area with deionized water, the pH of the developer in the via preparation area will drop rapidly due to the cleaning of the deionized water. The rapid drop in pH value will cause the photoresist that reacts with the developer and is developed out will precipitate out, resulting in the formation of developer residue in the via preparation area.

[0106] This application uses multiple rapid deionized water washing and nitrogen purging steps to replace the residual developer in the through-hole preparation area. Through multiple washing and nitrogen purging, the pH value of the developer can be reduced gradually, avoiding a sudden drop in pH. This can effectively avoid the developer residue caused by pH shock effect, thereby ensuring the morphology of the through-holes prepared in the subsequent process.

[0107] In one example, after development, the first photoresist layer and the second photoresist layer are hard baked, and the first photoresist layer 11 becomes a photoresist layer 16, and the second photoresist layer 12 becomes a photoresist sacrificial layer 17.

[0108] See Figure 8 Specifically, photoresist layer 16 and photoresist sacrificial layer 17 are shown.

[0109] S106. Etch the semiconductor structure at the bottom of the via fabrication area until the etching stop layer is reached to form a via.

[0110] In one example, step S106 includes: The first step is to etch the semiconductor structure at the bottom of the via fabrication area and simultaneously etch the second photoresist layer after hard baking (the second photoresist layer after hard baking is transformed into the photoresist sacrificial layer 17).

[0111] In one example, a plasma etching process is used, with an etching power of 100W to 500W, in an environment with a temperature of 20℃ to 90℃ and a pressure of 5Pa to 10Pa, and fluorine-based gas is used as the etching gas for etching.

[0112] For example, plasma etching is used in an environment with a temperature of 40°C and a pressure of 8Pa, with an etching power of 200W and fluorine-based gas as the etching gas.

[0113] As an example, fluorine-based gases may include , Any one of them.

[0114] It should be noted that the above-mentioned fluorine-based gas is only an example provided in this application and is not intended to limit this application. Those skilled in the art should understand that any gas that can etch the semiconductor structure and the second photoresist layer can be used as the etching gas in this application. The function of the etching gas in this application is to etch the photoresist sacrificial layer and the semiconductor structure.

[0115] See Figure 9 The etching direction of plasma etching is specifically shown.

[0116] The second step involves removing the second photoresist layer after hard baking, and continuing to etch the semiconductor structure at the bottom of the via fabrication area under the blocking effect of the first photoresist layer after hard baking, until the etching stop layer is reached to form a via.

[0117] See Figure 10 After the photoresist sacrificial layer 17 is removed, a "T"-shaped structure is formed at the bottom of the via fabrication area 15 (that is, the part of the semiconductor structure that is etched is "T"-shaped).

[0118] See Figure 11 Continue etching the semiconductor structure at the bottom of the via fabrication area 15. When etching reaches the surface of the etching barrier layer 100, the semiconductor structure at the bottom of the via fabrication area 15 is completely etched under the blocking effect of the etching barrier layer 100, and a plane is formed at the bottom of the via fabrication area, thereby obtaining a via 18 extending to the surface of the etching barrier layer.

[0119] It should be noted that, for ease of understanding, this application describes a substrate including an etch barrier layer as a semiconductor structure. However, in the actual via fabrication process, vias are usually used to fabricate vias that connect multilayer structures, and multilayer structures are not equivalent to the substrate and etch barrier layer in this application.

[0120] The third step is to remove the photoresist layer after the via is formed.

[0121] As an example, the photoresist layer 16 can be removed using an ashing process.

[0122] See Figure 12 The diagram shows the structure formed after the photoresist layer 16 is removed.

[0123] See Figure 13 For ease of understanding, the development process of this application is further explained.

[0124] The first step is to prepare the photoresist layer.

[0125] In the first step, the first photoresist layer and the second photoresist layer of this application are formed.

[0126] The second step is to expose the photoresist layer to facilitate the formation of patterns after subsequent development.

[0127] The third step is to develop the exposed photoresist layer with a developing solution to form a pattern.

[0128] As an example, the developer used was 2.38% TMAH (alkaline, pH 11.8).

[0129] It should be noted that the semiconductor structure is in a rotating state during the development process, thereby ensuring development efficiency.

[0130] The fourth step is to wash away any remaining developer with deionized water.

[0131] It should be noted that when cleaning with deionized water, the semiconductor structure is in a rotating state to ensure cleaning efficiency.

[0132] Step 5: Nitrogen purging to remove deionized water and developer.

[0133] Nitrogen gas is used to purge the residual liquid, and the developing process is then complete.

[0134] In the fifth step, the semiconductor structure is also in a rotating state, and the developing residue is quickly removed by nitrogen purging and substrate rotation.

[0135] Step six: Repeat steps four and five periodically to remove any remaining developer, then end the development process.

[0136] See Figure 14 The wafer prepared by the via preparation method of this application and the via preparation method in related technologies has a much lower surface development residue than the wafer prepared by related technologies. This is because the present application uses a first photoresist layer and a second photoresist layer with different electrostatic sensitivities, and uses periodic deionized water cleaning and nitrogen purging steps to prepare the via.

[0137] This application also provides a method for fabricating a semiconductor device, the method comprising: Figure 1 The method for preparing the through hole.

[0138] Finally, it is worth noting that the unexpected technical effects of the technical method provided in this application include: First, this application involves fabricating a second photoresist layer on the surface of a first photoresist layer. The second photoresist layer has lower insulation than the first photoresist layer and covers the first photoresist layer. An unexpected technical advantage is that by covering the first photoresist layer with a second photoresist layer that has lower electrostatic sensitivity, charge accumulation in the first photoresist layer can be avoided during development. Furthermore, the second photoresist layer, with its lower electrostatic sensitivity, has better charge migration capabilities than the first photoresist layer. The second photoresist layer itself does not accumulate charge and facilitates the release of accumulated charge in the first photoresist layer. This avoids the generation of an electrostatic field due to charge accumulation, thus preventing development residues from adhering to the via fabrication area after development due to electrostatic effects, ensuring a superior via fabrication result.

[0139] Secondly, this application uses periodic deionized water and nitrogen purging steps to clean the residual developer in the through-hole preparation area, which can avoid the pH shock effect and prevent the photoresist in the developer from precipitating out when using deionized water to clean the developer, thus avoiding the developer residue caused by the pH shock effect.

[0140] By combining the two methods described above to prepare the through-holes, the development residue can be avoided, thus ensuring the morphology of the through-holes.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a through hole, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including an etch stop layer; A first photoresist is coated on the surface of a semiconductor structure, and the first photoresist is baked with a first PRB to obtain a first photoresist layer. A second photoresist is coated on the surface of the first photoresist layer, and the second photoresist is baked with a second PRB to obtain a second photoresist layer. The electrostatic sensitivity of the second photoresist layer is lower than that of the first photoresist layer. The first and second photoresist layers are exposed. The first and second photoresist layers are developed to form a via fabrication region to expose the semiconductor structure at the bottom of the via fabrication region; The semiconductor structure at the bottom of the via fabrication area is etched until the etching stop layer is reached, thus forming the via.

2. The method for preparing a through hole according to claim 1, characterized in that, The PRB sensitivity of the second photoresist is higher than that of the first photoresist.

3. The method for preparing a through hole according to claim 1, characterized in that, The PRB baking temperature of the second photoresist is lower than that of the first photoresist.

4. The method for preparing a through hole according to claim 1, characterized in that, The PRB baking time for the second photoresist is shorter than that for the first photoresist.

5. The method for preparing a through hole according to any one of claims 1 to 4, characterized in that, The opening width of the second photoresist layer in the via fabrication area is smaller than the opening width of the first photoresist layer in the via fabrication area.

6. The method for preparing a through hole according to any one of claims 1 to 4, characterized in that, The thickness of the first photoresist layer is greater than the thickness of the etching stop layer.

7. The method for preparing a through hole according to any one of claims 1 to 4, characterized in that, The steps for developing the first and second photoresist layers include: Development step: The first photoresist layer and the second photoresist layer are developed using a developing solution; Deionized water cleaning step: Clean the first and second photoresist layers after development with deionized water; Nitrogen purging step: Nitrogen gas is used to purge the first and second photoresist layers; The first and second photoresist layers are periodically cleaned with deionized water and purged with nitrogen gas before development is completed.

8. The method for preparing a through hole according to any one of claims 1 to 4, characterized in that, The steps for etching the semiconductor structure at the bottom of the via fabrication region include: The semiconductor structure at the bottom of the via fabrication area is etched, and the second photoresist layer is etched simultaneously. After the second photoresist layer is removed, the semiconductor structure at the bottom of the via fabrication area continues to be etched under the blocking effect of the first photoresist layer until the etching stop layer is reached, forming a via.

9. The method for preparing a through hole according to claim 8, characterized in that, Plasma etching is employed in an environment with a temperature of 20℃~90℃ and a pressure of 5Pa~10Pa, using an etching power of 100W~500W and fluorine-based gas as the etching gas.

10. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes the method for fabricating a through-hole as described in any one of claims 1 to 9.

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