Duty cycle and quadrature four-phase clock detection and correction circuit

Abstract

The present application relates to a kind of duty cycle and quadrature four-phase clock detection and correction circuit, belong to integrated circuit design field.The circuit includes duty cycle and quadrature phase correction link unit and duty cycle and quadrature four-phase detection unit;Duty cycle and quadrature four-phase correction link unit includes duty cycle correction unit, quadrature four-phase correction unit and buffer;Duty cycle and quadrature four-phase detection unit includes duty cycle and quadrature four-phase sampling detection module and digital processing module.High-speed clock is in turn through duty cycle correction unit, buffer, quadrature four-phase correction unit, quadrature four-phase sampling detection module and digital processing module, and digital processing module output signal controls duty cycle correction unit and quadrature four-phase correction unit.The circuit of the present application can carry out duty cycle and quadrature four-phase detection and correction to high-speed or super high-speed clock signal, and can be applied in AD / DA, high-speed SerDes transceiver and other systems.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and relates to a duty cycle and quadrature four-phase clock detection and correction circuit. Background Technology

[0002] In modern SoCs and monolithic integrated circuit systems, clock signal integrity is crucial. Duty cycle and four-phase clock detection and correction techniques are widely used in critical modules such as AD / DA converters, phase-locked loops (PLLs), and high-speed serial-to-deserializers (SerDes). The performance of these systems is highly dependent on the quality of the clock signal; an undesirable duty cycle or phase deviation can lead to serious problems such as data sampling errors and timing disorders, thereby affecting the overall system reliability and transmission rate.

[0003] Traditional solutions primarily employ RC charging and discharging for clock detection, determining clock parameters by measuring the charging and discharging time constant. However, this analog method has significant limitations: firstly, the RC time constant is significantly affected by variations in process angle, voltage, and temperature (PVT), making it difficult to guarantee detection accuracy; secondly, the charging and discharging process requires a relatively long time, limiting its applicability to low-frequency clocks (typically below 100MHz). In modern high-speed interfaces such as SerDes, clock frequencies reach several GHz or even tens of GHz, rendering the RC method completely inadequate for high-speed signal processing requirements.

[0004] For high-speed applications, the industry has explored various alternative solutions. These include architectures combining multiplexers with low-pass filters, or digital detection techniques based on tapped line average voltage measurements. However, these methods still suffer from high circuit complexity, large area overhead, or insufficient correction accuracy. Particularly in four-phase clock correction, existing technologies struggle to simultaneously guarantee high-speed processing capabilities and phase alignment accuracy. With the development of 3D chips and heterogeneous integration technologies, higher demands are placed on clock synchronization, necessitating the development of novel high-speed detection and correction circuits to overcome existing technological bottlenecks. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a duty cycle and quadrature four-phase clock detection and correction circuit, which can be applied to AD / DA and high-speed SerDes interface circuits. Through this circuit, the duty cycle and quadrature four-phase detection and correction of high-speed or ultra-high-speed clock signals can be realized.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A duty cycle and quadrature four-phase clock detection and correction circuit includes a duty cycle and quadrature four-phase correction link unit 100 and a duty cycle and quadrature four-phase detection unit 200; the duty cycle and quadrature four-phase correction link unit 100 includes a DCC unit 101, a QEC unit 102 and a buffer, wherein the DCC unit represents the duty cycle correction unit and the QEC unit represents the quadrature four-phase correction unit; the duty cycle and quadrature four-phase detection unit 200 includes a duty cycle and quadrature four-phase sampling and detection module 201 and a digital processing module 202.

[0008] A high-speed clock is input to DCC unit 101, and the output signal of DCC unit 101 is input to QEC unit 102 after passing through a buffer. The output signal of QEC unit 102 is input to duty cycle and quadrature four-phase sampling detection module 201. The output signal of duty cycle and quadrature four-phase sampling detection module 201 is input to digital processing module 202 for analysis and processing, and the output signal controls DCC unit 101 and QEC unit 102.

[0009] Preferably, the duty cycle and quadrature four-phase sampling and detection module 201 includes five D flip-flops and a clock generation unit (OSC, i.e., oscillator);

[0010] The D port of the first D flip-flop is connected to the high-speed clock CKIP / IN signal; the D port of the second D flip-flop is connected to the high-speed clock CKQP / QN signal; the D port of the third D flip-flop is connected to the high-speed clock CKIP signal; the D port of the fourth D flip-flop is connected to the high-speed clock CKQP signal; the D port of the fifth D flip-flop is connected to the high-speed clock CKIN signal; the low-frequency signal generated by the clock generation unit is connected to the clock input of all D flip-flops; the Q output of all D flip-flops is connected to the digital processing module 202.

[0011] Preferably, the digital processing module 202 includes four counters, two subtractors, two AND gates, and a digital state control (FSM) module;

[0012] The Q outputs of the first and second D flip-flops are both connected to the first and second counters, respectively. The outputs of the first and second counters are both connected to the input of the first subtractor. The Q output of the third D flip-flop is connected to the first input of the first AND gate. The Q output of the fourth D flip-flop is connected to the second input of the first AND gate and the first input of the second AND gate, respectively. The Q output of the fifth D flip-flop is connected to the second input of the second AND gate. The output of the first AND gate is connected to the input of the third counter, and the output of the second NAND gate is connected to the input of the fourth counter. The outputs of the third and fourth counters are both connected to the input of the second subtractor. The outputs of the first and second subtractors are both connected to the digital state control (FSM) module.

[0013] Preferably, the DCC unit 101 includes an I signal path duty cycle correction unit and a Q signal path duty cycle correction unit; the I signal path duty cycle correction unit includes an IP signal duty cycle correction structure and an IN signal duty cycle correction structure; the Q signal path duty cycle correction unit includes a QP signal duty cycle correction structure and a QN signal duty cycle correction structure; the IN signal duty cycle correction structure, the QN signal duty cycle correction structure, and the QP signal duty cycle correction structure are all consistent with the IP signal duty cycle correction structure;

[0014] The IP signal duty cycle correction structure includes three inverters and four controllable power supplies. The IP signal is output after passing through the three inverters. Two controllable current sources are connected in parallel between every two inverters. One end of the controllable current source is connected to the power supply voltage, and the other end is connected to the ground.

[0015] Preferably, the QEC unit 102 includes an I signal path phase correction unit and a Q signal path phase correction unit; the I signal path phase correction unit includes an IN signal phase correction structure and an IP signal phase correction structure; the Q signal path phase correction unit includes a QN signal phase correction structure and a QP signal phase correction structure; the IN signal phase correction structure, the QN signal phase correction structure, and the QP signal phase correction structure are all consistent with the IP signal phase correction structure.

[0016] Preferably, the buffer includes an I-signal path buffer and a Q-signal path buffer; the I-signal path buffer includes two buffers and two inverters, one buffer's input is connected to the IP signal output of the I-signal path duty cycle correction unit, and one inverter's input is connected to the other inverter's output; the other buffer's input is connected to the IN signal output of the I-signal path duty cycle correction unit, one inverter's output, and the other inverter's input; the Q-signal path buffer has the same structure as the I-signal path buffer.

[0017] Preferably, two inverters with opposite directions are connected in parallel between the two output terminals of the QEC unit 102.

[0018] Preferably, when the duty cycle and quadrature four-phase detection unit 200 detects that the duty cycle of the transmitted signal is not 50% or the phase difference between signals I and Q is not 180°, the digital processing module 202 outputs a signal to control the DCC unit 101 to adjust the duty cycle of the transmitted signal to 50%; after the duty cycle is adjusted to 50%, the digital processing module 202 outputs a signal to control the QEC unit 102 to start phase correction until the four-phase signals are orthogonal, that is, the phase difference between signals I and Q is 180°.

[0019] The beneficial effects of this invention are as follows:

[0020] (1) High-performance correction capability: The circuit of this invention can perform precise duty cycle correction (adjusted to 50%) and quadrature four-phase correction (achieving 180° phase difference) on high-speed or ultra-high-speed clock signals (from several GHz to tens of GHz), meeting the stringent requirements of AD / DA, high-speed SerDes transceivers and other systems for clock signals.

[0021] (2) Innovative detection method: Using statistical principles, the high-speed signal is converted to a low-speed conversion by sampling the fast clock with a slow clock. Combined with digital counter comparison and state machine control, the detection accuracy and efficiency are significantly improved.

[0022] (3) Modular design: The circuit of this invention is divided into a detection unit (including a sampling detection module and a digital processing module) and a correction unit (DCC and QEC units). The structure is clear and easy to expand. It supports the integration of mixed digital and analog signals and has the characteristics of easy large-scale integration and low power consumption.

[0023] (4) Adaptive adjustment mechanism: The circuit of this invention dynamically adjusts the current source of the DCC unit and the capacitor load of the QEC unit through the digital state control (FSM) module to achieve closed-loop control and ensure the stability and reliability of the correction process.

[0024] (5) Wide applicability: The circuit of this invention can be applied to various integrated circuit scenarios such as SOC and ASIC, improving the integrity of the system clock signal and its anti-interference capability.

[0025] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0027] Figure 1 The principle block diagram of the duty cycle and four-phase clock detection and correction circuit provided by the present invention;

[0028] Figure 2 This is a circuit diagram of a duty cycle correction (DCC) unit provided in an embodiment of the present invention;

[0029] Figure 3 The circuit diagram of the orthogonal four-phase correction (QEC) unit provided in the embodiment of the present invention;

[0030] Figure 4 The circuit diagram of the orthogonal four-phase detection unit provided in the embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram illustrating the duty cycle detection and comparison principle provided in an embodiment of the present invention.

[0032] Figure 6 This is a schematic diagram of the orthogonal four-phase detection and comparison principle provided in an embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of the duty cycle correction principle of the circuit of the present invention;

[0034] Reference numerals: 100-Duty cycle and quadrature phase correction link unit, 101-DCC unit (duty cycle correction unit), 102-QEC unit (quadrature four-phase correction unit), 200-Duty cycle and quadrature four-phase detection unit, 201-Duty cycle and quadrature four-phase sampling and detection module, 202-Digital processing module. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0036] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0037] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0038] This invention provides a duty cycle and quadrature four-phase clock detection and correction circuit, such as... Figure 1 As shown, the circuit includes a duty cycle and quadrature phase correction link unit 100 and a duty cycle and quadrature four-phase detection unit 200. The duty cycle and quadrature phase correction link unit 100 includes a duty cycle correction (DCC) unit 101, a quadrature four-phase correction (QEC) unit 102, and a buffer. The duty cycle and quadrature four-phase detection unit 200 includes a duty cycle and quadrature four-phase sampling and detection module 201 and a digital processing module 202. A high-speed clock is input to the DCC unit 101, and the output signal of the DCC unit 101 is input to the QEC unit 102 via the buffer; the output signal of the QEC unit 102 is input to the duty cycle and quadrature four-phase sampling and detection module 201; the output signal of the duty cycle and quadrature four-phase sampling and detection module 201 is input to the digital processing module 202 for analysis and processing, and the output signal controls the DCC unit 101 and the QEC unit 102.

[0039] Example 1:

[0040] DCC unit 101 includes an I signal path duty cycle correction unit and a Q signal path duty cycle correction unit. The I signal path duty cycle correction unit includes an IP signal duty cycle correction structure and an IN signal duty cycle correction structure. The Q signal path duty cycle correction unit includes a QP signal duty cycle correction structure and a QN signal duty cycle correction structure. The IN signal duty cycle correction structure, QN signal duty cycle correction structure, and QP signal duty cycle correction structure are all consistent with the IP signal duty cycle correction structure. The IP signal duty cycle correction structure includes three inverters and four controllable power supplies. The IP signal is output after passing through the three inverters. Two controllable current sources are connected in parallel at the circuit node between every two inverters. One end of one controllable current source is connected to the power supply voltage, and the other controllable current source is connected to ground.

[0041] Example 2:

[0042] QEC unit 102 includes an I signal path phase correction unit and a Q signal path phase correction unit; the I signal path phase correction unit includes an IN signal phase correction structure and an IP signal phase correction structure; the Q signal path phase correction unit includes a QN signal phase correction structure and a QP signal phase correction structure; the IN signal phase correction structure, QN signal phase correction structure and QP signal phase correction structure are all consistent with the IP signal phase correction structure.

[0043] The buffer includes an I-signal path buffer and a Q-signal path buffer. The I-signal path buffer includes two buffers and two inverters. The input of one buffer is connected to the IP signal output of the I-signal path duty cycle correction unit, and the input of one inverter is connected to the output of the other inverter. The input of the other buffer is connected to the IN signal output of the I-signal path duty cycle correction unit, the output of one inverter, and the input of the other inverter. The Q-signal path buffer has the same structure as the I-signal path buffer.

[0044] Example 3:

[0045] like Figure 4 As shown, the duty cycle and quadrature four-phase sampling detection module 201 includes five D flip-flops and a clock generation unit (OSC, i.e., oscillator); the D port of the first D flip-flop is connected to the high-speed clock CKIP / IN signal; the D port of the second D flip-flop is connected to the high-speed clock CKQP / QN signal; the D port of the third D flip-flop is connected to the high-speed clock CKIP signal; the D port of the fourth D flip-flop is connected to the high-speed clock CKQP signal; the D port of the fifth D flip-flop is connected to the high-speed clock CKIN signal; the low-frequency signal generated by the clock generation unit is connected to the clock input of all D flip-flops; the Q output of all D flip-flops is connected to the digital processing module 202.

[0046] The digital processing module 202 includes four counters, two subtractors, two AND gates, and a digital state control (FSM) module. The Q outputs of the first and second D flip-flops are both connected to the first and second counters, respectively; the outputs of the first and second counters are both connected to the input of the first subtractor. The Q output of the third D flip-flop is connected to the first input of the first AND gate; the Q output of the fourth D flip-flop is connected to the second input of both the first and second AND gates; the Q output of the fifth D flip-flop is connected to the second input of the second AND gate. The output of the first AND gate is connected to the input of the third counter; the output of the second NAND gate is connected to the input of the fourth counter; the outputs of the third and fourth counters are both connected to the input of the second subtractor; and the outputs of the first and second subtractors are both connected to the digital state control (FSM) module.

[0047] Clock signal duty cycle and quadrature four-phase detection process:

[0048] First, perform duty cycle detection, such as... Figure 4 As shown, when the high-speed clock signal CKIP / IN or CKQP / QN has duty cycle distortion, it is sampled through a D flip-flop, such as... Figure 5As shown, it should be noted that at this time, the sampling D flip-flop does not work under the condition that a fast clock samples a slow clock (because the frequency of the high-speed clock signal CKIP / IN or CKQP / QN here is as high as several GHz to tens of GHz). Based on the statistical principle, this invention adopts a slow clock to sample a fast clock, and the relationship between the two clocks is T slow = N·T fast + Δt, 0 < Δt < T fast , wherein T slow represents a sampling clock period, T fast represents a detection clock signal, Δt represents an uncorrelated part of the two clocks. The smaller Δt is, the higher achievable accuracy is, but greater resource overhead of digital counters will also exist, so a trade-off needs to be considered here. When the above clock period relationship is satisfied, the high-speed clock signal CKIP / IN or CKQP / QN can be sampled and converted into a low-speed clock signal S_CKIP / IN or S_CKQP / QN with the same duty cycle characteristic. Then the counter counter_H[n:0] and the counter counter_L[n:0] in the digital processing module 202 count the high level and low level after sampling respectively, and then compare the counting results. If counter_H[n:0] > counter_L[n:0], it indicates that the duty cycle of CKIP / IN or CKQP / QN is greater than 50%, otherwise, the duty cycle is less than 50%. Then the comparison result is sent to the finite state machine control FSM to generate a control signal of the duty cycle adjustment unit to realize duty cycle adjustment. After the duty cycle is adjusted to 50%, quadrature four-phase detection is performed (note: when duty cycle detection is performed, quadrature four-phase detection does not work). The high-speed clock signals CKIP, CKQP and CKIN are sampled, and the sampling principle is the same as that of duty cycle detection. At this time, the high-speed clock signals CKIP, CKQP and CKIN are converted into low-speed signals SQ_CKIP, SQ_CKQP and SQ_CKIN with the same phase relationship. AND operation is performed on SQ_CKIP and SQ_CKQP to obtain Q1, AND operation is performed on SQ_CKQP and SQ_CKIN to obtain Q2, then, as Figure 4 shown, counters count1_H[n:0] and count2_H[n:0] count Q1 and Q2 respectively. The count values of count1_H[n:0] and count2_H[n:0] are compared. If count1_H[n:0] > count2_H[n:0], the differential clock signals CKQP / CKQN need to be delayed simultaneously so as to achieve four-phase quadrature. If count1_H[n:0] < count2_H[n:0], the differential clock signals CKIP / CKIN need to be delayed simultaneously so as to achieve four-phase quadrature.

[0049] Duty cycle and quadrature four-phase correction process of clock signal:

[0050] After the duty cycle is compared by the duty cycle and quadrature four-phase detection unit 200, the finite state machine (FSM) digital state control module outputs a signal to control the DCC unit 101. One implementation of the DCC unit 101 is as Figure 2 shown, and its working principle is as follows: when the duty cycle detected by the duty cycle and quadrature four-phase sampling detection module 201 is greater than 50%, the DCCP[m:0] control code output by the digital processing module 202 controls and adjusts Figure 2 the current source in (consisting of MP0 to MP i to form the current source) to increase the current, thereby reducing the duty cycle. The process is as Figure 7 shown; on the contrary, when the duty cycle detected by the duty cycle and quadrature four-phase sampling detection module 201 is less than 50%, the DCCN[m:0] control code output by the digital processing module 202 controls and adjusts Figure 2 the current source in (consisting of MN0 to MN i to form the current source) to increase the current, thereby increasing the clock duty cycle. The above process is repeated until the duty cycle is adjusted to 50%, and the process ends. After the duty cycle is adjusted to 50%, the quadrature four-phase correction unit 102 starts to operate, and then the finite state machine (FSM) digital state control module outputs a control signal to the QEC unit 102. One implementation of the QEC unit 102 is as Figure 3 shown, and its working principle is as follows: when it is detected that count1_H[n:0]>count2_H[n:0], that is, when Q1>Q2 as shown in Figure 6 , the differential clock signals CKQP / CKQN need to be delayed at the same time. That is, the delay is adjusted by controlling the size of the capacitor connected to the transmission link through the QEC[m:0] control code. On the contrary, when Q1<Q2, the differential clock signals CKIP / CKIN need to be delayed at the same time. The above process is repeated until the four phases CKIP / CKQP / CKIN / CKQN achieve quadrature.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all such modifications and equivalent substitutions shall be covered by the scope of the claims of the present invention.

Claims

1. A duty cycle and quadrature four-phase clock detection and correction circuit, characterized in that, The circuit includes a duty cycle and quadrature phase correction link unit (100) and a duty cycle and quadrature four-phase detection unit (200); the duty cycle and quadrature four-phase correction link unit (100) includes a DCC unit (101), a QEC unit (102) and a buffer, wherein the DCC unit represents the duty cycle correction unit and the QEC unit represents the quadrature four-phase correction unit; the duty cycle and quadrature four-phase detection unit (200) includes a duty cycle and quadrature four-phase sampling and detection module (201) and a digital processing module (202). A high-speed clock is input to the DCC unit (101), and the output signal of the DCC unit (101) is input to the QEC unit (102) through a buffer. The output signal of the QEC unit (102) is input to the duty cycle and quadrature four-phase sampling detection module (201). The output signal of the duty cycle and quadrature four-phase sampling detection module (201) is input to the digital processing module (202) for analysis and processing, and the output signal controls the DCC unit (101) and the QEC unit (102). The duty cycle and quadrature four-phase sampling detection module (201) includes five D flip-flops and a clock generation unit; the D port of the first D flip-flop is connected to the high-speed clock CKIP / IN signal; the D port of the second D flip-flop is connected to the high-speed clock CKQP / QN signal; the D port of the third D flip-flop is connected to the high-speed clock CKIP signal; the D port of the fourth D flip-flop is connected to the high-speed clock CKQP signal; the D port of the fifth D flip-flop is connected to the high-speed clock CKIN signal; the low-frequency signal generated by the clock generation unit is connected to the clock input of all D flip-flops; the Q output of all D flip-flops is connected to the digital processing module (202). The digital processing module (202) includes four counters, two subtractors, two AND gates, and a digital state control module. The Q outputs of the first and second D flip-flops are both connected to the first and second counters, and the outputs of the first and second counters are both connected to the input of the first subtractor. The Q output of the third D flip-flop is connected to the first input of the first AND gate, the Q output of the fourth D flip-flop is connected to the second input of the first AND gate and the first input of the second AND gate, respectively, and the Q output of the fifth D flip-flop is connected to the second input of the second AND gate. The output of the first AND gate is connected to the input of the third counter, and the output of the second AND gate is connected to the input of the fourth counter. The outputs of the third and fourth counters are both connected to the input of the second subtractor. The outputs of the first and second subtractors are both connected to the digital state control module.

2. The duty cycle and quadrature four-phase clock detection and correction circuit according to claim 1, characterized in that, The DCC unit (101) includes an I signal path duty cycle correction unit and a Q signal path duty cycle correction unit; the I signal path duty cycle correction unit includes an IP signal duty cycle correction structure and an IN signal duty cycle correction structure; the Q signal path duty cycle correction unit includes a QP signal duty cycle correction structure and a QN signal duty cycle correction structure; the IN signal duty cycle correction structure, the QN signal duty cycle correction structure, and the QP signal duty cycle correction structure are all consistent with the IP signal duty cycle correction structure; The IP signal duty cycle correction structure includes three inverters and four controllable power supplies. The IP signal is output after passing through the three inverters. Two controllable current sources are connected in parallel between every two inverters. One end of the controllable current source is connected to the power supply voltage, and the other end is connected to the ground.

3. The duty cycle and quadrature four-phase clock detection and correction circuit according to claim 1, characterized in that, The QEC unit (102) includes an I signal path phase correction unit and a Q signal path phase correction unit; the I signal path phase correction unit includes an IN signal phase correction structure and an IP signal phase correction structure; the Q signal path phase correction unit includes a QN signal phase correction structure and a QP signal phase correction structure; the IN signal phase correction structure, the QN signal phase correction structure, and the QP signal phase correction structure are all consistent with the IP signal phase correction structure.

4. The duty cycle and quadrature four-phase clock detection and correction circuit according to claim 1, characterized in that, The buffer includes an I-signal path buffer and a Q-signal path buffer. The I-signal path buffer includes two buffers and two inverters. The input of one buffer is connected to the IP signal output of the I-signal path duty cycle correction unit, and the input of one inverter is connected to the output of the other inverter. The input of the other buffer is connected to the IN signal output of the I-signal path duty cycle correction unit, the output of one inverter, and the input of the other inverter. The Q-signal path buffer has the same structure as the I-signal path buffer.

5. The duty cycle and quadrature four-phase clock detection and correction circuit according to claim 1 or 3, characterized in that, Two inverters with opposite directions are connected in parallel between the two output terminals of the QEC unit (102).

6. The duty cycle and quadrature four-phase clock detection and correction circuit according to claim 1, characterized in that, When the duty cycle and quadrature four-phase detection unit (200) detect that the duty cycle of the transmitted signal is not 50% or the phase difference between signal I and Q is not 180°, the digital processing module (202) outputs a signal to control the DCC unit (101) to adjust the duty cycle of the transmitted signal to 50%; when the duty cycle is adjusted to 50%, the digital processing module (202) outputs a signal to control the QEC unit (102) to start phase correction until the four-phase signals are quadrature, that is, the phase difference between signal I and Q is 180°.

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