Spaceborne coherent optical laser communication high-speed signal processing unit based on industrial-grade devices

Abstract

This invention relates to a high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices. All of its devices are industrial-grade, and the hardware has been reinforced by a specific spaceborne irradiation hardening scheme to withstand harsh conditions such as vacuum thermal alternation and irradiation. This results in a high communication rate, high signal-to-noise ratio, and strong anti-interference capability with smaller size, lighter weight, and lower power consumption, making it an excellent choice for commercial aerospace.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit ruggedized design technology, and relates to a high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices. Background Technology

[0002] In recent years, space laser links have been widely used in high-speed transmission of massive amounts of data. Because the carrier frequency of lasers is more than three orders of magnitude higher than that of microwaves, laser links can achieve higher communication rates. Laser terminals also have the advantages of smaller size, weight, and lower power consumption. Inter-satellite laser links, with their advantages of high communication rates, high signal-to-noise ratios, and strong anti-interference capabilities, are one of the development directions for inter-satellite links. Future Earth observation satellites, communication satellites, relay satellites, space-based integrated information networks, deep space exploration, manned spacecraft, and space stations all present an urgent need to accelerate the development of space data transmission technology. However, to ensure the reliable operation of laser communication units in inter-satellite laser links, they need to be radiation-hardened. Traditional satellite communication systems use high-grade aerospace-grade components to improve on-orbit reliability, but this hardening method is costly and has a long development cycle. Therefore, it is necessary to research and develop high-speed signal processing units for spaceborne coherent optical laser communication using industrial-grade components to meet the application requirements of inter-satellite laser links. Summary of the Invention

[0003] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices. This unit can be implemented using industrial-grade devices to meet the application requirements of inter-satellite laser links.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: A high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices is provided, including a signal processing FPGA, a monitoring FPGA, a high-speed ADC, a clock PLL, an optical driver DAC, an optical module, and a power module. The signal processing FPGA is connected to the monitoring FPGA, the high-speed ADC, the clock PLL, the optical driver DAC, and the optical module. The clock PLL is connected to the high-speed ADC. The input terminal of the high-speed ADC is used to connect to an analog signal conditioning circuit. The output terminal of the optical driver DAC is used to connect to an optical driver through a connector. The signal processing FPGA is used to receive and decode analog signals transmitted from the laser demodulation module, complete hardware acceleration in baseband protocol processing, and perform encryption / decryption or interface conversion. The monitoring FPGA is used to complete system reconstruction according to the firmware, execute the transmission and reception of various satellite commands, collect and report the single-board status information of the modules, and control the system power-on timing. It is also used to load the program of the signal processing FPGA and refresh it periodically through SelectMap. The firmware of the signal processing FPGA is stored on the NAND FLASH external to the monitoring FPGA. The high-speed ADC is used to convert the digital signal transmitted from the laser demodulation module into an analog signal and output it to the signal processing FPGA. The optical module is used to complete the photoelectric signal conversion and output the processed signal at high speed. The clock PLL is used to provide the system clock and the service clock required by the data path. The optical driver DAC is used to convert the analog signal received and decoded by the signal processing FPGA into a digital control signal and output it to the corresponding optical driver through the connector. The power supply module is used to provide independent sequential power-on for the monitoring FPGA, signal processing FPGA, clock PLL and high-speed ADC.

[0005] In one embodiment, the signal processing FPGA is an SRAM-type FPGA, and the program files of the SRAM-type FPGA are stored in at least three different hardware locations in the NAND FLASH.

[0006] In one embodiment, serial triple-mode redundancy is configured at at least three different hardware locations of the NAND FLASH where the program file of the SRAM-type FPGA is stored.

[0007] In one embodiment, the monitoring FPGA is a FLASH type FPGA.

[0008] In one embodiment, the system clock is provided by adding a board-level crystal to a clock PLL.

[0009] In one embodiment, the aforementioned high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices also includes reserved NOR FLASH.

[0010] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned high-speed signal processing unit for spaceborne coherent optical laser communication, based on industrial-grade components, uses only industrial-grade devices. It employs a specific spaceborne irradiation hardening scheme to enhance the hardware design for harsh conditions such as vacuum thermal alternation and irradiation. This results in a smaller size, lighter weight, and lower power consumption while achieving high communication speed, high signal-to-noise ratio, and strong anti-interference capability, making it an excellent choice for commercial aerospace. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of a high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices in one embodiment; Figure 2 This is a schematic diagram of the power-on planning for a high-speed signal processing unit for onboard coherent optical laser communication in one embodiment; Figure 3 This is a clock link block diagram of a high-speed signal processing unit for spaceborne coherent optical laser communication in one embodiment. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0014] It should be noted that, in this document, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various locations throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments.

[0015] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0016] In one embodiment, such as Figure 1As shown, a high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices is provided, including a signal processing FPGA, a monitoring FPGA, a high-speed ADC, a clock PLL, an optical driver DAC, an optical module, and a power supply module. The signal processing FPGA is connected to the monitoring FPGA, the high-speed ADC, the clock PLL (Phase-Locked Loop), the optical driver DAC, and the optical module. The clock PLL is connected to the high-speed ADC, and the input of the high-speed ADC is used to connect to an analog signal conditioning circuit. The output of the optical driver DAC is used to connect to an optical driver via a connector.

[0017] The signal processing FPGA receives and decodes analog signals transmitted from the laser demodulation module, performs hardware acceleration in baseband protocol processing, and executes encryption / decryption or interface conversion. The monitoring FPGA performs system reconstruction based on firmware, executes onboard command transmission and reception, collects and reports single-board status information from modules, and controls system power-on timing. It also loads and periodically refreshes the signal processing FPGA's program via SelectMap. The signal processing FPGA's firmware is stored on the NAND flash memory external to the monitoring FPGA. The high-speed ADC converts the digital signals transmitted from the laser demodulation module into analog signals and outputs them to the signal processing FPGA. The optical module performs photoelectric signal conversion and outputs the processed signals at high speed. The clock PLL provides the system clock and the service clock required for the data path. The optical driver DAC converts the analog signals received and decoded by the signal processing FPGA into digital control signals and outputs them to the corresponding optical drivers via connectors. The power supply module provides independent sequential power-on for the monitoring FPGA, signal processing FPGA, clock PLL, and high-speed ADC.

[0018] It is understandable that the signal processing FPGA is used to receive and decode analog signals transmitted from the external laser demodulation module, complete hardware acceleration in baseband protocol processing, and implement dedicated functions such as encryption / decryption or interface conversion. The signal processing FPGA can be any existing type of FPGA. In terms of hardware, the signal processing FPGA's program file (bit file) is stored on the external NAND flash memory of the monitoring FPGA, and can be loaded and refreshed periodically via SelectMap to improve the reliability of the signal processing FPGA.

[0019] NAND flash memory is a type of non-volatile flash memory (data is not lost after power is off). It is one of the two main types of flash memory (the other being NOR flash). It is named for its circuit structure, which is similar to NAND logic gates. It features high storage density, low power consumption, and low cost. SelectMap is a parallel configuration interface used to transfer configuration programs from external storage (such as bitstreams in NAND flash memory) to the on-chip SRAM of an FPGA. Its characteristics include parallel transmission (data width can be configured to 8 bits or 16 bits, etc.), and fast transmission speed, making it suitable for scenarios requiring rapid configuration.

[0020] The monitoring FPGA is used to perform system reconfiguration based on firmware, including transmitting and receiving satellite commands (such as remote control commands, telemetry commands, control commands, and PPS (Pulse Per Second), acquiring and reporting single-board status information of modules, and controlling system power-on timing. It is also used to load programs and periodically refresh the signal processing FPGA. Different types of FPGAs can be selected for the monitoring FPGA, as long as they are not prone to single-event upsets. By using a FLASH-type FPGA as the "steward" of the entire system, it ensures that even if other modules fail, the monitoring FPGA can still perform status monitoring and firmware updates, thus improving the overall system reliability.

[0021] The optical module performs photoelectric signal conversion and outputs the processed signal at high speed. It includes a main and a backup optical module, forming a redundant design to improve module reliability. The high-speed ADC converts the digital signal transmitted from the laser demodulation module into an analog signal and outputs it to the signal processing FPGA for further processing. The optical driver DAC converts the analog signal received and decoded by the signal processing FPGA into a digital control signal and outputs it to the corresponding optical driver via a connector.

[0022] The power supply module provides a stable and ripple-free power supply to the entire unit. The power supply module chips are connected in a logical manner to form an independent power topology, capable of individually powering the signal processing FPGA, monitoring FPGA, high-speed ADC, and high-performance clock PLL. The system power supply can be designed to power on sequentially, for example... Figure 2 As shown, each minimum system (such as the aforementioned modules) is powered on independently. This design avoids excessive inrush current caused by the simultaneous startup of various modules, while also ensuring the independence of the power supply between each module, thereby improving system reliability.

[0023] A high-performance clock PLL is used to provide the system clock and the service clock required for the data path for the entire unit. It can be understood that the clock of a spaceborne coherent optical laser communication high-speed signal processing unit can be divided into two clock links: a system clock and a service clock. Figure 3 As shown; considering that each functional module of the spaceborne coherent optical laser communication high-speed signal processing unit can operate independently from other modules of the system, the system clock can be provided by adding a board-level crystal oscillator (such as a temperature-compensated crystal oscillator) to a high-performance clock PLL; while the service clock can be multiplied and distributed by the onboard high-performance clock PLL to achieve the effect of all data clocks originating from the same source.

[0024] It is understood that in this embodiment, the number of clock PLLs and high-speed ADCs can both be no less than two. The specific number can be set according to the actual application requirements of the spaceborne coherent optical laser communication high-speed signal processing unit, as long as it can meet the required clock supply and signal conversion functions.

[0025] The aforementioned high-speed signal processing unit for spaceborne coherent optical laser communication, based on industrial-grade components, uses only industrial-grade devices. It employs a specific spaceborne irradiation hardening scheme to enhance the hardware design for harsh conditions such as vacuum thermal alternation and irradiation. This results in a smaller size, lighter weight, and lower power consumption while achieving high communication speed, high signal-to-noise ratio, and strong anti-interference capability, making it an excellent choice for commercial aerospace.

[0026] It should be noted that the aforementioned high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices may also include an analog acquisition module, an analog signal conditioning circuit, a DDR (Double Data Rate) memory, various SMA (Sub-Miniature Version A) ports, and various connectors, etc. The specific functions of these components can be understood by referring to the existing components in laser communication units in this field. After the clock PLL processes the reference clock, it outputs signals such as FPGA-DCLK± and FPGA-SY SREF± back to the signal processing FPGA for clock synchronization and other operations within the signal processing FPGA. On the other hand, it outputs signals such as SY SREF±, DCLK±, and SYNC to the other two clock PLLs on the right, and also has signals such as Trigger± and FPGA-GTHREF± interacting with the GTH (High-Speed ​​Serial Transceiver) of the signal processing FPGA. The other two clock PLLs on the right further generate clock and synchronization signals such as DCLK± and SYSREF±, providing clock (DCLK) and synchronization reference (SYSREF) for the high-speed ADC. This ensures the accuracy and consistency of the clock and synchronization signals when the high-speed ADC is acquiring data, thereby guaranteeing the performance of the entire high-speed data acquisition operation and enabling the signal processing FPGA to accurately process the data acquired by the high-speed ADC. Both GTX1 and GTX2 are high-speed serial transceiver interfaces.

[0027] In one embodiment, the signal processing FPGA is an SRAM-type FPGA, and the program files of the SRAM-type FPGA are stored in at least three different hardware locations in the NAND FLASH.

[0028] It is understood that in this embodiment, the signal processing FPGA can be an SRAM (Static Random-Access Memory) type FPGA. In terms of hardware design, the program file (bit file) of the SRAM type FPGA is stored on the NAND FLASH external to the monitoring FPGA, and can be loaded and refreshed periodically through SelectMap. Considering the bit error caused by single-event upsets and possible signal flips in the storage device itself in the space environment, in terms of hardware design, the program file can be stored in at least three different hardware locations in the NAND FLASH. The probability of an anomaly occurring in three different hardware locations at the same time is extremely low. Therefore, such a redundant design can significantly improve the firmware refresh success rate of the signal processing FPGA, thereby improving the radiation resistance of the signal processing FPGA.

[0029] In one embodiment, serial triple redundancy is configured at at least three different hardware locations of the NAND FLASH where the program file of the SRAM-type FPGA is stored.

[0030] Furthermore, for signal processing FPGAs, in terms of software design, serial triple redundancy can be configured at each different hardware location to ensure the correctness of program file data at each different hardware location; after the aforementioned two triple redundancy data processing, the probability of firmware data anomalies in the signal processing FPGA can be made close to 0, thereby further improving the reliability of the signal processing FPGA.

[0031] Triple Modular Redundancy (TMR) is a technique to improve system reliability and data accuracy. Its core idea is to tolerate errors through hardware or software redundancy. Three identical modules (either hardware circuit modules or software program modules) are placed at critical hardware locations or program execution stages to process the same set of data or instructions simultaneously. After processing, a voter selects the outputs of the three modules, choosing the output that is identical for at least two modules as the final output. Thus, even if one module fails and outputs an incorrect result, it will not affect the final output because the outputs of the other two normal modules will constitute a majority, thereby ensuring the correctness of the output data.

[0032] In one embodiment, the monitoring FPGA is a FLASH type FPGA.

[0033] It is understood that in this embodiment, a FLASH-type FPGA can be selected for monitoring, taking advantage of the characteristic that FLASH-type FPGAs are less prone to single-event upsets. By using the FLASH-type FPGA as the "steward" of the entire system, it is ensured that even if other modules of the system fail, the monitoring FPGA can still perform normal functions such as system status monitoring and firmware updates, thereby improving the reliability of the entire system. At the same time, FLASH-type FPGAs do not require an additional PROM (programmable read-only memory) and have a very short power-on time.

[0034] In one embodiment, the aforementioned high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices may further include reserved NOR FLASH. The reserved NOR FLASH can be used for backup and expansion, and is typically not required.

[0035] Compared with traditional technologies, the above solution utilizes industrial-grade components to realize a high-speed signal processing unit for spaceborne coherent optical laser communication for commercial aerospace. The space communication link supports high-speed and highly reliable data transmission over distances up to 50,000 km, with a communication rate of 10 Gbps. It features flexible transmission and reception configuration and multiple configurable communication rates. The inter-satellite bidirectional communication rate supports configurable rates of 10 Gbps, 5 Gbps, 2.5 Gbps, 1.25 Gbps, 0.625 Gbps, and 0.3125 Gbps.

[0036] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0037] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices, characterized in that, It includes a signal processing FPGA, a monitoring FPGA, a high-speed ADC, a clock PLL, an optical driver DAC, an optical module, and a power module. The signal processing FPGA is connected to the monitoring FPGA, the high-speed ADC, the clock PLL, the optical driver DAC, and the optical module. The clock PLL is connected to the high-speed ADC. The input terminal of the high-speed ADC is used to connect to the analog signal conditioning circuit. The output terminal of the optical driver DAC is used to connect to the optical driver through a connector. The signal processing FPGA is used to receive and decode analog signals transmitted from the laser demodulation module, complete hardware acceleration in baseband protocol processing, and perform encryption / decryption or interface conversion. The monitoring FPGA is used to complete system reconstruction according to the firmware, execute the transmission and reception of various satellite commands, collect and report the single-board status information of the modules, and control the system power-on timing. It is also used to load the program of the signal processing FPGA and refresh it periodically through SelectMap. The firmware of the signal processing FPGA is stored on the NAND FLASH external to the monitoring FPGA. The high-speed ADC is used to convert the digital signal transmitted from the laser demodulation module into an analog signal and output it to the signal processing FPGA. The optical module is used to complete the photoelectric signal conversion and output the processed signal at high speed. The clock PLL is used to provide the system clock and the business clock required by the data path. The optical driver DAC is used to convert the analog signal received and decoded by the signal processing FPGA into a digital control signal and output it to the corresponding optical driver through the connector. The power module is used to provide independent sequential power-on for the monitoring FPGA, signal processing FPGA, clock PLL, and high-speed ADC; The signal processing FPGA is an SRAM-type FPGA, and the program files of the SRAM-type FPGA are stored in at least three different hardware locations in the NAND FLASH. The program files of an SRAM-type FPGA are also configured with serial triple-mode redundancy at at least three different hardware locations in the NAND FLASH where they are stored.

2. The high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices according to claim 1, characterized in that, The monitoring FPGA is a FLASH type FPGA.

3. The high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices according to claim 2, characterized in that, The system clock is provided by adding a board-level crystal oscillator to the clock PLL.

4. The high-speed signal processing unit for spaceborne coherent optical laser communication based on industrial-grade devices according to claim 2, characterized in that, It also includes reserved NOR FLASH.

Images