Semiconductor device and method of manufacturing the same, power device

Abstract

The application discloses a semiconductor device and a preparation method thereof and a power device. The semiconductor device comprises an emitter group, a first base region and a second base region. The emitter group comprises a first emitter and a second emitter, and the conductive types of the first emitter and the second emitter are opposite. The first base region is arranged between the first emitter and the second emitter along a first direction, and the conductive type of the first base region is opposite to that of the first emitter. The second base region is arranged between the first base region and the second emitter along the first direction, and the conductive type of the second base region is opposite to that of the second emitter. At least one of the first base region and the second base region comprises a plurality of first doped regions arranged in a stack along the first direction. A second doped region is arranged between at least two first doped regions adjacent along the first direction, and the second doped region is doped with deep-level impurities. According to the embodiment of the application, the semiconductor device can reduce the on-state voltage drop under the strong surge current working condition to inhibit the further increase of the junction temperature.

Claims

1. A semiconductor device, characterized by, include: An emitter group includes a first emitter and a second emitter, wherein the first emitter and the second emitter have opposite conductivity types; A first base region is disposed between the first emitter and the second emitter along a first direction, wherein the conductivity type of the first base region is opposite to that of the first emitter; A second base region is disposed between the first base region and the second emitter along the first direction, and the second base region and the second emitter have opposite conductivity types; Wherein, at least one of the first base region and the second base region includes a plurality of first doped regions stacked along the first direction, and a second doped region is disposed between at least two adjacent first doped regions along the first direction. The second doped region is doped with deep-level impurities, and the on-state carrier concentration of each first doped region gradually increases along the direction away from the second doped region.

2. The semiconductor device according to claim 1, wherein The specific location of the second doped region is determined by the following formula: In the formula, The distance between the end of the second emitter furthest from the first emitter and the second doped region. To maximize the injected carrier lifetime, The second emitter current density, For unit charge, This represents the average thickness of the first and second base regions.

3. The semiconductor device according to claim 1, characterized in that, The deep-level impurity level of the second doped region is lower than the conduction band bottom of the emitter group and the difference is at least 0.1 eV, or the deep-level impurity level of the second doped region is higher than the valence band top of the emitter group and the difference is at least 0.1 eV.

4. The semiconductor device according to claim 3, characterized in that, The deep-level impurities in the second doped region include at least one of arsenic, selenium, sulfur, indium, and thallium.

5. The semiconductor device according to claim 1, characterized in that, The orthogonal projection of the second doped region onto the second emitter falls within the orthogonal projection range of the first doped region onto the second emitter.

6. The semiconductor device according to claim 1, characterized in that, The first base region surrounds the first emitter, and the surface of the first emitter facing away from the second emitter is flush with the surface of the first base region facing away from the second emitter.

7. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A first doped region is formed on one side of the second emitter along its own thickness direction. The conductivity type of the first doped region is opposite to that of the second emitter. A second doped region is formed, and at least one first doped region is disposed between the second doped region and the second emitter. Along the direction away from the second doped region, the on-state carrier concentration of each first doped region gradually increases. Annealing is performed on the second doped region to activate deep-level impurities; A first base region is formed on the side of the second doped region away from the second emitter. At least one first doped region is disposed between the first base region and the second doped region. The first base region and the first doped region have opposite conductivity types. A first emitter is formed on the side of the first base region away from the second emitter, and the first emitter has the opposite conductivity type to the first base region.

8. An electric power device, characterized in that, It includes the semiconductor device as described in any one of claims 1 to 6, or the semiconductor device prepared by the method described in claim 7.

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