High electron mobility transistor, preparation method and power amplifier / switch

Abstract

The invention discloses a high electron mobility transistor and a preparation method thereof, a power amplifier and a power switch, and relates to the technical field of semiconductors. The high-electron-mobility transistor comprises a substrate, a GaN layer, an AlGaN layer and a GaN cap layer which are sequentially connected in a stacked mode, a first ion injection region and a second ion injection region which are arranged at intervals are arranged on the surface, opposite to the AlGaN layer, of the GaN cap layer, and the first ion injection region and the second ion injection region are provided with a first blind hole and a second blind hole respectively. The first blind hole and the second blind hole are filled with source electrode metal and drain electrode metal respectively, so that the source electrode metal and the drain electrode metal are in contact with the inner walls of the first blind hole and the second blind hole respectively, the contact area between the source electrode metal and the semiconductor material and the contact area between the drain electrode metal and the semiconductor material are increased, the contact resistance is reduced, and the contact potential barrier is reduced. And the ohmic contact resistance can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a high electron mobility transistor and its fabrication method, a power amplifier, and a power switch. Background Technology

[0002] AlGaN / GaN heterojunction high electron mobility transistors (HEP transistors) possess advantages such as high frequency, high power density, and high operating temperature, making them promising candidates for high-frequency, high-power microwave communications. As three-terminal devices, GaN-based HEP transistors utilize ohmic contact technology to fabricate metal electrodes at both their source and drain terminals, enabling signal grounding and output. The quality of these ohmic contacts directly impacts key performance indicators such as saturation output current, on-resistance, and breakdown voltage, as well as the device's performance and reliability in high-frequency and high-temperature applications.

[0003] Currently, forming ohmic contacts typically requires high-temperature processing. At high temperatures, side reactions easily occur at the contact area between the metal and semiconductor materials, generating byproducts with high resistance, leading to increased ohmic contact resistance. The contact between metal and semiconductor materials is usually a direct two-dimensional planar contact, and its contact area is limited by the size of high-electron-mobility transistors, resulting in a relatively small contact area. Furthermore, metals often come into direct contact with AlGaN materials, where the contact barrier is high and the contact resistance is also large, both of which are detrimental to reducing ohmic contact resistance. Summary of the Invention

[0004] This application provides a high electron mobility transistor and its fabrication method, a power amplifier, and a power switch. By setting a first blind hole and a second blind hole in the first ion implantation region and the second ion implantation region respectively, the source metal and the drain metal are in contact with the inner walls of the first blind hole and the second blind hole respectively. At the same time, the contact area between the source metal and the drain metal and the semiconductor material is increased, the contact resistance is reduced, and the contact barrier is lowered, which is beneficial to reducing the ohmic contact resistance.

[0005] In a first aspect, this application provides a high electron mobility transistor, comprising a substrate, a GaN layer, an AlGaN layer, and a GaN cap layer stacked sequentially; the surface of the GaN cap layer facing away from the AlGaN layer has a first ion implantation region and a second ion implantation region spaced apart, the first ion implantation region and the second ion implantation region each having a first blind via and a second blind via, the first blind via and the second blind via both extending along a first direction opposite to the stacking direction, and both the first blind via and the second blind via being partially located in the GaN layer; the high electron mobility transistor further includes a source metal and a drain metal located in the first ion implantation region and the second ion implantation region respectively, the source metal and the drain metal respectively filling the first blind via and the second blind via and both contacting the GaN layer.

[0006] The high electron mobility transistor provided in this application includes a substrate, a GaN layer, an AlGaN layer, and a GaN cap layer stacked sequentially. The surface of the GaN cap layer facing away from the AlGaN layer has a first ion implantation region and a second ion implantation region spaced apart. The first ion implantation region and the second ion implantation region each have a first blind hole and a second blind hole, respectively. The source metal and the drain metal fill the first blind hole and the second blind hole, respectively, so that the source metal and the drain metal not only contact and connect with the surface of the GaN cap layer facing away from the AlGaN layer, but also contact and connect with the inner walls of the first blind hole and the second blind hole, respectively. This increases the contact area between the source metal and the drain metal and the semiconductor material, which is beneficial for reducing ohmic contact resistance.

[0007] Both the first and second blind vias extend along a first direction opposite to the stacking direction. Both are partially located within the GaN layer, allowing portions of the source and drain metals to directly contact the GaN layer. The contact barriers between the source and drain metals and the GaN layer are lower than those between the source and drain metals and the AlGaN layer, reducing the contact resistance in these regions. Furthermore, neither the inner wall of the first nor the second blind via has a high-resistivity layer, further reducing the contact resistance between the source and drain metals and the semiconductor material, which is beneficial for lowering ohmic contact resistance.

[0008] In one possible implementation, the bottom walls of both the first and second blind vias are located within the GaN layer. By ensuring that the bottom walls of both the first and second blind vias are located within the GaN layer, it is guaranteed that when the source and drain metals fill the first and second blind vias respectively, a portion of the source metal and a portion of the drain metal can contact the GaN layer. This simplifies the fabrication process of the first and second blind vias, improves their fabrication efficiency, and consequently enhances the manufacturing efficiency of high electron mobility transistors.

[0009] In one possible implementation, the ratio of the depth of the first or second blind via in the GaN layer to the thickness of the GaN layer is 2% to 90%. By ensuring that the ratio of the depth of the first or second blind via in the GaN layer to the thickness of the GaN layer meets this range, the depths of the first and second blind vias are reasonably configured, guaranteeing the contact area between the source and drain metals and the GaN layer, which helps to reduce ohmic contact resistance.

[0010] In one possible implementation, both the first ion implantation region and the second ion implantation region extend from the GaN cap layer toward the first direction. In the first direction, the depth of the first ion implantation region is greater than the depth of the first blind via, and the depth of the second ion implantation region is greater than the depth of the second blind via. By making the depth of the first ion implantation region greater than the depth of the first blind via, and the depth of the second ion implantation region greater than the depth of the second blind via, the first blind via is located within the first ion implantation region, and the second blind via is located within the second ion implantation region. When the source metal and drain metal fill the first and second blind vias, respectively, the source metal and drain metal are located in the first and second ion implantation regions, respectively. The first and second ion implantation regions are conductive, allowing both the source metal and drain metal to be located in the conductive region of the semiconductor material. This increases the contact area between the source metal and drain metal and the conductive semiconductor material, which helps to reduce ohmic contact resistance.

[0011] In one possible implementation, the number of the first blind vias is at least two, and the at least two first blind vias are spaced apart. By having at least two first blind vias, and the at least two first blind vias are spaced apart, the total area of ​​the inner wall of the first blind vias is increased, thereby increasing the contact area between the source metal and the semiconductor material, which is beneficial for reducing ohmic contact resistance.

[0012] In one possible implementation, the ratio of the total area of ​​the first blind aperture opening to the projected area of ​​the first ion implantation region in the first direction is 40% to 70%. By ensuring that the ratio of the total area of ​​the first blind aperture opening to the projected area of ​​the first ion implantation region in the first direction meets this range, the size of the first blind aperture opening and the size of the first ion implantation region are reasonably configured, appropriately increasing the contact area between the source metal and the semiconductor material, which is beneficial for reducing ohmic contact resistance.

[0013] In one possible implementation, the source metal includes a first part and a second part connected together. The first part protrudes from the surface of the GaN cap layer facing away from the AlGaN layer in the stacking direction. The second part fills the first blind via. In the first direction, the projection of the first part completely covers the projection of the second part. By ensuring that the projection of the first part completely covers the projection of the second part, the integrity of the first part structure and the area at the connection between the first and second parts are guaranteed, thus ensuring the conductivity of the first and second parts. Simultaneously, it also facilitates the complete filling of the first blind via by the source metal, ensuring the contact area between the source metal and the inner wall of the first blind via, thereby reducing the ohmic contact resistance.

[0014] Secondly, this application also provides a method for fabricating a high electron mobility transistor, comprising: providing a substrate, and sequentially forming a GaN layer, an AlGaN layer, and a GaN cap layer on the substrate; implanting ions into the surface of the GaN cap layer opposite to the AlGaN layer to form a first ion implantation region and a second ion implantation region spaced apart; coating the first ion implantation region and the second ion implantation region with nanospheres to form a mask; etching the areas of the first ion implantation region and the second ion implantation region other than the mask; forming a first blind hole and a second blind hole in the first ion implantation region and the second ion implantation region, respectively, wherein the first blind hole and the second blind hole are both partially located in the GaN layer; and filling the first blind hole and the second blind hole with a metal material to form a source metal and a drain metal in contact with the GaN layer, respectively.

[0015] The high electron mobility transistor fabrication method provided in this application achieves indirect control of the shape and size of the mask by coating nanospheres in the first and second ion implantation regions to form a mask, thereby controlling the shape and size of the mask through the modulation of the nanopattern formed by the nanospheres. Since the areas of the first and second ion implantation regions other than the mask are etched to form the first and second blind holes respectively, the shape and size of the first and second blind holes are also indirectly controlled by the shape and size of the mask. That is, the shape and size of the first and second blind holes can be indirectly controlled by the modulation of the nanopattern formed by the nanospheres, which is beneficial to improving the controllability of the high electron mobility transistor fabrication process.

[0016] The source and drain metals fill the first and second blind vias, respectively. Because the first and second blind vias are etched, their inner walls lack a high-resistivity layer, allowing the source and drain metals to directly contact the semiconductor material. This helps reduce the contact resistance between the source and drain metals and the semiconductor material. Simultaneously, both the first and second blind vias are partially located within the GaN layer, allowing portions of the source and drain metals to contact the GaN layer, which has a lower contact barrier, further reducing the contact resistance between the source and drain metals and the semiconductor material. Furthermore, the contact between the source and drain metals and the inner walls of the first and second blind vias increases the contact area between the source and drain metals and the semiconductor material, all of which contribute to reducing ohmic contact resistance and improving the performance of high electron mobility transistors.

[0017] In one possible implementation, after coating both the first and second ion implantation regions with the nanospheres, the nanospheres are connected to the GaN cap layer, and a monolayer nanosphere layer is formed in both the first and second ion implantation regions. By forming a monolayer nanosphere layer in both the first and second ion implantation regions, the nanospheres do not stack in the stacking direction, simplifying the control of the nanosphere size and thus simplifying the control of the opening size of the first and second blind holes.

[0018] In one possible implementation, after coating both the first and second ion implantation regions with the nanospheres, the size of the nanospheres is controlled using plasma, with the nanospheres covering 30% to 60% of the area of ​​either the first or second ion implantation region. By ensuring that the proportion of the nanospheres covering the area of ​​the first or second ion implantation region meets this range, the size of the first blind hole opening relative to the size of the first ion implantation region, or the size of the second blind hole opening relative to the size of the second ion implantation region, is rationally configured. This appropriately increases the contact area between the source or drain metal and the semiconductor material, while avoiding affecting the concentration of the two-dimensional electron gas, which is beneficial for reducing ohmic contact resistance.

[0019] In one possible implementation, the step of forming the mask includes: after forming the monolayer nanosphere layer in both the first ion implantation region and the second ion implantation region, depositing a layer of the mask on the surface of the GaN cap layer facing away from the AlGaN layer to replace the nanospheres in the monolayer nanosphere layer. By replacing the nanospheres in the monolayer nanosphere layer with the mask, the shape and size of the mask can be indirectly controlled by regulating the nanopatterns formed by the nanospheres, which is beneficial to improving the controllability in the fabrication process of high electron mobility transistors.

[0020] In one possible implementation, the step of forming the mask further includes: after forming the monolayer nanospheres in both the first and second ion implantation regions, first forming a metal layer on the side of the GaN cap layer facing away from the AlGaN layer to fill the gaps in the monolayer nanospheres; then cleaning with a first solvent to remove the nanospheres, thereby creating gaps between the metal layers in the first and second ion implantation regions; and finally forming the mask on the surface of the GaN cap layer facing away from the AlGaN layer to fill the gaps in the metal layer, thus achieving the replacement of the nanospheres by the mask. By filling the gaps in the monolayer nanospheres with a metal layer, cleaning to remove the nanospheres, and then filling the gaps in the metal layer with a mask, the replacement of the nanospheres by the mask is achieved. This utilizes the difference in polarity between the metal layer material, the nanosphere material, and the mask material, simplifying the process of replacing the nanospheres by the mask.

[0021] In one possible implementation, after depositing a mask layer on the surface of the GaN cap layer facing away from the AlGaN layer to fill the gaps in the metal layer, the metal layer is removed by cleaning with a second solvent. By removing the metal layer with the second solvent, gaps are formed in the areas of the mask where the metal layer was originally located, leaving etching areas to facilitate the formation of a first blind via and a second blind via in the first ion implantation region and the second ion implantation region, respectively.

[0022] In one possible implementation, the metal layer forms a first metal protrusion in the first ion implantation region and a second metal protrusion in the second ion implantation region. The first metal protrusion corresponds to the first blind via, and the second metal protrusion corresponds to the second blind via. The number of the first metal protrusion and / or the second metal protrusion is at least two. By having at least two first metal protrusions and / or second metal protrusions, the number of first blind vias and / or second blind vias is also at least two. Increasing the number of first blind vias and / or second blind vias helps to increase the total area of ​​the inner wall of the first or second blind via, thereby increasing the contact area between the source metal or drain metal and the semiconductor material and reducing the ohmic contact resistance.

[0023] In one possible implementation, at least two of the first metal protrusions are spaced apart, and / or at least two of the second metal protrusions are spaced apart. By spacing the at least two first metal protrusions and / or at least two second metal protrusions apart, it is beneficial to increase the specific surface area of ​​the inner wall of the first or second blind via, thereby increasing the contact area between the source metal or drain metal and the semiconductor material and reducing the ohmic contact resistance.

[0024] Thirdly, this application also provides a power amplifier, including a high electron mobility transistor fabricated by the fabrication method of the high electron mobility transistor described in any embodiment of the first aspect or any embodiment of the second aspect, and other electronic components. The source of the high electron mobility transistor is grounded, the drain is connected to one of the electronic components, and the gate is connected to another electronic component. The beneficial effects of this embodiment are similar to those of the above embodiments, and will not be repeated here.

[0025] Fourthly, this application also provides a power switch, comprising a high electron mobility transistor and other electronic components fabricated by the fabrication method of the high electron mobility transistor described in any embodiment of the first aspect or the high electron mobility transistor described in any embodiment of the second aspect, wherein the source of the high electron mobility transistor is grounded, the drain is connected to one of the electronic components, and the gate is connected to another of the electronic components. The beneficial effects of this embodiment are similar to those of the above embodiments, and will not be repeated here. Attached Figure Description

[0026] Figure 1 This is a schematic cross-sectional view of the high electron mobility transistor provided in the embodiments of this application;

[0027] Figure 2 This is a schematic cross-sectional view of the high electron mobility transistor provided in the embodiments of this application without source and drain metals.

[0028] Figure 3 yes Figure 2 A top view of the high electron mobility transistor provided in the illustrated embodiment;

[0029] Figure 4 This is a schematic diagram of the system for fabricating a high electron mobility transistor according to an embodiment of this application;

[0030] Figure 5 This is a cross-sectional structural diagram of the protective layer formed during the HEMT preparation process according to the embodiments of this application;

[0031] Figure 6 This is a schematic cross-sectional view of the photoresist layer formed during the HEMT fabrication process according to an embodiment of this application;

[0032] Figure 7 This is a schematic cross-sectional view of the formation of the first ion implantation region and the second ion implantation region during the HEMT preparation process provided in the embodiments of this application;

[0033] Figure 8 This is a schematic cross-sectional view of the annealing medium protective layer formed during the HEMT preparation process according to an embodiment of this application;

[0034] Figure 9 This is a schematic cross-sectional view of the activated first and second ion implantation regions during the HEMT preparation process provided in the embodiments of this application.

[0035] Figure 10 This is a schematic cross-sectional view of the coated nanospheres during the HEMT preparation process provided in the embodiments of this application;

[0036] Figure 11 This is a schematic cross-sectional view of the structure for controlling the size of nanospheres during the HEMT preparation process provided in the embodiments of this application;

[0037] Figure 12 This is a schematic cross-sectional view of the metal layer formed during the HEMT fabrication process provided in the embodiments of this application;

[0038] Figure 13 This is a schematic diagram of the cross-sectional structure after removing nanospheres during the HEMT preparation process provided in the embodiments of this application;

[0039] Figure 14 This is a schematic cross-sectional view of the HEMT fabrication process after the photoresist layer has been removed, according to an embodiment of this application.

[0040] Figure 15 This is a schematic cross-sectional view of the mask formed during the HEMT fabrication process according to an embodiment of this application;

[0041] Figure 16 This is a cross-sectional structural diagram of the formation of the first and second blind holes by removing the metal layer during the HEMT fabrication process provided in the embodiments of this application;

[0042] Figure 17 This is a partial schematic diagram of the power amplifier provided in an embodiment of this application;

[0043] Figure 18 This is a partial schematic diagram of the power switch provided in the embodiments of this application. Detailed Implementation

[0044] The embodiments of this application are described below with reference to the accompanying drawings.

[0045] For ease of understanding, the English abbreviations and related technical terms used in the embodiments of this application will be explained and described below.

[0046] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0047] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0048] It should be understood that the term "and / or" used in this document is merely a description of the same field in the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0049] Depending on the context, the word "if" as used herein can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0050] It should be understood that the terms "first," "second," etc., used in this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order.

[0051] In the description of this application, the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0052] In the description of this application, it should be noted that due to manufacturing or assembly errors, there may be slight angular deviations in the design that should be perpendicular or parallel. For example, a deviation within 15 degrees is also considered perpendicular or parallel as described in this embodiment.

[0053] The phrase "within the range" used in this application, unless otherwise specified, includes both endpoints of the range by default. For example, in the range of 1 to 5, it includes the values ​​1 and 5.

[0054] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation", "connection" and "joining" should be interpreted broadly, for example, they can be fixed connections, detachable connections, mating connections or integral connections; those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0055] It should be understood that in this application, "electrical connection" can be understood as physical contact and electrical conduction between components; it can also be understood as the form in which different components in a circuit structure are connected through physical lines that can transmit signals, such as copper foil or wires on a printed circuit board (PCB). "Connection" and "connected" can both refer to a mechanical or physical connection relationship. For example, A and B being connected or A and B being connected can mean that there are fastening components (such as screws, bolts, rivets, etc.) between A and B, or that A and B are in contact with each other and are difficult to separate.

[0056] Gallium nitride (GaN) semiconductor materials possess excellent properties such as a large bandgap, high breakdown field strength, and high saturated electron drift velocity, making GaN high electron mobility transistors (GaN HEMTs) highly promising for high-frequency power applications. High electron mobility transistors formed by GaN and aluminum gallium nitride (AlGaN) materials can create AlGaN / GaN heterojunctions. Due to the polarization difference between AlGaN and GaN materials, the AlGaN / GaN structure exhibits piezoelectric polarization and spontaneous polarization, leading to the formation of a two-dimensional electron gas (2DEG) at the heterojunction interface under the influence of an electric field. This 2DEG possesses high electron density and electron mobility, giving AlGaN / GaN heterojunction high electron mobility transistors advantages such as high frequency, high power density, and high operating temperature, making them promising for applications in high-frequency, high-power microwave communications.

[0057] GaN-based high electron mobility transistors (HEPs) are three-terminal devices. Both their source and drain electrodes are fabricated using ohmic contact (metal-semiconductor material contact) technology to achieve signal grounding and signal output functions. The performance of the ohmic contact directly affects key performance indicators such as saturation output current, on-resistance, and breakdown voltage, as well as the device's performance and reliability in high-frequency and high-temperature applications. Common methods for forming ohmic contacts include those based on Ti / Al high-temperature alloys, ion-implanted ohmic contacts, and secondary epitaxial highly n++ GaN ohmic contacts.

[0058] Ohmic contacts based on Ti / Al high-temperature alloys typically form an ohmic contact by connecting the alloy to GaN material. The high alloying temperature makes it prone to side reactions during alloying, resulting in alloys with higher resistance and thus increasing the ohmic contact resistance. In traditional Ti / Al / X / Au multilayer metal ohmic solutions, the melting point of Al is approximately 660.4℃, and the alloying temperature generally exceeds 800℃. During high-temperature alloying, Al is in a molten state and reacts with Au to form high-resistivity AlAu2 or AlAu4 alloys, further increasing the ohmic contact resistance. Simultaneously, the high-temperature process can also cause surface roughness of the metal electrodes, leading to spike electric fields. This reduces the breakdown characteristics of the device with the ohmic contact, causes uneven current distribution, and attenuates the signal, ultimately affecting the device's reliability.

[0059] Ohmic contacts based on ion implantation and those based on secondary epitaxial highly doped n++ GaN generally form ohmic contacts by high-concentration doping in the contact region followed by metal deposition. AlGaN, compared to GaN, has a greater affinity and bandgap, resulting in a higher barrier height and greater contact resistance when in contact with metal. The metal typically contacts AlGaN directly, which is detrimental to reducing ohmic contact resistance. Furthermore, the direct two-dimensional planar contact between the ohmic metal and the highly doped region limits the contact area, making it relatively small. During the high-temperature activation of the highly doped region, the GaN epitaxial layer and annealed dielectric protective layer are prone to side reactions at high temperatures, forming a high-resistivity layer. The direct contact between the metal and this high-resistivity layer further increases the contact resistance and reduces the contact area, both of which are detrimental to reducing ohmic contact resistance.

[0060] This application provides a high electron mobility transistor 100; please refer to [link to relevant documentation]. Figure 1 and Figure 2 , Figure 1 This diagram shows a cross-sectional view of the high electron mobility transistor 100 provided in an embodiment of this application. Figure 2This diagram shows a cross-sectional view of a high electron mobility transistor 100 provided in an embodiment of this application without the source metal 17 and drain metal 18. The high electron mobility transistor 100 includes a substrate 11, a GaN layer 12, an AlGaN layer 13, and a GaN cap layer 14 stacked sequentially. The surface of the GaN cap layer 14 facing away from the AlGaN layer 13 has a first ion implantation region 15 and a second ion implantation region 16 spaced apart. The first ion implantation region 15 and the second ion implantation region 16 each have a first blind via 151 and a second blind via 161. The high electron mobility transistor 100 also includes a source metal 17 and a drain metal 18, which are located in the first ion implantation region 15 and the second ion implantation region 16, respectively, and fill the first blind via 151 and the second blind via 161.

[0061] With the direction from substrate 11 to GaN cap layer 14 as the stacking direction of the high electron mobility transistor 100, both source metal 17 and drain metal 18 protrude from the surface of GaN cap layer 14 facing away from AlGaN layer 13 in the stacking direction. The height of the source metal 17 and drain metal 18 protruding from the surface of GaN cap layer 14 facing away from AlGaN layer 13 in the stacking direction can be set according to actual needs. Source metal 17 and drain metal 18 are located in the first ion implantation region 15 and the second ion implantation region 16, respectively. The source metal 17 and drain metal 18 are spaced apart to provide space for the gate 190 between them and to prevent short circuits caused by contact between them. The relationship between the projected area of ​​source metal 17 and the projected area of ​​the first ion implantation region 15 in the stacking direction can be set according to actual needs. The drain metal 18 and the second ion implantation region 16 are similarly configured. In one embodiment, please refer to... Figure 1 The projected area of ​​the source metal 17 in the stacking direction is larger than the projected area of ​​the first ion implantation region 15 in the stacking direction, and the projected area of ​​the drain metal 18 in the stacking direction is larger than the projected area of ​​the second ion implantation region 16 in the stacking direction. This ensures that the contact areas of the source metal 17 and the drain metal 18 with the first ion implantation region 15 and the second ion implantation region 16 are respectively, which is beneficial to reducing the ohmic contact resistance.

[0062] With the direction opposite to the stacking direction as the first direction, both the first blind via 151 and the second blind via 161 extend along the first direction. Both the first blind via 151 and the second blind via 161 penetrate the GaN cap layer 14 and the AlGaN layer 13, so that the first blind via 151 and the second blind via 161 can reach the GaN layer 12. Both the first blind via 151 and the second blind via 161 penetrate at least a portion of the GaN layer 12, so that both the first blind via 151 and the second blind via 161 are partially located in the GaN layer 12. The first blind via 151 or the second blind via 161 can penetrate the GaN layer 12, or the first blind via 151 or the second blind via 161 can penetrate a portion of the GaN layer 12. When the first blind via 151 or the second blind via 161 penetrates the GaN layer 12, the first blind via 151 or the second blind via 161 penetrating the GaN layer 12 can also penetrate a portion of the substrate 11.

[0063] When the source metal 17 and the drain metal 18 fill the first blind via 151 and the second blind via 161 respectively, the source metal 17 and the drain metal 18 contact and connect with the inner walls of the first blind via 151 and the second blind via 161 respectively. Since the first blind via 151 and the second blind via 161 are both partially located in the GaN layer 12, the source metal 17 and the drain metal 18 can directly contact and connect with the GaN layer 12. The source metal 17 includes a portion protruding from the surface of the GaN cap layer 14 facing away from the AlGaN layer 13 and a portion located within the first blind via 151. The drain metal 18 includes a portion protruding from the surface of the GaN cap layer 14 facing away from the AlGaN layer 13 and a portion located within the second blind via 161. The portions of the source metal 17 and the drain metal 18 protruding from the surface of the GaN cap layer 14 facing away from the AlGaN layer 13 are in direct contact and connected to the surface of the GaN cap layer 14 facing away from the AlGaN layer 13. The portion of the source metal 17 located within the first blind via 151 and the portion of the drain metal 18 located within the second blind via 161 are in direct contact and connected to the GaN cap layer 14, the AlGaN layer 13, and the GaN layer 12.

[0064] The source metal 17 is in contact with and connected not only to the first ion implantation region 15 on the surface of the GaN cap layer 14 facing away from the AlGaN layer 13, but also to the inner wall of the first blind via 151. Similarly, the drain metal 18 is in contact with and connected not only to the second ion implantation region 16 on the surface of the GaN cap layer 14 facing away from the AlGaN layer 13, but also to the inner wall of the second blind via 161. Compared to the source metal 17 and drain metal 18 only contacting and connecting to the surface of the GaN cap layer 14 facing away from the AlGaN layer 13, this increases the contact area between the source metal 17 and drain metal 18 and the semiconductor material, which helps to reduce ohmic contact resistance and thus improve the operating performance of the high electron mobility transistor 100.

[0065] High-temperature annealing is required to activate the ions in the first ion implantation region 15 and the second ion implantation region 16. During the high-temperature annealing activation process, an annealing dielectric layer is typically coated on the surface of the GaN cap layer 14 facing away from the AlGaN layer 13 to protect the GaN cap layer 14, AlGaN layer 13, and GaN layer 12. However, due to the excessively high reaction temperature during the high-temperature annealing activation process, the contact surface between the annealing dielectric layer and the GaN cap layer 14 is prone to side reactions at high temperatures, forming a high-resistivity layer. Even after removing the annealing dielectric layer, a portion of the high-resistivity layer remains on the side of the GaN cap layer 14 away from the AlGaN layer 13. When the source metal 17 and drain metal 18 contact the surface of the GaN cap layer 14 facing away from the AlGaN layer 13, the source metal 17 and drain metal 18 contact the high-resistivity layer on the side of the GaN cap layer 14 away from the AlGaN layer 13, resulting in a large ohmic contact resistance. The inner walls of the first blind via 151 and the second blind via 161 do not have a high-resistivity layer. Part of the source metal 17 contacts the inner wall of the first blind via 151, and part of the drain metal 18 contacts the inner wall of the second blind via 161. This prevents a portion of the source metal 17 and a portion of the drain metal 18 from contacting the high-resistivity layer. Furthermore, these portions of the source metal 17 and the drain metal 18 can directly contact and connect with the GaN cap layer 14, the AlGaN layer 13, and the GaN layer 12, which helps to reduce ohmic contact resistance.

[0066] The contact barrier between AlGaN layer 13 and the metal is higher than that between GaN layer 12 and the metal, resulting in a greater contact resistance between the metal and AlGaN layer 13 than between the metal and GaN layer 12. Both the first blind via 151 and the second blind via 161 are partially located within GaN layer 12, allowing a portion of source metal 17 and a portion of drain metal 18 to directly contact and connect with the GaN layer 12, which has a lower contact barrier. Compared to situations where source metal 17 and drain metal 18 only contact AlGaN layer 13, this arrangement, where a portion of source metal 17 and drain metal 18 contacts AlGaN layer 13 and another portion contacts GaN layer 12, reduces the contact resistance in certain regions of source metal 17 and drain metal 18, thus helping to reduce ohmic contact resistance.

[0067] GaN layer 12 serves as the channel layer, and AlGaN layer 13 serves as the barrier layer. The interaction between AlGaN layer 13 and GaN layer 12 forms an AlGaN / GaN heterojunction. A two-dimensional electron gas (2DEG) is generated at the interface between GaN layer 12 and AlGaN layer 13, polarized at this interface. Electrons in the 2DEG can only move freely in two directions, resulting in high electron density and electron mobility. Source metal 17 and drain metal 18 are used to allow the 2DEG to flow within the channel layer between source metal 170 and drain metal 180 under the influence of an electric field. Conduction between source metal 170 and drain metal 180 occurs at the 2DEG in the channel layer. By allowing source metal 17 and drain metal 18 to pass through the AlGaN / GaN heterojunction interface, electrons in GaN layer 12 can directly enter source metal 17 and drain metal 18, which helps reduce ohmic contact resistance.

[0068] In one embodiment, please refer to Figure 1 The source metal 17 and drain metal 18 fill the first blind via 151 and the second blind via 161 respectively, avoiding the problem of a reduced contact area between the source metal 17 and the inner wall of the first blind via 151 or the drain metal 18 and the inner wall of the second blind via 161 due to gaps. This ensures the contact area between the source metal 17 and the inner wall of the first blind via 151 and the drain metal 18 and the inner wall of the second blind via 161, which helps to reduce the ohmic contact resistance.

[0069] This application provides a high electron mobility transistor 100, which includes a substrate 11, a GaN layer 12, an AlGaN layer 13, and a GaN cap layer 14 stacked sequentially. The AlGaN layer 13 and the GaN layer 12 can form an AlGaN / GaN heterojunction, which forms a two-dimensional electron gas with high electron density and electron mobility at the heterojunction interface, which is beneficial for the high electron mobility transistor 100 to achieve high frequency, high power density, and high operating temperature performance.

[0070] The GaN cap layer 14 has a first ion implantation region 15 and a second ion implantation region 16 spaced apart on the surface facing away from the AlGaN layer 13. The first ion implantation region 15 and the second ion implantation region 16 have a first blind via 151 and a second blind via 161, respectively. The high electron mobility transistor 100 also includes a source metal 17 and a drain metal 18. The source metal 17 and the drain metal 18 fill the first blind via 151 and the second blind via 161, respectively, so that the source metal 17 and the drain metal 18 are located in the first ion implantation region 15 and the second ion implantation region 16, respectively. The source metal 17 and the drain metal 18 are spaced apart, which helps to avoid short circuits when the source metal 17 and the drain metal 18 come into contact, and provides space for the gate 190. Meanwhile, the source metal 17 and drain metal 18 not only contact and connect with the surface of the GaN cap layer 14 facing away from the AlGaN layer 13, but also contact and connect with the inner walls of the first blind hole 151 and the second blind hole 161, respectively, which increases the contact area between the source metal 17 and drain metal 18 and the semiconductor material, which is beneficial to reducing the ohmic contact resistance.

[0071] Both the first blind via 151 and the second blind via 161 extend along a first direction opposite to the stacking direction. Both are partially located within the GaN layer 12, allowing a portion of the source metal 17 and a portion of the drain metal 18 to directly contact the GaN layer 12. The contact barrier between the source metal 17 and the drain metal 18 and the GaN layer 12 is lower than the contact barrier between the source metal 17 and the drain metal 18 and the AlGaN layer 13, thus reducing the contact resistance in certain regions of the source metal 17 and the drain metal 18. Simultaneously, neither the inner wall of the first blind via 151 nor the inner wall of the second blind via 161 has a high-resistivity layer, reducing the contact resistance between the source metal 17 and the drain metal 18 and the semiconductor material, which is beneficial for reducing ohmic contact resistance.

[0072] For one possible implementation, please refer to Figure 2The bottom walls of the first blind via 151 and the second blind via 161 are both located in the GaN layer 12, so that the first blind via 151 and the second blind via 161 both penetrate a portion of the GaN layer 12. This ensures that when the source metal 17 and the drain metal 18 fill the first blind via 151 and the second blind via 161 respectively, a portion of the source metal 17 and a portion of the drain metal 18 can contact the GaN layer 12. Meanwhile, compared to the first blind via 151 and / or the second blind via 161 completely penetrating the GaN layer 12, the first blind via 151 and the second blind via 161 have a smaller depth in the first direction, which helps to simplify the processing of the first blind via 151 and the second blind via 161 and improve the processing efficiency of the first blind via 151 and the second blind via 161. The smaller depth of the first blind via 151 and the second blind via 161 also simplifies the filling process of the source metal 17 and the drain metal 18 on the first blind via 151 and the second blind via 161 respectively, thereby improving the manufacturing efficiency of the high electron mobility transistor 100.

[0073] The depths of the first blind via 151 and the second blind via 161 at the GaN layer 12 can be set according to actual needs. In the first direction, the depths of the first blind via 151 and the second blind via 161 can be the same or different, and this application does not impose any restrictions on this. It is understood that when the bottom wall of the first blind via 151 or the bottom wall of the second blind via 161 is located at the interface between the GaN layer 12 and the AlGaN layer 13, it should also be considered that the bottom wall of the first blind via 151 or the bottom wall of the second blind via 161 is located at the GaN layer 12.

[0074] In one embodiment, please refer to Figure 2 The first blind via 151 has a depth of h1 in the GaN layer 12, and the second blind via 161 has a depth of h2 in the GaN layer 12. The thickness of the GaN layer 12 is H. The first blind via 151 and the GaN layer 12 satisfy the following relationship: 2% ≤ h1 / H ≤ 90%; the second blind via 161 and the GaN layer 12 satisfy the following relationship: 2% ≤ h2 / H ≤ 90%.

[0075] By ensuring that the first blind via 151, the second blind via 161, and the GaN layer 12 satisfy the above-mentioned relationship, the depths of the first blind via 151 and the second blind via 161 are rationally configured. This guarantees the contact area between the source metal 17 and the drain metal 18 and the GaN layer 12. A portion of the source metal 17 and a portion of the drain metal 18 contact the GaN layer 12, which has a lower contact barrier, thus helping to reduce ohmic contact resistance. If the depth is below the above-mentioned relationship, the depth of the first blind via 151 or the second blind via 161 is too small, resulting in insufficient contact area between the source metal 17 or the drain metal 18 and the GaN layer 12, and the effect on reducing ohmic contact resistance is not significant. If the depth is above the above-mentioned relationship, the depth of the first blind via 151 or the second blind via 161 is too large, which is not conducive to simplifying the setting of the first blind via 151 or the second blind via 161.

[0076] The GaN cap layer 14 has a first ion implantation region 15 and a second ion implantation region 16 spaced apart on its surface facing away from the AlGaN layer 13. Both the first ion implantation region 15 and the second ion implantation region 16 extend from the GaN cap layer 14 in a first direction, making both three-dimensional regions. In the first direction, the depth of the first ion implantation region 15 is greater than the depth of the first blind via 151, and the depth of the second ion implantation region 16 is greater than the depth of the second blind via 161, such that the first blind via 151 is located within the first ion implantation region 15, and the second blind via 161 is located within the second ion implantation region 16. When the source metal 17 and the drain metal 18 fill the first blind via 151 and the second blind via 161 respectively, the source metal 17 and the drain metal 18 are located in the first ion implantation region 15 and the second ion implantation region 16 respectively. The first ion implantation region 15 and the second ion implantation region 16 are conductive, so that the source metal 17 and the drain metal 18 can be located in the conductive region of the semiconductor material, which increases the contact area between the source metal 17 and the drain metal 18 and the conductive semiconductor material, which is beneficial to reducing the ohmic contact resistance.

[0077] By placing the bottom walls of the first blind via 151 and the second blind via 161 both within the GaN layer 12, the depth of the first blind via 151 and / or the second blind via 161 in the first direction is reduced compared to when the first blind via 151 and / or the second blind via 161 completely penetrate the GaN layer 12. While ensuring that the depth of the first ion implantation region 15 is greater than the depth of the first blind via 151 and the depth of the second ion implantation region 16 is greater than the depth of the second blind via 161, the depth of the first ion implantation region 15 and the second ion implantation region 16 in the first direction is also reduced. This simplifies the ion implantation process of the first ion implantation region 15 and the second ion implantation region 16, and improves the manufacturing efficiency of the high electron mobility transistor 100.

[0078] In one embodiment, please refer to Figure 1The bottom walls of the first blind via 151 and the second blind via 161 are both located in the GaN layer 12. In the first direction, the depth of the first ion implantation region 15 is greater than the depth of the first blind via 151, and the depth of the second ion implantation region 16 is greater than the depth of the second blind via 161. The depths of the first ion implantation region 15 and the second ion implantation region 16 are both less than the total thickness of the GaN cap layer 14, the AlGaN layer 13, and the GaN layer 12. This makes the side of the first ion implantation region 15 and the second ion implantation region 16 away from the GaN cap layer 14 located in the GaN layer 12. This helps to reduce the depth of the first ion implantation region 15 and the second ion implantation region 16 in the first direction, thereby simplifying the setting process of the first ion implantation region 15 and the second ion implantation region 16.

[0079] In the first direction, the projected area of ​​the first ion implantation region 15 and the projected area of ​​the second ion implantation region 16 can be the same or different. In the first direction, the sum of the projected areas of the first ion implantation region 15 and the second ion implantation region 16 is less than the projected area of ​​the surface of the GaN cap layer 14 facing away from the AlGaN layer 13, so as to provide space for the setting of the gate 190. The ratio of the sum of the projected areas of the first ion implantation region 15 and the second ion implantation region 16 to the projected area of ​​the surface of the GaN cap layer 14 facing away from the AlGaN layer 13 can be set according to actual needs.

[0080] In one embodiment, please refer to Figure 2 and Figure 3 , Figure 3 It shows Figure 2 The illustrated embodiment provides a top view of a high electron mobility transistor 100. In the first direction, the projected area of ​​the first ion implantation region 15 is the same as the projected area of ​​the second ion implantation region 16, and the depths of the first ion implantation region 15 and the second ion implantation region 16 are the same. This facilitates improved uniformity of the ion implantation process for the first ion implantation region 15 and the second ion implantation region 16, thereby improving the setup efficiency of the first ion implantation region 15 and the second ion implantation region 16. It also avoids the situation where the completion time of one of the first ion implantation regions 15 and the second ion implantation region 16 differs from that of the other, thus affecting the setup efficiency of the first ion implantation region 15 and the second ion implantation region 16.

[0081] For one possible implementation, please refer to Figures 1 to 3The number, size, or shape of the first blind via 151 in the first ion implantation region 15 and the second blind via 161 in the second ion implantation region 16 may be the same or different, and this application does not impose any restrictions on this. The number of the first blind via 151 or the second blind via 161 may be single, which is beneficial to simplifying the arrangement of the first blind via 151 or the second blind via 161; the number of the first blind via 151 or the second blind via 161 may also be at least two, which is beneficial to increase the total area of ​​the inner wall of the first blind via 151 or the second blind via 161, thereby increasing the contact area between the source metal 17 or the drain metal 18 and the semiconductor material, and reducing the ohmic contact resistance.

[0082] In one embodiment, please refer to Figure 1 The first ion implantation region 15 has at least two first blind holes 151, which are spaced apart. Source metal 17 fills at least two of the first blind holes 151, and the source metal 17 contacts and connects to the inner wall of each first blind hole 151, increasing the contact area between the source metal 17 and the semiconductor material, which helps reduce ohmic contact resistance. Similarly, the second ion implantation region 16 can also have at least two second blind holes 161, which are spaced apart. Drain metal 18 fills at least two of the second blind holes 161, and the drain metal 18 contacts and connects to the inner wall of each second blind hole 161, increasing the contact area between the drain metal 18 and the semiconductor material, which also helps reduce ohmic contact resistance.

[0083] In one embodiment, please refer to Figure 2 and Figure 3 At least two first blind holes 151 have the same shape and size, and at least two second blind holes 161 have the same shape and size. The fact that the first blind holes 151 and the second blind holes 161 have the same shape and size helps to simplify the setting of the first blind holes 151 and the second blind holes 161.

[0084] For one possible implementation, please refer to Figure 3 The area of ​​the opening of the first blind via 151 is m1, the projected area of ​​the first ion implantation region 15 in the first direction is M1, and the area of ​​the opening of the first blind via 151 is the area enclosed by the edge of the GaN cap layer 14 surrounding the first blind via 151. When the number of first blind vias 151 in the first ion implantation region 15 is at least two, the area of ​​the opening of the first blind via 151 is the total area of ​​the openings of at least two first blind vias 151. The first blind via 151 and the first ion implantation region 15 satisfy the relationship: 40% ≤ m1 / M1 ≤ 70%.

[0085] By ensuring that the first blind via 151 and the first ion implantation region 15 satisfy the above-mentioned relationship, the size of the opening of the first blind via 151 and the size of the first ion implantation region 15 are reasonably configured, appropriately increasing the contact area between the source metal 17 and the semiconductor material, which is beneficial for reducing ohmic contact resistance. Below the above relationship, the opening size of the first blind via 151 is too small. At the same depth, the inner wall area of ​​the first blind via 151 is small, and the contact area between the source metal 17 and the semiconductor material is small, resulting in an insignificant effect on reducing ohmic contact resistance. Above the above relationship, the opening size of the first blind via 151 is too large, and the source metal 17 occupies a large volume in the first ion implantation region 15, leading to a reduction in the contact area between the AlGaN layer 13 and the GaN layer 12 at the first ion implantation region 15. This makes it difficult to maintain a high concentration of two-dimensional electron gas, easily affecting electron density and electron mobility.

[0086] The projected area of ​​the opening of the second blind via 161 is m2, and the projected area of ​​the second ion implantation region 16 in the first direction is M2. When the number of second blind vias 161 in the second ion implantation region 16 is at least two, the projected area of ​​the second blind via 161 is the total area of ​​at least two second blind vias 161. The second blind via 161 and the second ion implantation region 16 satisfy the relationship: 40% ≤ m2 / M2 ≤ 70%. By making the second blind via 161 and the second ion implantation region 16 satisfy the above relationship, the size of the opening of the second blind via 161 and the size of the second ion implantation region 16 are reasonably configured, and the contact area between the drain metal 18 and the semiconductor material is appropriately increased, which is beneficial to reducing the ohmic contact resistance.

[0087] In one embodiment, please refer to Figure 1 The source metal 17 includes a first part 171 and a second part 172 connected together. The first part 171 protrudes from the surface of the GaN cap layer 14 facing away from the AlGaN layer 13 in the stacking direction. The second part 172 fills the first blind via 151. The first part 171 and the second part 172 are an integral structure. When there are at least two first blind vias 151, there are at least two second parts 172. The number of second parts 172 is the same as the number of first blind vias 151, and the second parts 172 and the first blind vias 151 are arranged in a one-to-one correspondence, so that the source metal 17 can fill all the first blind vias 151, increasing the contact area between the source metal 17 and the semiconductor material, which is beneficial to reducing the ohmic contact resistance.

[0088] In the first direction, the projection of the first part 171 completely covers the projection of the second part 172, ensuring the structural integrity of the first part 171 and the area at the connection between the first part 171 and the second part 172, thus ensuring the conductivity of the first part 171 and the second part 172. Simultaneously, it also facilitates the complete filling of the first blind via 151 by the source metal 17 during the filling process, ensuring the contact area between the source metal 17 and the inner wall of the first blind via 151, thereby reducing ohmic contact resistance. Similarly, the drain metal 18 includes a connected third part and a fourth part. The third part protrudes from the surface of the GaN cap layer 14 facing away from the AlGaN layer 13 in the stacking direction, and the fourth part fills the second blind via 161. The third and fourth parts are an integral structure, and in the first direction, the projection of the third part completely covers the projection of the fourth part.

[0089] This application also provides a method for fabricating a high electron mobility transistor 100, please refer to [link to method]. Figure 4 , Figure 4 A schematic diagram of a system for fabricating a high electron mobility transistor 100 according to an embodiment of this application is shown. The fabrication method of the high electron mobility transistor 100 includes:

[0090] Step S10: Provide a substrate 11, and sequentially form a GaN layer 12, an AlGaN layer 13, and a GaN cap layer 14 on the substrate 11;

[0091] Step S20: Ions are implanted on the surface of the GaN cap layer 14 facing away from the AlGaN layer 13 to form a first ion implantation region 15 and a second ion implantation region 16 spaced apart.

[0092] Step S30: Coating nanospheres 26 in the first ion implantation region 15 and the second ion implantation region 16 to form a mask 28;

[0093] Step S40: Etch the areas of the first ion implantation region 15 and the second ion implantation region 16 other than the mask 28, and form a first blind hole 151 and a second blind hole 161 in the first ion implantation region 15 and the second ion implantation region 16 respectively. The first blind hole 151 and the second blind hole 161 are both partially located in the GaN layer 12.

[0094] Step S50: Fill the first blind via 151 and the second blind via 161 with metallic material to form the source metal 17 and drain metal 18 that are in contact with the GaN layer 12, respectively.

[0095] The method for fabricating a high electron mobility transistor 100 provided in this application involves coating nanospheres 26 in the first ion implantation region 15 and the second ion implantation region 16 to form a mask 28. This method indirectly controls the shape and size of the mask 28 by regulating the nanopatterns formed by the nanospheres 26. Since the areas of the first ion implantation region 15 and the second ion implantation region 16 other than the mask 28 are etched to form a first blind hole 151 and a second blind hole 161, respectively, the shape and size of the first blind hole 151 and the second blind hole 161 are also indirectly controlled by the shape and size of the mask 28. In other words, the shape and size of the first blind hole 151 and the second blind hole 161 can be indirectly controlled by regulating the nanopatterns formed by the nanospheres 26, which is beneficial to improving the controllability of the fabrication process of the high electron mobility transistor 100.

[0096] The source metal 17 and drain metal 18 fill the first blind via 151 and the second blind via 161, respectively. Since the first blind via 151 and the second blind via 161 are etched, their inner walls lack a high-resistivity layer, allowing the source metal 17 and drain metal 18 to directly contact the semiconductor material. This helps reduce the contact resistance between the source metal 17 and the drain metal 18 and the semiconductor material. Simultaneously, both the first blind via 151 and the second blind via 161 are partially located in the GaN layer 12, allowing a portion of the source metal 17 and a portion of the drain metal 18 to contact the GaN layer 12, which has a lower contact barrier. This further helps reduce the contact resistance between the source metal 17 and the drain metal 18 and the semiconductor material. Furthermore, the contact between the source metal 17 and the drain metal 18 and the inner walls of the first blind via 151 and the second blind via 161 increases the contact area between the source metal 17 and the drain metal 18 and the semiconductor material, all of which contribute to reducing ohmic contact resistance and improving the performance of the high electron mobility transistor 100.

[0097] Please see Figure 5 , Figure 5 A cross-sectional structural diagram of the protective layer 21 formed during the HEMT fabrication process according to an embodiment of this application is shown. In step S10, a protective layer 21 can also be formed on the surface of the GaN cap layer 14 facing away from the AlGaN layer 13. That is, GaN layer 12, AlGaN layer 13, GaN cap layer 14 and protective layer 21 are sequentially formed on the substrate 11. The protective layer 21 is used to protect GaN layer 12, AlGaN layer 13 and GaN cap layer 14 during ion implantation. GaN layer 12, AlGaN layer 13, GaN cap layer 14 and protective layer 21 can be sequentially formed on the substrate 11 using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0098] The substrate 11 is made of at least one material selected from Si, SiC, GaN, and sapphire, and the protective layer 21 is made of SiN. x At least one of SiO2, SiN x Including but not limited to Si3N4, Si2N2, SiN, etc. In one embodiment, the thickness of the substrate 11 is 300nm to 1.2μm, the thickness of the GaN layer 12 is 50nm to 500nm, the thickness of the AlGaN layer 13 is 0.1nm to 50nm, the thickness of the GaN cap layer 14 is 0.1nm to 10nm, and the thickness of the protective layer 21 is 10nm to 200nm.

[0099] Please see Figure 6 , Figure 6 This diagram illustrates a cross-sectional structure of the photoresist layer 22 formed during the HEMT fabrication process according to an embodiment of this application. In step S20, before ion implantation on the surface of the GaN cap layer 14 facing away from the AlGaN layer 13, the area to be implanted is first defined by photolithography on the surface of the protective layer 21 facing away from the GaN cap layer 14. That is, the GaN layer 12, AlGaN layer 13, GaN cap layer 14, protective layer 21, and photoresist layer 22 are sequentially formed on the substrate 11. Photoresist is coated on the surface of the protective layer 21 facing away from the GaN cap layer 14, and the area to be implanted is removed, so that the area to be implanted is not coated with photoresist, thus defining the area to be implanted.

[0100] In one embodiment, the step of photolithographically defining the area to be ion implanted on the surface of the protective layer 21 facing away from the GaN cap layer 14 includes: first forming a photoresist layer 22 completely covering the surface of the protective layer 21 facing away from the GaN cap layer 14; then exposing and developing the photoresist layer 22 to locally remove it. The area where the photoresist layer 22 is removed forms a spaced-apart source window region and a drain window region. The photoresist layer 22 can be formed by a coating method, specifically by coating the surface of the protective layer 21 facing away from the GaN cap layer 14 with photoresist and then baking and curing it.

[0101] Please see Figure 7 , Figure 7 This diagram illustrates a cross-sectional structure of the formation of a first ion implantation region 15 and a second ion implantation region 16 during the HEMT fabrication process according to an embodiment of this application. In step S20, ion implantation is performed in a designated ion implantation region to form a first ion implantation region 15 and a second ion implantation region 16 spaced apart. Both the first ion implantation region 15 and the second ion implantation region 16 have a certain depth, such that both the first ion implantation region 15 and the second ion implantation region 16 are located at the GaN layer 12, the AlGaN layer 13, the GaN cap layer 14, and the protective layer 21.

[0102] The implanted ions are selected from at least one of Si ions and Ge ions. In one embodiment, Si ions are used as the implanted ions, the implantation energy is 20 keV to 200 keV, and the implantation dose is 1 × 10⁻⁶. 14 cm -2 ~1×10 16 cm -2 .

[0103] Please see Figure 8 , Figure 8 This diagram illustrates a cross-sectional structure of the annealed dielectric protective layer 25 formed during the HEMT fabrication process according to an embodiment of this application. In step S20, after forming the first ion implantation region 15 and the second ion implantation region 16, the ions at the first ion implantation region 15 and the second ion implantation region 16 are in an inactive state, i.e., the inactive first ion implantation region 23 and the inactive second ion implantation region 24. The inactive first ion implantation region 23 and the inactive second ion implantation region 24 need to be activated under high temperature conditions so that the first ion implantation region 15 and the second ion implantation region 16 form conductive regions. When activating the ions at the first ion implantation region 15 and the second ion implantation region 16, the protective layer 21 and the photoresist are first removed, and then the annealed dielectric protective layer 25 is formed on the surface of the GaN cap layer 14 facing away from the AlGaN layer 13. That is, the GaN layer 12, the AlGaN layer 13, the GaN cap layer 14 and the annealed dielectric protective layer 25 are sequentially formed on the substrate 11, and then the implanted ions are activated by high-temperature annealing. The ions implanted into the first ion implantation region 15 and the second ion implantation region 16 are arranged in a disordered manner. High-temperature annealing can activate the ion rearrangement and repair the lattice damage caused during ion implantation, forming an n-type heavily doped region, which is beneficial to improving the conductivity of the first ion implantation region 15 and the second ion implantation region 16.

[0104] Photoresist can be removed using a photoresist solvent, such as N-methylpyrrolidone (NMP); the protective layer 21 can be removed using a BOE (Buffered Oxide Etchant) solution. The annealing dielectric layer can be formed on the GaN cap layer 14 using chemical vapor deposition, and the material of the annealing dielectric layer is selected from SiN. x At least one of SiO2. In one embodiment, the thickness of the annealing dielectric layer is 10 nm to 200 nm. The high-temperature annealing temperature is 1050 °C to 1300 °C, and N2 is introduced as a protective gas during the annealing process.

[0105] Please see Figure 9 , Figure 9This diagram illustrates a cross-sectional structure of the activated first ion implantation region 15 and second ion implantation region 16 during the HEMT fabrication process according to an embodiment of this application. In step S20, after high-temperature annealing activates the ions in the first ion implantation region 15 and second ion implantation region 16, the annealing dielectric layer is removed, leaving the substrate 11, GaN layer 12, AlGaN layer 13, and GaN cap layer 14. The annealing dielectric layer can be removed using a BOE solution. Depending on the difficulty of removal, the BOE solution can be heated to a certain temperature to improve the removal efficiency.

[0106] Please see Figure 10 , Figure 10 A cross-sectional structural diagram of the coated nanospheres 26 during the HEMT fabrication process provided in this application embodiment is shown. In step S30, before coating the first ion implantation region 15 and the second ion implantation region 16 with nanospheres 26, the first ion implantation region 15 and the second ion implantation region 16 are first defined by photolithography on the surface of the GaN cap layer 14 facing away from the AlGaN layer 13. That is, a photoresist layer 22 is formed again on the side of the GaN cap layer 14 facing away from the AlGaN layer 13, and a portion of the photoresist layer 22 is removed to form a source window region and a drain window region that are spaced apart.

[0107] Nanospheres 26 are then coated in both the first ion implantation region 15 and the second ion implantation region 16. Under the action of van der Waals forces, the nanospheres 26 are connected to the surface of the GaN cap layer 14 facing away from the AlGaN layer 13. That is, GaN layer 12, AlGaN layer 13, GaN cap layer 14, and photoresist layer 22 are sequentially formed on the substrate 11, with the nanospheres 26 located in the area of ​​the photoresist layer 22 where no photoresist is coated. The nanospheres 26 form a single layer in both the first ion implantation region 15 and the second ion implantation region 16, meaning the nanospheres 26 are not stacked in the stacking direction. This simplifies the control of the size of the nanospheres 26, thereby simplifying the control of the opening size of the first blind via 151 and the second blind via 161, and preventing the nanospheres 26 from covering the first ion implantation region 15 and the second ion implantation region 16 too large an area, which would affect the subsequent setting of the source metal 17 and drain metal 18.

[0108] Please see Figure 11 , Figure 11A cross-sectional structural schematic diagram of the HEMT fabrication process for controlling the size of nanospheres 26 provided in this application embodiment is shown. In step S30, after nanospheres 26 are coated in both the first ion implantation region 15 and the second ion implantation region 16, plasma is used to control the size of the nanospheres 26 to reduce their size. In one embodiment, during the plasma-controlled size control of the nanospheres 26, the plasma encapsulates the nanospheres 26 and reacts with the outer surface of the nanospheres 26 to uniformly reduce their size. Because the nanospheres 26 and the surface of the GaN cap layer 14 have van der Waals forces, the nanospheres 26 will not detach from the GaN cap layer 14 during the plasma-controlled size control process, and the nanospheres 26 and the surface of the GaN cap layer 14 remain connected.

[0109] In one embodiment, the diameter of the nanosphere 26 before modulation is 200 nm to 500 μm, and the diameter of the nanosphere 26 after modulation is 50 nm to 500 nm.

[0110] The nanospheres 26 can be made of polystyrene, and the plasma can be at least one of oxygen plasma and fluorine plasma. This helps to ensure that van der Waals forces are formed between the nanospheres 26 and the GaN cap layer 14, making the surfaces of the nanospheres 26 and the GaN cap layer 14 relatively fixed. At the same time, the size of the nanospheres 26 can be controlled directly by the reaction between the plasma and the nanospheres 26, thereby obtaining the desired nanopattern. Compared with the preparation of nanopatterns using a high-precision photolithography machine, this simplifies the process of controlling the size of the nanospheres 26 and helps to save costs.

[0111] In one embodiment, after using plasma to control the size of the nanospheres 26, the projected area of ​​the nanospheres 26 in the first ion implantation region 15 in the stacking direction accounts for 30% to 60% of the projected area of ​​the first ion implantation region 15 in the stacking direction, so that the nanospheres 26 cover 30% to 60% of the area of ​​the first ion implantation region 15. When the number of nanospheres 26 in the first ion implantation region 15 is at least two, the projected area of ​​the nanospheres 26 in the first ion implantation region 15 in the stacking direction is the total projected area of ​​at least two nanospheres 26 in the stacking direction. By making the nanospheres 26 and the first ion implantation region 15 satisfy the above relationship, the size of the opening of the first blind hole 151 is reasonably configured relative to the size of the first ion implantation region 15. The ratio of the area of ​​the opening of the first blind hole 151 to the size of the first ion implantation region 15 is 40% to 70%, which appropriately increases the contact area between the source metal 17 and the semiconductor material and avoids affecting the concentration of the two-dimensional electron gas, which is beneficial to reducing the ohmic contact resistance, as detailed above.

[0112] Similarly, after using plasma to control the size of the nanospheres 26, the projected area of ​​the nanospheres 26 in the stacking direction of the second ion implantation region 16 accounts for 30% to 60% of the projected area of ​​the second ion implantation region 16 in the stacking direction, so that the nanospheres 26 cover 30% to 60% of the area of ​​the second ion implantation region 16. By making the nanospheres 26 and the second ion implantation region 16 satisfy the above relationship, the size of the opening of the second blind hole 161 is reasonably configured relative to the size of the second ion implantation region 16, which appropriately increases the contact area between the drain metal 18 and the semiconductor material, and avoids affecting the concentration of the two-dimensional electron gas, which is beneficial to reducing the ohmic contact resistance.

[0113] Please see Figure 12 , Figure 12 A cross-sectional structural diagram of the metal layer 27 formed during the HEMT fabrication process according to an embodiment of this application is shown. In step S30, after the size of the nanospheres 26 is controlled by plasma, a metal layer 27 is formed on the side of the GaN cap layer 14 facing away from the AlGaN layer 13. The nanospheres 26 in the monolayer nanosphere layer are spaced apart, and the metal layer 27 fills the gaps in the monolayer nanosphere layer, so that the nanospheres 26 are located within the metal layer 27. Since the metal layer 27 is formed integrally on the side of the GaN cap layer 14 facing away from the AlGaN layer 13, a metal layer 27 is also formed on the surface of the photoresist layer 22 facing away from the GaN cap layer 14.

[0114] The material of the metal layer 27 is selected from at least one of Ni, Pt, Cr, Pd, and Mo metals. In one embodiment, the thickness of the metal layer 27 is 200 nm to 500 nm.

[0115] Please see Figure 13 , Figure 13 This diagram shows a cross-sectional structure after removing the nanospheres 26 during the HEMT fabrication process according to an embodiment of this application. In step S30, after forming a metal layer 27 on the side of the GaN cap layer 14 opposite to the AlGaN layer 13, the nanospheres 26 are removed by cleaning with a first solvent, resulting in gaps forming in the regions of the metal layer 27 in the first ion implantation region 15 and the second ion implantation region 16 where the nanospheres 26 were originally located.

[0116] By forming a metal layer 27 on the side of the GaN cap layer 14 facing away from the AlGaN layer 13, the nanospheres 26 can be easily removed from the metal layer 27 due to the difference in polarity between the metal layer 27 and the nanospheres 26, thus defining the original region of the nanospheres 26 and facilitating the acquisition of the desired nanopattern. If a mask 28 is formed directly on the side of the GaN cap layer 14 facing away from the AlGaN layer 13, filling the gaps in the monolayer nanospheres, the similar polarity of the mask 28 and nanospheres 26 makes it difficult to remove the nanospheres 26 from the mask 28, thus failing to obtain the desired nanopattern. Furthermore, the growth temperature of the mask 28 is relatively high; directly growing the mask 28 to fill the gaps in the monolayer nanospheres would affect the integrity of the nanospheres 26's shape. The metal layer 27, however, has a lower growth temperature and can be grown at room temperature. Growing the metal layer 27 within the nanosphere layer helps ensure the integrity of the nanospheres 26's shape.

[0117] The first solvent is selected from at least one of acetone, toluene, ethanol, isopropanol, ethyl acetate, and chloroform.

[0118] Please see Figure 14 , Figure 14 This diagram illustrates a cross-sectional structure after removing the photoresist layer 22 during the HEMT fabrication process according to an embodiment of this application. In step S30, after removing the nanospheres 26 using a first solvent, the photoresist layer 22 is removed, causing the metal layer 27 facing away from the GaN cap layer 14 to be removed as well. That is, a GaN layer 12, an AlGaN layer 13, a GaN cap layer 14, and a metal layer 27 are sequentially formed on the substrate 11. The metal layer 27 is located in the first ion implantation region 15 and the second ion implantation region 16. The photoresist layer 22 can be removed using at least one of acetone, toluene, ethanol, isopropanol, ethyl acetate, and chloroform.

[0119] In one embodiment, the metal layer 27 forms a first metal protrusion 271 in the first ion implantation region 15, and a second metal protrusion 272 in the second ion implantation region 16. Both the first metal protrusion 271 and the second metal protrusion 272 protrude from the surface of the GaN cap layer 14 facing away from the AlGaN layer 13.

[0120] Please see Figure 15 , Figure 15This diagram illustrates a cross-sectional structure of the mask 28 formed during the HEMT fabrication process according to an embodiment of this application. In step S30, after removing the photoresist layer 22, a mask 28 is formed on the surface of the GaN cap layer 14 facing away from the AlGaN layer 13. The mask 28 fills the gaps in the metal layer 27 at the first ion implantation region 15 and the second ion implantation region 16, such that the mask 28 surrounds the first metal protrusion 271 and the second metal protrusion 272 of the metal layer 27. Since the gaps in the metal layer 27 were originally areas where nanospheres 26 were disposed, the mask 28 replaces the positions of the nanospheres 26.

[0121] The material of the mask 28 is selected from at least one of SiO2 and Si3N4. In one embodiment, the thickness of the mask 28 is 20 nm to 100 nm.

[0122] Please see Figure 16 , Figure 16 This diagram illustrates a cross-sectional structure of the HEMT fabrication process provided in this application, where the metal layer 27 is removed to form the first blind via 151 and the second blind via 161. In step S40, before etching the areas of the first ion implantation region 15 and the second ion implantation region 16 other than the mask 28, the metal layer 27 is removed by cleaning with a second solvent, resulting in gaps in the areas of the mask 28 where the metal layer 27 was originally located.

[0123] By forming a mask 28 on the surface of the GaN cap layer 14 facing away from the AlGaN layer 13, and utilizing the difference in polarity between the mask 28 material and the metal layer 27 material, the metal layer 27 can be successfully removed from the mask 28, defining the original region of the metal layer 27. This facilitates the definition of nanopatterns by nanospheres 26, the reservation of nanopatterns by the metal layer 27, and the redefinition of nanopatterns by the mask 28. In other words, the mask 28 replaces the region of the nanospheres 26. The gap between the masks 28 is the region of the first blind hole 151 or the second blind hole 161, thereby enabling the control of the shape and size of the first blind hole 151 and the second blind hole 161.

[0124] The material of the second solvent is selected from at least one of hydrochloric acid and hydrogen peroxide. By removing the metal layer 27 with the second solvent, gaps are formed in the area of ​​the mask 28 where the metal layer 27 was originally located, leaving an etching area to facilitate the formation of the first blind hole 151 and the second blind hole 161 in the first ion implantation region 15 and the second ion implantation region 16, respectively.

[0125] The areas of the first ion implantation region 15 and the second ion implantation region 16 other than the mask 28 are etched to form a first blind via 151 and a second blind via 161 in the first ion implantation region 15 and the second ion implantation region 16, respectively. Both the first blind via 151 and the second blind via 161 are partially located in the GaN layer 12.

[0126] In one embodiment, chlorine plasma is used to etch the semiconductor material, with an etching depth of 30nm to 50nm, an etching rate of 15nm / min, and an etching time of 2min to 3min20s.

[0127] Please see Figures 11 to 16 The first metal protrusion 271 corresponds to the first blind hole 151, and the second metal protrusion 272 corresponds to the second blind hole 161. That is, the positions of the first metal protrusion 271 and the first blind hole 151 are opposite and equal in number, and the positions of the second metal protrusion 272 and the second blind hole 161 are opposite and equal in number. The nanospheres 26 in the first ion implantation region 15 correspond to the solid region surrounding the first blind hole 151, and the nanospheres 26 in the second ion implantation region 16 correspond to the solid region surrounding the second blind hole 161. By controlling the shape of the nanospheres 26 in the first ion implantation region 15 or the second ion implantation region 16, the shape, size, and number of the first metal protrusion 271 or the second metal protrusion 272 can be controlled, thereby indirectly controlling the shape, size, and number of the first blind hole 151 or the second blind hole 161.

[0128] In one embodiment, the number of first metal protrusions 271 is at least two, such that the number of first blind vias 151 formed by subsequent processes in the fabrication method of the high electron mobility transistor is at least two. Increasing the number of first blind vias 151 helps to increase the total area of ​​the inner wall of the first blind vias 151, thereby increasing the contact area between the source metal 17 and the inner wall of the first blind vias 151. The at least two first metal protrusions 271 can be spaced apart, such that the at least two first blind vias 151 are spaced apart, which helps to increase the specific surface area of ​​the inner wall of the at least two first blind vias 151, thereby increasing the contact area between the source metal 17 and the inner wall of the first blind vias 151 and reducing the ohmic contact resistance.

[0129] Similarly, the number of second metal protrusions 272 is at least two, so that the number of second blind vias 161 formed by subsequent processes in the fabrication method of the high electron mobility transistor is at least two. Increasing the number of second blind vias 161 increases the total area of ​​the inner walls of the second blind vias 161, thereby increasing the contact area between the drain metal 18 and the inner walls of the second blind vias 161. The at least two second metal protrusions 272 can be spaced apart, so that the at least two second blind vias 161 are spaced apart, which increases the specific surface area of ​​the inner walls of the at least two second blind vias 161, thereby increasing the contact area between the drain metal 18 and the second blind vias 161 and reducing ohmic contact resistance.

[0130] Please see Figure 2 , Figure 2This diagram shows a cross-sectional view of the high electron mobility transistor 100 provided in this embodiment of the invention, without the source metal 17 and drain metal 18. In step S50, before filling the first blind via 151 and the second blind via 161 with metal material, the mask 28 is removed by cleaning with a third solvent before the source metal 17 and drain metal 18 are formed. The third solvent can be a BOE solution.

[0131] Please see Figure 1 , Figure 1 A cross-sectional structural schematic diagram of a high electron mobility transistor 100 provided in an embodiment of this application is shown. Metal materials are filled into the first blind via 151 and the second blind via 161 to form source metal 17 and drain metal 18, respectively, which are in contact with the GaN layer 12. The metal materials are in direct contact with the GaN layer 12.

[0132] In one embodiment, the metal material is a multilayer metal stack structure with Ti as the substrate, that is, Ti is in direct contact with the GaN layer 12. The multilayer metal stack structure can be Ti / Pt / Au, with the thickness of the first Ti layer being 20-100 nm, the thickness of the second Pt layer being 30-200 nm, and the thickness of the third Au layer being 50-500 nm.

[0133] This application also provides a power amplifier 200, please refer to [reference needed]. Figure 17 , Figure 17 A partial schematic diagram of a power amplifier 200 provided in an embodiment of this application is shown. The power amplifier 200 includes the high electron mobility transistor 100 described above or the high electron mobility transistor 100 fabricated by the above-described method, and other electronic components, including resistors, inductors, capacitors, etc.

[0134] In this embodiment, the source 170 of the high electron mobility transistor 100 is grounded, the gate 190 of the high electron mobility transistor 100 is electrically connected to the input matching network 202, and the drain 180 of the high electron mobility transistor 100 is electrically connected to the compensator 201. The compensator 201 includes a plurality of first resistors 203 connected in series, and the input matching network 202 includes a plurality of second resistors 204 connected in series. It is understood that the power amplifier 200 is not limited to... Figure 17 As shown, the design and adjustment can be made according to the needs of the circuit design. The electronic components connected to the gate 190 and drain 180 of the high electron mobility transistor 100 can also be designed and adjusted accordingly according to the circuit design.

[0135] It is understood that the power amplifier 200 in this embodiment has the high electron mobility transistor in the above embodiments. Therefore, the power amplifier 200 in this embodiment has all the technical effects of the high electron mobility transistor in the above embodiments. Since the technical effects of the high electron mobility transistor have been fully explained in the above embodiments, they will not be repeated here.

[0136] This application also provides a power switch 300, please refer to [link to relevant documentation]. Figure 18 , Figure 18 A partial schematic diagram of a power switch 300 provided in an embodiment of this application is shown. The power switch 300 includes the high electron mobility transistor 100 described above or the high electron mobility transistor 100 prepared by the above-described method, and other electronic components, including a power supply 303, an inductor 302, a diode 301, etc.

[0137] In this embodiment, the source 170 of the high electron mobility transistor 100 is grounded, the gate 190 of the high electron mobility transistor 100 is electrically connected to the diode 301 and the inductor 302, and the drain 180 of the high electron mobility transistor 100 is connected to the power supply 303. It is understood that the power switch 300 is not limited to... Figure 18 As shown, the design and adjustment can be made according to the needs of the circuit design. The electronic components connected to the gate 190 and drain 180 of the high electron mobility transistor 100 can also be designed and adjusted accordingly according to the circuit design.

[0138] It is understood that the power switch 300 in this embodiment has the high electron mobility transistor in the above embodiments. Therefore, the power switch 300 in this embodiment has all the technical effects of the high electron mobility transistor in the above embodiments. Since the technical effects of the high electron mobility transistor have been fully explained in the above embodiments, they will not be repeated here.

[0139] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A high electron mobility transistor, characterized in that, It includes a substrate, a GaN layer, an AlGaN layer, and a GaN cap layer that are stacked and connected in sequence; The surface of the GaN cap layer facing away from the AlGaN layer has a first ion implantation region and a second ion implantation region spaced apart. The first ion implantation region and the second ion implantation region each have a first blind hole and a second blind hole. The first blind hole and the second blind hole both extend along a first direction opposite to the stacking direction. The first blind hole and the second blind hole are both partially located in the GaN layer. The high electron mobility transistor further includes a source metal and a drain metal located in the first ion implantation region and the second ion implantation region, respectively. The source metal and the drain metal fill the first blind via and the second blind via, respectively, and are both in contact with the GaN layer.

2. The high electron mobility transistor according to claim 1, characterized in that, The bottom walls of both the first blind hole and the second blind hole are located in the GaN layer.

3. The high electron mobility transistor according to claim 2, characterized in that, The ratio of the depth of the first blind via or the second blind via in the GaN layer to the thickness of the GaN layer is 2% to 90%.

4. The high electron mobility transistor according to any one of claims 1 to 3, characterized in that, Both the first ion implantation region and the second ion implantation region extend from the GaN cap layer toward the first direction. In the first direction, the depth of the first ion implantation region is greater than the depth of the first blind via, and the depth of the second ion implantation region is greater than the depth of the second blind via.

5. The high electron mobility transistor according to any one of claims 1 to 4, characterized in that, The number of the first blind holes is at least two, and the at least two first blind holes are spaced apart.

6. The high electron mobility transistor according to any one of claims 1 to 5, characterized in that, The ratio of the total area of ​​the first blind hole opening to the projected area of ​​the first ion implantation region in the first direction is 40% to 70%.

7. The high electron mobility transistor according to any one of claims 1 to 6, characterized in that, The source metal includes a first part and a second part connected together. The first part protrudes from the surface of the GaN cap layer opposite to the AlGaN layer in the stacking direction. The second part fills the first blind via. In the first direction, the projection of the first part completely covers the projection of the second part.

8. A method for fabricating a high electron mobility transistor, characterized in that, include: A substrate is provided on which a GaN layer, an AlGaN layer, and a GaN cap layer are sequentially formed. Ions are implanted into the surface of the GaN cap layer facing away from the AlGaN layer to form a first ion implantation region and a second ion implantation region that are spaced apart. Nanospheres are coated in the first ion implantation region and the second ion implantation region to form a mask; Etch the areas of the first ion implantation region and the second ion implantation region other than the mask, and form a first blind hole and a second blind hole in the first ion implantation region and the second ion implantation region, respectively. Both the first blind hole and the second blind hole are partially located in the GaN layer. Metal materials are filled into the first and second blind vias to form source metal and drain metal that are in contact with the GaN layer, respectively.

9. The method for fabricating a high electron mobility transistor according to claim 8, characterized in that, After the nanospheres are coated in both the first ion implantation region and the second ion implantation region, the nanospheres are connected to the GaN cap layer, and a monolayer nanosphere layer is formed in both the first ion implantation region and the second ion implantation region.

10. The method for fabricating a high electron mobility transistor according to claim 9, characterized in that, After coating both the first ion implantation region and the second ion implantation region with the nanospheres, the size of the nanospheres is controlled by plasma, and the nanospheres cover 30% to 60% of the area of ​​the first ion implantation region or the second ion implantation region.

11. The method for fabricating a high electron mobility transistor according to claim 9 or 10, characterized in that, The step of forming the mask includes: after forming the monolayer nanosphere layer in both the first ion implantation region and the second ion implantation region, depositing a layer of the mask on the surface of the GaN cap layer opposite to the AlGaN layer to replace the nanospheres in the monolayer nanosphere layer.

12. The method for fabricating a high electron mobility transistor according to claim 11, characterized in that, The step of forming the mask further includes: after forming the monolayer nanosphere layer in both the first ion implantation region and the second ion implantation region, first forming a metal layer on the side of the GaN cap layer facing away from the AlGaN layer to fill the gaps in the monolayer nanosphere layer, then cleaning the nanospheres with a first solvent to remove them, so that the metal layers in the first ion implantation region and the second ion implantation region form gaps, and then forming the mask on the surface of the GaN cap layer facing away from the AlGaN layer to fill the gaps in the metal layer, so as to realize the replacement of the nanospheres by the mask.

13. The method for fabricating a high electron mobility transistor according to claim 12, characterized in that, After depositing a mask layer on the surface of the GaN cap layer opposite to the AlGaN layer to fill the gaps in the metal layer, the metal layer is removed by cleaning with a second solvent.

14. The method for fabricating a high electron mobility transistor according to claim 12 or 13, characterized in that, The metal layer forms a first metal protrusion in the first ion implantation region and a second metal protrusion in the second ion implantation region. The first metal protrusion corresponds to the first blind hole, and the second metal protrusion corresponds to the second blind hole. The number of the first metal protrusion and / or the second metal protrusion is at least two.

15. The method for fabricating a high electron mobility transistor according to claim 14, characterized in that, At least two of the first metal protrusions are spaced apart, and / or at least two of the second metal protrusions are spaced apart.

16. A power amplifier, characterized in that, The high electron mobility transistor includes the high electron mobility transistor according to any one of claims 1 to 7 or the high electron mobility transistor prepared by any one of claims 8 to 15 and other electronic components, wherein the source of the high electron mobility transistor is grounded, the drain is connected to one of the electronic components, and the gate is connected to another of the electronic components.

17. A power switch, characterized in that, The high electron mobility transistor includes the high electron mobility transistor according to any one of claims 1 to 7 or the high electron mobility transistor prepared by any one of claims 8 to 15 and other electronic components, wherein the source of the high electron mobility transistor is grounded, the drain is connected to one of the electronic components, and the gate is connected to another of the electronic components.

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