一种带宽自适应的树形分层总线仲裁器和总线仲裁方法
By employing a three-level hybrid arbitration architecture and a dynamic latch controller, the problems of insufficient arbitration accuracy and poor latency scalability in large-scale integrated circuits are solved, achieving high-precision bandwidth allocation and low-latency bus arbitration, which is suitable for multi-core system chips and on-chip networks.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2025-09-18
- Publication Date
- 2026-07-17
AI Technical Summary
Existing technologies in large-scale integrated circuits suffer from imbalances in arbitration accuracy and bandwidth allocation, scalability bottlenecks and latency degradation, and fairness issues under non-uniform requests. In particular, it is difficult to achieve high-precision bandwidth allocation and low-latency expansion of large-scale ports in multi-core system chips and on-chip networks.
A three-level hybrid arbitration architecture is adopted, including two-level arbitration units at the leaf node level, a parallel prefix arbitrator at the intermediate node level, and a dynamic latch controller at the root node level. Through fixed priority pre-selection, bandwidth ratio polling, and Lock signal feedback mechanisms, the authorization ratio and state freezing of the request source are dynamically adjusted to optimize arbitration latency.
It achieves high-precision bandwidth allocation, reduces arbitration latency, supports large-scale port expansion, eliminates deadlock risk, and ensures stable system operation under non-uniform requests.
Smart Images
Figure CN120892369B_ABST