Display device

Abstract

The application provides a display device, wherein a first gate drive circuit and a second gate drive circuit of the same stage respectively transmit two first gate signals to two rows of pixels through two first gate lines, and the two first gate drive circuit and the second gate drive circuit respectively transmit a second gate signal and a third gate signal to the same row of pixels through a second gate line and a third gate line, a first output module in the two first gate drive circuit and the second gate drive circuit is used for generating a first gate signal of the current stage according to a signal of a third node of the current stage, the amplitude of the signal of the third node is a first amplitude, a second amplitude and the first amplitude in sequence, and the absolute value of the difference between the time length for the amplitude of the signal of the third node changing from the first amplitude to the second amplitude is less than 0.5xH, 1H is the time length for scanning one row of pixels, and the transverse dense horizontal lines of the display picture are improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] In medium-sized display panels, the CMOS (Complementary Metal-Oxide-Semiconductor) gate drive circuit, in order to balance large driving capability and small bezel width, outputs two different gate signals to different transistors in the same row of pixel circuits for odd-numbered and even-numbered gate drive circuits. It also outputs two other gate signals to the data write transistors in both the odd-numbered and even-numbered pixel circuits. Because the controlled signals of the odd-numbered and even-numbered gate drive circuits differ significantly, the write potentials of the nodes used to control the drive current differ between the two circuits. This results in differences in the magnitude of the drive current generated by the odd-numbered and even-numbered pixel circuits, leading to dense horizontal stripes on the display screen. Summary of the Invention

[0003] Embodiments of the present invention provide a display device for improving the phenomenon of dense horizontal stripes in the display image of a medium-sized display panel.

[0004] An embodiment of the present invention provides a display device, including multiple pixel groups, multiple first gate lines, multiple second gate lines, multiple third gate lines, cascaded multi-stage first gate driving circuits and cascaded multi-stage second gate driving circuits, wherein the pixel group includes a row of pixels;

[0005] The first gate driving circuit transmits a corresponding first gate signal to a pixel group through a first gate line, and the second gate driving circuit at the same level transmits another corresponding first gate signal to another pixel group through another first gate line.

[0006] The first gate driving circuit transmits a corresponding second gate signal to the pixel group through a second gate line, and the second gate driving circuit at the same level transmits a corresponding third gate signal to the same pixel group through the third gate line.

[0007] Both the first gate driving circuit and the second gate driving circuit include a first output module. The first output module is used to generate the first gate signal of the current stage based on the signal of the third node of the current stage. The amplitude of the signal of the third node of the current stage is, in sequence, a first amplitude, a second amplitude, and a first amplitude. One of the first amplitude and the second amplitude is the maximum amplitude of the signal of the third node, and the other is the minimum amplitude of the signal of the third node.

[0008] Wherein, the absolute value of the difference between the third time interval during which the amplitude of the signal at the third node of the first gate driving circuit changes from the first amplitude to the second amplitude, and the fourth time interval during which the amplitude of the signal at the third node of the second gate driving circuit changes from the first amplitude to the second amplitude, is less than 0.5×H, and 1H is the duration of scanning one pixel group.

[0009] In the display device provided in the embodiments of the present invention, the first output module in the first and second gate driving circuits of the display device is used to generate the first gate signal of the current level according to the signal of the third node of the current level, and the amplitude of the signal of the third node of the current level is sequentially a first amplitude, a second amplitude, and a first amplitude. One of the first amplitude and the second amplitude is the maximum amplitude of the signal of the third node, and the other is the minimum amplitude of the signal of the third node. By setting the absolute value of the difference between the amplitude of the signal of the third node changing from the first amplitude to the second amplitude to less than 0.5×H, where 1H is the scanning time of the pixel group, the phenomenon of dense horizontal stripes in the display screen is improved. Attached Figure Description

[0010] Figure 1 , Figure 13 This is a schematic diagram of the driving architecture of a display device provided in an embodiment of the present invention.

[0011] Figure 2 This is a timing diagram of the two first gate signals generated by the first gate driving circuit and the second gate driving circuit of the nth stage provided in the embodiment of the present invention.

[0012] Figure 3 This is a circuit diagram of the light-emitting element and pixel circuit provided in an embodiment of the present invention.

[0013] Figure 4 This is a timing diagram of the two first gate signals generated by the first gate driving circuit and the second gate driving circuit of the nth stage provided in the comparative example of the present invention.

[0014] Figure 5This is a circuit diagram provided by an embodiment of the present invention, applicable to a first gate driving circuit and a second gate driving circuit.

[0015] Figure 6 , Figure 10 This is a timing diagram of some nodes and signals in the first gate driving circuit and the second gate driving circuit of the nth stage provided in the embodiments of the present invention.

[0016] Figure 7 , Figure 9 This is a timing diagram of some nodes and signals in the first gate driving circuit and the second gate driving circuit of the nth stage provided as a comparative example of the present invention.

[0017] Figure 8 , Figure 12 This is a timing diagram of some signals in the multi-stage first gate driving circuit and second gate driving circuit provided in the embodiments of the present invention.

[0018] Figure 11 This is a timing diagram of some signals controlling the first and second pixel groups provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention.

[0020] The embodiments of the present invention provide a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0021] In some embodiments, such as Figure 1As shown, the display device 100 includes multiple pixel groups 10, multiple first gate lines G1, multiple second gate lines G2, multiple third gate lines G3, cascaded multi-stage first gate driving circuits CMOS_T3 and cascaded multi-stage second gate driving circuits CMOS_T4. Each pixel group includes a row of pixels Pi. The multi-stage first gate driving circuits CMOS_T3 transmit a portion of the corresponding first gate signal Pscan to a portion of the pixel groups 101 through a portion of the first gate lines G1. The multi-stage second gate driving circuits CMOS_T4 transmit another portion of the corresponding first gate signal Pscan to another portion of the pixel groups 101 through another portion of the first gate lines G1. The first gate driving circuits CMOS_T3 transmit corresponding second gate signals Nscan_T3 and corresponding third gate signals Nscan_T4 to the pixel groups 101 through a second gate line G2 and through the third gate line G3, respectively.

[0022] Specifically, the first gate driving circuit CMOS_T3 transmits a corresponding first gate signal Pscan to a pixel group 101 through a first gate line G1, and the second gate driving circuit CMOS_T4 at the same level transmits another corresponding first gate signal Pscan to another pixel group 101 through another first gate line G1.

[0023] Among them, combined Figure 1 , Figure 5 and Figure 6As shown, this example uses the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the nth stage. Both include a control module 201. The input terminal of the control module 201 in the first gate driving circuit CMOS_T3 is electrically connected to the first frame start line STV1 or the first node P[n-1] of the previous stage first gate driving circuit CMOS_T3. The input terminal of the control module 201 in the second gate driving circuit CMOS_T4 is electrically connected to the second frame start line STV2 or the first node P[n-1] of the previous stage second gate driving circuit CMOS_T4. The control terminal of the control module 201 is electrically connected to the corresponding first clock line ECK. The control module 201 is used to determine the first frame start signal stv1 transmitted by the first frame start line STV1, the second frame start signal stv2 transmitted by the second frame start line STV2, and the control module 201 based on ... The signal p[n-1] of the first node P[n-1] of the previous stage and the first clock signal eck transmitted by the corresponding first clock line control the signal of the second node K[n] of this stage; the first output module 202, the control terminal of the first output module 202 is electrically connected to the second node K[n], and the input terminal of the first output module 202 is electrically connected to the corresponding second clock line PCK. The first output module 202 is used to control the amplitude of the signal q[n] of the third node Q of this stage to be the first amplitude a1, the second amplitude a2, and the first amplitude a1 in sequence according to the signal of the second node K[n] and the second clock signal pck transmitted by the corresponding second clock line PCK, and is used to generate the corresponding first gate signal Pscan (Pscan[n_1] or Pscan[n_2]) according to the signal of the third node Q and the second clock signal pck.

[0024] Wherein, one of the first amplitude a1 and the second amplitude a2 is the maximum amplitude of the signal q[n] of the third node Q, and the other is the minimum amplitude of the signal q[n] of the third node Q.

[0025] Specifically, both the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 include a control module 201 and a first output module 202, the difference being:

[0026] The input terminal of the control module 201 in the first gate driving circuit CMOS_T3 is electrically connected to the first frame start line STV1 or the first node of the previous stage first gate driving circuit CMOS_T3, so that the control module 201 can control the signal of the second node K[n] of this stage according to one of the first frame start signal stv1 transmitted by the first frame start line STV1, the signal p[n-1] of the corresponding first node P[n-1] of the previous stage, and the corresponding first clock signal eck;

[0027] The input terminal of the control module 201 in the second gate drive circuit CMOS_T4 is electrically connected to the second frame start line STV2 or the first node of the previous stage second gate drive circuit CMOS_T4, so that the control module 201 can control the signal of the second node K[n] of this stage according to one of the second frame start signal stv2 transmitted by the second frame start line STV2, the signal p[n-1] of the corresponding first node P[n-1] of the previous stage, and the corresponding first clock signal eck.

[0028] Wherein, the first frame start signal stv1 corresponding to the first gate driving circuit CMOS_T3 is different from the second frame start signal stv2 corresponding to the second gate driving circuit CMOS_T4, and the signal p[n] of the first node P[n] of the first gate driving circuit CMOS_T3 is different from the signal p[n] of the first node P[n] of the second gate driving circuit CMOS_T4 at the same level.

[0029] That is, the degree of difference between the signals of the second node K[n] in the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the same level is controlled by the degree of difference between the first frame start signal stv1 and the second frame start signal stv2 (which is the same as the degree of difference between the signals p[n-1] of the first node P[n-1] of the previous level of both), and is also controlled by the degree of difference between the corresponding two first clock signals eck.

[0030] Furthermore, the degree of difference in the signal of the second node K[n] in the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the same level, and the degree of difference in the corresponding two second clock signals pck, jointly control the degree of difference in the signal q[n] of the third node Q in the two. For example, it can control the degree of difference in the duration of at least one of the first amplitude a1 and the second amplitude a2 in the signal q[n] of the third node Q in the two.

[0031] Furthermore, the degree of difference between the signal q[n] of the third node Q in the first gate drive circuit CMOS_T3 and the second gate drive circuit CMOS_T4 of the same level, and the degree of difference between the corresponding two second clock signals pck, jointly control the degree of difference between the first gate signals Pscan[n_1] and Pscan[n_2] generated by the two respectively.

[0032] Among them, such as Figure 6 As shown, one of the first amplitude a1 and the second amplitude a2 is the maximum amplitude of the signal q[n] of the third node Q, and the other is the minimum amplitude of the signal q[n] of the third node Q. The absolute value of the difference between the third time t3 during which the amplitude of the signal q[n] of the third node Q of the first gate driving circuit CMOS_T3 changes from the first amplitude a1 to the second amplitude a2, and the fourth time t4 during which the amplitude of the signal q[n] of the third node Q of the second gate driving circuit CMOS_T4 changes from the first amplitude a1 to the second amplitude a2 is less than 0.5 × H, where 1H is the duration of scanning one pixel group 101. Specifically, 1H can be equal to 1 / [refresh rate × total number of vertical lines]. The total number of vertical lines can be equal to the sum of the number of effective display lines and the number of lines in the vertical blanking period. The total number of vertical lines can be greater than or equal to the number of pixel groups 101 mentioned above.

[0033] Furthermore, the absolute value of the difference between the third duration t3 and the fourth duration t4 is less than 0.2 × H. That is, the duration during which the amplitude of the signal q[n] of the third node of the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 changes from the first amplitude a1 to the second amplitude a2 is closer.

[0034] It is important to note that, such as Figure 7 As shown, in the comparative example, the absolute value of the difference between the third comparison time t3' and the fourth comparison time t4' of the signal q'[n] of the third node Q[n] in the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the nth stage is relatively large, causing the following... Figure 4 As shown, the difference in the "fall duration" of the two first contrast gate pulses p1' corresponding to the first contrast gate signals Pscan'[n_1] and Pscan'[n_2] generated by the two is large, resulting in dense horizontal stripes on the display screen.

[0035] Understandable, such as Figure 6As shown, this embodiment adjusts the duration of at least one of the signals controlled by at least one of the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 (which can be at least one of the first frame start signal stv1, the second frame start signal stv2, the corresponding two first clock signals eck, and the corresponding two second clock signals pck) by comparing and contrasting them. This adjustment allows for the adjustment of the duration of at least one of the first amplitude a1 and the second amplitude a2 in the signal q[n] of the third node Q in one of the two circuits, so that the amplitude of the signal q[n] of the third node Q changes from the first amplitude a1 to the second amplitude a2. The absolute value of the difference between the third duration t3 and the fourth duration t4 (defined as the charging duration of the third node Q) is less than 0.5×H, or even less than 0.2×H. That is, the difference in the charging duration of the third node Q between the two is small. Consequently, the first gate pulse p1 in the first gate signal Pscan[n_1] and the first gate signal Pscan[n_2] generated by the two can achieve a small absolute value of the difference between the first duration t1 and the second duration t2 occupied by the rising or falling edge from the start time. This reduces the difference in the degree of influence on the control of the corresponding nodes in the pixel circuit 102 of the pixel group 10 driven by each, thereby improving the horizontal dense horizontal stripe phenomenon of the display screen.

[0036] For example, combining Figure 2 As shown in Table 1, the absolute value of the difference between the first duration t1, which is the rising or falling edge of the first gate pulse p1 in the first gate signal Pscan generated by the first gate driving circuit CMOS_T3 from the start time, and the second duration t2, which is the rising or falling edge of the first gate pulse p1 in the first gate signal Pscan generated by the second gate driving circuit CMOS_T4 from the start time, is less than or equal to 10 nanoseconds. Furthermore, the absolute value of the difference between the first duration t1 and the second duration t2 can be less than or equal to 5 nanoseconds.

[0037] Table 1

[0038]

[0039] Among them, such as Figure 1 As shown, for ease of description, this embodiment uses an array of multiple pixels Pi as an example. The aforementioned pixel group 10 may include multiple pixels Pi in the same row, so it can be considered that the multiple pixel groups 10 are arranged along the row direction. Figure 3As shown, pixel Pi may include an electrically connected light-emitting element Di and pixel circuit 102. The gates of multiple transistors in pixel circuit 102 may be controlled by at least the first gate signal Pscan, the second gate signal Nscan_T3 and the third gate signal Nscan_T4, respectively, so as to control the conduction period of multiple transistors in pixel circuit 102 under the control of at least the above three gate signals, thereby generating a driving current flowing through light-emitting element Di, thereby driving light-emitting element Di to emit light.

[0040] As discussed above, in this embodiment, the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 respectively drive at least one pixel group 101 to transmit the corresponding two first gate signals Pscan through the corresponding two first gate lines G1. For ease of description, as follows... Figure 1 As shown, this example illustrates the following: the number of first gate driving circuits CMOS_T3 is equal to the number of second gate driving circuits CMOS_T4, and the multi-level first gate driving circuits CMOS_T3 transmit the corresponding multi-level first gate signal Pscan to one of the pixel groups 10 in all odd-numbered rows and the pixel groups 10 in all even-numbered rows, while the multi-level second gate driving circuits CMOS_T4 transmit the corresponding multi-level first gate signal Pscan to the other of the pixel groups 10 in all odd-numbered rows and the pixel groups 10 in all even-numbered rows.

[0041] It is important to note that, such as Figure 1 As shown, since the first gate driving circuit CMOS_T3 also generates a second gate signal Nscan_T3 transmitted to one type of transistor in the pixel group 101 through the second gate line G2, and the second gate driving circuit CMOS_T4 also generates a third gate signal Nscan_T4 transmitted to another type of transistor in the same pixel group 101 through the third gate line G3, since the second gate signals Nscan_T3 and CMOS_T4 required by the two types of transistors in the same pixel circuit 102 are different, if no interference is applied, this will cause the two first gate signals Pscan generated by the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 at the same level to act on two different pixel groups 101 to be different.

[0042] Specifically, combined Figure 4As shown in Table 2, in the comparative example, the first comparison gate signals Pscan' (corresponding to the first gate signal Pscan in the embodiment) generated by the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the same level (e.g., the nth level, where n is a positive integer) are applied to the pixel group 10 of the odd-numbered row and the pixel group 10 of the corresponding even-numbered row, respectively. The corresponding first comparison gate signals Pscan'[n_1] and Pscan'[n_2] are applied to the pixel group 10 of the 2n-1th row and the pixel group 10 of the 2nth row, respectively. Here, the effective potential of the first comparison gate pulse p1' (corresponding to the first gate pulse p1 in the embodiment) in the first comparison gate signal Pscan' is taken as the corresponding low potential.

[0043] Based on the above analysis, it can be seen that the first comparison gate signals Pscan'[n_1] and Pscan'[n_2] generated by the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 in the nth stage of the comparative example are different. Specifically, the difference can be reflected in the significant difference between the first comparison duration t1' and the second comparison duration t2' (collectively referred to as "fall duration") occupied by the falling edge of the two corresponding first comparison gate pulses p1' from the start time. For example, they are 597 nanoseconds and 553 nanoseconds respectively, with a difference of 44 nanoseconds. Under the same conditions, this will cause different degrees of influence on the control of the corresponding nodes in the pixel circuit 102 of the pixel group 10 driven by each, resulting in dense horizontal stripes on the display screen.

[0044] Table 2

[0045]

[0046] Specifically, in this embodiment, taking the two first gate signals Pscan generated by the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the same level as acting on the pixel group 10 of the even-numbered row and the corresponding pixel group 10 of the odd-numbered row as an example, that is, the first gate signals Pscan[1_2] and Pscan[1_1] generated by the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the first level act on the pixel group 10 of the second row and the pixel group 10 of the first row, respectively. The first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 generate the first gate signal Pscan[2_2] and the first gate signal Pscan[2_1], respectively, which are applied to the pixel group 10 in the 4th row and the pixel group 10 in the 3rd row. The first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 generate the first gate signal Pscan[n_2] and the first gate signal Pscan[n_1], respectively, which are applied to the pixel group 10 in the 2nth row and the pixel group 10 in the 2n-1th row.

[0047] Understandable, combined Figure 2 As shown in Table 1, in this invention, by appropriately adjusting the proportions of at least one signal controlled by at least one of the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 at the same level, the waveform of the first gate signal Pscan generated by one of them can be adjusted. Specifically, the duration occupied by the rising or falling edge of the first gate pulse p1 from the start time is adjusted, so that the absolute value of the difference between the first duration t1 and the second duration t2 occupied by the rising or falling edge of the first gate pulse p1 in the corresponding two first gate signals Pscan is less than or equal to 5 nanoseconds. (For example, the four "fall durations" corresponding to the first gate signal Pscan[1_1], first gate signal Pscan[1_2], first gate signal Pscan[2_1], and first gate signal Pscan[2_2] of the pixel group 10 in rows 1 to 4 are 601 nanoseconds, 597 nanoseconds, 601 nanoseconds, and 596 nanoseconds respectively, and the difference between adjacent ones is less than or equal to 5 nanoseconds), thereby reducing the difference in the degree of influence on the control of the corresponding nodes in the pixel circuit 102 of the pixel group 10 driven by each, reducing the difference in the write potential of the node between the two, and thus improving the phenomenon of dense horizontal stripes in the display screen.

[0048] In some embodiments, combined with Figure 5 and Figure 6As shown, the ratio of the amplitude of the signal q[n] of the third node Q of the first gate driving circuit CMOS_T3 changing from the first amplitude a1 to the second amplitude a2 and the duration of the first amplitude a1 (the fifth duration t5) is greater than or equal to 0.5; the ratio of the amplitude of the signal q[n] of the third node Q of the second gate driving circuit CMOS_T4 changing from the first amplitude a1 to the second amplitude a2 and the duration of the first amplitude a1 (the sixth duration t6) is greater than or equal to 0.5.

[0049] In the comparative example, such as Figure 7 As shown, the amplitude of the signal q[n] of the third node Q[n] in the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the nth stage changes from the first amplitude a1 to the second amplitude a2. The fifth comparison time t5' and the sixth comparison time t6' that the first amplitude a1 passes through are the same. However, as analyzed above, the absolute value of the difference between the third comparison time t3' and the fourth comparison time t4' corresponding to the two is large, resulting in a large difference in the proportion of the charging time of the third node Q[n] of the two, thus causing the display screen to produce dense horizontal stripes.

[0050] Understandably, in this embodiment, the ratio of the third duration t3 to the fifth duration t5 corresponding to the first gate drive circuit CMOS_T3 of the nth stage, and the ratio of the fourth duration t4 to the sixth duration t6 corresponding to the second gate drive circuit CMOS_T4 of the same stage, are both set to be greater than or equal to 0.5. This makes the proportion of the charging duration of the third node Q[n] of both circuits as large as possible, so that the charging duration of the third node Q[n] of both circuits is large enough, which is beneficial to achieving the above-mentioned "the absolute value of the difference between the first duration t1 and the second duration t2 occupied by the rising edge or falling edge from the start time is less than or equal to 5 nanoseconds".

[0051] For example Figure 6 As shown, in this embodiment, the fifth duration t5 and the sixth duration t6 of the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the same stage can both be 4 units of duration, and the pulse width of the first gate pulse p1 can be 1 unit of duration. Therefore, the third duration t3 and the fourth duration t4 can both be 2 or 3 units of duration. This not only makes the proportion of the charging time of the third node Q of both stages larger to reduce the difference between them, but also avoids the first gate pulse p1 of the corresponding stage being incomplete or even non-existent due to the charging time of the third node Q being too long.

[0052] In some embodiments, combined with Figure 5 and Figure 6As shown, taking the first gate driving circuit CMOS_T3 of the nth stage and the second gate driving circuit CMOS_T4 of the nth stage as an example: the first output module 202 is used to control the start time of the amplitude q[n] of the third node Q[n] from the first amplitude a1 to the second amplitude a2 according to the overlapping time period of the pulse of the second node K[n] signal and the pulse pp2 of the first node P[n-2] signal p[n-2] of the first node i (i is a positive integer, i is 2 here as an example) stage; and to control the end time of the amplitude of the third node Q[n] signal q[n] from the first amplitude a1 to the second amplitude a2 according to the start time of the second clock pulse pc2 corresponding to the second clock signal pck; wherein, the time interval Δt between the end time of the overlapping time period and the start time of the corresponding second clock pulse pc2 is the corresponding third duration t3 or the corresponding fourth duration t4.

[0053] Specifically, such as Figure 5 As shown, taking the nth level as an example, both the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 further include a first frequency divider module 2031, electrically connected between the second node K[n] and the fourth node M[n], used to control whether a current path is formed between the second node K[n] and the fourth node M[n] according to the first frequency divider control signal transmitted by the first frequency divider control line PLF. The first frequency divider module 2031 controls, at least according to the first frequency divider control signal, whether the first gate signal Pscan[n_1] or the first gate signal Pscan[n_2] output by the first output module 202 includes the corresponding first gate pulse p1, thereby controlling whether the multi-level first gate signals Pscan[n_1] and Pscan[n_2] output by the multi-level first gate driving circuit CMOS_T3 and the multi-level second gate driving circuit CMOS_T4 within multiple frames include the corresponding first gate pulse p1, thereby realizing the segmented frequency setting within the display area of ​​the display device 100.

[0054] Specifically, such as Figure 5 As shown, the first frequency divider module 2031 may include a first frequency divider transistor T19, a second frequency divider transistor T20, and a third capacitor C3. For specific connection details, please refer to [reference needed]. Figure 5When the signal p[n] of the first node P[n] is at the corresponding effective potential, the second frequency divider transistor T20 transmits the first frequency divider control signal to the fifth node J[n] (otherwise, it does not transmit to the fifth node J[n]). When the first frequency divider control signal makes the signal of the fifth node J[n] at the corresponding effective potential, the signal of the second node K[n] is transmitted to the fourth node M[n] (otherwise, it can be considered that no current path is formed between the second node K[n] and the fourth node M[n]). At the same time, through the coupling effect of the third capacitor C3, the potential of the signal m[n] of the fourth node M[n] also changes with the potential of the signal of the fifth node J[n], which helps to make the signal m[n] of the fourth node M[n] closer to the signal of the second node K[n].

[0055] Specifically, such as Figure 5 As shown, taking the nth stage as an example, the first output module 202 includes: a first pull-up unit 2021, the first control terminal of the first pull-up unit 2021 is electrically connected to the second node K[n], the second control terminal of the first pull-up unit 2021 is electrically connected to the first node P[n-2] of the previous i-th stage, and the input terminal of the first pull-up unit 2021 is electrically connected to the corresponding second clock line PCK. The first pull-up unit 2021 is used to adjust the signal p[n-2] of the first node P[n-2] of the previous i-th stage, the signal of the second node K[n] of this stage, and the signal p[n-2] of the second node P[n] of the current stage. The second clock signal pck controls the signal q[n] of the third node Q[n] of this stage and the first gate signal Pscan[n] of this stage; the first pull-down unit 2022, the control terminal of the first pull-down unit 2022 is electrically connected to the first node P[n], the input terminal of the first pull-down unit 2022 is electrically connected to the first level line PVGH, and the first pull-down unit 2022 is used to control the first gate signal Pscan[n] of this stage according to the signal p[n] of the first node P[n] of this stage and the first level signal transmitted by the first level line PVGH.

[0056] The first pull-up unit 2021 includes a first capacitor C1 and a first pull-down transistor T6. The first plate of the first capacitor C1 and the gate of the first pull-down transistor T6 are both electrically connected to the third node Q[n]. One of the source and drain of the first pull-down transistor T6 is electrically connected to the corresponding second clock line PCK. The second plate of the first capacitor C1 and the other of the source and drain of the first pull-down transistor T6 are both electrically connected to the first gate line G1 of this stage.

[0057] The other specific components and their connections in the first output module 202 are described in reference to... Figure 5 .

[0058] For ease of description, this embodiment only takes the example of the first frequency divider module 2031 controlling the signal m[n] of the fourth node M[n] to be close to the signal of the second node K[n], that is, the area displays the screen at a relatively high refresh rate. As can be seen from the above analysis, at this time, the signal of the second node K[n] can control the signal m[n] of the fourth node M[n]. The signal m[n] of the fourth node M[n], combined with the signal p[n-2] of the first node P[n-2] of the previous two stages, can control the signal q[n] of the third node Q[n]. Therefore, when the signal p[n-2] of the first node P[n-2] of the previous two stages is the corresponding effective potential, the starting time of the pulse of the signal of the second node K[n] in this embodiment (that is, the starting time of the fourth node pulse pm of the corresponding signal m[n] of the fourth node M[n]) and the ending time of the signal p[n-2] of the first node P[n-2] of the previous two stages can control the starting time of the switching of the amplitude q[n] of the signal of the third node Q[n] from the first amplitude a1 to the second amplitude a2.

[0059] Combination Figure 5 and Figure 6 As shown, since the start time of the fourth node pulse pm of the signal m[n] of the fourth node M[n] is earlier than the end time of the first preceding node pulse pp2 of the signal p[n-2] of the first node P[n-2] of the first two stages, the latter is used to control the start time of the switching of the amplitude q[n] of the signal of the third node Q[n] from the first amplitude a1 to the second amplitude a2; at the same time, based on the connection relationship of the first capacitor C1 and the first pull-down transistor T6, it can be known that the start time of the second clock pulse pc2 of the second clock signal pck can control the amplitude of the signal q[n] of the third node Q[n] to quickly change from the first amplitude a1 to the second amplitude a2 through the action of the first gate line G1 and the first capacitor C1.

[0060] Therefore, the time interval Δt between the later of the pulse start time of the second node K[n] signal (i.e. the start time of the fourth node pulse pm), the end time of the first preceding node pulse pp2 of the first node P[n-2] signal p[n-2] of the first two stages, and the start time of the second clock pulse pc2 is the corresponding third duration t3 or the corresponding fourth duration t4.

[0061] In some embodiments, combined with Figure 5 and Figure 6As shown, in the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the first stage, the control module 201 is used to control the pulse width of the signal of the second node K[n] (i.e. the pulse width of the fourth node pulse pm) according to the pulse width of the first frame start pulse ps1 of the corresponding first frame start signal stv1 or the pulse width of the second frame start pulse ps2 of the corresponding second frame start signal stv2, and is used to control the pulse start time of the signal of the second node K[n] (i.e. the start time of the fourth node pulse pm) according to the start time of the corresponding first clock pulse pc1 of the corresponding first clock signal eck; wherein, the pulse width of the signal of the second node K[n] is equal to the pulse width of the corresponding first frame start pulse ps1 or the pulse width of the corresponding second frame start pulse ps, and the start time of the signal of the second node K[n] is the same as the start time of the corresponding first clock pulse pc1.

[0062] Specifically, such as Figure 5 As shown, the control module 201 described above may include a shift register module 2011 (for specific components and their connections, please refer to...). Figure 5 The shift register module 2011 is electrically connected to one of the corresponding first frame start line STV1, second frame start line STV2, first level line PVGH, second level line NVGL, and first clock line ECK. It is used to shift the first frame start signal stv1 or the second frame start signal stv2 according to the time period of the first clock pulse pc1 of the first clock signal eck, to obtain the signal of the second node K[n]. Figure 6 As shown, since the first clock signal eck is the closest to the first frame start signal stv1 or the second frame start signal stv2 corresponding to the first clock pulse pc1 with a duration of two units, the fourth node pulse pm is also delayed by two units of duration to the corresponding first frame start pulse ps1 or the second frame start pulse ps2, and the pulse width of the fourth node pulse pm is equal to the pulse width of the corresponding first frame start pulse ps1 or the second frame start pulse ps2.

[0063] The control module 201 mentioned above also includes a self-stabilizing module 2012 electrically connected to the second node K[n], the first node P[n], the control line Control, the first level line PVGH, the second level line NVGL, and the third level line PVGL (see [link to specific components and their connections]). Figure 5The control signal transmitted by the control line Control can control the first gate signal Pscan[n], the second gate signal Nscan_T3, and the third gate signal Nscan_T4 to be the corresponding invalid potentials after power-on, so as to discharge the display area. After that, the self-stabilizing module 2012 is used to stabilize the signal of the second node K[n] and the signal p[n] of the first node P[n].

[0064] Based on the above analysis, it can be seen that in the embodiments of the present invention, considering that the ratio of the third duration t3 to the fifth duration t5 and the ratio of the fourth duration t4 to the sixth duration t6 are both greater than or equal to 0.5, the following analysis can be made regarding the above requirements:

[0065] The aforementioned fifth duration t5 and sixth duration t6 are jointly determined by the signal p[n-2] of the first node P[n-2] of the corresponding two preceding levels and the signal m[n] of the fourth node M[n] of this level; furthermore, the signal m[n] of the fourth node M[n] of this level and the signal p[n-2] of the first node P[n-2] of the corresponding two preceding levels are both determined by one of the corresponding first frame start signal stv1, the second frame start signal stv2, and the corresponding first clock signal eck; therefore, the aforementioned fifth duration t5 and sixth duration t6 are determined by one of the corresponding first frame start signal stv1, the second frame start signal stv2, and the corresponding first clock signal eck.

[0066] The aforementioned third duration t3 and fourth duration t4 are determined by the time period of the corresponding first clock pulse pc1 in the corresponding second clock signal pck, that is, by the corresponding second clock signal pck.

[0067] Therefore, by reasonably setting the first frame start signal stv1, the first clock signal eck, and the second clock signal pck corresponding to the first gate drive circuit CMOS_T3, and by reasonably setting the second frame start signal stv2, the first clock signal eck, and the second clock signal pck corresponding to the second gate drive circuit CMOS_T4, the ratio of the third duration t3 to the fifth duration t5 and the ratio of the fourth duration t4 to the sixth duration t6 can be made to be greater than or equal to 0.5.

[0068] The timing diagrams for the aforementioned signals can be referenced. Figure 8The multiple first clock signals eck include four first clock signals eck1, eck2, eck3, and eck4 that act on the odd-numbered first gate driving circuit CMOS_T3, the even-numbered first gate driving circuit CMOS_T3, the odd-numbered second gate driving circuit CMOS_T4, and the even-numbered second gate driving circuit CMOS_T4, respectively. The multiple second clock signals pck include four second clock signals pck1, pck2, pck3, and pck4 that act on the odd-numbered second gate driving circuit CMOS_T4, the odd-numbered first gate driving circuit CMOS_T3, the even-numbered second gate driving circuit CMOS_T4, and the even-numbered first gate driving circuit CMOS_T3, respectively.

[0069] contrast Figure 9 and Figure 10 The figures shown are timing diagrams of signals from multiple nodes in the first gate drive circuit CMOS_T3 and the second gate drive circuit CMOS_T4 of the nth stage in the comparative example and embodiment, respectively.

[0070] like Figure 9 As shown, in the comparative example, the signals q'[n] of the third node Q[n] of the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the nth stage, the signal m'[n] of the fourth node M[n], and the signal p'[n-2] of the first node P[n-2] of the first two stages are all different, and the phases of the corresponding two second clock signals pck are also different, resulting in a large absolute value of the difference between the third comparison duration t3' and the fourth comparison duration t4'.

[0071] like Figure 10 As shown, due to the adoption of the following in the embodiments Figure 6 and Figure 7 The above configuration makes the time interval between the end time of the signal p[n-2] of the first node P[n-2] of the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the nth stage and the time interval of the corresponding second clock pulse pc2 in the second clock signal pck similar, so that the absolute value of the difference between the three comparison durations t3 and the fourth duration t4 is small.

[0072] In some embodiments, combined with Figure 5 and Figure 6 As shown, both the first gate drive circuit CMOS_T3 and the second gate drive circuit CMOS_T4 further include: a second output module 204 (also electrically connected to the fourth level line NVGH, the specific components and their connections are shown in the reference). Figure 5The second output module 204 in the first gate driving circuit CMOS_T3 is electrically connected between the corresponding second node K[n] and the corresponding second gate line G2, and is used to generate the corresponding second gate signal Nscan_T3 according to the signal of the second node K[n]. The second output module 204 in the second gate driving circuit CMOS_T4 is electrically connected between the corresponding second node K[n] and the corresponding third gate line G3, and is used to generate the corresponding third gate signal Nscan_T4 according to the signal of the second node K[n]. The multi-level second gate signal Nscan_T3 is used to control one transistor in the multiple pixel groups 101 to be turned on or off, and the multi-level third gate signal Nscan_T4 is used to control another transistor in the multiple pixel groups 101 to be turned on or off.

[0073] Specifically, the second gate signal Nscan_T3 is used to control one transistor in the pixel group to be turned on or off, and the third gate signal Nscan_T4 at the same level is used to control another transistor in the same pixel group to be turned on or off.

[0074] That is, the second gate signal Nscan_T3 and the third gate signal Nscan_T4 of the same level can be applied to two different transistors in the pixel circuit 102 of the same pixel.

[0075] Furthermore, both the first gate drive circuit CMOS_T3 and the second gate drive circuit CMOS_T4 also include a second frequency divider module 2032 (for specific components and their connections, please refer to...). Figure 5 The second frequency divider module 2032 is used to control whether a current path is formed between the second node K[n] and the sixth node W[n]. The seventh node H[n] in the second frequency divider module 2032 can be compared with the fifth node J[n] in the first frequency divider module 2031. The working principle of the second frequency divider module 2032 can be referred to the working principle of the first frequency divider module 2031.

[0076] Specifically, such as Figure 3As shown, the pixel circuit 102 includes: a driving transistor M1, used to generate a driving current according to a data signal Data to drive the light-emitting element Di to emit light; a data writing transistor M2, electrically connected to one of the source and drain of the driving transistor M1, used to transmit the data signal Data, and the gate of the data writing transistor M2 is electrically connected to the corresponding first gate line G1 to receive a first gate signal Pscan[n]; a compensation transistor M3, electrically connected between the other of the source and drain of the driving transistor M1 and the gate of the driving transistor M1, and the gate of the compensation transistor M3 is electrically connected to the corresponding second gate line G2 to receive a second gate signal Nscan_T3; and a first reset transistor M4, electrically connected to the gate of the driving transistor M1, used to transmit a first reset signal Vi_G, and the gate of the first reset transistor M4 is electrically connected to the corresponding third gate line to receive a third gate signal Nscan_T4.

[0077] Among them, combined Figure 1 , Figure 3 and Figure 5 As shown, the first gate driving circuit CMOS_T3 transmits a corresponding first gate signal Pscan[n_2] to the gates of multiple data write transistors M2 of a pixel group 101 (e.g., an even-numbered row of pixels Pi) via a first gate line G1. The corresponding second gate driving circuit CMOS_T4 transmits another corresponding first gate signal Pscan[n_1] to the gates of multiple data write transistors M2 of another pixel group 101 (e.g., the corresponding previous odd-numbered row of pixels Pi) via another first gate line G1. A gate driving circuit CMOS_T3 transmits the same second gate signal Nscan_T3 to the gates of multiple compensation transistors M3 in two pixel groups 101 (e.g., an adjacent odd-numbered row pixel Pi and an even-numbered row pixel Pi) via the second gate line G2. The second gate driving circuit CMOS_T4 transmits the same third gate signal Nscan_T4 to the gates of multiple first reset transistors M4 in two pixel groups 101 (the aforementioned adjacent odd-numbered row pixel Pi and even-numbered row pixel Pi) via the third gate line G3.

[0078] That is, the second gate signal Nscan_T3 and the third gate signal Nscan_T4 generated by the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 of the same level can be applied to the compensation transistor M3 and the first reset transistor M4 in the pixel circuit 102 of the same pixel, respectively. Furthermore, the first gate signals Pscan[n_2] and Pscan[n_1] generated by these two circuits can be applied to the data writing transistor M2 in the even-numbered row pixel circuit 102 and the preceding odd-numbered row pixel circuit 102, respectively. Therefore, as... Figure 1 As shown, the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 have the same number of stages, which can both be half the number of pixel groups 101.

[0079] Furthermore, such as Figure 1 As shown, the display device 100 further includes multiple fourth gate lines G4, multiple fifth gate lines G5, cascaded multi-stage third gate driving circuits EM_T and cascaded multi-stage fourth gate driving circuits Pscan2_T; the third gate driving circuit EM_T transmits the same fourth gate signal EM to at least two pixel groups 101 (the aforementioned adjacent odd-numbered row pixels Pi and even-numbered row pixels Pi) through one of the fourth gate lines Pscan2_T, and the fourth gate driving circuit Pscan2_T transmits the same fifth gate signal Pscan2 to at least two pixel groups (the aforementioned adjacent odd-numbered row pixels Pi and even-numbered row pixels Pi) through one of the fifth gate lines G5.

[0080] Specifically, such as Figure 3 As shown, the pixel circuit 102 further includes: a first switching transistor M5, electrically connected between the source and drain of the driving transistor M1 and the first voltage line VDD; a second switching transistor M6, electrically connected between the other of the source and drain of the driving transistor M1 and the light-emitting element Di, wherein the gates of the first switching transistor M5 and the second switching transistor M6 are both electrically connected to the corresponding fourth gate line G4 to receive the fourth gate signal EM; a second reset transistor M7, electrically connected between the other of the source and drain of the driving transistor M1 and the light-emitting element Di, for transmitting the second reset signal Vi_ANo; and a third reset transistor M8, electrically connected between the source and drain of the driving transistor M1, for transmitting the third reset signal Vi3, wherein the gates of the second reset transistor M7 and the third reset transistor M8 are both electrically connected to the corresponding fifth gate line G5.

[0081] The other specific components and their connections in the pixel circuit 102 are described in reference to... Figure 3 .

[0082] That is, the fourth gate signal EM and the fifth gate signal Pscan2 generated by the third gate driving circuit EM_T act on the first switching transistor M5 and the second switching transistor M6 in the pixel circuit 102 of a pixel, and the fifth gate signal Pscan2 generated by the fourth gate driving circuit Pscan2_T acts on the second reset transistor M7 and the third reset transistor M8 in the pixel circuit 102 of the same pixel. Therefore, as Figure 1 As shown, the third gate driving circuit EM_T and the fourth gate driving circuit Pscan2_T have the same number of stages, which can both be the number of pixel groups 101.

[0083] In summary, as shown in Table 3, this embodiment takes the four gate driving circuits mentioned above as being dual-sided driving as an example. The fourth gate signal EM and the fifth gate signal Pscan2 generated by the third gate driving circuit EM_T and the fourth gate driving circuit Pscan2_T at the same level are both applied to the two pixel groups 101 in adjacent even-numbered rows and odd-numbered rows, so the driving method is "dual-sided one-drive-two". The second gate signal Nscan_T3 and the third gate signal Nsc generated by the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 at the same level are respectively... Both an_T4 act on the compensation transistor M3 and the first reset transistor M4 in the two adjacent even-numbered and odd-numbered pixel groups 101, so the driving mode is "double-sided one-drives-two"; while the first gate driving circuit CMOS_T3 and the second gate driving circuit CMOS_T4 at the same level generate the first gate signal Pscan[n_2] and the first gate signal Pscan[n_1] respectively, which act on the data writing transistor M2 in the two adjacent even-numbered and odd-numbered pixel groups 101, so the driving mode is "double-sided one-drives-one".

[0084] Table 3

[0085]

[0086] like Figure 11 As shown, Figure 3 The timing diagram required for the first and second pixel groups 101 is shown. Among them, the first-level fourth gate signal EM[1] and the second-level fourth gate signal EM[2] drive the first and second pixel groups 101 respectively, the x-level second gate signal Nscan_T3[x] drives the compensation transistor M3 in the first and second pixel groups 101, the y-level third gate signal Nscan_T4[y] drives the first reset transistor M4 in the first and second pixel groups 101, and the first-level first gate signal Pscan[n_2] and the first-level first gate signal Pscan[n_1] drive the first and second pixel groups 101 respectively.

[0087] Combination Figure 3 and Figure 11 As shown, the first reset transistor M4 in the first and second pixel groups 101 is first turned on by the third gate signal Nscan_T4[y] at the y-th stage to reset the gate of the driving transistor M1 in the first and second pixel groups 101; the compensation transistor M3 in the first and second pixel groups 101 is then turned on by the second gate signal Nscan_T3[x] at the x-th stage to form a current path between the source and drain of the driving transistor M1 in the first and second pixel groups 101 and its gate; thereafter the first stage... A gate signal Pscan[n_1] and a first-level gate signal Pscan[n_2] control the data writing transistors M2 in the first and second pixel groups 101 to be turned on in sequence to write data signals Data; finally, a first-level fourth gate signal EM[1] and a second-level fourth gate signal EM[2] control the formation of a current path between the first voltage line VDD and the second voltage line VSS in the first and second pixel groups 101, so as to form a driving current in sequence to control the first and second pixel groups 101 to emit light.

[0088] However, as Figure 12 As shown, including Figure 1 The timing diagrams of the first-stage third gate signal Nscan_T4[1] to the fifth-stage third gate signal Nscan_T4[5] and the first-stage first gate signal Pscan[1_1] to the fifth-stage first gate signal Pscan[5_1] generated by the second gate driving circuit CMOS_T4 of the first to fifth stages corresponding to the driving architecture shown are observed. It can be seen that the end time of the pulse in the third gate signal Nscan_T4[n] of the same stage (e.g., the nth stage) is delayed by the start time of the first gate pulse p1 in the corresponding first gate signal Pscan[n_1], and is not the same as the start time of the first gate pulse p1 in the first gate signal Pscan[n_1]. Figure 11 The end time of the pulse in the third gate signal Nscan_T4 required for pixel group 101 in the same odd-numbered row has a first time interval Δt1 between the end time of the pulse in the third gate signal Nscan_T4 and the start time of the first gate pulse p1 in the first gate signal Pscan. Similarly, it is not the same as... Figure 11 There is a second time interval Δt2 between the end time of the pulse in the third gate signal Nscan_T4 required for pixel group 101 in the same even row and the start time of the first gate pulse p1 of the first gate signal Pscan, that is... Figure 11 x in the equation is not equal to 1; similarly, analysis also shows that... Figure 11 y in the equation is not equal to 1.

[0089] contrast Figure 11 and Figure 12As shown, it can be found that, for example, there may be the above-mentioned first time interval Δt1 between the end moment of the pulse in the first-stage third gate signal Nscan_T4[1] and the first gate pulse p1 of the actual first gate signal Pscan[5 odd] at the 5th stage, correspondingly, there must also be the above-mentioned second time interval Δt2 between the end moment of the pulse in the first-stage third gate signal Nscan_T4[1] and the first gate pulse p1 of the first gate signal Pscan[5 even] at the 5th stage. Therefore, the third gate signals Nscan_T4 of the previous 4 stages can be borrowed to drive the two adjacent pixel groups 101 in odd rows and even rows corresponding to the first gate signal Pscan of the current stage.

[0090] Similarly, through comparison, it can also be found that, for example, there may be Figure 11 the required corresponding time interval between the end moment of the pulse in the 7th-stage second gate signal Nscan_T3[7] and the first gate pulse p1 of the actual first gate signal Pscan[5 odd] at the 5th stage, so the second gate signals Nscan_T3 of the latter 2 stages can be borrowed to drive the two adjacent pixel groups 101 in odd rows and even rows corresponding to the first gate signal Pscan of the current stage.

[0091] It should be noted that the above specific stage borrowing relationship is only for illustration, and the embodiments of the present invention do not limit the specific stage borrowing relationship.

[0092] In some embodiments, in combination with Figure 1 , Figure 5 , Figure 12 and Figure 13 as shown, the display device 100 further comprises: cascaded multi-stage first gate redundant circuits CMOS_T3', which are cascaded before the first-stage first gate driving circuit CMOS_T3 or after the last-stage first gate driving circuit CMOS_T3, and the multi-stage first gate redundant circuits CMOS_T3' transmit corresponding second gate signals Nscan_T3 to corresponding pixel groups 101 through corresponding second gate lines G2; cascaded multi-stage second gate redundant circuits CMOS_T4', which are cascaded before the first-stage second gate driving circuit CMOS_T4 or after the last-stage second gate driving circuit CMOS_T4, and the multi-stage second gate redundant circuits CMOS_T4' transmit corresponding third gate signals Nscan_T4 to corresponding pixel groups 101 through corresponding third gate lines G3.

[0093] Combined with the above about Figure 11 and Figure 12Analysis shows that, in this embodiment, by setting the above-mentioned cascaded multi-level first gate redundancy circuit CMOS_T3' and cascaded multi-level second gate redundancy circuit CMOS_T4', the output signals can respectively replace the second gate signals Nscan_T3 generated by the first gate driving circuit CMOS_T3 and the third gate signals Nscan_T4 generated by the second gate driving circuit CMOS_T4 to act on the corresponding pixel group 101.

[0094] The cascading relationship of the multi-stage first gate redundancy circuit CMOS_T3' and the specific circuit of each can be found in the multi-stage first gate drive circuit CMOS_T3, and the cascading relationship of the multi-stage second gate redundancy circuit CMOS_T4' and the specific circuit of each can be found in the multi-stage second gate drive circuit CMOS_T4.

[0095] Furthermore, the cascaded multi-stage first gate redundancy circuits CMOS_T3' are cascaded before the first-stage first gate drive circuit CMOS_T3, and the cascaded multi-stage second gate redundancy circuits CMOS_T4' are cascaded after the last-stage second gate drive circuit CMOS_T4; or, the cascaded multi-stage first gate redundancy circuits CMOS_T3' are cascaded after the last-stage first gate drive circuit CMOS_T3, and the cascaded multi-stage second gate redundancy circuits CMOS_T4' are cascaded before the first-stage second gate drive circuit CMOS_T4. Figure 12 The following example illustrates the latter scenario.

[0096] Specifically, such as Figure 13 As shown, the cascaded two-stage first gate redundancy circuits CMOS_T3' are cascaded after the final stage first gate drive circuit CMOS_T3, and the cascaded four-stage second gate redundancy circuits CMOS_T4' are cascaded before the first stage second gate drive circuit CMOS_T4. This allows the current stage's first gate drive circuit CMOS_T3 to borrow from the next two stages' first gate drive circuits CMOS_T3 or first gate redundancy circuits CMOS_T3' (for example, the last stage's Nth (a positive integer greater than n) first gate drive circuit CMOS_T3 can borrow from the next two stages' first gate redundancy circuits CMOS_T3'), and the current stage's second gate drive circuit CMOS_T4 can borrow from the previous four stages' second gate drive circuits CMOS_T4 or second gate redundancy circuits CMOS_T4' (for example, the first stage's second gate drive circuit CMOS_T4 can borrow from the previous four stages' second gate redundancy circuits CMOS_T4').

[0097] Furthermore, in Figure 13Based on the illustration, the display device 100 further includes: at least one third gate redundancy circuit CMOS_T3”, cascaded before the first-stage first gate driving circuit CMOS_T3, and the at least one third gate redundancy circuit CMOS_T3” is used to provide the first frame start signal stv1 to the first-stage first gate driving circuit CMOS_T3.

[0098] It should be noted that the reference Figure 5 It can be seen that for the first gate driving circuit CMOS_T3 or the second gate driving circuit CMOS_T4 of the first stage, if the required first frame start signal stv1 or second frame start signal stv2 and the corresponding first node P signals of the first two stages are all boosted by external signal sources, then there are many types of signals required.

[0099] It is understandable that this embodiment takes into account that... Figure 2 Based on the illustration, since the aforementioned cascaded four-stage second gate redundancy circuit CMOS_T4' is set before the first-stage second gate driving circuit CMOS_T4, it is sufficient to provide the first-stage second gate driving circuit CMOS_T4 with the corresponding second frame start signal stv2 and the signal of the first node P of the previous two stages; however, since the aforementioned first gate redundancy circuit CMOS_T3' is not set before the first-stage first gate driving circuit CMOS_T3, in this embodiment, for example, two cascaded third gate redundancy circuits CMOS_T3' can also be set before the first-stage first gate driving circuit CMOS_T3 to provide the first frame start signal stv1 and the signal of the first node P of the previous two stages.

[0100] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display device, characterized in that, It includes multiple pixel groups, multiple first gate lines, multiple second gate lines, multiple third gate lines, cascaded multi-stage first gate driving circuits, and cascaded multi-stage second gate driving circuits, wherein the pixel group includes a row of pixels; The first gate driving circuit transmits a corresponding first gate signal to a pixel group through a first gate line, and the second gate driving circuit at the same level transmits another corresponding first gate signal to another pixel group through another first gate line. The first gate driving circuit transmits a corresponding second gate signal to the pixel group through a second gate line, and the second gate driving circuit at the same level transmits a corresponding third gate signal to the same pixel group through the third gate line. Both the first gate driving circuit and the second gate driving circuit include a first output module. The first output module is used to generate the first gate signal of the current stage based on the signal of the third node of the current stage. The amplitude of the signal of the third node of the current stage is, in sequence, a first amplitude, a second amplitude, and a first amplitude. One of the first amplitude and the second amplitude is the maximum amplitude of the signal of the third node, and the other is the minimum amplitude of the signal of the third node. Wherein, the absolute value of the difference between the third time interval during which the amplitude of the signal at the third node of the first gate driving circuit changes from the first amplitude to the second amplitude, and the fourth time interval during which the amplitude of the signal at the third node of the second gate driving circuit changes from the first amplitude to the second amplitude, is less than 0.5×H, and 1H is the duration of scanning one pixel group.

2. The display device according to claim 1, characterized in that, The absolute value of the difference between the third duration and the fourth duration is less than 0.2 × H.

3. The display device according to claim 1, characterized in that, The amplitude of the signal at the third node of the first gate driving circuit changes from the first amplitude to the second amplitude in sequence, the duration of the first amplitude is the fifth duration, and the ratio of the third duration to the fifth duration is greater than or equal to 0.

5. The amplitude of the signal at the third node of the second gate driving circuit changes from the first amplitude to the second amplitude in sequence, the duration of the first amplitude is the sixth duration, and the ratio of the fourth duration to the sixth duration is greater than or equal to 0.

5.

4. The display device according to claim 1, characterized in that, The absolute value of the difference between the first duration occupied by the rising or falling edge of the first gate pulse in the first gate signal generated by the first gate driving circuit from the start time and the second duration occupied by the rising or falling edge of the first gate pulse in the first gate signal generated by the second gate driving circuit of the same level from the start time is less than or equal to 10 nanoseconds.

5. The display device according to any one of claims 1 to 4, characterized in that, Both the first gate driving circuit and the second gate driving circuit further include a control module; In the first gate drive circuit: The input terminal of the control module is electrically connected to the first frame start line or the first node of the first gate drive circuit of the previous stage, and the control terminal of the control module is electrically connected to the corresponding first clock line. The control module is used to control the signal of the second node of the current stage according to one of the first frame start signal transmitted by the first frame start line, the signal of the first node of the previous stage, and the first clock signal transmitted by the corresponding first clock line. The control terminal of the first output module is electrically connected to the second node, and the input terminal of the first output module is electrically connected to the corresponding second clock line. The first output module is used to control the amplitude of the signal of the third node of this stage to be the first amplitude, the second amplitude, and the first amplitude in sequence according to the signal of the second node and the second clock signal transmitted by the corresponding second clock line, and is used to generate the first gate signal of this stage according to the signal of the third node of this stage and the second clock signal. In the second gate drive circuit: The input terminal of the control module is electrically connected to the second frame start line or the first node of the previous stage second gate drive circuit, and the control terminal of the control module is electrically connected to the corresponding first clock line. The control module is used to control the signal of the second node of this stage according to one of the second frame start signal transmitted by the second frame start line, the signal of the corresponding first node of the previous stage, and the corresponding first clock signal transmitted by the corresponding first clock line. The control terminal of the first output module is electrically connected to the second node, and the input terminal of the first output module is electrically connected to the corresponding second clock line. The first output module is used to control the amplitude of the signal of the third node of this stage to be the first amplitude, the second amplitude, and the first amplitude in sequence according to the signal of the second node and the second clock signal transmitted by the corresponding second clock line, and is used to generate the first gate signal of this stage according to the signal of the third node of this stage and the second clock signal. Wherein, the first frame start signal is different from the second frame start signal, and the signal of the first node of the first gate drive circuit is different from the signal of the first node of the second gate drive circuit at the same level.

6. The display device according to claim 5, characterized in that, In the first gate driving circuit and the second gate driving circuit: The first output module is used to control the start time of switching the amplitude of the signal of the third node from the first amplitude to the second amplitude according to the overlapping time period of the pulse of the signal of the second node and the pulse of the corresponding pulse of the first node of the preceding i stages, and to control the end time of switching the amplitude of the signal of the third node from the first amplitude to the second amplitude according to the start time of the corresponding second clock pulse of the corresponding second clock signal, where i is a positive integer; The time interval between the end time of the overlapping period and the start time of the corresponding second clock pulse is the corresponding third duration or the corresponding fourth duration.

7. The display device according to claim 6, characterized in that, In the first gate driving circuit and the second gate driving circuit of the first stage: The control module is used to control the pulse width of the signal pulse of the second node according to the pulse width of the first frame start pulse of the corresponding first frame start signal or the pulse width of the second frame start pulse of the corresponding second frame start signal, and to control the start time of the signal pulse of the second node according to the start time of the corresponding first clock pulse of the corresponding first clock signal. Wherein, the pulse width of the signal pulse of the second node is equal to the pulse width of the corresponding first frame start pulse or the pulse width of the corresponding second frame start pulse, and the start time of the signal pulse of the second node is the same as the start time of the corresponding first clock pulse.

8. The display device according to claim 5, characterized in that, Both the first gate driving circuit and the second gate driving circuit further include a second output module; In the first gate driving circuit, the second output module is electrically connected between the corresponding second node and the corresponding second gate line, and is used to generate the corresponding second gate signal according to the signal of the second node; In the second gate driving circuit, the second output module is electrically connected between the corresponding second node and the corresponding third gate line, and is used to generate the corresponding third gate signal according to the signal of the second node; The second gate signal is used to control one transistor in the pixel group to be turned on or off, and the third gate signal at the same level is used to control another transistor in the same pixel group to be turned on or off.

9. The display device according to claim 8, characterized in that, The display device further includes: A cascaded multi-stage first gate redundancy circuit is cascaded before the first-stage first gate driving circuit or after the last-stage first gate driving circuit. The first gate redundancy circuit transmits the corresponding second gate signal to the corresponding pixel group through a second gate line. A cascaded multi-stage second gate redundancy circuit is cascaded before the first-stage second gate driving circuit or after the last-stage second gate driving circuit. The second gate redundancy circuit transmits the corresponding third gate signal to the corresponding pixel group through a third gate line.

10. The display device according to claim 9, characterized in that, The cascaded multi-stage first gate redundant circuits are cascaded before the first-stage first gate driving circuit, and the cascaded multi-stage second gate redundant circuits are cascaded after the last-stage second gate driving circuit. Alternatively, multiple cascaded first gate redundant circuits are cascaded after the last stage first gate driving circuit, and multiple cascaded second gate redundant circuits are cascaded before the first stage second gate driving circuit.

11. The display device according to claim 10, characterized in that, The cascaded multi-stage first gate redundant circuits are cascaded after the last stage first gate driving circuit, and the cascaded multi-stage second gate redundant circuits are cascaded before the first stage second gate driving circuit. The display device further includes: At least one third gate redundancy circuit is cascaded before the first gate driving circuit of the first stage, and the at least one of the third gate redundancy circuits is used to provide the first frame start signal to the first gate driving circuit of the first stage.

12. The display device according to claim 8, characterized in that, The pixel includes an electrically connected pixel circuit and a light-emitting element, the pixel circuit including: A driving transistor is used to generate a driving current based on a data signal to drive the light-emitting element to emit light. A data writing transistor is electrically connected to one of the source and drain of the driving transistor for transmitting the data signal, and the gate of the data writing transistor is electrically connected to the corresponding first gate line. A compensation transistor is electrically connected between the source and drain of the driving transistor and the gate of the driving transistor, and the gate of the compensation transistor is electrically connected to the corresponding second gate line. A first reset transistor is electrically connected to the gate of the driving transistor and is used to transmit a first reset signal. The gate of the first reset transistor is electrically connected to the corresponding third gate line.

13. The display device according to claim 12, characterized in that, The first gate driving circuit transmits a corresponding first gate signal to the gate of a plurality of data write transistors in a pixel group through a first gate line, and the second gate driving circuit at the same level transmits another corresponding first gate signal to the gate of a plurality of data write transistors in another pixel group through another first gate line. The first gate driving circuit transmits the same second gate signal to the gates of the plurality of compensation transistors in the two pixel groups via the second gate line, and the second gate driving circuit transmits the same third gate signal to the gates of the plurality of first reset transistors in the two pixel groups via the third gate line.

14. The display device according to claim 12, characterized in that, The display device further includes multiple fourth gate lines, multiple fifth gate lines, cascaded multi-stage third gate driving circuits, and cascaded multi-stage fourth gate driving circuits. The third gate driving circuit transmits the same fourth gate signal to at least two pixel groups through a fourth gate line, and the fourth gate driving circuit transmits the same fifth gate signal to at least two pixel groups through a fifth gate line.

15. The display device according to claim 14, characterized in that, The pixel circuit also includes: The first switching transistor is electrically connected between one of the source and drain of the driving transistor and the first voltage line, or electrically connected between the other of the source and drain of the driving transistor and the light-emitting element, and the gate of the first switching transistor is electrically connected to the corresponding fourth gate line. The second reset transistor is electrically connected to the other of the source and drain of the driving transistor and the light-emitting element, and is used to transmit a second reset signal. The gate of the second reset transistor is electrically connected to the corresponding fifth gate line.

16. The display device according to claim 5, characterized in that, The first output module includes: The first pull-up unit has a first control terminal electrically connected to the second node, a second control terminal electrically connected to the first node of the previous i-th stage, and an input terminal electrically connected to the corresponding second clock line. The first pull-up unit is used to control the signal of the third node of the current stage and the first gate signal of the current stage according to the signal of the first node of the previous i-th stage, the signal of the second node of the current stage, and the second clock signal, where i is a positive integer. The first pull-down unit has its control terminal electrically connected to the first node and its input terminal electrically connected to the first level line. The first pull-down unit is used to control the first gate signal of the current stage according to the signal of the first node of the current stage and the first level signal transmitted by the first level line. The first pull-up unit includes a first capacitor and a first pull-down transistor. The first plate of the first capacitor and the gate of the first pull-down transistor are both electrically connected to the third node. One of the source and drain of the first pull-down transistor is electrically connected to the corresponding second clock line. The second plate of the first capacitor and the other of the source and drain of the first pull-down transistor are both electrically connected to the first gate line of this stage.

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