A bonding apparatus and a bonding method for a semiconductor wafer

Abstract

This application improves the bonding strength between wafers in semiconductor manufacturing processes through a simple structure. This application provides a semiconductor wafer bonding apparatus 34 for bonding semiconductor wafers W1 and W2 together. After plasma treatment of semiconductor wafers W1 and W2 to activate their surfaces, they are kept in a high vacuum state for a specified time, thereby polarizing the surface ions of semiconductor wafers W1 and W2. By applying a high-frequency power supply 110 to semiconductor wafers W1 and W2, ions move on the surfaces of semiconductor wafers W1 and W2, thereby improving the bonding strength between semiconductor wafers W1 and W2.

Description

Technical Field

[0001] This invention relates to a bonding apparatus and bonding method for semiconductor wafers, which, in semiconductor manufacturing processes, for example, bond homogeneous or heterogeneous semiconductor wafers together by high-frequency ion-flow activated bonding (RFIFB) method. Background Technology

[0002] Hybrid bonding is part of a traditional semiconductor manufacturing process, which includes plasma treatment, cleaning, drying and bonding processes.

[0003] In the plasma treatment process, for example, atmospheric pressure plasma or vacuum plasma is used to activate the surface of the semiconductor wafer. In the cleaning process, for example, the semiconductor wafer is rotated around its central axis while the flow rate and position of the cleaning solution (pure water or chemical solution) are controlled to achieve uniform cleaning of the wafer surface. In the drying process, for example, the semiconductor wafer is rotated at high speed around its central axis, causing water droplets on the wafer surface to disperse. In the bonding process, for example, two semiconductor wafers that have undergone the plasma treatment and drying processes are arranged opposite each other and finally bonded using a bonding device.

[0004] In traditional bonding apparatus, two semiconductor wafers are placed face-to-face on a planar platform with opposite orientations. The pair of semiconductor wafers are bonded together using surface activated bonding (SAB) at room temperature (hereinafter referred to as "SAB method").

[0005] Surface-activated bonding involves ionizing an inert gas such as argon to generate an ion beam, which is then used to irradiate the surface of the material to be bonded. This removes the oxide film and contaminant layer on the material surface, forming dangling bonds. Bonding is then achieved at low or room temperature by applying pressure.

[0006] However, in the SAB method, due to the small irradiation area, it is impossible to uniformly activate and remove the oxide film from the entire wafer surface in one go. Instead, the surface is treated by moving the wafer or beam source. However, this method of movement results in poor surface uniformity of the activated material, and the surface of overlapping areas becomes rough, leading to a decrease in the bonding strength between semiconductor wafers. Furthermore, moving the wafer or beam through point irradiation with an Ar ion beam generates particles, causing voids and bubbles in the bonding interlayer.

[0007] Citing patent literature

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2018-201022

[0009] Summary of the invention

[0010] The problem the invention aims to solve

[0011] Therefore, in view of the above problems, the present invention provides a bonding device and bonding method with a simple structural design that improves the strength of the wafer bonding interface while simplifying the complexity of the device.

[0012] Problem Solving Methods

[0013] This invention relates to a bonding apparatus and method for semiconductor wafers. After plasma activation of the semiconductor wafer surface, it is placed in a high vacuum state for a specified time, during which ions on the semiconductor wafer surface become polarized. By applying a high-frequency power supply to the semiconductor wafer, the migration behavior of ions on the semiconductor wafer surface is controlled, achieving a spatially uniform distribution, thereby improving the bonding strength between semiconductor wafers. This apparatus can also be used as a bonding method for semiconductor wafers.

[0014] The specified time is 0 to 30 seconds. Ideally, bonding should be performed as soon as possible after the plasma stops. 0 seconds refers to bonding while maintaining plasma activation and applying a high-fidelity state. Alternatively, bonding can be performed while maintaining plasma activation.

[0015] Two different high frequencies are applied to the upper and lower wafers (stages) to remove the surface oxide film and form dangling bonds. Pressure is then applied to the wafers while the dangling bonds are in the formed (activated) state to form a bond. At this time, the wafers should be kept as narrow as possible, and bonding must be completed before the dangling bonds disappear.

[0016] The aforementioned specified time is more preferably 0 to 5 seconds.

[0017] The effects of the invention

[0018] According to the present invention, the bonding strength between semiconductor wafers in semiconductor manufacturing processes can be improved through a simple structure. Attached Figure Description

[0019] Figure 1 This is a structural diagram of a semiconductor wafer bonding apparatus according to an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of a semiconductor wafer bonding apparatus according to an embodiment of the present invention, which performs plasma processing and bonding processing on a semiconductor wafer.

[0021] Figure 3 This is an engineering diagram of a semiconductor wafer bonding apparatus according to an embodiment of the present invention, showing the plasma treatment and bonding process of a semiconductor wafer.

[0022] Figure 4This is an example flowchart of high-frequency ion flow activation bonding treatment.

[0023] Figure 5 This is a plan view of a semiconductor manufacturing system assembled from a semiconductor wafer bonding apparatus according to one embodiment of the present invention.

[0024] Figure 6 This is a side view of a semiconductor manufacturing system assembled from a semiconductor wafer bonding apparatus according to one embodiment of the present invention.

[0025] Figure 7 This is a diagram illustrating the structure of a unipolar electrostatic chuck.

[0026] Figure 8 This is a diagram illustrating the structure of a bipolar electrostatic chuck.

[0027] Figure 9 This is a configuration diagram of a semiconductor wafer bonding apparatus of one embodiment of the present invention, showing the state of a bipolar electrostatic chuck bonding a semiconductor wafer. Detailed Implementation

[0028] First, an embodiment of the present invention, a semiconductor wafer bonding apparatus and bonding method, will be described.

[0029] One embodiment of the present invention is a semiconductor wafer bonding apparatus and bonding method. A plasma chamber or a vacuum chamber is used to perform bonding between semiconductor wafers. The plasma chamber or vacuum chamber may also be referred to as a bonding chamber, bonding assembly, bonding apparatus, bonding device, etc.

[0030] [Technical Logic of the Invention]

[0031] The technical logic of this invention is that a semiconductor wafer bonding device improves the bonding strength by bonding a pair of opposing wafers to each other by utilizing radio frequency high-frequency ion flow and Coulomb force (also known as "electrostatic force", hereinafter the same) inside a vacuum chamber where the wafer is subjected to plasma treatment, i.e. in a vacuum environment (plasma environment).

[0032] The aforementioned vacuum chamber contains a pair of wafer holding mechanisms, which are positioned opposite each other on a stage. While the wafers are held in place by the wafer holding mechanisms, plasma is applied between the wafers, causing at least one of the wafer holding mechanisms to move, thereby bonding the opposing wafers together.

[0033] Here, before bonding the opposing wafers to each other, a silicon electrode is prepared on one of the wafers, and a semiconductor wafer is used on the other wafer. Ideally, after performing a first plasma activation treatment on the silicon electrode and the other semiconductor wafer, the silicon electrode is replaced with a bonding wafer, and a second plasma activation treatment is performed on the bonding wafer and the semiconductor wafer.

[0034] Between the first plasma treatment and the second plasma treatment, the oxide film formed on the opposing semiconductor wafer surfaces can be removed by supplying an etching gas.

[0035] The technical concept of the present invention described above is not limited to bonding apparatus for semiconductor wafers, but is also applicable to bonding methods for semiconductor wafers having the same characteristics described above.

[0036] [Structure of a semiconductor wafer bonding device]

[0037] like Figure 1 As shown, the semiconductor wafer bonding apparatus 34 of this embodiment is used to bond various wafers together. It should be noted that the semiconductor wafer and bonding wafer can be, for example, silicon wafers, but are not limited to silicon wafers. It is also possible to use semiconductor wafers of different materials that have been used previously, or to bond semiconductor wafers of different materials together.

[0038] like Figure 1 As shown, the semiconductor wafer bonding apparatus 34 includes a chamber 14 serving as a housing, a first stage 36 located on the upper side of the chamber, and a second stage 38 located on the lower side of the chamber. A first wafer holding mechanism 102 capable of holding a semiconductor wafer or an electrode (e.g., a silicon target) is disposed on the first stage 36. A second wafer holding mechanism 104 capable of holding a semiconductor wafer or an electrode (e.g., a silicon target) is disposed on the second stage 38.

[0039] Alternatively, the chamber 14 or bonding device 34, which serves as the outer shell, can also be referred to as a "vacuum chamber".

[0040] Here, the first stage 36 and the second stage 38, or the first wafer holding mechanism 102 and the second wafer holding mechanism 104, may use, for example, an electrostatic chuck or a mechanical clamp. It should be noted that the electrostatic chuck may, for example, use... Figures 7 to 9 The electrostatic chucks shown are 78 and 80. Regarding... Figures 7 to 9 The structure of the electrostatic chucks 78 and 80 will be described later.

[0041] In addition, such as Figure 2As shown, a first replacement device 106 is provided on or near the first stage 36 on the upstream side of the direction of gravity to replace the first wafer fixing mechanism 102 and the semiconductor wafer W1 or silicon target G1 held by the first wafer fixing mechanism 102 with semiconductor wafers or silicon targets held by other wafer fixing mechanisms. It should be noted that although it is ideal to replace the silicon target G1 and the semiconductor wafer W1 in groups, with the silicon target G1 and the first wafer fixing mechanism 102 holding the silicon target G1 as one group and the semiconductor wafer W1 and the first wafer fixing mechanism 102 holding the semiconductor wafer W1 as another group, this method is not limited to this approach.

[0042] Silicon sputtering targets G1 are known, for example, also referred to as virtual wafers or bare silicon wafers.

[0043] The semiconductor wafer W1 held by the first wafer fixing mechanism 102 may include, for example, a bonding wafer G2 in addition to the silicon wafer electrode G1.

[0044] The first replacement device 106 is not limited to a structure located on one side of the first stage 36, but can also be used as another structure of the bonding device 34, or configured outside the bonding device 34.

[0045] Additionally, a second replacement device 108 may be configured at or near the second stage 38 on the downstream side of the direction of gravity to replace the second wafer fixing mechanism 38 and the semiconductor wafer W2 or silicon target held by the second wafer fixing mechanism 38 with semiconductor wafer W2 or silicon target held by other wafer fixing mechanisms. It should be noted that the replacement process of the silicon target and the semiconductor wafer W2 is preferably performed in groups, with the silicon target and the second wafer fixing mechanism 104 holding the silicon target as one group, and the semiconductor wafer W2 and the second wafer fixing mechanism 104 holding the semiconductor wafer W2 as another group, but it is not limited to this method.

[0046] The second replacement device 108 is not limited to a structure located on one side of the second stage 38, but can also be used as another structure of the bonding device 34, or configured outside the bonding device 34.

[0047] In addition, either the first replacement device 106 or the second replacement device 108 is preferably configured with at least one of them.

[0048] Here, the first replacement device 106 and the second replacement device 108 may be, for example, a robotic arm, but are not limited thereto.

[0049] Semiconductor wafers W1 held by the first wafer fixing mechanism 102 and semiconductor wafers W2 held by the second wafer fixing mechanism 104 can be, for example, Si wafers or SiC wafers, but are not limited thereto.

[0050] like Figure 1 As shown, the high-frequency power supply 110 is connected to the first stage 36 and the second stage 38, respectively. The high-frequency power supply 110 has the capability to generate a high-frequency electric field (13.56MHz, 200W). By applying the high-frequency power supply 110, the electric field promotes the flow and diffusion of atoms, thereby improving the bonding tightness of the bonding surfaces of semiconductor wafers W1 and W2.

[0051] The semiconductor wafer bonding apparatus 34 is equipped with an automatic pressure control device 112 (APC) that controls the internal pressure of the housing. The pressure inside the housing is controlled by the automatic pressure control device 112.

[0052] The bonding device 34 for the semiconductor wafer is equipped with a turbomolecular pump 114 (TMP). The turbomolecular pump 114, for example, consists of a rotor (moving blades) and a stator (stationary blades) having turbine-type blades.

[0053] The turbomolecular pump 114 is a 1×10 -6 High-performance pump with fast exhaust speed in high vacuum environments.

[0054] [Effect of semiconductor wafer bonding devices]

[0055] The bonding between the individual wafers has become stronger.

[0056] When bonding semiconductor wafers requiring different plasma processing times, the plasma processing time can be shortened by using a semiconductor wafer with a shorter required plasma processing time as the bonding wafer and replacing it with the silicon target. This allows for shorter plasma processing times on the bonding wafers. Consequently, the surface of the bonding wafers does not deteriorate due to longer plasma processing times, preventing quality degradation in semiconductor products (semiconductor devices, etc.) formed by bonding individual wafers.

[0057] [Execution of the first plasma treatment]

[0058] like Figure 1 and Figure 2As shown, the semiconductor wafer bonding apparatus 34 has a parallel planar electrode structure. The interior of the housing is placed in a vacuum. With a silicon target G1 (e.g., also called a "silicon wafer electrode") held by a first wafer holding mechanism 102 and a semiconductor wafer W2 (e.g., a silicon wafer) held by a second wafer holding mechanism 104, a first plasma treatment is performed using argon plasma or the like. Here, inside the vacuum chamber 14, silicon is sputtered from the silicon target G1 using argon plasma, and the surface of the semiconductor wafer W2 held by the second wafer holding mechanism 104 is activated by the plasma, forming a silicon-based vapor-deposited film X on the surface of the semiconductor wafer W2. Furthermore, when activating the surface of the semiconductor wafer W2 with plasma, gases such as argon (Ar) or nitrogen (N2) are used to remove oxide films and contaminants from the surface of the semiconductor wafer W2, respectively. The same effect is achieved when activating the surface of the semiconductor wafer W2 in the second plasma treatment.

[0059] Here, since a high-frequency power supply 110 is used, the energy is reduced, which can reduce plasma damage on the surface of the semiconductor wafer W2. In addition, a thin vapor-deposited film X is formed on the semiconductor wafer W2 by sputtering the plasma electrode G1, which serves as the silicon wafer electrode.

[0060] Isotropic etching

[0061] Additionally, between the first plasma treatment and the second plasma treatment described below, an isotropic etching process can be performed to remove the oxide film formed on the surface of the semiconductor wafer W2 by supplying an etching gas such as SF6. After the isotropic etching process, the plasma gas is switched to argon (gas replacement), and the wafer surface is activated in the second plasma treatment.

[0062] [Execution of the second plasma treatment]

[0063] Next, the silicon target G1 is replaced with a bonding wafer G2, i.e., a semiconductor wafer W1. For example, a silicon wafer or other semiconductor wafer, but not limited to silicon. The replacement process of the silicon target G1 and the bonding wafer W1 can be performed, for example, by replacing the silicon target G1 and the first wafer holding mechanism 102 holding the silicon target G1 as one set of components with another set of components consisting of the bonding wafer G2 and the first wafer holding mechanism 102 holding the bonding wafer G2. Alternatively, the first wafer holding mechanism 102 can remain unchanged and be used together, separating the silicon target G1 from the first wafer holding mechanism 102 and then holding the bonding wafer G2 within the first wafer holding mechanism 102. During and after the replacement process, plasma treatment is performed using gases such as argon (Ar) or nitrogen (N2) to activate the surfaces of the bonding wafer G2 held by the first wafer holding mechanism 102 and the semiconductor wafer W2 held by the second wafer holding mechanism 104. The oxide films and contaminants on the surfaces of the bonding wafer G2 held by the first wafer holding mechanism 102 and the semiconductor wafer W2 held by the second wafer holding mechanism 104 are removed respectively. Then, under the continuous application of the high-frequency power supply 110, the supply of gases such as argon (Ar) or nitrogen (N2) is stopped, and the automatic pressure control device 112 is driven at high output to bring the vacuum level inside the chamber 14 to the target vacuum level (e.g., 1×10⁻⁶) within approximately 10 seconds. -6 At this time, the plasma disappears, but the surfaces of the bonding wafer G2 held by the first wafer fixing mechanism 102 and the semiconductor wafer W2 held by the second wafer fixing mechanism 104 are respectively in an ion-polarized state.

[0064] The time required for the interior of chamber 14 to reach a vacuum level is not limited to approximately 10 seconds; for example, it can be set in the range of 1 to 30 seconds, more preferably in the range of 1 to 15 seconds, and even more preferably in the range of 1 to 10 seconds. The faster the time required for the interior of chamber 14 to reach a vacuum level, the better.

[0065] [Execution of wafer bonding process]

[0066] In this state, for example, Figure 3As shown, by moving the first stage 36 and / or the second stage 38 closer together, the spacing between the bonding wafer G2 held by the first wafer fixing mechanism 102 and the semiconductor wafer W2 held by the second wafer fixing mechanism 104 is reduced. Due to the Coulomb force (electrostatic force) generated on their surfaces, the interatomic spacing between the wafers becomes closer, and they will soon come into contact. At this time, the first stage 36 can be fixed, and the second stage 38 can be moved closer to the first stage 36. Alternatively, the second stage 38 can be fixed, and the first stage 36 can be moved closer to the second stage 38. The initial bonding force between the bonding wafer G2 held by the first wafer fixing mechanism 102 and the semiconductor wafer W2 held by the second wafer fixing mechanism 104 becomes stronger. However, even after the wafers G2 and W2 are in contact with each other, by continuing to apply the high-frequency power supply 110, the RF high frequency flows between the surfaces of each wafer G2 and W2. Due to the ion flow (atomic diffusion) generated by the electric field, the bonding between the two becomes stronger.

[0067] The semiconductor wafer manufacturing method of this embodiment is an industry-first manufacturing method, called high-frequency ion flow activated bonding (RF Ion Flow Bonding, RFIFB).

[0068] In addition, for the bonding wafer G2 held by the first wafer fixing mechanism 102, the plasma processing is performed only once, while for the semiconductor wafer W2 held by the second wafer fixing mechanism 104, the plasma processing is performed twice.

[0069] Furthermore, instead of the first wafer fixing mechanism 102 and the silicon target G1 held by the first wafer fixing mechanism 102, a bonding wafer G2 held by another first wafer fixing mechanism 102 and a bonding wafer G2 held by the second wafer fixing mechanism 104 is preferred, but not limited to, a structure in which the bonding wafer G2 held by the first wafer fixing mechanism 102 is bonded to the semiconductor wafer W2 held by the second wafer fixing mechanism 104. Additionally, it is preferable that the first wafer fixing mechanism 102 is located upstream (upper) in the direction of gravity, and the second wafer fixing mechanism 104 is located downstream (lower) in the direction of gravity.

[0070] On the one hand, as an existing technology, there is atomic diffusion bonding (ADB). Atomic diffusion bonding is a technique known as room temperature activated bonding, which is known to activate the semiconductor wafer surface through Ar beam or Si sputtering. However, regardless of the method, it takes several minutes to bond the activated semiconductor wafers together.

[0071] Generally, because the activated state of a semiconductor wafer surface deteriorates in a short time, it is necessary to quickly evacuate the vacuum and perform bonding.

[0072] Therefore, according to this embodiment, after the wafer surface is activated by plasma treatment, for example within about 10 seconds, a turbomolecular pump 114 is used to evacuate to the ultimate pressure, and the wafers are bonded together to minimize the activity decay after the wafer surface is activated, thereby achieving a bonding interface with an ultimate atomic diffusion effect.

[0073] In other words, this embodiment provides a vertically oriented parallel flat plasma electrode device, characterized by the provision of upper and lower electrodes to maintain the wafer structure (e.g., electrostatic chuck, mechanical clamp, etc.), wherein one electrode is designed to be replaceable with the bonding wafer.

[0074] According to this embodiment, sputtering of the silicon target G1 causes surface roughness of the electrode, resulting in the formation of microparticles within the parallel planar wafer plasma, thus creating voids. Furthermore, the silicon grown from secondary sputtering detaches from the surface of the silicon target G1. These detached silicon particles continue to undergo Brownian motion and remain suspended, contributing to the formation of wafer void defects. However, in this embodiment, since the silicon target G1 (e.g., a bare silicon wafer) is used instead of the bonding wafer G2 in the initial stage, the damage to the bonding wafer G2 caused by voids can be reduced. Therefore, this method avoids quality degradation and deterioration of the semiconductor product obtained through bonding the bonding wafer G2 to the semiconductor wafer W2. Additionally, the silicon target G1 is preferably replaced periodically, once or multiple times.

[0075] As described above, by surface activation of the wafers used on one or both sides of the parallel plate and by soft sputtering by applying a high-frequency power supply 110 to the silicon target G1, an extremely thin vapor-deposited film X of high purity Si is generated on the processed surface of the semiconductor wafer W2 opposite to the silicon target G1.

[0076] In a plasma environment, the surface of the semiconductor wafer W2 is bombarded by ions, thus exposing a clean surface. After the surface of the semiconductor wafer W2 is cleaned, a high-frequency power supply 110 of different frequencies is applied to the silicon target G1 (e.g., a silicon wafer) located at the upper part (upper side). As a result, tiny Si particles fly out from the silicon target G1 and accumulate on the surface of the semiconductor wafer W2 located at the lower part (lower side), forming a thin film, namely the vapor-deposited film X, which is formed by vapor deposition.

[0077] Alternatively, this step can be omitted if it is not necessary to form a thin film by vapor deposition.

[0078] Secondly, during the bonding process between the bonding wafer G2 and the semiconductor wafer W2, for example, when the bonding wafer G2 is positioned as an electrode on the upper part (upper side), the surface of the bonding wafer G2 is activated using a gas such as argon (Ar) or nitrogen (N2). At this time, the surface of the semiconductor wafer W2, which is positioned on the lower part (lower side), is also activated. Therefore, the surface activation of the bonding wafer G2 is performed only once, and the surface activation of the semiconductor wafer W2 is performed only twice.

[0079] Inside chamber 14, which serves as an outer shell, opposing electrodes are arranged to apply plasma pressure and maintain it at the highest possible vacuum level, thereby activating the surfaces of the two wafers (bonding wafer G2 and semiconductor wafer W2). As an electrode structure, magnetrons, ICP coils, and other components can be added to maintain the plasma under high vacuum.

[0080] Furthermore, after plasma surface activation, the spacing between the bonding wafer G2 disposed on the upper side and the semiconductor wafer W2 disposed on the lower side should be as narrow as possible. Similarly, the spacing between the silicon target G1 disposed on the upper side and the semiconductor wafer W2 disposed on the lower side should also be as narrow as possible. For example, during plasma processing, this spacing should be the smallest possible between electrodes capable of uniformly applying plasma, and after processing, when changing the pressure to a high vacuum, it can be in the range of 10 μm to 50 μm. This is because by reducing the spacing, external particles are less likely to intrude between the electrodes, preventing particle contamination during the wafer bonding process, and shortening the time from reaching a vacuum state to bonding.

[0081] After activating the surfaces of the bonding wafer G2 and the semiconductor wafer W2 by plasma treatment, the supply of gases such as argon (Ar) or nitrogen (N2) is stopped, and the automatic pressure control device 112 is driven to reach the ultimate vacuum pressure of the turbomolecular pump 114 (or cryogenic pump) within, for example, about 10 seconds. At this time, the high-frequency power supply 110 is continuously applied, but is not limited to this.

[0082] Thus, polarized ions (electrons) remain on the surfaces of the bonding wafer G2 and the semiconductor wafer W2, respectively. During the bonding of the bonding wafer G2 and the semiconductor wafer W2 in a high vacuum, the increased atomic motion due to the charged ion potentials on the surfaces of the bonding wafer G2 and the semiconductor wafer W2 makes it easier for atoms to temporarily move on their respective surfaces. Furthermore, applying a high-frequency power supply 110 after bonding the bonding wafer G2 and the semiconductor wafer W2 further increases atomic motion, making it easier for atoms to temporarily move on their respective surfaces. Through these synergistic effects, atoms are reconfigured to a more stable energy state. Especially when the surfaces of the bonding wafer G2 and the semiconductor wafer W2 are activated, atoms are more easily reconfigured to more ideal positions. As a result, the energy on the surfaces of the bonding wafer G2 and the semiconductor wafer W2 is minimized, and the bonding strength between the bonding wafer G2 and the semiconductor wafer W2 is improved.

[0083] Generally, the time from plasma activation of the wafer surface to bonding of the semiconductor wafers, the time for transferring the semiconductor wafers from the plasma processing chamber to the bonding chamber, and the time for plasma processing and handling of the second semiconductor wafer, combined with these factors, result in a waiting period of several minutes. During this period, the surface activity of the semiconductor wafers deteriorates by approximately 10% to 50% immediately after the plasma processing (deterioration rate 10% to 50%).

[0084] In contrast, in this embodiment, since instantaneous bonding is performed immediately after plasma treatment of the bonding wafer G2 and the semiconductor wafer W2, the bonding wafer G2 and the semiconductor wafer W2 are bonded while the activation state on the respective surfaces of the bonding wafer G2 and the semiconductor wafer W2 maintains a decay rate of less than 1%. As a result, the bonding between the bonding wafer G2 and the semiconductor wafer W2 becomes strong.

[0085] [No void bonding]

[0086] Most voids are caused by silicon sputtering debris and particles within the cavity. Frequent replacement of the silicon target G1 eliminates sputtering debris and particles, thereby reducing voids. Furthermore, in vacuum plasma, organic matter that serves as a seed for intrusive voids between the bonding wafer G2 and the semiconductor wafer W2 is removed. Moreover, the plasma prevents organic matter from intruding between the wafers from the outside. Through these measures, void-free bonding is achieved.

[0087] [Characteristics of high-frequency ion flow-activated bonding]

[0088] High-frequency ion flow activated bonding has the following characteristics.

[0089] (1) By plasma treatment and instantaneous vacuum management and control, the activation and cleaning of the wafer surface can be achieved.

[0090] (2) Coulomb force (electrostatic force) can be used to strengthen the initial bonding force between wafers.

[0091] (3) By promoting the flow and diffusion of atoms through high-frequency power supply (RF high frequency), the bonding strength between wafers can be improved.

[0092] [Flowchart of High-Frequency Ion Flow Activation Bonding Treatment]

[0093] The following is an example of a high-frequency ion flow activation bonding process.

[0094] like Figure 4 As shown, for example, a wafer is removed from the wafer cassette (S100), and wafer alignment is performed (S200). The wafer is cleaned (S300), and then transported to the loading and locking chamber (S400). The wafer undergoes plasma treatment (S500), and the wafers are bonded together (S600). Afterwards, the semiconductor product formed by the wafer bonding is removed from the loading and locking chamber (S700), and the semiconductor product is inspected (S800).

[0095] Here, for example, the time required from the end of the plasma processing step (S500) of the wafer to the end of the bonding step (S600) is preferably less than 10 seconds.

[0096] As described above, for example, by using the Coulomb force control of the ESC chuck to assist bonding, misalignment can be prevented when opposite wafers come into contact with each other, and high-strength bonding can be achieved through high-frequency ion flow activated bonding technology.

[0097] (Example)

[0098] Next, examples of high-frequency ion flow-activated bonding will be described.

[0099] [Overview]

[0100] (1) In the parallel planar electrode construction, two silicon wafers are placed in a vacuum.

[0101] (2) A replaceable silicon wafer electrode is used on one side, and the surface of the silicon wafer electrode is activated by argon plasma.

[0102] (3) Silicon sputtered from the silicon wafer electrode surface is deposited onto the semiconductor wafer surface opposite the silicon wafer electrode by sputtering vapor deposition.

[0103] [project]

[0104] (1) Surface activation via silicon wafer electrodes

[0105] The silicon wafer electrode and the surface of the semiconductor wafer opposite the silicon wafer electrode are activated by plasma treatment using argon plasma (first time), and silicon is sputtered from the silicon wafer electrode.

[0106] The silicon wafer electrodes are replaced with bonded wafers that serve as bonding targets.

[0107] Argon plasma treatment (second time) is performed on the bonded wafer and semiconductor wafer. After the gas supply is stopped, a turbomolecular pump or similar device is used to achieve an ultimate vacuum level, for example, within about 10 seconds.

[0108] By evacuating the vacuum, the plasma disappears, but ions remain in a polarized state on the surfaces of the mating wafer and the semiconductor wafer, which are facing each other.

[0109] (2) Bonding between wafers

[0110] The ions trapped on the surfaces of the bonding wafer and the semiconductor wafer due to polarization generate Coulomb force (electrostatic force), which reduces the interatomic spacing between the wafers and brings them into contact.

[0111] Radio frequency high-frequency current flows on the surface of each wafer, and the electric field induces ion flow (atomic diffusion), thereby achieving strong bonding between wafers.

[0112] [Specific Structure]

[0113] (1) Parallel planar plasma electrode structure

[0114] (1-1) Wafer holding mechanism

[0115] As the wafer holding mechanism, electrostatic chucks or mechanical clamps are used to ensure that the upper and lower electrodes can hold each wafer separately.

[0116] At least one of the upper or lower electrodes should be designed with a replaceable bonding wafer structure. Replacement is best performed by a robotic arm or similar device. Furthermore, it is preferable to replace the bonding wafer of the upper electrode. This helps suppress particles generated due to electrode surface roughness.

[0117] (1-2) Electrode sputtering

[0118] As electrodes, silicon targets made from bare silicon wafers are used to control particles during the plasma processing. This reduces voids generated during the bonding of bonding wafers to semiconductor wafers.

[0119] (1-3) Surface activation of opposing single-sided or double-sided wafers

[0120] By applying a high-frequency power supply to each electrode for soft sputtering, silicon sputtered from the electrodes accumulates on the opposing wafer surfaces, forming a high-purity thin silicon film. Alternatively, the step of forming the high-purity silicon film (silicon thin film) can be omitted if necessary.

[0121] High-frequency power supplies of different frequencies can also be applied to the upper electrode to sputter silicon (Si).

[0122] (2) Setting up the bonding wafer

[0123] (2-1) Activation of wafer surface using gas

[0124] The wafer surface is activated using Ar (argon) or N2 (nitrogen) gas.

[0125] For two wafers placed one above the other, plasma processing is performed simultaneously in one chamber.

[0126] (2-2) Plasma treatment

[0127] Plasma processing is performed in a high vacuum. Magnetrons or ICP coils can be used.

[0128] The electrode space adopts a structure that ensures uniform plasma flow and is not affected by external factors such as dust intrusion.

[0129] (2-3) Vacuuming after plasma treatment

[0130] Stop supplying argon and nitrogen to the chamber and activate the automatic pressure control device (APC) to bring the chamber pressure to the ultimate vacuum pressure, for example, in about 10 seconds via a turbomolecular pump.

[0131] Depending on the product, you can continue to apply high-frequency power to the upper and lower electrodes, or you can stop applying it.

[0132] (2-4) Vacuum bonding (vacuum bonding)

[0133] The charged wafers are brought close together and brought into contact using Coulomb force (electrostatic force). This Coulomb force enhances the initial bonding strength between the wafers. Furthermore, the increased atomic movement due to the Coulomb force makes it easier for atoms residing on each wafer surface to move.

[0134] By applying a high-frequency power supply to each electrode, atoms rearrange to a stable energy state, thereby forming a strong bond between wafers.

[0135] (3) Instant bonding of wafers after plasma treatment (instant bonding)

[0136] After the surface of each wafer is activated, bonding is performed, for example, over a period of about 10 seconds, thereby maximally suppressing the degradation of the active state (activity) of the wafer surface.

[0137] In contrast, in conventional room-temperature activated bonding or atomic diffusion bonding, the bonding between wafers requires time. Specifically, if a waiting time of several minutes occurs, the active state will decrease by approximately 20%. Semiconductor wafer products have previously experienced quality degradation issues, but this problem has been solved through the high-frequency ion flow activated bonding of this embodiment.

[0138] [In high vacuum (1×10)] -6 [Pa) Attenuation rate after surface activation]

[0139] The decay rate after 10 seconds in a vacuum is: A(10 seconds) ≈ 99.83%, A(10 seconds) = 99.83%, which means the decay rate is 0.17%.

[0140] The decay rate after 2 minutes in a vacuum is: A(2 minutes) ≈ 81.87%, A(2 minutes) = 81.87%, which means the decay rate is 18.13%.

[0141] In summary, rapid vacuuming and wafer bonding are crucial for maintaining the surface activation state, and the results demonstrate that a strong bond between wafers can be achieved.

[0142] Next, the silicon wafers were subjected to plasma treatment in a vacuum to activate their surfaces. After the gas supply was stopped, the surface activity was maintained under high-speed vacuum. The wafers were then bonded together, and a high-frequency power supply was applied to analyze the ion diffusion in the high-frequency ion flow activation bonding process.

[0143] [High-frequency ion flow activated bonding process]

[0144] (1) Plasma surface activation

[0145] Organic contaminants and oxides on the wafer surface are chemically removed by plasma etching using fluorine-based gases. Argon sputtering removes any remaining minute contaminants and uneven chemical residues. While the wafer surface is cleaned through activation and plasma etching, argon sputtering physically impacts the surface, further activating the atoms and improving bonding efficiency between wafers.

[0146] Due to the dual effects of wafer surface cleaning and activation, atoms can diffuse, resulting in higher bonding strength between wafers.

[0147] (2) Gas stoppage and high-speed vacuum pumping

[0148] After plasma treatment of the wafer, the supply of argon and nitrogen is stopped, and a turbomolecular pump is used for control to achieve a high vacuum (1×10⁻⁶) at high speed. -6 Pa).

[0149] By reaching the ultimate vacuum level within approximately 10 seconds, the activated state of the wafer surface is maintained.

[0150] (3) Wafer bonding

[0151] The wafers are bonded together while polarized ions remain on the surface of each wafer.

[0152] Due to Coulomb force (electrostatic force), the interatomic spacing between closely spaced wafer surfaces decreases, thus strengthening the contact between wafers.

[0153] (4) Apply high-frequency power supply

[0154] After the wafers are bonded together, a high-frequency power supply is applied to generate an electric field on the surface of each wafer.

[0155] This electric field causes ions to flow on the wafer surface, strengthening the bonds between atoms.

[0156] [A Discussion on Ion Diffusion]

[0157] (1) State of ions on the wafer surface

[0158] Due to the activation effect of plasma treatment, the ions remaining on the wafer surface are in a polarized state.

[0159] Ions in a polarized state are strongly adsorbed onto the wafer surface, making their movement easier.

[0160] In a high vacuum environment, the electrodes are in an insulating state, and ions will not ionize (discharge), but will remain on the wafer surface.

[0161] (2) High vacuum state

[0162] In a high vacuum, the active state of the wafer surface is maintained, and recontamination of the wafer surface is suppressed.

[0163] (3) Effects of high-frequency power supply

[0164] The high-frequency electric field (13.56MHz, 200W) has the following effects on the wafer surface and interface.

[0165] (3-1) Fluctuations in surface potential

[0166] Due to the high-frequency electric field, an alternating electric field is generated on the wafer surface. As a result, the potential on the wafer surface fluctuates, causing the following effects.

[0167] Surface potential fluctuations: A potential of ±200V fluctuates at a frequency of 13.56MHz, causing the movement of electrons and ions on the wafer surface.

[0168] The effects of high-frequency electric fields: Due to the high-frequency electric field (alternating electric field), the atoms and ions on the wafer surface rearrange.

[0169] (3-2) Promote atomic diffusion at the interface

[0170] High-frequency electric fields have the following effects on the wafer surface.

[0171] Ion movement: Alternating electric fields make it easier for ions to move on the wafer surface.

[0172] Changes between atoms: Alternating electric fields cause changes in the interatomic forces between wafers, resulting in stronger bonds.

[0173] The reduction in activation energy: The alternating electric field reduces the energy required for atomic diffusion, thus promoting interatomic bonding.

[0174] [Mechanism of ion diffusion]

[0175] By applying a high-frequency power source, ions diffuse through the following mechanism.

[0176] (1) Ion movement induced by electric field

[0177] Due to the high-frequency electric field (the effect generated by the high-frequency electric field), ions on the wafer surface are attracted or squeezed out. As a result, ions move uniformly across the entire wafer surface.

[0178] (2) Surface diffusion

[0179] Ions move on the wafer surface, causing atoms to rearrange.

[0180] A more stable energy state is formed by rearranging the atoms on the wafer surface.

[0181] (3) Strengthening of interatomic bonds

[0182] By rearranging the atoms on the wafer surface, the bonds between atoms are strengthened. As a result, the bonding between wafers becomes stronger.

[0183] According to the high-frequency ion flow activated bonding process, specifically by chemically reacting a silicon wafer in a vacuum to isotropically etch the oxide film on the wafer surface, followed by soft sputtering with argon gas to activate the wafer surface. Then, a high-vacuum environment is created, for example, at a high speed of about 10 seconds, and the wafers are bonded together while maintaining the activated state of the wafer surface. Furthermore, by continuously applying a high-frequency power supply between the wafers, ions on the wafer surface diffuse and move, strengthening the interatomic bonds. Thus, the bonding between the wafers becomes stronger. Therefore, high-frequency ion flow activated bonding technology is very effective in wafer bonding, simultaneously improving both bonding strength and bonding quality between wafers.

[0184] Furthermore, frequent automatic electrode replacement and the use of bare wafers help reduce the flakes and particles formed by silicon sputtering, achieving void-free bonding. This significantly reduces the frequency of cleaning within the chamber, helping to decrease equipment maintenance time and improve equipment uptime.

[0185] [An example of a semiconductor manufacturing system]

[0186] An example of assembling a semiconductor wafer bonding apparatus into a semiconductor manufacturing system according to this embodiment and example will be described.

[0187] like Figure 5 and Figure 6 As shown, the bonding device 34 for semiconductor wafers can also be assembled into the semiconductor manufacturing system 200 to replace the plasma chamber 10 of the conventional system. Figure 5 and Figure 6 The semiconductor manufacturing system 200 shown has a central chamber 202 housing a robotic arm, and around it are a semiconductor wafer bonding device 34 for plasma processing and inter-wafer bonding, a vacuum bonding chamber 204, an atomic bonding chamber 206, a rotary cleaning chamber 208, a standby chamber 210, and a load locking chamber 212. Near the load locking chamber 212 are a wafer transport mechanism 214 and multiple wafer cassettes 216.

[0188] [An example of a wafer holding mechanism]

[0189] Next, an example of a wafer holding mechanism used to hold each wafer will be described.

[0190] Regarding the semiconductor wafer bonding apparatus and bonding method of this embodiment, an electrostatic chuck 80 (see reference) is provided as a wafer holding mechanism on the first stage 36 and the second stage 38 used to hold the semiconductor wafers W1 and W2. Figures 7 to 9 Alternatively, an electrostatic chuck 80 can be used as an alternative (see reference). Figures 7 to 9The structure is configured with the first wafer fixing mechanism 102 and the second wafer fixing mechanism 104.

[0191] Figure 7 and Figure 8 The structures of a unipolar electrostatic chuck 78 and a bipolar electrostatic chuck 80 are shown. The electrostatic chucks 78 and 80 are made of insulating materials such as alumina (Al2O3) and aluminum nitride (ALN). Their structure consists of an electrode built into the insulator, which is applied to the electrode to attract semiconductor wafers W1, W2, and other objects 86 and 92.

[0192] Figure 7 The unipolar electrostatic chuck 78 shown is unipolar and includes a base substrate 82 and an internal electrode (also called an electrode sheet or polyimide film electrode layer) 84 disposed on the base substrate 82. The base substrate 82 applies a positive (+) or negative (-) voltage to the internal electrode 84. For example, when a positive (+) voltage is applied to the internal electrode 84, negative (-) charges move on the surface of the object to be attracted 86, and the object to be attracted 86 is attracted by the unipolar electrostatic chuck 78. Conversely, when a negative (-) voltage is applied to the internal electrode 84, positive (+) charges move on the surface of the object to be attracted 86, and the object to be attracted 86 is attracted by the unipolar electrostatic chuck 78.

[0193] Figure 8 The electrostatic chuck 80 shown is bipolar, having a base substrate 88 and internal electrodes (also called electrode sheets or polyimide film electrode layers) 90 disposed on the base substrate 88. The base substrate 88 applies both positive (+) and negative (-) voltages to the internal electrodes 90. For example, on the surface of the object 92 opposite to the internal electrode 90 to which a positive (+) voltage is applied, negative (-) charges move, and on the surface of the object 92 opposite to the internal electrode 90 to which a negative (-) voltage is applied, positive (+) charges move, thereby causing the object 92 to be adsorbed onto the bipolar electrostatic chuck 80.

[0194] This section illustrates an example of using a bipolar electrostatic chuck in a semiconductor wafer bonding apparatus. For example... Figure 9 As shown, the electrostatic chucks 80 are preferably built into the first stage 36 and the second stage 38, respectively. For ease of explanation, the electrostatic chuck 80 built into the first stage 36 is referred to as the first electrostatic chuck 80A, and the electrostatic chuck 80 built into the second stage 38 is referred to as the second electrostatic chuck 80B. Each electrostatic chuck 80A and 80B is, for example, bipolar. Since the first stage 36 and the second stage 38 are arranged opposite each other, the electrostatic chucks 80A and 80B are arranged in opposite positions, thus forming a pair of electrostatic chucks.

[0195] The first electrostatic chuck 80A has a first base substrate 88A and a first internal electrode 90A disposed on the first base substrate 88A. The first internal electrode 90A is grounded. The first base substrate 88A controls the voltage applied to the first internal electrode 90A. The first internal electrode 90A is composed of two or more adjacent first unit electrodes 91A, and positive and negative voltages are applied between adjacent first unit electrodes 91A respectively.

[0196] The second electrostatic chuck 80B is positioned opposite the first electrostatic chuck 80A. The second electrostatic chuck 80B has the same structure as the first electrostatic chuck 80A, including a second base substrate 88B and a second internal electrode 90B disposed on the second base substrate 88B. The second internal electrode 90B is grounded. The second base substrate 88B controls the voltage applied to the second internal electrode 90B. The second internal electrode 90B is composed of two or more adjacent second unit electrodes 91B, with opposite voltages applied between adjacent second unit electrodes 91B.

[0197] Here, the first unit electrode 91A on the side of the first electrostatic chuck 80A and the second unit electrode 91B on the side of the second electrostatic chuck 80B, which are opposite to the first unit electrode 91A, are controlled by the first base substrate 88A and the second base substrate 88B, respectively, to apply voltages of opposite polarities (positive and negative). Therefore, the first unit electrode 91A in the first internal electrode 90A of the first electrostatic chuck 80A, which is subjected to a negative (-) voltage, is positioned opposite to the second unit electrode 91B in the second internal electrode 90B of the second electrostatic chuck 80B, which is subjected to a positive (+) voltage. Similarly, the first unit electrode 91A in the first internal electrode 90A of the first electrostatic chuck 80A, which is subjected to a positive (+) voltage, is positioned opposite to the first unit electrode 91B in the second internal electrode 90B of the second electrostatic chuck 80B, which is subjected to a negative (-) voltage.

[0198] As per the general principle of the bipolar electrostatic chuck 80, with a semiconductor wafer W1 placed on the first electrostatic chuck 80A and a semiconductor wafer W2 placed on the second electrostatic chuck 80B, a positive voltage and a negative voltage are applied to the first internal electrode 90A and the second internal electrode 90B, respectively. As a result, the positive and negative charges on the semiconductor wafers W1 and W2 move in the direction of attraction to their respective internal electrodes 90A and 90B (dielectric polarization). Consequently, adsorption forces are generated between the first internal electrode 90A and the semiconductor wafer W1, and between the second internal electrode 90B and the semiconductor wafer W2, thereby fixing the semiconductor wafers W1 and W2 in place.

[0199] like Figure 7As shown, generally speaking, in a unipolar electrostatic chuck 78, by applying a voltage between the object being attracted (such as a semiconductor wafer) 86 and the internal electrode 84 (also called a chuck or holding device), a charge is generated on the surface of the object being attracted (such as a semiconductor wafer) 86. Specifically, if the internal electrode 84 is positively (+), then the surface of the object being attracted (such as a semiconductor wafer) 86 opposite to it is negatively (-); and if the internal electrode 84 is negatively (-), then the surface of the object being attracted (such as a semiconductor wafer) 86 opposite to it is positively (+). This principle is... Figure 8 The same applies to the bipolar electrostatic chuck 80 shown.

[0200] Typically, the surfaces of semiconductor wafers W1 and W2, after plasma treatment and activation, will be negatively charged (or possibly positively charged). Therefore, when attempting to bond semiconductor wafers W1 and W2, both with negatively charged (or positively charged) surfaces, they will generate electrical repulsion. In this state, if semiconductor wafers W1 and W2 are forcibly bonded together, they will repel each other, causing positional shifts and resulting in a decrease in the bonding accuracy of semiconductor wafers W1 and W2.

[0201] like Figure 9 As shown, by making the surface of one semiconductor wafer W1, which is facing each other, positively (negatively) charged, and the surface of the other semiconductor wafer W2, negatively (positively) charged, a state with opposite polarity charges is intentionally formed between the semiconductor wafers to be bonded. Thus, for example, the van der Waals forces (intermolecular forces) and Coulomb forces (electrostatic forces) generated between them are used to enhance the adsorption force, thereby assisting the bonding between semiconductor wafers W1 and W2.

[0202] Generally speaking, objects with negative static electricity will repel each other when they approach each other (or objects with positive static electricity will repel each other when they approach each other). This is one of the fundamental properties of static electricity: charges of the same sign (e.g., both are negative) will repel each other, while charges of opposite polarities (e.g., one is positive and the other is negative) will attract each other.

[0203] By making semiconductor wafers W1 and W2 have opposite polarities (reverse polarities) and controlling the voltage between their surfaces to prevent discharge, when the positively (+) charged semiconductor wafer W1 (or W2) comes into contact with the negatively (-) charged semiconductor wafer W2 (or W1), electrons move from the positively (+) charged object to the negatively (-) charged object, thus neutralizing the charge. This reduces the effect of electrostatics and increases the bonding and adsorption forces during bonding.

[0204] In a typical bipolar electrostatic chuck (ESC), the electrical balance of the semiconductor wafer surface is maintained by applying the same voltage (absolute value) to both the positive (+) and negative (-) sides.

[0205] In contrast, instead of applying voltages of equal magnitude (absolute value) for positive and negative (negative) signals, different magnitudes of voltage are deliberately applied to intentionally disrupt the balance between positive and negative (negative) signals. In other words, an imbalance is created between positive and negative voltages by adjusting the magnitude of the applied voltage.

[0206] like Figure 9 As shown, for example, a voltage of -400 volts is applied to the first unit electrode 91A on one side of the first internal electrode 90A constituting the first electrostatic chuck 80A, and a voltage of +500 volts is applied to the first unit electrode 91A on the other side. Simultaneously, a voltage of +400 volts is applied to the second unit electrode 91B on one side of the second internal electrode 90B constituting the second electrostatic chuck 80B, and a voltage of -500 volts is applied to the second unit electrode 91B on the other side.

[0207] Here, in the first internal electrode 90A of the first electrostatic chuck 80A, the first unit electrode 91A on the side where a -400 volt voltage is applied is positioned opposite to the second unit electrode 91B on the side where a +400 volt voltage is applied in the second internal electrode 90B of the second electrostatic chuck 80B. Although their polarities are different, their absolute values ​​are the same.

[0208] Furthermore, the first unit electrode 91A on the side of the first internal electrode 90A of the first electrostatic chuck 80A, to which a +500 volt voltage is applied, and the second unit electrode 91B on the side of the second internal electrode 90B of the second electrostatic chuck 80B, to which a -500 volt voltage is applied, are positioned opposite each other. Although their polarities are different, their absolute values ​​are the same.

[0209] Through these processes, the surface of the semiconductor wafer W1, opposite to the first electrostatic chuck 80A, is charged by the difference of +500 volts and -400 volts, i.e., +100 volts, from the first electrostatic chuck 80A. Similarly, the surface of the semiconductor wafer W2, opposite to the second electrostatic chuck 80B, is charged by the difference of +400 volts and -500 volts, i.e., -100 volts, from the second electrostatic chuck 80B.

[0210] At this point, floating charges will be generated on the surfaces of semiconductor wafers W1 and W2. Consequently, by applying a reverse voltage between the opposing internal electrodes 90A and 90B (or between unit electrodes), semiconductor wafers W1 and W2 will attract and adhere to each other due to a strong Coulomb force. As a result, bubbles generated during the adhesion of semiconductor wafers W1 and W2 can be suppressed.

[0211] Here, semiconductor wafers W1 and W2 are held by a pair of electrostatic chucks 80A and 80B, with the spacing between them preferably set in a micro-space (minimum space) environment of 10μm or more and 50μm or less. Within the micro-space, semiconductor wafers W1 and W2 maintain a planar orientation while being bonded.

[0212] Furthermore, this embodiment and example only demonstrate one aspect of the invention, and the invention is not limited thereto. Differences in design modifications and other aspects of this embodiment and example are, of course, also included within the scope of the technical concept of the invention.

[0213] [Explanation of Symbols]

[0214] 14 chambers

[0215] 16 platforms

[0216] 34 Semiconductor wafer bonding device

[0217] 36. Platform 1

[0218] 38. Second platform

[0219] 78 Unipolar electrostatic chuck

[0220] 80 Bipolar Electrostatic Chuck

[0221] 80A First Electrostatic Chuck

[0222] 80B Second Electrostatic Chuck

[0223] 82 Base substrate

[0224] 84 Internal Electrodes

[0225] 86 Adsorbed body

[0226] 88 base substrate

[0227] 88A First Baseboard

[0228] 88B Second Baseboard

[0229] 90 Internal Electrode

[0230] 90A First Internal Electrode

[0231] 90B Second Internal Electrode

[0232] 91A First Unit Electrode

[0233] 91B Second Unit Electrode

[0234] 92 Adsorbed body

[0235] 102 First Wafer Fixing Mechanism

[0236] 104 Second Wafer Fixing Mechanism

[0237] 106 First Replacement Device

[0238] 108 Second Replacement Device

[0239] 110 High-Frequency Power Supply

[0240] 112 Automatic pressure control device

[0241] 114 turbomolecular pump

[0242] 200 Semiconductor Manufacturing Systems

[0243] 202 Central Chamber

[0244] 204 Vacuum Bonding Chamber

[0245] 206 Atomic Bonding Chamber

[0246] 208 Rotary Cleaning Chamber

[0247] 210 Standby Chamber

[0248] 212 Load-locking chamber

[0249] 214 Wafer Handling Mechanism

[0250] 216 wafer box

[0251] G1 silicon wafer

[0252] G2 bonded wafer

[0253] W1 Semiconductor Wafer

[0254] W2 Semiconductor wafer.

Claims

1. A semiconductor wafer bonding apparatus for plasma processing and bonding of a semiconductor wafer held by parallel planar plasma electrodes, characterized in that, After the semiconductor wafer is plasma-treated to activate its surface, the device is placed in a high vacuum state to polarize ions on the surface of the semiconductor wafer. By applying a high-frequency power supply to the semiconductor wafer, the ions are moved on the surface of the semiconductor wafer, thereby bonding the semiconductor wafers together.

2. The semiconductor wafer bonding apparatus according to claim 1, characterized in that, An electrostatic chuck is used as the parallel plate plasma electrode.

3. A bonding method for semiconductor wafers held by parallel planar plasma electrodes, wherein plasma treatment is performed and bonding is carried out, characterized in that, After plasma treatment to activate the surface of the semiconductor wafer, it is placed in a high vacuum state to polarize the ions on the surface of the semiconductor wafer. By applying a high-frequency power supply to the semiconductor wafer, the ions move on the surface of the semiconductor wafer, thereby bonding the semiconductor wafers together.

4. The bonding method for semiconductor wafers according to claim 3, characterized in that, An electrostatic chuck is used as the parallel plate plasma electrode.

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