A message uploading method, a data processing unit and a network processor
By obtaining the buffer unit length and descriptor read count through the data processing unit, descriptors are read in batches and written to the buffer unit, which solves the problem of excessive descriptor reads in the Virtio system and improves message processing speed and performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN JAGUAR MICROSYSTEMS CO LTD
- Filing Date
- 2025-07-21
- Publication Date
- 2026-07-14
AI Technical Summary
In existing Virtio systems, increasing the number of virtualization queues does not effectively improve performance, and the high number of descriptor reads leads to large PCIe overhead, affecting packet processing rate.
The data processing unit obtains the buffer unit length of the virtualization queue, determines the number of descriptors to be read, and reads descriptors in batches through a single PCIe read operation, writing the packets into the corresponding buffer units to reduce the number of descriptor reads.
This greatly improves the processing rate of ultra-large frame messages, reduces PCIe overhead, and optimizes the performance of the data processing unit.
Smart Images
Figure CN120896984B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of Virtio technology, specifically to a message uploading method, a data processing unit, and a network processor. Background Technology
[0002] Virtio is a general-purpose paravirtualized I / O framework, comprising a Virtio driver, Virtio devices, and virtualized queues (Virtqueues). Data interaction between the Virtio driver and Virtio devices is achieved through Virtqueues. Taking SplitVirtqueues as an example, the Virtio driver mainly consists of three parts: a descriptor ring, an available ring, and a used ring. Each descriptor entry in the descriptor ring contains a buffer address, a buffer length, a flag, and a next pointer. The available and used rings store pointers (ids) that point to a descriptor entry in the descriptor ring. Before receiving a packet, the Virtio driver needs to prepare the buffer and then notify the Virtio device. The Virtio device then begins receiving packet data. The Virtio device's data reception process is as follows:
[0003] (1) The Virtio device receives Ethernet packets and stores them in the local cache of the Virtio device;
[0004] (2) The Virtio device initiates a read operation on the available ring table of the Virtio driver to obtain the pointer (id) of the available ring table.
[0005] (3) Read the descriptor of the descriptor table based on the pointer (id) obtained from the available ring table, and obtain information such as cache address, cache length, flag and next hop pointer;
[0006] (4) Read the Ethernet packet from the Virtio device’s local buffer and upload it to the buffer unit pointed to by the descriptor;
[0007] (5) Update the used descriptors, that is, update the index and pointer (id) of the used ring table. The Virtio driver obtains the Ethernet packets in the buffer unit by reading the index and pointer (id) of the used ring table and reclaims the descriptor entries of the descriptor table for continued use.
[0008] like Figure 1As shown, the Virtio device reads one descriptor at a time, and only initiates the next round of descriptor reading after the current descriptor is used up. If the descriptor return time is 1µs, then the packet processing performance of a virtualized queue is 1Mpps (packets / second). If you want to improve the performance of the entire Virtio system, you can only enable multiple virtualized queues to achieve pipelined processing. However, due to the limitations of the number of virtualized queues, the logical resources of the Virtio device, and the area, it is not possible to improve the overall performance simply by increasing the number of virtualized queues. Summary of the Invention
[0009] The purpose of this application is to propose a message uploading method, a data processing unit, and a network processor to reduce the number of times the descriptor is read when uploading messages to the virtio driver, reduce PCIe overhead, and greatly improve the processing rate of ultra-large frame messages.
[0010] To achieve the above objectives, embodiments of this application provide a message uploading method, the method comprising:
[0011] Receive at least one message from any virtualization queue;
[0012] Obtain the length of the cache unit corresponding to the virtualization queue;
[0013] The number of descriptors to be read is determined based on the length of the at least one message and the length of the buffer unit;
[0014] The number of descriptors read is obtained by a single PCIe read operation;
[0015] Write the at least one message into the cache unit pointed to by the corresponding descriptor.
[0016] This application embodiment also provides a data processing unit, including a message receiving module, a message uploading module, a buffer length acquisition module, a descriptor number determination module, and a descriptor reading module;
[0017] The message receiving module is used to receive at least one message from any virtualization queue;
[0018] The cache length acquisition module is used to obtain the cache unit length corresponding to the virtualization queue;
[0019] The descriptor number determination module is used to determine the number of descriptors to be read based on the length of the at least one message and the length of the buffer unit;
[0020] The descriptor reading module is used to read the descriptor corresponding to the number of descriptors read in a single PCIe read operation;
[0021] The message uploading module is used to write the at least one message into the cache unit pointed to by the corresponding descriptor.
[0022] This application embodiment also provides a data processing unit, including:
[0023] A communication interface used for communicating with other electronic devices;
[0024] Memory is used to store computer program instructions;
[0025] A processor is configured to execute the computer program instructions to support the data processing unit in implementing the above-described method.
[0026] This application also provides a network processor, including a Virtio driver and a data processing unit as described above, wherein the Virtio driver runs on the host side and is used at least to generate the descriptor.
[0027] This application also provides a computer program product, including computer program instructions, which instruct a computer device to perform the operations corresponding to the above-described methods.
[0028] The message uploading method, data processing unit, and network processor of this application embodiment have the following beneficial effects:
[0029] The data processing unit communicates with the Virtio driver through at least one virtualized queue. When receiving at least one message from any virtualized queue, it obtains the length of the buffer unit corresponding to the virtualized queue. Each virtualized queue has a corresponding buffer unit length. Based on the length of the at least one message and the buffer unit length, it can determine how many buffer units are needed to satisfy the reporting of the at least one message. Each descriptor points to one buffer unit. Therefore, the number of descriptors to be read can be determined. Then, the corresponding number of descriptors are read in batches at once, and the at least one message is sent to the buffer unit pointed to by the corresponding descriptor. This reduces the number of times descriptors are read when sending messages to the Virtio driver, reduces PCIe overhead, and greatly improves the processing rate of very large frame messages. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1The above is a flowchart of the message uploading process disclosed in the background technology.
[0032] Figure 2 This is a flowchart of a message uploading method in an embodiment of this application.
[0033] Figure 3 This is a schematic diagram illustrating the interaction between the data processing unit and the Virtio driver in an embodiment of this application.
[0034] Figure 4 This is a schematic diagram of the message transmission in the embodiments of this application.
[0035] Figure 5 This is a schematic diagram of the structure of a data processing unit in an embodiment of this application. Detailed Implementation
[0036] The detailed description of the accompanying drawings is intended to illustrate the present embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.
[0037] See Figures 2-3 One embodiment of this application provides a message uploading method, which aims to reduce the number of times descriptors are read when uploading messages to the virtio driver, reduce PCIe overhead, and greatly improve the processing rate of very large frame messages. The method of this embodiment includes:
[0038] Step S10: Receive at least one message from any virtualization queue;
[0039] Specifically, before receiving a message, the Virtio driver needs to prepare a buffer unit and then notify the data processing unit (DPU). The data processing unit then starts receiving message data and buffers it locally. In the data processing unit, the received messages are buffered according to a queue.
[0040] Step S20: Obtain the length of the cache unit corresponding to the virtualization queue;
[0041] Specifically, the Virtio driver and the data processing unit communicate through multiple virtualized queues. After receiving a message, the data processing unit parses the message to obtain the queue number carried by the message, and determines which virtualized queue the message belongs to based on the queue number. The buffer lengths corresponding to different virtualized queues may be different because different virtualized queues may be used for the transmission of different types of messages. The buffer length can be obtained by querying local data based on the queue number.
[0042] Step S30: Determine the number of descriptors to be read based on the length of the at least one message and the length of the buffer unit;
[0043] Specifically, based on the length of the at least one message and the buffer length, the required number of buffers to satisfy the reporting of the at least one message can be determined. That is, the message length is divided by the descriptor length and rounded up to the nearest integer to obtain the number of descriptors required for one message. Then, the number of descriptors is obtained by multiplying the number of messages by the number of descriptors required for a single message. Each descriptor points to one buffer. For example, if a message is 9600 bytes long and the buffer length is 4096 bytes, then 3 buffers are needed to store this message. Assuming there are 4 such messages, then 12 buffers are needed; therefore, the number of descriptors to be read can be determined to be 12.
[0044] Step S40: Read the number of descriptors read in a single PCIe read operation;
[0045] Specifically, taking Split Virtqueues as an example, each virtualization queue (Virtqueue) includes three parts: a descriptor ring, an available ring, and a used ring. The corresponding available ring can be found based on the queue number of the virtualization queue. Then, a pointer is read from the available ring, and the descriptor pointed to by that pointer is read from the descriptor ring. Each descriptor contains next field information. Based on the next field information, the corresponding next descriptor can be found. The number of descriptors is read in a single PCIe read operation, that is, 12 descriptors are read in one PCIe read operation.
[0046] Step S50: Write the at least one message into the cache unit pointed to by the corresponding descriptor.
[0047] Specifically, after reading a certain number of descriptors in batches, the messages received in step S10 are sequentially written into at least one buffer corresponding to their respective descriptors, and then the used ring table of the virtualization queue is updated to notify the Virtio driver.
[0048] As described above, the method in this embodiment reduces the number of times the data processing unit reads the descriptor when sending messages to the Virtio driver, thereby reducing PCIe overhead and greatly improving the processing rate of very large frame messages, providing an effective solution for optimizing the performance of the data processing unit.
[0049] In some embodiments, step S20 includes:
[0050] The descriptor length memory is queried according to the queue number of the virtualization queue to obtain the cache unit length corresponding to the virtualization queue; wherein, the descriptor length memory stores the cache unit length corresponding to each virtualization queue.
[0051] Specifically, the descriptor length memory is a RAM structure, such as... Figure 4 As shown, Figure 4 The image shows a descriptor length RAM, which includes four storage units corresponding to queues 1 through 4, storing the buffer lengths of queues 1 through 4 (for example, the buffer length of queue 4 is 4096 bytes).
[0052] Step S30 includes:
[0053] The number of descriptors to be read for each message is determined based on the length of each message and the length of the buffer unit, and the number of descriptors to be read is obtained based on the number of descriptors to be read for each message.
[0054] Specifically, assuming a message is 9600 bytes long and the buffer is 4096 bytes long, then 3 buffers are needed to store the message. If there are 3 such messages, then 9 buffers are needed. Therefore, it can be determined that the number of descriptor reads is 9.
[0055] In some embodiments, the method further includes:
[0056] After reading the descriptor corresponding to the number of descriptors read in a single PCIe read operation, the cache unit length corresponding to the last descriptor read is obtained, and the cache unit length corresponding to the virtualization queue stored in the descriptor length memory is updated to the cache unit length corresponding to the last descriptor.
[0057] Specifically, such as Figure 4 As shown, Figure 4The image shows the descriptor length RAM, which includes four storage units corresponding to queues 1 to 4. The initial buffer length of queues 1 to 4 is 4096 bytes. After reading the descriptor, the last descriptor read by queue 1 points to a buffer length of 2048 bytes. Therefore, the buffer length of queue 1 is updated to 2048 bytes.
[0058] In some embodiments, step S30 includes:
[0059] After determining the number of descriptor reads, the number of descriptor reads is stored in the descriptor number memory; the descriptor number memory includes multiple storage units corresponding one-to-one with multiple virtualization queues, and each storage unit is used to store the number of descriptor reads for the corresponding virtualization queue;
[0060] Specifically, the descriptor read count memory is a RAM structure, such as... Figure 4 As shown, Figure 4 The table shows the descriptor read count RAM, which contains 4 storage units corresponding to queues 1 to 4. The descriptor read count of the storage unit corresponding to queue 1 is 12, indicating that 12 descriptors corresponding to queue 1 need to be read. The descriptor read count of the storage units corresponding to queues 2 to 4 is 0, indicating that no descriptors need to be read.
[0061] After each message is sent, update the descriptor read count corresponding to the virtualization queue in the descriptor count memory;
[0062] Specifically, such as Figure 4 As shown, during the message uploading process, it is necessary to update the descriptor read count of each storage unit in the Descriptor Read Count RAM. For example, the descriptor read count of the storage unit corresponding to queue 1 in the Descriptor Read Count RAM is 12. When message 1 in queue 1 is written to buffer 1~3, the descriptor read count of the storage unit corresponding to queue 1 in the Descriptor Read Count RAM is updated to 12-3=9 when the uploading of message 1 is completed.
[0063] In some embodiments, step S40 includes:
[0064] Obtain the valid bitmap of the message and the waiting bitmap, and determine the target virtualization queue to be scheduled based on the valid bitmap of the message and the waiting bitmap.
[0065] Read the number of descriptors corresponding to the target virtualization queue from the descriptor number memory;
[0066] The number of descriptors read is obtained by a single PCIe read operation;
[0067] The message valid bitmap and the read wait bitmap each include multiple bits corresponding to multiple virtualization queues. Each bit of the message valid bitmap indicates whether a message corresponding to a virtualization queue has not been sent, and each bit of the read wait bitmap indicates whether a read descriptor has been initiated.
[0068] Specifically, a bitmap contains multiple bits, such as... Figure 4 As shown, Figure 4 The valid bitmap and read wait bitmap of the message are shown. Both the valid bitmap and the read wait bitmap consist of 4 bits, corresponding to queues 1 to 4 respectively. Figure 4 In the valid bitmap of the message, the value of the bit corresponding to queue 1 is 1, which means that the data processing unit has not sent the message corresponding to queue 1. The value of the bit corresponding to queues 2 to 4 is 0, which means that the data processing unit has not received the message corresponding to queues 2 to 4 or the message corresponding to queues 2 to 4 has been sent to the corresponding buffer.
[0069] In some embodiments, the method includes:
[0070] When any message is received from any virtualization queue, the message and the number of descriptors to be read are stored in the message memory.
[0071] When the message memory stores at least one message of any virtualization queue, the bit corresponding to the virtualization queue in the message validity bitmap is set to 1; when the message memory does not store at least one message of any virtualization queue, the bit corresponding to the virtualization queue in the message validity bitmap is set to 0.
[0072] Specifically, the message storage is a RAM structure, such as... Figure 4 As shown, Figure 4 The message storage RAM is shown. The message storage RAM contains multiple storage units, each used to store a message and the number of descriptors to be read. Assuming that the number of descriptors to be read when sending message 1 is 3, and the total number of descriptors to be read when sending messages 1 to 4 is 12, then after sending message 1 to the corresponding buffer, the number of descriptors to be read in the descriptor read count RAM will be updated to 12-3=9 based on the number of descriptors to be read when sending message 1 recorded in the message storage RAM as 3. If messages 1 to 4 have all been sent to the buffer, and there is no message corresponding to queue 1 in the message storage RAM, the bit corresponding to queue 1 in the message valid bitmap needs to be set to 0.
[0073] In some embodiments, step S40 includes:
[0074] The read descriptors are stored in the descriptor FIFO module corresponding to the target virtualization queue; each virtualization queue has a corresponding descriptor FIFO module;
[0075] Specifically, when the FIFO descriptor module corresponding to any virtualization queue is empty, the bit corresponding to that virtualization queue in the read wait bitmap is set to 0; when the FIFO descriptor module corresponding to any virtualization queue is not empty, the bit corresponding to that virtualization queue in the read wait bitmap is set to 1.
[0076] Specifically, such as Figure 4 As shown, the read wait bitmap shows the four bits corresponding to queues 1 to 4. The initial value of the four bits of the read wait bitmap is 1, indicating that the descriptor read has not been issued.
[0077] Queues 1-4 participate in round-robin scheduling. The "valid message bitmap" and "read waiting bitmap" are logically ANDed to obtain a new bitmap. If bit 0 of the new bitmap is 1, it means that queue 1 has a message stored in RAM and has not initiated a descriptor read to the driver. In this case, queue 1 can participate in subsequent round-robin scheduling. If queue 1 is selected, bit 0 of "read waiting bitmap" is set to 0, indicating that the descriptor read of queue 1 has been sent and it will no longer participate in round-robin scheduling.
[0078] based on Figure 4 To illustrate, let's take an example. Assuming VIRTIO has negotiated the MERGEABLE feature, the following description uses a Virtqueue (queue 1) as an example to illustrate the data processing unit's message receiving and descriptor reading process in this embodiment:
[0079] ① When the data processing unit receives the Ethernet packet from queue 1, it queries the "Descriptor Length RAM" to obtain the descriptor buffer length of queue 1 (assuming an initial value of 4096 bytes). Assuming the packet length is 9600 bytes, it divides the packet length by the descriptor length and rounds up to obtain the number of descriptors required for the current packet, which is 3. Then, it saves the packet and the number of descriptors to be read into the "Packet Storage RAM".
[0080] ② Update the number of descriptors required for all messages in queue 1 to the "Descriptor Read Count RAM". Assuming that queue 1 receives 4 messages and each message requires 3 descriptors, the final number updated to the "Descriptor Read Count RAM" is 12.
[0081] ③ The initial value of "Message Valid Bitmap" is 0, indicating that no messages are stored in RAM. When queue 1 receives a message, bit 0 of "Message Valid Bitmap" is set to 1.
[0082] ④ After performing a logical AND operation between the “valid message bitmap” and the “read waiting bitmap”, a new bitmap is obtained. If bit 0 of the new bitmap is 1, it means that there are messages stored in RAM in queue 1 and no descriptor read has been initiated to the Virtio driver. In this case, queue 1 can participate in the subsequent polling scheduling.
[0083] ⑤ The initial value of all bits in the "Read Waiting Bitmap" is 1, indicating that the descriptor read has not been issued. The result of step 4 is used in the round-robin scheduling. If queue 1 is selected, bit 0 of the "Read Waiting Bitmap" is set to 0, indicating that the descriptor read has been issued and it will no longer participate in the round-robin scheduling.
[0084] ⑥ Initiate a descriptor read from queue 1 of the Virtio driver, reading 12 descriptors.
[0085] ⑦ Since step ⑥ reads 12 descriptors, the Virtio driver continuously returns 12 descriptors and saves them to the "Descriptor Storage FIFO" in the data processing unit. At the same time, the value of queue 1 in the "Descriptor Length RAM" is updated to the buffer length of the currently received descriptor (assumed to be 2048 bytes). When a message is received from queue 1 again, the number of descriptors required for the message is calculated using the updated buffer length.
[0086] ⑧ After the descriptor is stored in the FIFO, read the message in the "Message Storage RAM" and the number of descriptors required for the message and the descriptors in the "Descriptor Storage FIFO", and send the message to the buffer pointed to by the descriptor.
[0087] ⑨ After reading the last descriptor of queue 1 from the "Descriptor Storage FIFO", set bit 0 of "Read Waiting Bitmap" to 1. If the message in "Message Storage RAM" has not been read at this time, queue 1 can participate in the polling schedule again and repeat the above steps.
[0088] ⑩ Each time a message from queue 1 is completely read from the "Message Storage RAM", the value in the "Descriptor Read Count RAM" is updated by subtracting the number of descriptors required for the current message from the value in the "Descriptor Read Count RAM" (the number of descriptors required for the message in step 1 is stored together with the message in the "Message Storage RAM"). After the last message is completely read from the "Message Storage RAM", bit 0 of the "Message Valid Bitmap" is set to 0, indicating that the data processing unit no longer has messages from queue 1.
[0089] See Figure 5 Another embodiment of this application provides a data processing unit, including a message receiving module 1, a buffer length acquisition module 2, a descriptor number determination module 3, a descriptor reading module 4, and a message uploading module 5;
[0090] The message receiving module 1 is used to receive at least one message from any virtualization queue;
[0091] The cache length acquisition module 2 is used to acquire the cache unit length corresponding to the virtualization queue;
[0092] The descriptor number determination module 3 is used to determine the number of descriptors to be read based on the length of the at least one message and the length of the buffer unit.
[0093] The descriptor reading module 4 is used to read the descriptor corresponding to the number of descriptors read in a single PCIe read operation;
[0094] The message uploading module 5 is used to write the at least one message into the cache unit pointed to by the corresponding descriptor.
[0095] In some embodiments, the cache length acquisition module 2 is used to query the descriptor length memory according to the queue number of the virtualization queue to obtain the cache unit length corresponding to the virtualization queue; wherein, the descriptor length memory stores the cache unit length corresponding to each virtualization queue;
[0096] The descriptor number determination module 3 is used to determine the number of descriptors that need to be read for each message based on the length of each message and the length of the buffer unit, and to obtain the number of descriptors read based on the number of descriptors that need to be read for each message.
[0097] In some embodiments, the data processing unit further includes a cache length update module, which is used to obtain the cache unit length corresponding to the last read descriptor after reading the descriptor corresponding to the number of descriptors read in a single PCIe read operation, and update the cache unit length corresponding to the virtualization queue stored in the descriptor length memory to the cache unit length corresponding to the last descriptor.
[0098] In some embodiments, the method further includes a descriptor count storage module, configured to store the descriptor read count in a descriptor count memory after determining the descriptor read count; the descriptor count memory includes a plurality of storage units corresponding one-to-one with a plurality of virtualization queues, each storage unit being configured to store the descriptor read count of the corresponding virtualization queue; and configured to update the descriptor read count corresponding to the virtualization queue in the descriptor count memory each time a message is sent.
[0099] In some embodiments, the descriptor reading module 4 is used to obtain a packet valid bitmap and a read wait bitmap, determine the target virtualization queue to be scheduled based on the packet valid bitmap and the read wait bitmap, read the number of descriptors corresponding to the target virtualization queue from the descriptor number memory, and read the descriptors corresponding to the number of descriptors read in a single PCIe read operation; wherein, both the packet valid bitmap and the read wait bitmap include multiple bits that correspond one-to-one with multiple virtualization queues, each bit of the packet valid bitmap indicates whether a packet for a corresponding virtualization queue has not been sent, and each bit of the read wait bitmap indicates whether a descriptor read has been initiated.
[0100] In some embodiments, the message receiving module 1 is configured to store any message and the number of descriptors to be read into the message memory when receiving any message from any virtualization queue.
[0101] The data processing unit further includes a bitmap management module, which is used to set the bit corresponding to the virtualization queue in the valid bitmap of the message to 1 when the message memory stores at least one message of any virtualization queue, and to set the bit corresponding to the virtualization queue in the valid bitmap of the message to 0 when the message memory does not store at least one message of any virtualization queue.
[0102] In some embodiments, the descriptor reading module 4 is further configured to store the read descriptors into a descriptor FIFO module corresponding to the target virtualization queue; each virtualization queue has a corresponding descriptor FIFO module;
[0103] The bitmap management module is further configured to set the bit corresponding to the virtualization queue in the read wait bitmap to 0 when the descriptor FIFO module corresponding to any virtualization queue is empty, and to set the bit corresponding to the virtualization queue in the read wait bitmap to 1 when the descriptor FIFO module corresponding to any virtualization queue is not empty.
[0104] It should be noted that the data processing unit in this embodiment corresponds to the method in the above embodiment. The contents of the data processing unit in this embodiment that are not described in detail can be obtained by referring to the contents of the method in the embodiment, and will not be described again in this embodiment.
[0105] Another embodiment of this application provides a data processing unit, including:
[0106] A communication interface used for communicating with other electronic devices;
[0107] Memory is used to store computer program instructions;
[0108] A processor is configured to execute the computer program instructions to support the data processing unit in implementing the method described in the above embodiments.
[0109] In this embodiment, the memory mainly includes a program storage area and a data storage area. The program storage area can store the operating device, applications required for at least one function, etc., and the data storage area can store related data, etc. Furthermore, the memory can be a high-speed random access memory, or a non-volatile memory, such as a plug-in hard disk, a smart media card (SMC), a secure digital card (SD), and a flash card, or other volatile solid-state storage devices.
[0110] The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or the processor can be any conventional processor. The processor is the control center of the data processing unit and uses various interfaces and lines to connect the various parts of the data processing unit.
[0111] Another embodiment of this application provides a network processor, characterized in that it includes a Virtio driver and the data processing unit described in the above embodiments, wherein the Virtio driver runs on the host side and is used at least to generate the descriptor.
[0112] Another embodiment of this application provides a computer program product, including computer program instructions that instruct a computer device to perform operations corresponding to the message uploading method described in the above embodiments.
[0113] Specifically, the computer program product includes a series of computer program instructions, which are codes written in a computer program. These instructions define how to perform specific operations. The computer program instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which refer to the various steps in the message uploading method described in the above embodiments. In this way, the computer program product of this embodiment provides a complete software solution that can run on various computer devices to implement the message uploading method of the above embodiments.
[0114] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A message uploading method, characterized in that, The method includes: Receive at least one message from any virtualization queue; Obtain the length of the cache unit corresponding to the virtualization queue; The number of descriptors to be read is determined based on the length of the at least one message and the length of the buffer unit; The number of descriptors read is obtained by a single PCIe read operation; Write the at least one message into the cache unit pointed to by the corresponding descriptor.
2. The method according to claim 1, characterized in that, The step of obtaining the cache unit length corresponding to the virtualization queue includes: The descriptor length memory is queried according to the queue number of the virtualization queue to obtain the cache unit length corresponding to the virtualization queue; wherein, the descriptor length memory stores the cache unit length corresponding to each virtualization queue; Determining the number of descriptor reads based on the length of the at least one message and the length of the buffer unit includes: The number of descriptors to be read for each message is determined based on the length of each message and the length of the buffer unit, and the number of descriptors to be read is obtained based on the number of descriptors to be read for each message.
3. The method according to claim 2, characterized in that, The method further includes: After reading the descriptor corresponding to the number of descriptors read in a single PCIe read operation, the cache unit length corresponding to the last descriptor read is obtained, and the cache unit length corresponding to the virtualization queue stored in the descriptor length memory is updated to the cache unit length corresponding to the last descriptor.
4. The method according to claim 1, characterized in that, The method further includes: After determining the number of descriptor reads, the number of descriptor reads is stored in the descriptor number memory; the descriptor number memory includes multiple storage units corresponding one-to-one with multiple virtualization queues, and each storage unit is used to store the number of descriptor reads for the corresponding virtualization queue; After each message is sent, the number of descriptors read from the corresponding virtualization queue in the descriptor count memory is updated.
5. The method according to claim 4, characterized in that, The step of reading the descriptor corresponding to the number of descriptors read in a single PCIe read operation includes: Obtain the valid bitmap of the message and the waiting bitmap, and determine the target virtualization queue to be scheduled based on the valid bitmap of the message and the waiting bitmap. Read the number of descriptors corresponding to the target virtualization queue from the descriptor number memory; The number of descriptors read is obtained by a single PCIe read operation; The message valid bitmap and the read wait bitmap each include multiple bits corresponding to multiple virtualization queues. Each bit of the message valid bitmap indicates whether a message corresponding to a virtualization queue has not been sent, and each bit of the read wait bitmap indicates whether a read descriptor has been initiated.
6. The method according to claim 5, characterized in that, The method includes: When any message is received from any virtualization queue, the message and the number of descriptors to be read are stored in the message memory. When the message memory stores at least one message of any virtualization queue, the bit corresponding to the virtualization queue in the message validity bitmap is set to 1; when the message memory does not store at least one message of any virtualization queue, the bit corresponding to the virtualization queue in the message validity bitmap is set to 0.
7. The method according to claim 5, characterized in that, The method further includes: The read descriptors are stored in the descriptor FIFO module corresponding to the target virtualization queue; each virtualization queue has a corresponding descriptor FIFO module; Specifically, when the FIFO descriptor module corresponding to any virtualization queue is empty, the bit corresponding to that virtualization queue in the read wait bitmap is set to 0; when the FIFO descriptor module corresponding to any virtualization queue is not empty, the bit corresponding to that virtualization queue in the read wait bitmap is set to 1.
8. A data processing unit, characterized in that, It includes a message receiving module, a message uploading module, a buffer length acquisition module, a descriptor number determination module, and a descriptor reading module; The message receiving module is used to receive at least one message from any virtualization queue; The cache length acquisition module is used to obtain the cache unit length corresponding to the virtualization queue; The descriptor number determination module is used to determine the number of descriptors to be read based on the length of the at least one message and the length of the buffer unit; The descriptor reading module is used to read the descriptor corresponding to the number of descriptors read in a single PCIe read operation; The message uploading module is used to write the at least one message into the cache unit pointed to by the corresponding descriptor.
9. The data processing unit according to claim 8, characterized in that, The cache length acquisition module is used to query the descriptor length memory according to the queue number of the virtualization queue to obtain the cache unit length corresponding to the virtualization queue; wherein, the descriptor length memory stores the cache unit length corresponding to each virtualization queue; The descriptor number determination module is used to determine the number of descriptors that need to be read for each message based on the length of each message and the length of the buffer unit, and to obtain the descriptor read count based on the number of descriptors that need to be read for each message.
10. The data processing unit according to claim 8, characterized in that, The descriptor reading module is used to obtain the valid bitmap of the message and the read waiting bitmap, and to determine the target virtualization queue to be scheduled based on the valid bitmap of the message and the read waiting bitmap. The number of descriptors corresponding to the target virtualization queue is read from the descriptor number memory; the descriptor corresponding to the number of descriptors read is read through a single PCIe read operation; wherein, the packet valid bitmap and the read wait bitmap each include multiple bits corresponding one-to-one with multiple virtualization queues, each bit of the packet valid bitmap indicates whether a packet corresponding to a virtualization queue has not been sent, and each bit of the read wait bitmap indicates whether a descriptor read has been initiated.
11. The data processing unit according to claim 10, characterized in that, The message receiving module is used to store any message and the number of descriptors to be read into the message storage when receiving any message from any virtualization queue. The data processing unit further includes a bitmap management module, which is used to set the bit corresponding to the virtualization queue in the valid bitmap of the message to 1 when the message memory stores at least one message of any virtualization queue, and to set the bit corresponding to the virtualization queue in the valid bitmap of the message to 0 when the message memory does not store at least one message of any virtualization queue.
12. The data processing unit according to claim 11, characterized in that, The descriptor reading module is also used to store the read descriptors into the descriptor FIFO module corresponding to the target virtualization queue; each virtualization queue has a corresponding descriptor FIFO module; The bitmap management module is further configured to set the bit corresponding to the virtualization queue in the read wait bitmap to 0 when the descriptor FIFO module corresponding to any virtualization queue is empty, and to set the bit corresponding to the virtualization queue in the read wait bitmap to 1 when the descriptor FIFO module corresponding to any virtualization queue is not empty.
13. A data processing unit, characterized in that, include: A communication interface used for communicating with other electronic devices; Memory is used to store computer program instructions; A processor for executing the computer program instructions to support the data processing unit in implementing the method of any one of claims 1 to 7.
14. A network processor, characterized in that, The device includes a Virtio driver and a data processing unit as described in any one of claims 9 to 12, wherein the Virtio driver runs on the host side and is used at least to generate the descriptor.
15. A computer program product, characterized in that, It includes computer program instructions that instruct a computer device to perform an operation corresponding to the method as described in any one of claims 1 to 7.